Pipeline multiplier

Abstract

The invention relates to the field of computer equipment based on a specific calculation model, can be used for designing neuromorphic processor equipment, and can also be used for the fields of central and graphics processor equipment and the like. The pipelined multiplier may be part of an arithmetic coprocessor of a neuromorphic VLSI (very large scale integrated circuit) processor core, intended to perform a multiplication operation on two binary operands, or a combined multiplication-addition operation (MAC operation) on three operands. The two primary operands are integers in the range from-32768 to 32767, 16 bits long, represented in additional codes. The third additional operand of the MAC operation and the operand of the operation result are 32-bit integers presented in additional codes. The pipelined multiplier includes the use of the claimed invention, capable of quickly performing a large number of multiplications or combined multiply-add operations in a pipelined operation mode, i.e., in each operation cycle, receiving a new set of operand values at the input and generating a new result at the output based on the old set of operand values.

Description

Technical Field

[0001] This invention relates to the field of computer devices based on a specific computational model, applicable to the design of neuromorphic processor devices, as well as central processing unit (CPU) and graphics processing unit (GPU) devices. The pipelined multiplier can be part of the arithmetic coprocessor within a neuromorphic VLSI (Very Large Scale Integration) processor core, designed to perform multiplication on two binary operands or combined multiplication-addition (MAC) operations on three operands. The two primary operands are 16-bit integers in the range -32768 to 32767, represented by additional codes. The third additional operand and the operand of the MAC operation are both 32-bit integers presented in the additional codes. Background Technology

[0002] A known prior art method is the pipelined arithmetic multiplier (see Russian Federation Patent No. 2546072, G06F 7 / 527, published in 2015). This device comprises two blocks with a cellular structure divided into columns and rows, storage elements, and elements for controlling information recording and reading from the memory. The first block is the input block, with the number of columns equal to the sum of the number of bits in the multiplicand and multiplier, and the number of rows one more than the number of bits in the multiplicand. The second block has the number of columns and rows equal to the number of bits in the multiplicand and multiplier, respectively. Four types of units with registers are used (OR, AND, half-adder, and adder).

[0003] The main drawback of this solution is the lack of an implementation for addition, making it impossible to implement multiplication-addition operations in a multiplier pipeline. Another drawback is the systolic array architecture of the multiplier, which is slower compared to architectures based on the Booth algorithm.

[0004] A prior art device for performing multiplication-addition operations is known (see US20190012143, published in 2019), comprising a multiplier, an adder, a first result register, and a second result register connected to the outputs of the multiplier and the adder, respectively. It includes four selection units. The first selection unit is configured to selectively provide a first value from a first set of values ​​to the multiplier in response to a first control signal. The second selection unit is configured to selectively provide a second value from a second set of values ​​to the multiplier in response to a second control signal. The third selection unit is configured to selectively provide a third value from a third set of values ​​to the adder in response to a third control signal. The fourth selection unit is configured to selectively provide a fourth value from a fourth set of values ​​to the adder in response to a fourth control signal.

[0005] The main drawback of this solution is the sequential execution of MAC operations, i.e., the multiplication of two operands followed by the addition of the multiplication result to a third operand. This results in different execution speeds for multiplication and multiplication-addition operations, which complicates the processor's arithmetic queue controller and reduces the overall execution speed of multiplication-addition operations.

[0006] The closest in technical essence to the claimed device is a multiplication-addition device and its operation method (US Patent No. US7730118, published in 2006, IPC G06F 7 / 38), which includes an arithmetic unit for selectively implementing one of multiplication or multiplication-addition instructions, including a multiplier, a convolution pipeline, a result register, and accumulator circuitry. The multiplier is configured to receive first and second operands and is capable of generating multiplication terms. The adder circuitry is used to obtain the multiplication terms from the multiplier and has the ability to combine them to obtain the multiplication result. The result register is used to obtain the multiplication result from the adder. An operation selection multiplexer circuit is connected to receive the value stored in the result register and an accumulation control signal to determine whether the arithmetic unit performs a multiplication or a MAC operation. Devices known in the art use an intermediate value generator based on the Booth algorithm, a six-stage Wallace tree convolution pipeline for 17 intermediate values, and a multiplexer for selecting multiplication / combined multiplication-addition operations.

[0007] The drawback of this prototype is its use of the standard Booth algorithm, which generates more intermediate values, thus increasing the pipeline size. For current neuromorphic computing tasks, this 32-bit calculator version hinders the implementation of more compact, efficient, and energy-saving solutions. Summary of the Invention

[0008] The purpose of this invention is to improve the speed of performing multiplication or combined multiplication-addition operations, and to reduce device area and energy consumption.

[0009] The technological result is a reduction in the number of intermediate values ​​produced, leading to increased speed, reduced area, and lower energy consumption.

[0010] The resulting technical outcome is that the pipelined multiplier includes an intermediate value generator configured to receive first and second operands and generate intermediate multiplication results; a "Wallace tree" intermediate value convolution pipeline used to add the obtained intermediate values ​​and obtain the multiplication result; a multiplexer used to select the multiplication operation or to perform a combined multiplication-addition operation with a third operand. The multiplier input operands have a bit capacity of 16 bits, and the result bit capacity is 32 bits, so the third operand capacity for MAC operations is also 32 bits, which is necessary for efficient use of device resources; the clock signal blocks are configured such that each subsequent block operates on the inverse edge of the clock signal relative to the previous block; the intermediate value generator is based on the improved Radix 8Booth algorithm, which achieves parallel generation of all intermediate value variants within half a cycle; and the three-layer pipeline adds 6 intermediate values.

[0011] The intermediate value convolution pipeline is a three-layer Wallace tree pipeline, in which intermediate values ​​are added in pairs to produce the result.

[0012] The generation of intermediate value variants from the multiplicand operands occurs within the intermediate value generator block.

[0013] The intermediate value generator multiplexer consists of six parallel multiplexers.

[0014] The convolution pipeline performs addition in three stages, each handled by a separate set of adders.

[0015] While generating intermediate values ​​and loading them into the intermediate value convolution pipeline, the operation selection multiplexer, based on the value of the operation selection flag, switches the multiplexer to write the value of the 32-bit operand (if it is a combined multiplication-addition operation) or "logic 0" (if it is a multiplication operation) into a 32-bit register, which then transfers the value to the intermediate value convolution pipeline.

[0016] The impact of the "16-bit multiplier input operand capacity" on the technical results is as follows: due to the shorter operands, fewer intermediate values ​​are generated, which reduces the number of adders in the first layer of the intermediate value convolution pipeline, thereby reducing the number of layers in the intermediate value convolution pipeline, resulting in an increase in the speed, area and power consumption of the device.

[0017] The bit capacity of the 32-bit operation result affects the technical result because reducing the bit capacity of the output operand reduces the bit capacity of adders, registers, multiplexers and other device components, thereby reducing power consumption and device area.

[0018] The blocks are configured according to the clock signal, so that each subsequent block is operated on the reverse edge of the clock signal relative to the previous block, resulting in an increase in the block operation frequency, thereby increasing the device speed.

[0019] Parallel generation of intermediate values ​​within half a clock cycle allows for pipelined processing of input operands, thereby improving device performance.

[0020] Implementing a three-layer pipeline with six intermediate values ​​can optimize the structure of the intermediate value convolution pipeline, thereby improving performance and reducing device size and power consumption.

[0021] The number of intermediate values ​​generated can be reduced by generating intermediate values ​​at once based on several elements of the multiplier operand. In the case of the Radix 8 variant, the multiplier is divided into bit "quadruple groups", which determine the coefficients, and these coefficients are multiplied by the multiplier to obtain a set of intermediate values.

[0022] Using the Radix 8 algorithm increases the size of the redundant encoding applied to the multiplier, resulting in a reduction in the number of intermediate values. Conversely, reducing the bit capacity of the input operands from 32 bits (see prototype) to 16 bits also leads to a reduction in the number of intermediate values. The cumulative effect of using these solutions allows for a reduction in the width and depth of the convolution pipeline, as the pipeline adds only 6 intermediate values ​​instead of 17 in the prototype, which in turn leads to optimization of the desired features. Attached Figure Description

[0023] Figure 1 The basic schematic diagram of the device is shown, where block 1 is the intermediate value generator, block 2 is the operation selection multiplexer, block 3 is the intermediate value convolution pipeline, input 4 is the 16-bit operand-multiplicand, input 5 is the 16-bit operand-multiplier, input 6 is logic 0, input 7 is the 32-bit operand of the MAC operation, input 8 is the MAC operation selection flag, and output 9 is the result of the device operation.

[0024] Figure 2 An intermediate value generator is shown, where 11 is a block of an intermediate value generator with a coefficient of 4, 12 is a block of an intermediate value generator with a coefficient of 3, 13 is a block of an intermediate value generator with a coefficient of 2, 14 is a block of an intermediate value generator with a coefficient of 1, 15 is a block of an intermediate value generator with a coefficient of -1, 16 is a block of an intermediate value generator with a coefficient of -2, 17 is a block of an intermediate value generator with a coefficient of -3, 18 is a block of an intermediate value generator with a coefficient of -4, and 19 is an intermediate value generator multiplexer.

[0025] Figure 3 The intermediate value generator block with a coefficient of 1 is shown, where block 141 is an 18-bit register.

[0026] Figure 4The intermediate value generator block with a coefficient of 2 is shown, where block 131 is an 18-bit register.

[0027] Figure 5 The intermediate value generator block with a coefficient of 3 is shown, where block 121 is an 18-bit full binary adder.

[0028] Figure 6 The intermediate value generator block with a coefficient of 4 is shown, where block 111 is an 18-bit register.

[0029] Figure 7 The diagram shows intermediate value generator blocks with a coefficient of -1, where block 151 is an 18-bit logic inverter and block 152 is an 18-bit full binary adder.

[0030] Figure 8 The diagram shows an intermediate value generator block with a coefficient of -2, where block 161 is an 18-bit logic inverter and block 162 is an 18-bit full binary adder.

[0031] Figure 9 The intermediate value generator block with a coefficient of -3 is shown, where block 171 is an 18-bit logic inverter and block 172 is an 18-bit full binary adder.

[0032] Figure 10 The intermediate value generator block with a coefficient of -4 is shown, where block 181 is an 18-bit logic inverter and block 182 is an 18-bit full binary adder.

[0033] Figure 11 The circuit of the intermediate value generator multiplexer is shown, where blocks 191, 192, 193, 194, 195, and 196 are multiplexers.

[0034] Figure 12 The arithmetic selection multiplexer is shown, where block 21 is the multiplexer and block 22 is a 32-bit register.

[0035] Figure 13 The intermediate value convolution pipeline is shown, where blocks 31, 32, 33, 34, 35, and 36 are 32-bit full binary adders.

[0036] Figure 14 The table shows the changes in bit quads and their corresponding coefficients.

[0037] Figure 15 The general working principle of the invention is illustrated in the form of a timing diagram. Detailed Implementation

[0038] The device comprises three functional blocks: an intermediate value generator (block 1, see...). Figure 2 ), Operation selection multiplexer (block 2, see Figure 12 ) and convolutional blocks (block 3, see Figure 13 ).

[0039] The generation of intermediate value variants of the multiplicand operand (input 4) occurs in the intermediate value generator block (blocks 11-18, see...). Figure 3-10 )middle.

[0040] The intermediate value generator block with a coefficient of "4" (block 11) writes the value of the multiplier operand (input 4) into an 18-bit register, and then generates and stores an 18-bit value (block 111) by left-shifting by 2 bits. This value is then transferred to the input of block 19 (see [link to block 19]). Figure 6 ).

[0041] The intermediate value generator block (block 12) with coefficient "3" shifts the value of the multiplicand operand (input 4) left by 1 bit and extends the most significant bit by 1 bit; and extends the most significant bit of the value of the multiplicand operand (input 4) by 2 bits; feeds it into an 18-bit adder (121), where an 18-bit value is generated and stored through addition, and then transmitted to the input of block 19 (see...). Figure 5 ).

[0042] The intermediate value generator block (block 13) with a coefficient of "2" writes the value of the multiplier operand (input 4) into an 18-bit register, and generates and stores the 18-bit value (block 131) by left shifting it by 1 bit and extending the most significant bit by 1 bit. This value is then transferred to the input of block 19 (see [link to block 13]). Figure 4 ).

[0043] The intermediate value generator block (block 14) with a coefficient of "1" writes the value of the multiplier operand (input 4) into an 18-bit register, and generates and stores an 18-bit value (block 141) by extending the most significant bit by 2 bits, and then transmits it to the input of block 19 (see...). Figure 3 ).

[0044] The intermediate value generator block (block 15) with a coefficient of "negative 1" feeds the value of the multiplicand operand (input 4) (with the most significant bit extended by 2 bits) into an 18-bit inverter (block 151) to obtain a value equal to the negative multiplicand minus 1. This value is then fed into an adder (block 152), where it is incremented by 1 to obtain and store an 18-bit value equal to the negative multiplicand. This value is then transmitted to the input of block 19 (see...). Figure 7 ).

[0045] The intermediate value generator block (block 16) with a coefficient of "-2" shifts the value of the multiplicand operand (input 4) left by 1 bit and extends the most significant bit by 1 bit, feeding it into an 18-bit inverter (block 161); this yields a value equal to twice the negative multiplicand minus one, which is then fed into an adder (block 162). In the adder, it is incremented by 1 to obtain and store the value of twice the negative multiplicand, which is then transmitted to the input of block 19 (see...). Figure 8 ).

[0046] The intermediate value generator block (block 17) with a coefficient of "-3" shifts the value of the multiplicand operand (input 4) left by 2 bits and feeds it into an 18-bit inverter (block 171) to obtain a value of four times the negative multiplicand minus one. This value is then fed into an adder (block 182), where it is added to the value of the multiplicand operand (input 4) after being extended to 2 bits and 1 bit by the most significant bit. This results in a value of three times the negative multiplicand, which is then transmitted to the input of block 19 (see...). Figure 9 ).

[0047] The intermediate value generator block (block 18) with a coefficient of "-4" shifts the value of the multiplicand operand (input 4) left by 2 bits and feeds it into an 18-bit inverter (block 181) to obtain a value equal to four times the negative multiplicand minus one. This value is then fed into an adder (block 182), where it is incremented by 1 to obtain and store a value equal to four times the negative multiplicand. This value is then transmitted to the input of block 19 (see...). Figure 10 ).

[0048] Intermediate value generator multiplexer (block 19, see Figure 11 The intermediate values ​​and logic 0 lines obtained from blocks 11-18 (input 6), corresponding to the quartets obtained from the multiplier operands (input 5) (see...) Figure 14 Loaded into the intermediate value convolution pipeline (block 3), the logic 0 line (input 6) is equal to the result of multiplying the multiplicand by the zero coefficient. 。 The intermediate value generator multiplexer comprises six parallel multiplexers (blocks 191-196). When the intermediate value is transmitted to the convolutional tree, the multiplexer normalizes it to a 32-bit capacity. Therefore, multiplexer (block 191) extends the most significant bit of the transmitted intermediate value by 14 bits, multiplexer (block 192) shifts the value left by 3 bits and extends the most significant bit of the transmitted intermediate value by 11 bits, multiplexer (block 193) shifts the value left by 6 bits and extends the most significant bit of the transmitted intermediate value by 8 bits, multiplexer (block 194) shifts the value left by 9 bits and extends the most significant bit of the transmitted intermediate value by 5 bits, multiplexer (block 195) shifts the value left by 12 bits and extends the most significant bit of the transmitted intermediate value by 2 bits, and multiplexer (block 196) shifts the value left by 15 bits and discards the most significant bit of the intermediate value.

[0049] While generating intermediate values ​​(block 2) and loading them into the intermediate value convolution pipeline (block 3), the operation selection multiplexer (block 2) writes the value of the 32-bit operand (input 7) to the 32-bit register (block 22) by switching the multiplexer (block 21) according to the value of the operation selection flag (input 8), or writes logic 0 (input 6) to the 32-bit register when performing combined multiplication-addition operations, and then the value is transferred to the intermediate value convolution pipeline (block 3).

[0050] The intermediate value convolution pipeline (block 3) is a three-layer Wallace tree pipeline (see...). Figure 13 (where blocks 31-36 are 32-bit full binary adders), where intermediate values ​​are added in pairs to obtain the result, and then the result is transmitted to output 9.

[0051] The choice of a tree structure for convolutional blocks is related to the optimal performance of this structure relative to simulation and streaming capabilities.

[0052] To improve device speed, the operations of each stage are optimized relative to the clock signal: each subsequent stage of the multiplier operates on the reverse edge of the clock signal relative to the previous stage. Therefore, an execution speed equal to two clock cycles is achieved. The general operational principle of this invention is as follows: Figure 15 The timing diagram is shown in the figure.

[0053] At the start of the operation, two 16-bit operands are fed into the input of the intermediate value generator (block 1): the multiplicand (input 4) and the multiplier (input 5). Based on the multiplicand operand, all intermediate value variants used in the algorithm are generated, with coefficients ranging from 4 to -4 (blocks 11-18). In parallel, based on the multiplier operand, a quartet is generated, thereby feeding the intermediate value into the intermediate value convolution pipeline (block 3). This intermediate value is obtained by selecting based on the value of the quartet and normalizing it to a 32-bit width according to the quartet's index in a multiplexer (blocks 191-196). Next, in the intermediate value convolution pipeline (block 3), parallel pairwise arithmetic summation of the intermediate values ​​begins. After the intermediate value quartet enters the intermediate value convolution pipeline, the intermediate value generator (block 1) can begin generating new intermediate values ​​from a new pair of operands (input 4 and input 5). In parallel with the first convolution stage, when performing combined multiplication-addition operations, a third 32-bit operand (input 7) can be added to the intermediate value convolution pipeline via an operation selection multiplexer (block 2); otherwise, the operand is equal to zero (input 6), and a multiplication operation is performed. The operation selection is controlled by the operation selection flag (input 8). Regardless of the operation performed, the convolution pipeline performs three addition stages, each processed by a separate set of adders (blocks 31-36). After the third convolution stage, the result of the multiplication or combined multiplication-addition is transmitted to the output of device 9.

[0054] An example of performing a multiplication operation.

[0055] Assume the multiplicand operand (input 4) equals 0000000011111010 (hereinafter referred to as A), the multiplier operand (input 5) equals 0000110010100010 (hereinafter referred to as B), and the arithmetic selection flag (input 8) equals 0. In this case, since the device performs a multiplication operation, the value of the MAC arithmetic operand (input 7) is not considered. Therefore, reference logic 0 (input 6) is written to the arithmetic selection multiplexer register (block 22).

[0056] At the leading edge of the clock signal (hereinafter referred to as CK) in the intermediate value generator (block 1), the intermediate value generation block calculates the intermediate 18-bit value from A. Therefore, block 11 generates a 4*A value equal to 000000001111101000, block 12 generates a 3*A value equal to 000000001011101110, block 13 generates a 2*A value equal to 000000000111110100, block 14 generates an A value equal to 000000000011111010, block 15 generates a negative A value equal to 111111111100000110, block 16 generates a negative 2*A value equal to 111111111000001100, block 17 generates a negative 3*A value equal to 111111110100010010, and block 18 generates a negative 4*A value equal to 111111110000011000. Instead of generating an intermediate value for coefficient 0, it multiplies it by the reference value 0 (input 6).

[0057] Concurrently, the intermediate value generator multiplexer (block 19) performs the switching between the intermediate operation convolution pipeline and the generation block based on B (input 5). For this purpose, B (input 5) is divided into 6 bit groups, overlapping by 1 bit, and fed into the control inputs of the intermediate value generator multiplexer (blocks 191-196). At the control input of multiplexer (block 191), the bit groups are shifted left by 1 bit, while at the control input of multiplexer (block 196), the sign bit is extended, resulting in the following set of four-bit inputs: control input of block 191 = 0100, control input of block 192 = 1000, control input of block 193 = 0101, control input of block 194 = 1100, control input of block 195 = 0001, and control input of block 196 = 0000. Each intermediate value coefficient corresponds to a variant of one or more binary quartets (see...). Figure 14Furthermore, the intermediate value generator multiplexer (blocks 191-196) converts the intermediate value to 32-bit format by left-shifting the value by 3 times the value of the 4-bit group number and filling the remaining most significant bits by extending the sign bit (or vice versa, in the case of 4-bit group 5, by discarding the most significant bits of the intermediate value). Therefore, the intermediate value generator multiplexer transmits the following set of intermediate value pairs to the intermediate value convolution pipeline (block 3) to the first-layer adder: adder block 31 11111111111111111110000011000000 and 111111111111111100000011000000, adder block 32 0000000000000001011101110000000 and 111111111111100000110000000000, adder block 33000000000000111110100000000000 and 00000000000000000000000000000000000000.

[0058] Furthermore, at the falling edge of the CK clock signal, the first layer adders (blocks 31-33) in the intermediate value convolution pipeline begin to add the values ​​transmitted from the intermediate value generator (block 1) in pairs. Therefore, at the output of the first layer, three intermediate 32-bit values ​​are formed, which are transmitted to the adders of the second layer: adder block 34 11111111111111111110001010110100 and 111111111111110011001110000000, adder block 35 0000000000001111101000000000000.

[0059] Furthermore, at the next leading edge of the CK clock signal, the second-layer adder (blocks 34-35) in the intermediate value convolution pipeline begins to add the intermediate values ​​passed from the previous layer in pairs. Due to the multiplication operation, the value equal to 000000000000000000000000000000000 (input 6) is fed from the arithmetic selector multiplexer (block 2) to the input of adder block 35. Therefore, at the output of the first layer, two intermediate 32-bit values ​​are formed, which are fed into adder block 36: 11111111111111001011011000110100 and 00000000000011111010000000000000. In parallel, the intermediate value generator (block 1) and the arithmetic selector multiplexer (block 2) can begin processing the next set of operands.

[0060] Furthermore, at the falling edge of the CK clock signal, the last adder (block 3) in the intermediate value convolution pipeline performs the multiplication operation by adding the last intermediate values, resulting in a result equal to 00000000000011000101011000110100 (output 9). Then, until the next rising edge (positive edge) of CK, the result will remain at the output of the intermediate value convolution pipeline.

[0061] An example of performing a combined multiplication-addition operation (MAC operation).

[0062] Assuming the multiplicand operand (input 4) equals 0000000011111010 (hereinafter referred to as A), the multiplier operand (output 5) equals 0000110010100010 (hereinafter referred to as B), the operation selection flag (input 8) equals 1, and the MAC operation operand (input 7) equals 00001010111100110000101011110011, the value of the MAC operation operand (input 7) is written to the operation selection multiplexer register (block 22).

[0063] At the leading edge of the clock signal (hereinafter referred to as CK) in the intermediate value generator (block 1), the intermediate value generation block calculates the intermediate 18-bit value from A. Therefore, block 11 generates a 4*A value equal to 000000001111101000, block 12 generates a 3*A value equal to 000000001011101110, block 13 generates a 2*A value equal to 000000000111110100, block 14 generates an A value equal to 000000000011111010, block 15 generates a negative A value equal to 111111111100000110, block 16 generates a negative 2*A value equal to 111111111000001100, block 17 generates a negative 3*A value equal to 111111110100010010, and block 18 generates a negative 4*A value equal to 111111110000011000. Instead of generating an intermediate value for coefficient 0, it multiplies it by the reference value 0 (input 6).

[0064] Concurrently, the intermediate value generator multiplexer (block 19) performs the switching between the intermediate operation convolution pipeline and the generation block based on B (input 5). For this purpose, B (input 5) is divided into 6 bit groups, overlapping by 1 bit, and fed into the control inputs of the intermediate value generator multiplexer (blocks 191-196). At the control input of multiplexer (block 191), the bit groups are shifted left by 1 bit, while at the control input of multiplexer (block 196), the sign bit is extended, resulting in the following set of four-bit inputs: control input of block 191 = 0100, control input of block 192 = 1000, control input of block 193 = 0101, control input of block 194 = 1100, control input of block 195 = 0001, and control input of block 196 = 0000. Each intermediate value coefficient corresponds to a variant of one or more binary quartets (see...). Figure 14 In addition, the intermediate value generator multiplexer (blocks 191-196) converts the intermediate value to 32-bit format by shifting the value left by 3 times the value of the 4-bit group number and filling the remaining most significant bits by extending the sign bit (or vice versa, in the case of 4-bit group 5, by discarding the most significant bits of the intermediate value). Therefore, the intermediate value generator multiplexer (block 19) transmits the following set of intermediate value pairs to the intermediate value convolution pipeline (block 3) to the adder of the first layer: adder block 31 00000000000000000000000111110100 and 111111111111111111000001100000, adder block 32 00000000000000001011101110000000 and 1111111111111100000110000000000, adder block 33 0000000000001111101000000000000 and 000000000000000000000000000000000000.

[0065] Furthermore, at the falling edge of the CK clock signal, the first layer adders (blocks 31-33) in the intermediate value convolution pipeline begin to add the values ​​transmitted from the intermediate value generator (block 1) in pairs. Therefore, at the output of the first layer, three intermediate 32-bit values ​​are formed, which are transmitted to the adders of the second layer: adder block 34 11111111111111111110001010110100 and 111111111111110011001110000000, adder block 35 0000000000001111101000000000000.

[0066] Furthermore, at the next leading edge of the CK clock signal, the second-layer adder (blocks 34-35) in the intermediate value convolution pipeline begins to add the intermediate values ​​passed from the previous layer in pairs. Due to the MAC operation, the value equal to 00001010111100110000101011110011 (input 7) is fed from the arithmetic selector multiplexer (block 2) to the input of adder block 35. Therefore, at the output of the first layer, two intermediate 32-bit values ​​are formed, which are fed into adder block 36: 11111111111111001011011000110100 and 00001011000000101010101011110011. In parallel, the intermediate value generator (block 1) and the arithmetic selector multiplexer (block 2) can begin processing the next set of operands.

[0067] Furthermore, at the falling edge of the CK clock signal, the last adder (block 3) in the intermediate value convolution pipeline performs the multiplication operation by adding the last intermediate values, resulting in a result equal to 00001010111111110110000100100111 (output 9). Then, the result will remain at the output of the intermediate value convolution pipeline until the next rising edge of CK.

[0068] Using the claimed invention, a large number of multiplication or combined multiplication-addition operations can be performed quickly in a pipelined operation mode, that is, in each operation cycle, a new set of operand values ​​is received at the input and a new result based on the old set of values ​​is generated at the output.

Claims

1. A pipelined multiplier, comprising: intermediate values A generator, the intermediate value generator being configured to receive a first operand and a second operand and be able to generate intermediate multiplication results; a "Wallace tree" intermediate value convolution pipeline for adding the obtained intermediate values ​​and obtaining the multiplication result; a multiplexer for selecting a multiplication operation or performing a combined multiplication-addition operation with a third operand, characterized in that the multiplier input operand bit capacity is 16 bits, the operation result bit capacity is 32 bits, and the MAC operation third operand bit capacity is 32 bits; blocks are configured according to a synchronization signal such that each subsequent block is operated on the reverse edge of the clock signal relative to the previous block; the intermediate value generator is based on an improved Radix 8Booth algorithm, with accelerated generation of intermediate values ​​with non-unit coefficients occurring within half a cycle, parallel generation of all intermediate value variants, and a three-layer pipeline adding six intermediate values.

2. The pipelined multiplier according to claim 1, characterized in that, The intermediate value convolution pipeline is a three-layer "Wallace tree" pipeline, in which intermediate values ​​are added in pairs to produce the result.

3. The pipelined multiplier according to claim 1, characterized in that, The generation of intermediate value variants from the multiplicand operands occurs within the intermediate value generator block.

4. The pipelined multiplier according to claim 1, characterized in that, The intermediate value generator multiplexer consists of six parallel multiplexers.

5. The pipelined multiplier according to claim 1, characterized in that, The convolution pipeline performs addition in three stages, each stage being handled by a separate set of adders.

6. The pipelined multiplier according to claim 1, characterized in that, While generating intermediate values ​​and loading them into the intermediate value convolution pipeline, the operation selection multiplexer, based on the value of the operation selection flag, writes the value of the 32-bit operand to a 32-bit register in the case of combined multiplication-addition operations, or writes "logic 0" to a 32-bit register in the case of multiplication operations, and then the register transmits the value to the intermediate value convolution pipeline.

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