Semiconductor device with thermoelectric cooler

Abstract

Semiconductor devices including thermoelectric coolers and methods of operating the semiconductor devices are described. A semiconductor device (100) includes an SOI substrate (105) having one or more components (e.g., transistors) that generate heat during operation. The semiconductor device (100) includes a thermoelectric cooler (125) surrounding the transistor. The thermoelectric cooler (125) includes a first electrode (130) laterally surrounding the transistor, a porous silicon region (140) laterally surrounding and contacting the first electrode, and a second electrode (135) laterally surrounding and contacting the porous silicon region (140). The thermoelectric cooler (125) may reduce an operating temperature of the transistor when activated. In some cases, pre-cooling may be performed to further reduce the operating temperature.

Description

Technical Field

[0001] This specification relates to the field of semiconductor devices, and more specifically to semiconductor devices having thermoelectric coolers. Background Art

[0002] Some semiconductor devices (e.g., power transistors) generate heat during their operation, and managing the heat emitted from semiconductor devices is challenging. Power transistors using semiconductor-on-insulator (SOI) technology offer superior electrical characteristics compared to power transistors built on a bulk substrate, such as lower parasitic capacitance due to isolation from the bulk substrate, latch-up resistance due to the fully isolated n-well and p-well structures, and lower leakage current characteristics. However, power transistors built on SOI substrates face challenges associated with weaker heat dissipation, as heat tends to be confined within a relatively thin semiconductor layer rather than dissipated through the bulk substrate. Summary of the Invention

[0003] This specification relates to semiconductor devices comprising semiconductor thermoelectric coolers. This summary is not an exhaustive overview of the specification. In fact, the main purpose of this summary is to present some concepts in a simplified form as a prelude to the more detailed description that follows.

[0004] In some examples, a semiconductor device includes: a substrate having a dielectric layer and a semiconductor layer thereon; a first electrode that laterally surrounds a first region of the semiconductor layer; a second region of the semiconductor layer that laterally surrounds and contacts the first electrode; and a second electrode that laterally surrounds and contacts the second region of the semiconductor layer.

[0005] In some examples, a semiconductor device includes: a substrate having a dielectric layer and a semiconductor layer thereon; an array of first electrodes, each of the first electrodes laterally surrounding a corresponding first region of the semiconductor layer; a second region of the semiconductor layer laterally surrounding and contacting each of the first electrodes in the array; and a second electrode laterally surrounding and contacting the second region of the semiconductor layer.

[0006] In some examples, a method includes: applying an electrical bias to a first electrode that laterally surrounds a first region of a semiconductor layer, the first region containing one or more semiconductor components that generate heat during operation; and activating the one or more semiconductor components after the electrical bias is applied to the first electrode, wherein the semiconductor layer is disposed on an oxide layer of a substrate, a second region of the semiconductor layer laterally surrounds and contacts the first electrode, and a second electrode laterally surrounds and contacts the second region of the semiconductor layer. Attached Figure Description

[0007] Figures 1A to 1D Aspects of a semiconductor device having a thermoelectric cooler are shown in the examples in this specification;

[0008] Figure 2A and 2B A plan view of a semiconductor device with a thermoelectric cooler is shown in an example of this specification;

[0009] Figures 3A to 3C A diagram illustrating the operating characteristics of a semiconductor device with a thermoelectric cooler, as shown in the examples in this specification;

[0010] Figures 4A to 4C Aspects of an array of semiconductor devices having thermoelectric coolers are shown in examples of this specification; and

[0011] Figures 5A to 5C A diagram illustrating the operating characteristics of an array of semiconductor devices having thermoelectric coolers, as shown in the examples in this specification. Detailed Implementation

[0012] This specification is provided with reference to the accompanying drawings. The components in the drawings are not drawn to scale. The emphasis is on clearly illustrating the general features and principles of this specification. Examples in the drawings illustrate numerous specific details and relationships to provide an understanding of this specification. The drawings and examples are not intended to limit the scope of this specification to such examples, and other examples are possible by means of interchange or modification of at least some of the described or illustrated elements. Furthermore, where elements of this specification can be partially or completely implemented using known components, certain portions of such components that facilitate an understanding of this specification are described, and detailed descriptions of other portions of such components are omitted to avoid obscuring this specification.

[0013] As used herein, terms such as “first” and “second” are used to distinguish elements described by such terms. Therefore, these terms in this specification and claims do not indicate a temporal or other priority order of such elements. Furthermore, in consideration of the orientations shown in the figures, terms such as “front,” “back,” “top,” “bottom,” “above,” “below,” “vertical,” “horizontal,” “lateral,” “downward,” “upward,” “upper,” “lower,” etc., are used to refer to the relative orientation or position of features in a semiconductor device. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than other features. Such terms are interchangeable where appropriate so that examples of the techniques described herein can operate, for example, in orientations other than those shown or otherwise described herein. In the following description and claims, the terms “including,” “includes,” “having,” “has,” “with,” or variations thereof are inclusive in a manner similar to the term “comprising,” and are therefore interpreted as meaning “including, but not limited to.” Unless otherwise stated, in some examples, “about,” “roughly,” or “generally” preceding a value means + / - 10% of the stated value. In some examples, “about,” “roughly,” or “generally” preceding a value means + / - 20% of the stated value.

[0014] The various structures described herein can be formed using semiconductor process technologies. Layers comprising multiple materials can be formed over a substrate (e.g., a semiconductor wafer) using deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitriding, epitaxy), and / or other suitable techniques. Similarly, portions of the layers can be selectively removed, for example, using etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and / or other suitable techniques, some of which can be combined with photolithography steps. The electrical conductivity (or resistivity) of the substrate (or regions of the substrate) can be controlled by doping techniques using various chemical substances (which may also be referred to as dopants, dopant atoms, etc.), including but not limited to boron, gallium, indium, arsenic, phosphorus, or antimony. Doping can be performed during the initial formation or growth of the substrate (or epitaxial layer grown on the substrate) by ion implantation or other suitable doping techniques.

[0015] The increasing demand for high-performance semiconductor devices makes it attractive to fabricate semiconductor components (e.g., transistors) in semiconductor-on-insulator (SOI) substrates. An SOI substrate comprises a dielectric layer (e.g., an oxide layer) on a bulk semiconductor substrate and a semiconductor layer on top of the dielectric layer. In some examples, the semiconductor layer is a silicon layer and may be referred to as a silicon epitaxial layer, silicon epi-layer, device layer, etc. The dielectric layer can be considered as being “buried” beneath the semiconductor layer and may be referred to as a buried oxide (BOX) layer. A transistor constructed in an SOI substrate (e.g., within a semiconductor layer of an SOI substrate) may be referred to as an SOI transistor (or an SOI-based device). The BOX layer separates the semiconductor layer from the bulk semiconductor substrate, and SOI transistors can have reduced leakage current and enhanced electrostatic properties (e.g., reduced parasitic capacitance), at least in part, due to this separation, resulting in higher switching speeds and lower power consumption compared to similar transistors constructed in a bulk semiconductor substrate. However, the dielectric layer has poor thermal conductivity, which may hinder the heat dissipation generated in SOI transistors and may lead to self-heating problems.

[0016] This specification generally, but not exclusively, relates to promoting heat dissipation in semiconductor components (e.g., SOI transistors, SOI power transistors) constructed in SOI substrates and reducing temperatures within semiconductor components by utilizing thermoelectric cooling concepts. An SOI transistor may be surrounded by a thermoelectric cooler (TEC) that laterally dissipates heat from the SOI transistor. The TEC includes a first electrode proximate to the SOI transistor and a second electrode positioned away from the SOI transistor (and away from the first electrode). Furthermore, the TEC includes a portion of the semiconductor layer of the SOI substrate disposed between the first and second electrodes, wherein a plurality of cavities (e.g., an array of through-silicon vias) are formed. Individual cavities (e.g., holes) may extend throughout the semiconductor layer and terminate on a dielectric layer.

[0017] The portion of the semiconductor layer containing the silicon through-hole array (which may be referred to as porous silicon or a porous silicon structure) is combined with the first and second electrodes under appropriate bias conditions (e.g., when activated by applying a bias voltage to the first electrode relative to the second electrode) to function as a thermoelectric cooler (TEC). Trench etching processes or modified trench etching processes can be used to create the silicon through-hole array in the semiconductor layer of the SOI substrate. In some examples, the silicon through-holes may be filled with a dielectric material (or other suitable material). The dielectric-filled silicon through-holes can modify the heat transfer properties of the portion of the semiconductor layer (e.g., the porous silicon structure), for example, to facilitate heat transfer from the SOI transistor. Furthermore, the semiconductor layer may contain n-type dopants (e.g., arsenic, phosphorus) or p-type dopants (e.g., boron).

[0018] A TEC (e.g., a first electrode, a porous silicon structure with an array of trenches / holes, and a second electrode) may surround one or more SOI-based devices, such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors. In some examples, an array of SOI power devices (e.g., a power device array) may be formed with individual SOI power devices surrounded by corresponding porous silicon structures (e.g., TECs). One or more TECs may be selectively activated to reduce the temperature of one or more power devices in the power device array fabricated in the SOI substrate (e.g., cooling individual power devices), thereby improving the temperature uniformity of the entire power device array and / or reducing the overall temperature of the power device array. In some examples, a pre-cooling sequence (or duration) may be applied before turning on (activating) the LDMOS transistors, for example, to further enhance the temperature reduction.

[0019] By dynamically switching on the TEC at one or more locations by controlling the current / voltage pulses applied to the TEC (in some cases with a pre-cooling duration), the temperature in a power device array can be reduced. In this way, the overall temperature of the entire power device array can be reduced, for example, below the critical temperature for safe operation of the power device array, such as the Tcrit that could trigger thermal runaway and lead to permanent device failure. Therefore, the TEC mitigates the challenges associated with SOI substrates due to their poor thermal dissipation characteristics, enabling the construction of power devices in SOI substrates for high-power applications, such as those involving transient events.

[0020] Various examples are then described. While specific examples may illustrate aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below).

[0021] Figures 1A to 1D Aspects of a semiconductor device having a thermoelectric cooler are shown in the examples in this specification. Figure 1A A plan view of the semiconductor device 100 is shown. Figure 1B It shows along Figure 1A The image shows a cross-sectional view of a semiconductor device 100, taken by line AA'. The semiconductor device 100 includes a substrate 105 (e.g., bulk silicon), a dielectric layer 110 on the substrate 105, and a semiconductor layer 115 on the dielectric layer 110. This semiconductor layer may also be referred to as an epitaxial layer, epi-layer, device layer, etc. In some examples, the dielectric layer 110 has a thickness ranging from 0.1 μm to 20 μm. Figure 1B(represented as T_BOX). In some examples, the semiconductor layer 115 has a thickness ranging from 30 μm to 300 μm (in... Figure 1B (represented as T_DEV). In other examples, semiconductor layer 115 has a thickness of less than 30 μm. Semiconductor layer 115 may contain n-type or p-type dopants. In some examples, semiconductor layer 115 has a thickness ranging from 1 × 10⁻⁶ μm. 18 cm -3 With 1×10 21 cm -3 The p-type (or n-type) doping concentration between.

[0022] Furthermore, the semiconductor device 100 includes a first region 120 of a semiconductor layer 115, and one or more semiconductor components are located in the first region. The one or more semiconductor components generate heat during their operation. The first region has a dimension 122. In some examples, the dimension 122 (e.g., width) ranges from approximately 10 μm to 500 μm. In some examples, the one or more semiconductor components include a laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a hot spot 121. In some examples, the hot spot 121 may have a size ranging from approximately 1 μm to 100 μm. In other examples, the hot spot 121 has a size less than 1 μm. The hot spot 121 may correspond to the channel region of a transistor (e.g., an LDMOS transistor), where strong power dissipation can occur, resulting in localized hot spots (e.g., hot spot 121).

[0023] Semiconductor device 100 includes a first electrode 130 that laterally surrounds a first region 120 (which may also be referred to as a device region) of semiconductor layer 115, such as... Figure 1A As shown in the diagram. The first electrode 130 extends from a plane coplanar with the surface 116 of the semiconductor layer 115 to the dielectric layer 110, as... Figure 1B As shown in the diagram. The first electrode 130 has a width of 131. In some examples, the first electrode 130 comprises a conductive material, such as a silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide), tungsten, aluminum, copper, titanium, tantalum, or a suitable conductive material available in a semiconductor manufacturing environment. The semiconductor device 100 includes a second region 140 of a semiconductor layer 115 that laterally surrounds and contacts the first electrode 130. The second region 140 has, as shown in the diagram. Figure 1A The width 141 shown in the figure represents, for example, the shortest distance between the first electrode 130 and the second electrode 135.

[0024] Furthermore, the semiconductor device 100 includes a second electrode 135 that laterally surrounds and contacts a second region 140 of the semiconductor layer 115, such as... Figure 1AAs shown in the diagram. The second electrode 135 has a width of 136. Like the first electrode 130, the second electrode 135 extends from a plane coplanar with the surface 116 of the semiconductor layer 115 to the dielectric layer 110, as shown in the diagram. Figure 1B As shown in the illustration. In some examples, the second electrode 135 comprises a conductive material, such as a silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide), tungsten, aluminum, copper, titanium, tantalum, or a suitable conductive material available in a semiconductor manufacturing environment. In some examples, the first electrode 130 and the second electrode 135 comprise the same conductive material. In some examples, the first electrode 130 and the second electrode 135 comprise different conductive materials.

[0025] The second region 140 of the semiconductor layer 115 includes a plurality of cavities 145 (e.g., holes, openings, pores), such as Figure 1B As shown in the diagram. Each cavity 145 extends from a plane coplanar with the surface 116 of the semiconductor layer 115 to the dielectric layer 110, as... Figure 1B As shown in the figure. In some examples, one or more cavities 145 may have a circular, rectangular or oblong shape covering area (e.g., cross-sectional area in a plane parallel to the surface 116 of the semiconductor layer 115).

[0026] Figure 1C A perspective view of a portion of the second region 140 (e.g., a porous silicon region) is shown. Figure 1C In the example, the second region 140 contains holes 145. As described above, each hole 145 extends through the semiconductor layer 115, for example, through a thickness T_DEV, as... Figure 1C (and Figure 1B As shown in [reference needed]. The distance 146 between the holes 145 can be referred to as the neck distance. In some examples, the holes 145 can be arranged (e.g., tightly packed) to form a hexagon when viewed from a plan view, such as... Figure 1C The holes 145 are marked with dashed lines. In some examples, the holes 145 are filled with one or more dielectric materials. The overall distribution of the holes 145 (e.g., the areal density of the holes 145) can determine the porosity of the second region 140 of the semiconductor layer 115, such as the ratio between the total volume of the cavities and the volume of the semiconductor layer 115 in which the cavities are distributed. In some examples, the porosity of the second region 140 of the semiconductor layer 115 can vary between approximately 10% and 70%.

[0027] Various parameters associated with the second region 140 of the semiconductor layer 115 (e.g., a porous silicon structure) can be determined to obtain the desired thermal and electrical properties of the TEC 125. Such parameters may include T_DEV, n-type or p-type doping concentration, neck distance 146 between holes 145, diameter 147 of holes 145, porosity, dielectric material filling holes 145, width 141 of the second region 140 (e.g., the width of the porous silicon region surrounding hot spots), etc. In some examples, the second region 140 of the semiconductor layer 115 may have an in-plane thermal conductivity of approximately 0.5 W / mK to 2 W / mK. In some examples, the second region 140 of the semiconductor layer 115 may have a transplanar thermal conductivity of approximately 5 W / mK to 25 W / mK. In some examples, the second region 140 of the semiconductor layer 115 may have an in-plane thermal conductivity of approximately 5 × 10⁻⁶ W / mK. 3 S / m to 5×10 4 Effective conductivity S / m.

[0028] Figure 1D The semiconductor device 100 during operation is shown. That is, an electrical bias voltage (such as) is applied to the first electrode 130 relative to the second electrode 135. Figure 1D The Vbias shown in the figure. As a result of the applied electrical bias, the current (in Figure 1D The current flows from the first electrode 130 to the second electrode 135, denoted as I). In some examples, a temperature gradient is established between the first electrode 130 and the second electrode 135, for example, due to the Peltier effect triggered at the metal-semiconductor junction. In other words, the temperature T1 at the first electrode 130 can be lower than the temperature T2 at the second electrode 135. Therefore, the first electrode 130 can be referred to as a Peltier cooler (cooler electrode, cooler terminal), and the second electrode 135 can be referred to as a Peltier heater (heater electrode, heater terminal).

[0029] As a result of the applied bias voltage, heat (in) Figure 1D (represented by q) flows from the first electrode 130 to the second electrode 135, as shown in the figure. Figure 1D As shown in the diagram. In this way, the TEC 125 can transport heat energy emitted from the hot spot 121 (through the cooler first electrode 130 located near the hot spot 121) to a location away from the hot spot 121. In other words, the cooler environment surrounding the hot spot 121 provided by the first electrode 130 of the TEC 125 helps to lower the temperature of the hot spot 121. Therefore, heat transport can be considered as pushing heat from the hot spot 121 to the peripheral area surrounding the hot spot 121, for example, pushing it to the second electrode 135 through the second region 140.

[0030] Figure 2A and 2BA plan view of a semiconductor device with a thermoelectric cooler is shown in the example of this specification. Figure 2A A semiconductor device 205 incorporating various aspects of a semiconductor device 100 is shown, including, for example, a device region 120 containing a hot spot 121, a first electrode 130, and a second electrode 135. The semiconductor device 205 includes a porous silicon region 241 located between the first electrode 130 and the second electrode 135. The porous silicon region 241 includes an array of holes 145. Furthermore, the first electrode 130 and the second electrode 135 contact the porous silicon region 241 at corresponding locations, thereby forming a metal-semiconductor junction, for example, a colder junction at the interface between the first electrode 130 and the porous silicon region 241, and a warmer junction at the interface between the second electrode 135 and the porous silicon region 241. The porous silicon region 241 of the semiconductor device 205 includes holes 145 having uniform areal density (and porosity), the same size (same diameter), and the same neck distance.

[0031] In other examples, porous silicon regions can have the same characteristics as... Figure 2A The porous silicon regions 241 have different configurations. For example, Figure 2B A semiconductor device 210 comprising aspects of a semiconductor device 100 is shown, including, for example, a device region 120 including a hot spot 121, a first electrode 130, and a second electrode 135. The semiconductor device 210 includes a porous silicon region 242 located between the first electrode 130 and the second electrode 135. The porous silicon region 242 is shown having pores with varying areal densities, for example, a higher density of pores (higher porosity) near the first electrode 130 and a lower density of pores (lower porosity) near the second electrode 135, such as… Figure 2B As shown in the figure. In some examples, the porous silicon region 242 may contain a higher density of pores (higher porosity) near the second electrode 135 and a lower density of pores (lower porosity) near the first electrode 130. In some examples, the pores may have different sizes (diameters) or different distances between them.

[0032] Figures 3A to 3C A diagram illustrating the operating characteristics of a semiconductor device with a thermoelectric cooler, as shown in the examples in this specification.

[0033] Figure 3A Electrical pulses (or signals) 310 and 320 as functions of time are shown, in which... Figure 3AThe horizontal axis represents time in seconds. Electrical pulse 310 (e.g., voltage pulse, current pulse) can be an electrical pulse applied to one or more semiconductor components (e.g., LDMOS transistors) in device region 120 of semiconductor device 100 (or semiconductor devices 205, 210), and may be referred to as an LDMOS pulse. Electrical pulse 320 (e.g., voltage pulse, current pulse) can be an electrical pulse applied to TEC 125 (e.g.,... Figure 1D The Vbias described in the text can be referred to as the TEC pulse. Figure 3A The temperature distribution curves 315 and 325, as a function of time, are further shown in the figure.

[0034] For example, by applying an LDMOS pulse 310 to the LDMOS transistor, the LDMOS transistor in device region 120 can be turned on at time T1 and turned off at time T2. Temperature profile 315 can represent the temperature at or near hot spot 121 (e.g., the channel region of the LDMOS transistor) without activating TEC 125. When the LDMOS transistor operates in response to the LDMOS pulse 310, temperature profile 315 can exceed 200°C.

[0035] In contrast, temperature profile 325 can represent the temperature at or near hot spot 121 (e.g., the channel region of an LDMOS transistor) when TEC 125 is activated (i.e., by applying a TEC pulse 320 to TEC 125 (e.g., applying Vbias to TEC using a TEC pulse)), as referenced. Figure 1D As described. More specifically, the TEC pulse 320 is applied to TEC 125 approximately at time T1 when the LDMOS pulse 310 is applied to the LDMOS transistor. As a result of activating TEC 125, the peak temperature of the temperature profile 325 is significantly reduced to below 200°C. The difference in peak temperature between applying and not applying the TEC pulse 320 to TEC 125 can be approximately 68°C, as... Figure 3A As shown in the image.

[0036] Figure 3BThe effect of activating the TEC (e.g., TEC 125) before activating the LDMOS transistor in the activation device region 120 is illustrated. For example, LDMOS pulses 330, 340, 350, and 360 represent electrical (e.g., voltage or current) pulses applied to the LDMOS transistor at times Ta, Tb, Tc, and Td, respectively. The durations of the LDMOS pulses 330, 340, 350, and 360 are approximately the same. The various results described below demonstrate the benefits of activating the TEC before activating the LDMOS transistor, such as a pre-cooling effect. In some examples, the cooling flux generated by the TEC (e.g., the cooler temperature established at the first electrode 130 or Peltier cooler electrode 130) may take time to diffuse to the hot spot 121. Therefore, pre-cooling can be applied to overcome the delay associated with the diffusion of cooling flux in a rapid thermoelectric cooling environment, such as activating TEC 125 before activating the LDMOS transistor.

[0037] The TEC pulse 335 combined with the LDMOS pulse 330 represents the first condition, where the TEC is not activated when the LDMOS pulse 330 is applied at time Ta (e.g., the TEC pulse 335 is flat). Figure 3B The peak temperature (e.g., the hotspot temperature of an LDMOS transistor) is shown to reach 465°C under the first condition.

[0038] The TEC pulse 345 combined with the LDMOS pulse 340 represents the second condition, where the TEC is activated at time Tpc when the LDMOS pulse 340 is applied at a later time Tb. More specifically, TEC125 is activated slightly less than 100 μs before the LDMOS transistor is activated. Figure 3B The peak temperature (e.g., the hot spot temperature of an LDMOS transistor) can be reached at 439°C under the second condition, which is 26°C lower than under the first condition.

[0039] The TEC pulse 355 combined with the LDMOS pulse 350 represents a third condition, where the TEC is activated at time Tpc when the LDMOS pulse 350 is applied at a later time Tc. More specifically, TEC125 is activated slightly less than 200 μs before the LDMOS transistor is activated. Figure 3B The peak temperature (e.g., the hot spot temperature of an LDMOS transistor) can be reached at 433°C under the third condition, which is 32°C lower than under the first condition.

[0040] The TEC pulse 365 combined with the LDMOS pulse 360 ​​represents the fourth condition, where the TEC is activated at time Tpc when the LDMOS pulse 360 ​​is applied at a later time Td. More specifically, the TEC125 is activated slightly less than 300 μs before the LDMOS transistor is activated. Figure 3BThe peak temperature (e.g., the hotspot temperature of an LDMOS transistor) can be reached at 431°C under the fourth condition, which is 34°C lower than under the first condition. Figure 3B As demonstrated, the pre-cooling effect (e.g., by activating the TEC before activating the semiconductor device surrounded by the TEC) can help reduce the peak temperature of the semiconductor device during operation.

[0041] Figure 3C The effects of activating the TEC (e.g., TEC 125) before activating the semiconductor device (e.g., LDMOS transistor) in the device region 120 are also illustrated, such as a pre-cooling effect. For example, LDMOS pulses 370a to 370e represent electrical (e.g., voltage or current) pulses applied to the LDMOS transistor at different times relative to the TEC pulse 375 applied to TEC 125. The various results described below demonstrate the benefits of activating the TEC before activating the LDMOS transistor (e.g., pre-cooling), such as compensating for the delay associated with cooling flux diffusion as described above.

[0042] For example, LDMOS pulse 370a represents the condition for TEC activation approximately at the time when LDMOS pulse 370a is applied. (See reference...) Figure 3A As described, when comparing the peak temperature without TEC activation, simultaneous activation of TEC is expected to reduce the peak temperature of the semiconductor device (e.g., an LDMOS transistor). However, temperature profile 380a associated with LDMOS pulse 370a shows that the reduction in peak temperature is relatively smaller than under other conditions where TEC pulse 375 precedes LDMOS pulses (e.g., LDMOS pulses 370b to 370e). For example, LDMOS pulse 370c and the associated temperature profile 380c show that when TEC pulse 375 precedes LDMOS pulse 370c (e.g., TEC is activated before the LDMOS transistor is activated), the desired reduction in peak temperature may be more significant. (See reference...) Figures 3A to 3C As described, the TEC pulse can include rectangular pulses, triangular pulses, and any other pulse shape designed to reduce peak temperature (e.g., sawtooth pulses, stepped pulses), or combinations thereof.

[0043] Figures 4A to 4C Aspects of an array of semiconductor devices having thermoelectric coolers are shown in the examples in this specification. Figure 4A Showing included Figure 4B Semiconductor device 405 is an array of semiconductor devices 410. Semiconductor device 410 includes aspects of semiconductor device 100 (or semiconductor devices 205, 210).

[0044] Figure 4AExample semiconductor device 405 includes a total of twenty-five (25) semiconductor devices 410 arranged in a 5×5 array. Figure 4B A single semiconductor device 410 is shown, comprising a device region 120 having a hot spot 121, a first electrode 130 laterally surrounding the device region 120, and a porous silicon region 441 laterally surrounding and contacting the first electrode 130. Although Figure 4B The semiconductor device 410 is shown as having a porous silicon region 441 with uniform porosity (e.g., uniform pore surface density) throughout, but this specification is not limited thereto. For example, the porous silicon region 441 may have a gradually decreasing pore density as the distance from the first electrode 130 increases. In other examples, the porous silicon region 441 may have a gradually increasing pore density as the distance from the first electrode 130 increases.

[0045] The difference between an individual semiconductor device 410 and semiconductor device 100 in the semiconductor device array is that the second electrode 135 of semiconductor device 100 is omitted in each of the individual semiconductor devices 410. In fact, the second electrode 435 laterally surrounds the entire array of semiconductor devices 410, as... Figure 4A As shown in the diagram. The second electrode 435 can be considered as a common electrode (e.g., a common Peltier heater electrode) combined with the individual first electrodes 130 of the semiconductor device 410. In this way, the area efficiency of the semiconductor device 405 (e.g., an array of semiconductor devices 410) can be improved, for example, when compared to a similar array of semiconductor devices 100, each of which has its own second electrode 135. Figure 4A As shown, each of the device regions 120 in the array is laterally surrounded by a TEC, which includes a Peltier cooler electrode (e.g., a corresponding first electrode 130) close to the hot spot 121 and a Peltier heater electrode (e.g., a common second electrode 435) positioned away from the corresponding hot spot 121.

[0046] In other words, the semiconductor device 405 includes an array of first electrodes 130 (e.g., a total of twenty-five (25) first electrodes 130 arranged in a 5×5 array), and each of the first electrodes 130 laterally surrounds a corresponding first region (e.g., device region 120) of a semiconductor layer (e.g., semiconductor layer 115). The semiconductor device 405 also includes a second region of the semiconductor layer (e.g., porous silicon region 441) that laterally surrounds and contacts each of the array of first electrodes 130. Furthermore, the semiconductor device 405 includes a second electrode (e.g., second electrode 435) that laterally surrounds and contacts the second region 441 of the semiconductor layer.

[0047] In some examples, each of the first regions of the semiconductor layer (e.g., device region 120) includes one or more semiconductor devices (e.g., laterally diffused metal-oxide-semiconductor (LDMOS) transistors). Each of the first electrodes 130 can extend from a plane coplanar with the surface of the semiconductor layer to the dielectric layer, e.g., reference... Figure 1B The dielectric layer 110 is described. Furthermore, a second electrode can extend from a plane to the dielectric layer. A second region (e.g., a porous silicon region 140) of the semiconductor device 405 includes a plurality of cavities, and each of the plurality of cavities can extend from a plane coplanar with the surface of the semiconductor layer to the dielectric layer.

[0048] Figure 4C It was shown as Figure 4A An alternative embodiment of semiconductor device 405 is semiconductor device 415. Like semiconductor device 405, semiconductor device 415 includes individual semiconductor devices (e.g., Figure 4B The semiconductor device 415 is a 5×5 array of semiconductor devices 410. The difference between semiconductor device 415 and semiconductor device 405 is that the semiconductor layer disposed between the first electrode 130 and the second electrode 435 includes a first region 450 distributed throughout the semiconductor device 415, such as... Figure 4C As shown in the image. Zone 450 has [the following features]. Figure 4C The first width is denoted as "W1". Furthermore, the second region 455 (e.g., a porous silicon region) of the semiconductor layer located between the first region 450 and the individual Peltier cooler electrodes (e.g., the first electrode 130) has... Figure 4C The second width is denoted as "W2". In some examples, the first region 450 does not contain holes (e.g., hole 145). That is, in such examples, the first region 450 may not contain holes (or cavities). In other examples, the first region 450 may contain holes with a smaller areal density than the second region 455, for example, the areal density of the first region 450 is less than the areal density of the holes near the first electrode 130. In some examples, the first and second widths (W1 and W2) can be determined to obtain desired thermal and electrical characteristics of the semiconductor device 415. In some examples, holes with varying areal densities can alleviate certain semiconductor processing complexities associated with forming holes over an extended region of the semiconductor layer (e.g., trench etching processes).

[0049] Figures 5A to 5C A semiconductor device with a thermoelectric cooler is shown as an example in this specification (e.g., reference). Figure 4A A diagram illustrating the operating characteristics of the array of semiconductor devices 405 described. Figures 5A to 5C Multi-level selective activation of the TEC in semiconductor device 405 is illustrated, for example, by selectively applying one or more Vbias to the first electrode 130 of the array. Figures 5A to 5CIn the example, the selected (activated) first electrode 130 is represented by crossshading using different patterns corresponding to different voltages (e.g., V1 to V6). The unselected (inactive) first electrode 130 does not have a crossshading pattern. The common second electrode 435 remains at ground potential (e.g., VGND).

[0050] Selectively activating different portions of the TEC of the semiconductor device 405 by selectively applying different voltages to the array of first electrodes 130 can reduce the peak / maximum temperature and overall temperature distribution of the semiconductor device 405. In some examples, the effect of activating the first electrodes 130 in the array of first electrodes 130 can be considered as “draining heat” from the target device region 120 associated with the activated first electrodes 130. In other words, cooling the target device region 120 can transfer heat to the surrounding region. The surrounding region can be cooled by transferring heat toward the outer boundary of the semiconductor device 405 to the next surrounding region. In other words, by determining the different voltages applied to the first electrodes 130, the overall heat transfer can be designed to occur toward a common second electrode 435 laterally positioned away from the array of device regions 120, as described in more detail below.

[0051] For example, Figure 5A A first bias pattern 501 is shown, such that the first electrode located at the center (center electrode, center TEC) is biased at V1, and the first electrode immediately adjacent to (surrounding) the center electrode is biased at V2, which is less than V1. The remaining first electrodes are not biased (not activated). The peak temperature of the semiconductor device 405 under the first bias pattern 501 is about 22°C lower than the peak temperature associated with no activated TEC (e.g., the baseline bias pattern). Furthermore, the peak-to-peak temperature distribution within the semiconductor device 405 (e.g., the difference between the hottest and coldest temperatures) decreases from about 67°C (under the baseline bias pattern) to about 40°C (under the first bias pattern 501).

[0052] Figure 5B A second bias pattern 502 is shown, such that the first electrode located at the center (center electrode, center TEC) is biased at V1, and the first electrode vertically or horizontally adjacent to the center electrode is biased at V2, which is less than V1. Furthermore, the first electrode diagonally adjacent to the center electrode is biased at V3, which is less than V2. In other words, V2 and V3 are determined based on the distance of the corresponding first electrode from the center electrode. The remaining first electrodes are not biased (not activated). The peak temperature of the semiconductor device 405 under the second bias pattern 502 is approximately 27°C lower than the peak temperature of the baseline bias pattern. Furthermore, the peak-to-peak temperature distribution within the semiconductor device 405 (e.g., the difference between the hottest and coldest temperatures) decreases from approximately 67°C (under the baseline bias pattern) to approximately 35°C (under the second bias pattern 502).

[0053] Figure 5C A third bias pattern 503 is shown, such that the first electrode located at the center (center electrode, center TEC) is biased at V1, and the remaining first electrodes are biased based on their distance from the center electrode, i.e., V2 < V1, V3 < V2, V4 < V3, V5 < V4, and V6 < V5. All first electrodes are biased (activated). The peak temperature of the semiconductor device 405 under the third bias pattern 503 is about 35°C lower than the peak temperature of the baseline bias pattern. Furthermore, the peak-to-peak temperature distribution within the semiconductor device 405 (e.g., the difference between the hottest and coldest temperatures) decreases from about 67°C (under the baseline bias pattern) to about 10°C (under the third bias pattern 503).

[0054] In an n×n array where n is an integer greater than 1 (or an n×m array where n and m are integers and n is different from m), the voltage applied to the center electrode (or the central first electrode located in the central region of the array) can be the largest, while the voltage applied to the remaining first electrodes gradually decreases based on their distance from the center electrode. In other words, the voltage can be designed to gradually (or continuously) decrease towards the cooler electrodes located at the edges or corners of the array. Furthermore, although the cooling effect may be proportional to the applied voltage (e.g., the higher the voltage, the stronger the cooling effect), it may be necessary to maintain a balance between Peltier cooling and Joule heating (due to current flow through the porous silicon region).

[0055] The examples described above are by way of illustration only and not limitation. Many changes may be made to the examples in this specification without departing from the spirit or scope thereof. For example, although the above references... Figures 4A to 5CThe described examples include a 5×5 array of semiconductor device 410, but this specification is not limited thereto. In some examples, the semiconductor device may include a 1×2 array, a 1×3 array, a 2×2 array, a 3×3 array, or even a 10×20 array, etc. Furthermore, although the example semiconductor devices (e.g., semiconductor devices 100, 205, 210, 410) have a square shape, this specification is not limited thereto. For example, a semiconductor device including a TEC may have a rectangular shape, a pentagonal shape, a hexagonal shape, or any polygonal shape. In some cases, an LDMOS transistor (or a semiconductor component subject to the risk of self-heating during operation) may have a circular shape or a racetrack-like shape. Therefore, in such cases, a semiconductor device having a TEC surrounding an LDMOS transistor may have a circular shape or a racetrack shape. In addition to cooling SOI transistors, the concept of a TEC based on the porous silicon structure described herein can be applied to other SOI-based semiconductor components, such as SOIFinFETs and SOI gate-all-around (GAA) FETs.

[0056] Furthermore, while various features or components have been shown to have a particular arrangement or configuration in the illustrated embodiments, other arrangements and configurations are also possible. Moreover, aspects of the inventive technology described in the context of the exemplary embodiments may be combined or eliminated in other embodiments. Therefore, the breadth and scope of this specification are not limited to any of the embodiments described above.

Claims

1. A semiconductor device comprising: A substrate comprising a dielectric layer and a semiconductor layer thereon; The first electrode laterally surrounds the first region of the semiconductor layer; The second region of the semiconductor layer laterally surrounds and contacts the first electrode; as well as The second electrode laterally surrounds and contacts the second region of the semiconductor layer.

2. The semiconductor device of claim 1, wherein the first region of the semiconductor layer includes one or more semiconductor components that generate heat during operation.

3. The semiconductor device of claim 2, wherein the one or more semiconductor components comprise laterally diffused metal-oxide-semiconductor (LDMOS) transistors.

4. The semiconductor device according to claim 1, wherein: The first electrode extends from a plane coplanar with the surface of the semiconductor layer to the dielectric layer; and The first electrode contains a conductive material surrounding the first region of the semiconductor layer.

5. The semiconductor device of claim 4, wherein the conductive material comprises at least one of silicide, tungsten, aluminum, copper, titanium, and tantalum.

6. The semiconductor device of claim 1, wherein the second region of the semiconductor layer comprises a plurality of cavities, each of the plurality of cavities extending from a plane coplanar with the surface of the semiconductor layer to the dielectric layer.

7. The semiconductor device of claim 6, wherein one or more of the plurality of cavities have a coverage area in the shape of a circle, rectangle or oblong.

8. The semiconductor device of claim 6, wherein the second region of the semiconductor layer comprises: The first part has a first plurality of cavities, the first plurality of cavities having a first areal density; and The second part has a second plurality of cavities, the second plurality of cavities having a second areal density different from the first areal density.

9. The semiconductor device according to claim 1, wherein: The second electrode extends from a plane coplanar with the surface of the semiconductor layer to the dielectric layer; and The second electrode contains a conductive material that contacts the second region of the semiconductor layer.

10. The semiconductor device of claim 9, wherein the conductive material comprises at least one of silicide, tungsten, aluminum, copper, titanium, and tantalum.

11. A semiconductor device comprising: A substrate comprising a dielectric layer and a semiconductor layer thereon; An array of first electrodes, each of which laterally surrounds a corresponding first region of the semiconductor layer; The second region of the semiconductor layer laterally surrounds and contacts each of the first electrodes of the array; as well as The second electrode laterally surrounds and contacts the second region of the semiconductor layer.

12. The semiconductor device of claim 11, wherein each of the respective first regions of the semiconductor layer comprises one or more laterally diffused metal-oxide-semiconductor (LDMOS) transistors.

13. The semiconductor device according to claim 11, wherein: Each of the first electrodes extends from a plane coplanar with the surface of the semiconductor layer to the dielectric layer; and The second electrode extends from the plane to the dielectric layer.

14. The semiconductor device of claim 11, wherein the second region of the semiconductor layer comprises a plurality of cavities, each of the plurality of cavities extending from a plane coplanar with the surface of the semiconductor layer to the dielectric layer.

15. A method comprising: An electrical bias is applied to a first electrode that laterally surrounds a first region of a semiconductor layer, the first region containing one or more semiconductor components that generate heat during operation; as well as The one or more semiconductor components are activated after the electrical bias is applied to the first electrode, wherein: The semiconductor layer is disposed on the oxide layer of the substrate; The second region of the semiconductor layer laterally surrounds and contacts the first electrode; and The second electrode laterally surrounds and contacts the second region of the semiconductor layer.

16. The method of claim 15, wherein current flows from the first electrode to the second electrode due to the applied bias voltage.

17. The method of claim 15, wherein heat flows from the first electrode to the second electrode due to the application of the electrical bias voltage.

18. The method of claim 15, wherein the electrical bias comprises a rectangular pulse, a triangular pulse, a sawtooth pulse, or a combination thereof.

19. The method of claim 15, further comprising: The electrical bias is maintained when the one or more semiconductor components are activated.

20. The method of claim 15, further comprising: The electrical bias is terminated when one or more semiconductor components are activated.

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