Low dropout regulator integrated on four-loop chip

Abstract

The invention provides a four-loop on-chip integrated low dropout linear regulator, which comprises an error amplifier used for comparing a reference voltage with an output voltage to provide a control signal; the cascode type flip voltage follower is used for comparing the control signal with the output voltage so as to generate a first adjusting signal; the double-ring Class-AB error amplifier is used for comparing the reference voltage with the output voltage so as to generate a second adjusting signal; and a power tube; the power tube is used for adjusting output driving current based on the first adjusting signal and the second adjusting signal so as to output the output voltage through the voltage output end; and the bias module is used for providing bias voltage for the double-ring Class-AB error amplifier, the error amplifier and the cascode type flip voltage follower. The transient response performance of the voltage stabilizer can be improved under the condition of no off-chip large capacitance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit applications, and more particularly to a four-loop on-chip integrated low-dropout linear regulator. Background Technology

[0002] With the rapid development of technology, portable electronic devices are playing an increasingly important role in people's daily lives and work. From smartphones and wearable devices to IoT terminals, these devices not only place higher demands on functional diversity but also bring unprecedented challenges to the performance of power management systems.

[0003] Low dropout regulators (LDOs) are key components in modern power management systems and are widely used in various miniaturized electronic devices. They offer advantages such as low noise, high output accuracy, simple structure, and ease of integration, making them highly favored in scenarios with high requirements for power stability and energy efficiency. However, traditional LDO designs typically rely on large external capacitors to maintain stable output voltage, especially under rapidly changing load current conditions. This not only increases the space occupied on the circuit board and raises the overall system cost but may also affect response speed, making it difficult to meet the demands of current portable devices for thinner, lighter designs and higher integration.

[0004] However, existing on-chip integrated LDOs have shortcomings in transient response performance, which limits their application in high dynamic load scenarios. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention proposes a four-loop on-chip integrated low dropout linear regulator, which mainly solves the problems of large space occupation and insufficient transient response performance of low dropout linear regulators in related technologies.

[0006] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0007] This application provides a four-loop on-chip integrated low-dropout linear regulator, comprising: an error amplifier for comparing a reference voltage with an output voltage to provide a control signal; a cascode flip-flop voltage follower for comparing the control signal with the output voltage to generate a first adjustment signal; a dual-loop Class-AB error amplifier for comparing the reference voltage with the output voltage to generate a second adjustment signal; a power transistor whose gate is connected to the first and second adjustment signals, whose source is connected to the power supply voltage, and whose drain serves as a voltage output terminal; the power transistor adjusts the output drive current based on the first and second adjustment signals to output the output voltage through the voltage output terminal, thereby shortening the circuit response time and reducing output voltage fluctuations during load switching; and a bias module for providing bias voltages to the dual-loop Class-AB error amplifier, the error amplifier, and the cascode flip-flop voltage follower.

[0008] In one embodiment of this application, the biasing module includes: a current source, a first bias transistor, a second bias transistor, and a third bias transistor; the input terminal of the current source is connected to a power supply voltage, and the output terminal is connected to the drain of the first bias transistor; the gate and drain of the first bias transistor are shorted together and connected to the gate of the second bias transistor to serve as an output node for the first bias voltage; the source of the first bias transistor and the source of the second bias transistor are grounded; the drain of the second bias transistor is connected to the drain of the third bias transistor; the gate and drain of the third bias transistor are connected to serve as an output node for the second bias voltage; the source of the third bias transistor is connected to the power supply voltage.

[0009] In one embodiment of this application, the dual-ring Class-AB error amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; The sources of the first transistor, the second transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the nineteenth transistor, and the twentieth transistor are respectively grounded; the sources of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the twenty-first transistor, and the twenty-second transistor are respectively connected to the power supply voltage; the gates of the first transistor, the second transistor, and the eleventh transistor are connected to the power supply voltage. The gates of the first and twelfth transistors are respectively connected to the first bias voltage; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and drain of the third transistor are short-circuited and connected to the gate of the fifth transistor; the source of the third transistor is respectively connected to the source of the sixth transistor, the source of the thirteenth transistor, and the drain of the fifteenth transistor; the drain and gate of the fourth transistor are short-circuited and connected to the gate of the fifth transistor; the source of the fourth transistor is respectively connected to the source of the fifth transistor, the source of the fourteenth transistor, and the drain of the sixteenth transistor; the drain of the fifth transistor is connected to the... The drain of the seventh transistor is connected to the drain of the eighth transistor; the gate and drain of the seventh transistor are short-circuited and connected to the gate of the ninth transistor; the gate and drain of the eighth transistor are short-circuited and connected to the gate of the tenth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor, and the drain of the twenty-first transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the twenty-second transistor; the drain of the eleventh transistor is connected to the drain of the seventh transistor; the drain of the sixth transistor is short-circuited and connected to the drain of the eighth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor, and the drain of the twenty-first transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the ninth transistor, and the drain of the eleventh transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; The drain of the thirteenth transistor is connected to the gate of the fifteenth transistor and the gate of the seventeenth transistor; the gate of the thirteenth transistor serves as the non-inverting input of the dual-ring Class-AB error amplifier and is connected to the output voltage; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor and the gate of the eighteenth transistor; the gate of the fourteenth transistor serves as the inverting input of the dual-ring Class-AB error amplifier and is connected to the reference voltage; the drain of the eighteenth transistor is connected to the drain of the twentieth transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor.

[0010] In one embodiment of this application, the common-source common-gate flip-flop voltage follower includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor; The source of the 23rd transistor is grounded, its gate is connected to the second bias voltage, and its drain is connected to the drain of the 24th transistor as the output terminal of a cascode flip-flop voltage follower, and is also connected to the output terminal of the dual-ring Class-AB error amplifier. The gate of the 24th transistor is connected to the reference voltage, and its source is connected to the drains of the 25th and 26th transistors, respectively. The source of the 25th transistor serves as the non-inverting input terminal of the cascode flip-flop voltage follower, is connected to the non-inverting input terminal of the dual-ring Class-AB error amplifier, and is connected to the output voltage. The gate of the 25th transistor serves as the inverting input terminal of the cascode flip-flop voltage follower, and is connected to the output terminal of the error amplifier. The gate of the 26th transistor is connected to the first bias voltage, and its source is grounded.

[0011] In one embodiment of this application, the error amplifier includes: a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor; The source of the 27th transistor is grounded, its gate is connected to the first bias voltage, and its drain is connected to the source of the 28th transistor and the source of the 29th transistor, respectively. The gate of the 28th transistor serves as the inverting input of the error amplifier, is connected to the non-inverting input of the dual-ring Class-AB error amplifier, and is connected to the output voltage. The drain of the 28th transistor is connected to the drain of the 30th transistor as the output of the even-number error amplifier. The sources of the 30th transistor and the 31st transistor are connected to the power supply voltage, and the gate of the 30th transistor is connected to the gate of the 31st transistor, the drain of the 31st transistor, and the drain of the 29th transistor, respectively. The gate of the 29th transistor is connected to the reference voltage.

[0012] In one embodiment of this application, the output terminal of the low dropout linear regulator further includes a frequency compensation module, which is disposed between the gate and drain of the power transistor to provide frequency compensation so that the circuit remains stable.

[0013] In one embodiment of this application, the frequency compensation module includes a compensation capacitor, one end of which is connected to the gate of the power transistor, and the other end of which is connected to the drain of the power transistor.

[0014] In one embodiment of this application, the output terminal of the low dropout linear regulator further includes a bandgap reference module for providing the reference voltage.

[0015] As described above, the four-loop on-chip integrated low-dropout linear regulator proposed in this application has the following beneficial effects.

[0016] A bias module provides bias voltages for the cascode flip-flop voltage follower, the dual-loop Class-AB error amplifier, and some transistors within the error amplifier. A bandgap reference provides a reference voltage VREF for the cascode flip-flop voltage follower, the error amplifier, and some transistors within the dual-loop Class-AB error amplifier. A frequency compensation module is connected to the output of the four-loop on-chip integrated LDO and the gate of the power transistor MP to ensure the stability of the entire regulator circuit system. The error amplifier compares the reference voltage VREF with the output voltage VOUT and amplifies the resulting error signal for subsequent processing. The cascode flip-flop voltage follower provides the control signal; the cascode flip-flop voltage follower compares the control signal with the output voltage, while the dual-loop Class-AB error amplifier compares the reference voltage VREF with the output voltage, together providing the adjustment signal for the gate of the subsequent power transistor, adjusting the output drive current of the power transistor to shorten the loop response time and reduce the output voltage fluctuation during load switching; based on the dual-loop Class-AB error amplifier and the cascode flip-flop voltage follower, the gate of the power transistor is rapidly charged and discharged, improving the transient response performance of the regulator without the need for a large external capacitor. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall architecture of a four-loop on-chip low-dropout linear regulator in one embodiment of this application. Figure 2 This is a circuit schematic diagram of a four-loop on-chip integrated low dropout linear regulator in one embodiment of this application; Figure 3 This is a schematic diagram of the LDO transient response regulation mechanism in one embodiment of this application; Figure 4 This is a schematic diagram of the transient response curve of a low dropout linear regulator integrated on a four-loop chip in one embodiment of this application. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] The inventor discovered through research that: A System-on-Chip (SoC) is a highly integrated microelectronic device that integrates multiple functional modules onto a single chip, significantly improving system performance and efficiency. For power management, transient response performance is a crucial indicator of a linear regulator's ability to maintain stable output voltage during sudden changes in load current. Good transient response means the regulator can quickly and effectively handle load variations, ensuring system stability and reliability. This performance is typically influenced by factors such as circuit bandwidth, feedback loop design, and internal compensation mechanisms.

[0021] With the rapid development of technology, portable electronic devices have become an indispensable part of our daily lives and work. From smartphones to wearable devices, these devices not only place higher demands on functional versatility but also pose unprecedented challenges to power management systems. To meet the stable and reliable power requirements of portable devices, a wide variety of power solutions have emerged in the market, greatly enriching the electronic product ecosystem.

[0022] Low dropout regulators (LDOs) are widely used in miniaturized electronic devices as highly efficient and stable voltage regulators. Their excellent noise suppression, compact design, and ease of integration make them the preferred choice for many applications. However, traditional LDO designs typically rely on large external capacitors to ensure output voltage stability, especially under rapidly changing load current conditions. This dependence on large external capacitors leads to increased space requirements, higher costs, and slower response times, posing a significant challenge to modern electronic devices that prioritize slim and lightweight designs.

[0023] To address these issues, on-chip integrated LDOs were developed. By optimizing the circuit structure, on-chip integrated LDOs reduce the need for large external capacitors, enabling more compact and economical designs. Nevertheless, while on-chip integrated LDOs have made progress in reducing component count, their transient response performance remains poor, limiting their application under high dynamic load conditions.

[0024] Therefore, designing a low-dropout linear regulator (LDO) that can both reduce energy consumption and enhance transient response performance has become a key problem that urgently needs to be solved in the current technological field. An ideal solution must not only overcome the space limitations and cost challenges of traditional LDOs, but also find the optimal balance between transient response, power consumption, and system stability. Through innovative circuit design and technological optimization, more efficient and energy-saving power management solutions can be achieved to meet the growing demand for high-performance power supplies in modern portable electronic devices.

[0025] Based on the problems existing in the above-mentioned related technologies, this application proposes a four-loop on-chip integrated low dropout linear regulator. The technical solution of this application will be described in detail below with reference to specific embodiments.

[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the overall architecture of a four-loop on-chip integrated low-dropout linear regulator according to one embodiment of this application. The low-dropout linear regulator provided in this embodiment includes: an error amplifier for comparing a reference voltage with an output voltage to provide a control signal; a cascode flip-flop voltage follower for comparing the control signal with the output voltage to generate a first adjustment signal; a dual-loop Class-AB error amplifier for comparing the reference voltage with the output voltage to generate a second adjustment signal; a power transistor whose gate is connected to the first and second adjustment signals, whose source is connected to the power supply voltage, and whose drain serves as the voltage output terminal; the power transistor adjusts the output drive current based on the first and second adjustment signals to output an output voltage through the voltage output terminal, thereby shortening the circuit response time and reducing output voltage fluctuations during load switching; and a bias module for providing bias voltages to the dual-loop Class-AB error amplifier, the error amplifier, and the cascode flip-flop voltage follower. By using a dual-loop Class-AB error amplifier and a cascode flip-flop voltage follower to act on the gate of the power transistor, rapid charging and discharging of the power transistor gate improves the transient response performance of the regulator without the need for a large external capacitor. Through the bias module, cascode flip-flop voltage follower, dual-loop Class-AB error amplifier, error amplifier, and power transistor MP, the LDO possesses a local fast loop and a push-pull structure at the gate of the power transistor MP, thus exhibiting excellent transient response performance.

[0027] Please see Figure 2 , Figure 2This is a circuit schematic of a four-loop on-chip integrated low-dropout linear regulator according to an embodiment of this application. The bias module includes: a current source, a first bias transistor, a second bias transistor, and a third bias transistor; the input terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the drain of the first bias transistor; the gate and drain of the first bias transistor are shorted and connected to the gate of the second bias transistor to serve as the output node of the first bias voltage; the sources of the first and second bias transistors are grounded; the drain of the second bias transistor is connected to the drain of the third bias transistor; the gate and drain of the third bias transistor are connected to serve as the output node of the second bias voltage; the source of the third bias transistor is connected to the power supply voltage. Specifically, the current source in the bias module provides a reference current I. bias In the first bias transistor M B1 The gate generates a first bias voltage V bias1 The second bias voltage V is generated at the gate of the third bias transistor MB3. bias2 The first bias voltage V is provided to the gates of the first transistor M1, the second transistor M2, the eleventh transistor M11, and the twelfth transistor M12 in the dual-ring Class-AB error amplifier, the gate of the twenty-sixth transistor M26 in the cascode flip-flop voltage follower, and the gate of the twenty-seventh transistor M27 in the error amplifier, respectively. bias1 A second bias voltage V is provided to the gate of the twenty-third transistor M23 in the cascode flip-flop voltage follower. bias2 The specific magnitudes of the first and second bias voltages should be selected and adjusted according to actual application requirements; no restrictions are imposed here.

[0028] Please see Figure 2In one embodiment, the dual-ring Class-AB error amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; and the sources of the first transistor, the second transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor. The sources of the body transistor, the nineteenth transistor, and the twentieth transistor are grounded; the sources of the fifteenth, sixteenth, seventeenth, eighteenth, twenty-first, and twenty-second transistors are connected to the power supply voltage; the gates of the first, second, eleventh, and twelfth transistors are connected to the first bias voltage; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and drain of the third transistor are shorted and connected to the gate of the fifth transistor; the source of the third transistor is connected to the source of the sixth, thirteenth, and twelfth transistors respectively. The drain of transistor 5; the drain and gate of transistor 4 are shorted and connected to the gate of transistor 5; the source of transistor 4 is connected to the source of transistor 5, the source of transistor 14, and the drain of transistor 16; the drain of transistor 5 is connected to the drain of transistor 7; the drain of transistor 6 is connected to the drain of transistor 8; the gate and drain of transistor 7 are shorted and connected to the gate of transistor 9; the gate and drain of transistor 8 are shorted and connected to the gate of transistor 10; the drain of transistor 9 is connected to the drain of transistor 17, the drain of transistor 19, and the drain of transistor 21, serving as the output of the dual-ring Class-AB error amplifier; the drain of transistor 10 is connected to the drain of transistor 22. The drain of transistor 22 is shorted between its gate and drain, and connected to the gate of transistor 21. The drain of transistor 11 is connected to the drain of transistor 13, the gate of transistor 15, and the gate of transistor 17. The gate of transistor 13 serves as the non-inverting input of the dual-ring Class-AB error amplifier and is connected to the output voltage. The drain of transistor 12 is connected to the drain of transistor 14, the gate of transistor 16, and the gate of transistor 18. The gate of transistor 14 serves as the inverting input of the dual-ring Class-AB error amplifier and is connected to the reference voltage. The drain of transistor 18 is connected to the drain of transistor 20, the gate of transistor 20, and the gate of transistor 19. For details, please refer to [link to documentation]. Figure 3 , Figure 3 This is a schematic diagram of the transient response adjustment mechanism of an LDO in one embodiment of this application. The loop formed by the dual-loop Class-AB error amplifier includes: a first loop and a second loop; the first loop sequentially passes through the drain of power transistor MP, the gate of the thirteenth transistor, the source of the thirteenth transistor, the source of the sixth transistor, the drain of the sixth transistor, the gate of the tenth transistor, the drain of the tenth transistor, the gate of the twenty-first transistor, the drain of the twenty-first transistor, and then back to the gate of power transistor MP; the second loop sequentially passes through the drain of the power transistor, the gate of the thirteenth transistor, the drain of the thirteenth transistor, the gate of the seventeenth transistor, the drain of the seventeenth transistor, and then back to the gate of the power transistor. Under rapid load changes, these two loops can effectively suppress overshoot and undershoot phenomena in the output, improving the transient response performance of the LDO.

[0029] Please see Figure 2 In one embodiment, the cascode voltage follower includes: a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor; the source of the 23rd transistor is grounded, its gate is connected to a second bias voltage, and its drain is connected to the drain of the 24th transistor as the output terminal of the cascode voltage follower, and is also connected to the output terminal of a dual-ring Class-AB error amplifier; the gate of the 24th transistor is connected to a reference voltage, and its source is connected to the drains of the 25th and 26th transistors respectively; the source of the 25th transistor serves as the non-inverting input terminal of the cascode voltage follower, is connected to the non-inverting input terminal of the dual-ring Class-AB error amplifier, and is connected to the output voltage; the gate of the 25th transistor serves as the inverting input terminal of the cascode voltage follower, and is connected to the output terminal of the error amplifier; the gate of the 26th transistor is connected to a first bias voltage, and its source is grounded. For details, please refer to [link to relevant documentation]. Figure 3 The common-source common-gate flip-flop voltage follower includes a local fast loop, which sequentially passes through the drain of the power transistor, the source of the 25th transistor, the drain of the 25th transistor, the source of the 24th transistor, the drain of the 24th transistor, and finally the gate of the power transistor. This local fast loop effectively improves the transient response performance of the device.

[0030] Please see Figure 2In one embodiment, the error amplifier includes: a 27th transistor, a 28th transistor, a 29th transistor, a 30th transistor, and a 31st transistor; the source of the 27th transistor is grounded, its gate is connected to a first bias voltage, and its drain is connected to the sources of the 28th and 29th transistors, respectively; the gate of the 28th transistor serves as the inverting input of the error amplifier, connected to the non-inverting input of a dual-ring Class-AB error amplifier, and connected to the output voltage; the drain of the 28th transistor is connected to the drain of the 30th transistor as the output of the even-number error amplifier; the sources of the 30th and 31st transistors are connected to the power supply voltage, and the gate of the 30th transistor is connected to the gate of the 31st transistor, the drain of the 31st transistor, and the drain of the 29th transistor, respectively; the gate of the 29th transistor is connected to a reference voltage. For details, please refer to [link to relevant documentation]. Figure 3 The error amplifier contains a global slow loop that sequentially passes through the drain of the power transistor, the gate of the 28th transistor, the source of the 28th transistor, the source of the 29th transistor, the drain of the 29th transistor, the gate of the 30th transistor, the drain of the 30th transistor, the gate of the 25th transistor, and then back to the drain of the power transistor.

[0031] In one embodiment, the output of the low-dropout linear regulator further includes a frequency compensation module. This module is positioned between the gate and drain of the power transistor to provide frequency compensation, ensuring circuit stability. The frequency compensation module may employ a compensation capacitor, with one end connected to the gate of the power transistor and the other end connected to its drain. Connecting the compensation capacitor to both the output of the LDO and the output of the cascode flip-flop voltage follower ensures the stability of the regulator circuit system.

[0032] In one embodiment, the output of the low-dropout linear regulator further includes a bandgap reference module for providing a reference voltage. The specific circuit structure of the bandgap reference module can be set and adjusted according to actual application requirements, and is not limited here.

[0033] Please see Figure 4 , Figure 4 This is a schematic diagram of the transient response of a four-loop on-chip integrated low-dropout linear regulator (LDO) in one embodiment of this application. The first and second loops are both global slow loops. A push-pull architecture consisting of a local fast loop, three global slow loops, and the dual-loop Class-AB error amplifier itself is used to rapidly push-pull the gate of the power transistor (MP), thereby improving the transient response performance of the on-chip integrated LDO. Figure 4As shown, under the conditions of edge time of 300 ns and load capacitance of 100 pF, when the load current jumps from 1 mA to 50 mA, the undershoot voltage is 16.3 mV and the recovery time is less than 1 μs. When the load current jumps from 50 mA to 1 mA, the overshoot voltage is 13.2 mV and the recovery time is also less than 1 μs. The small overshoot and undershoot voltages and short recovery times effectively improve the transient response speed.

[0034] In one embodiment, the power supply voltage VIN is typically 1.5V to 1.8V. 1.5V is usually used as the power supply voltage for the low-dropout linear regulator. If the load capacitor CL is set to 0-100pF, a corresponding load drive current of 1-50mA can be obtained, thus stabilizing the output voltage VOUT of the low-dropout linear regulator at 1.2V. A first bias voltage V is generated through the bias module. bias1 Second bias voltage V bias2 The bandgap reference module provides a reference voltage VREF for some transistors in the error amplifier, cascode flip-flop voltage follower, and dual-loop Class-AB error amplifier. The frequency compensation module is connected to the output of the LDO and the output of the cascode flip-flop voltage follower to ensure the stability of the entire regulator circuit system. The error amplifier compares the reference voltage VREF with the output voltage VOUT and amplifies the resulting error signal to provide a control signal Vset for the subsequent cascode flip-flop voltage follower. The cascode flip-flop voltage follower compares the control signal Vset with the output voltage VOUT and amplifies the resulting first adjustment signal to adjust the gate voltage of the power transistor MP. The dual-loop Class-AB error amplifier compares the reference voltage VREF with the output voltage VOUT and amplifies the resulting second adjustment signal, which, together with the cascode flip-flop voltage follower, adjusts the gate voltage of the power transistor MP, thereby adjusting the output drive current of the power transistor MP to shorten the loop response time and reduce output voltage fluctuations during load switching. The LDO disclosed in this application improves the transient response performance of the voltage regulator by rapidly charging and discharging the gate of the power transistor MP using a dual-loop Class-AB error amplifier and a cascode switching voltage follower, without requiring large external capacitors. This four-loop on-chip integrated LDO regulator achieves several key technological breakthroughs in performance and integration. It not only supports full on-chip integration, effectively reducing dependence on external components, but also features wide load current regulation capability, providing high-precision output voltage. Its fast transient response characteristics effectively handle sudden load changes, ensuring the stability and reliability of system operation.

[0035] In terms of circuit design, this LDO achieves excellent stability and extremely low output voltage ripple while maintaining high gain and wide bandwidth through efficient power transistor area utilization. Furthermore, the regulator incorporates an innovative thermal management mechanism and optimized space layout design, significantly improving heat dissipation efficiency and chip area utilization.

[0036] These advantages make it an ideal power management solution for high-performance electronic products, especially suitable for applications with stringent requirements for reliability, energy efficiency and space constraints, such as smartphones, tablets, wearable devices and other portable smart terminals.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A four-loop on-chip integrated low-dropout linear regulator, characterized in that, The low-dropout linear regulator includes: An error amplifier is used to compare a reference voltage with an output voltage to provide a control signal; A common-source, common-gate, flip-flop voltage follower is used to compare the control signal with the output voltage to generate a first adjustment signal; A dual-loop Class-AB error amplifier is used to compare the reference voltage with the output voltage to generate a second adjustment signal; The power transistor has its gate connected to the first adjustment signal and the second adjustment signal, its source connected to the power supply voltage, and its drain as the voltage output terminal. The power transistor adjusts the output drive current based on the first adjustment signal and the second adjustment signal to output the output voltage through the voltage output terminal, thereby shortening the circuit response time and reducing the output voltage fluctuation during load switching. The bias module is used to provide bias voltage for the dual-loop Class-AB error amplifier, the error amplifier and the cascode flip-flop voltage follower.

2. The four-loop on-chip integrated low-dropout linear regulator according to claim 1, characterized in that, The bias module includes: a current source, a first bias transistor, a second bias transistor, and a third bias transistor; The input terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the drain of the first bias transistor. The gate and drain of the first bias transistor are shorted together and connected to the gate of the second bias transistor to serve as the output node of the first bias voltage. The source of the first bias transistor and the source of the second bias transistor are grounded. The drain of the second bias transistor is connected to the drain of the third bias transistor. The gate and drain of the third bias transistor are connected to serve as the output node of the second bias voltage. The source of the third bias transistor is connected to the power supply voltage.

3. The four-loop on-chip integrated low-dropout linear regulator according to claim 2, characterized in that, The dual-ring Class-AB error amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; The sources of the first transistor, the second transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the nineteenth transistor, and the twentieth transistor are respectively grounded; the sources of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the twenty-first transistor, and the twenty-second transistor are respectively connected to the power supply voltage; the gates of the first transistor, the second transistor, and the eleventh transistor are connected to the power supply voltage. The gates of the first and twelfth transistors are respectively connected to the first bias voltage; the drain of the first transistor is connected to the drain of the third transistor; the drain of the second transistor is connected to the drain of the fourth transistor; the gate and drain of the third transistor are short-circuited and connected to the gate of the fifth transistor; the source of the third transistor is respectively connected to the source of the sixth transistor, the source of the thirteenth transistor, and the drain of the fifteenth transistor; the drain and gate of the fourth transistor are short-circuited and connected to the gate of the fifth transistor; the source of the fourth transistor is respectively connected to the source of the fifth transistor, the source of the fourteenth transistor, and the drain of the sixteenth transistor; the drain of the fifth transistor is connected to the... The drain of the seventh transistor is connected to the drain of the eighth transistor; the gate and drain of the seventh transistor are short-circuited and connected to the gate of the ninth transistor; the gate and drain of the eighth transistor are short-circuited and connected to the gate of the tenth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor, and the drain of the twenty-first transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the twenty-second transistor; the drain of the eleventh transistor is connected to the drain of the seventh transistor; the drain of the sixth transistor is short-circuited and connected to the drain of the eighth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the nineteenth transistor, and the drain of the twenty-first transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the ninth transistor is connected to the drain of the seventeenth transistor, the drain of the ninth transistor, and the drain of the eleventh transistor, respectively, to serve as the output terminal of the dual-ring Class-AB error amplifier; the drain of the tenth transistor is connected to the drain of the twenty-second transistor; the gate and drain of the twenty-second transistor are short-circuited and connected to the gate of the twenty-first transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; the drain of the eleventh transistor is connected to the drain of the ninth transistor; The drain of the thirteenth transistor is connected to the gate of the fifteenth transistor and the gate of the seventeenth transistor; the gate of the thirteenth transistor serves as the non-inverting input of the dual-ring Class-AB error amplifier and is connected to the output voltage; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the gate of the sixteenth transistor and the gate of the eighteenth transistor; the gate of the fourteenth transistor serves as the inverting input of the dual-ring Class-AB error amplifier and is connected to the reference voltage; the drain of the eighteenth transistor is connected to the drain of the twentieth transistor, the gate of the twentieth transistor and the gate of the nineteenth transistor.

4. The four-loop on-chip integrated low-dropout linear regulator according to claim 2, characterized in that, The common-source common-gate flip-flop voltage follower includes: a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor; The source of the 23rd transistor is grounded, its gate is connected to the second bias voltage, and its drain is connected to the drain of the 24th transistor as the output terminal of a cascode flip-flop voltage follower, and is also connected to the output terminal of the dual-ring Class-AB error amplifier. The gate of the 24th transistor is connected to the reference voltage, and its source is connected to the drains of the 25th and 26th transistors, respectively. The source of the 25th transistor serves as the non-inverting input terminal of the cascode flip-flop voltage follower, is connected to the non-inverting input terminal of the dual-ring Class-AB error amplifier, and is connected to the output voltage. The gate of the 25th transistor serves as the inverting input terminal of the cascode flip-flop voltage follower, and is connected to the output terminal of the error amplifier. The gate of the 26th transistor is connected to the first bias voltage, and its source is grounded.

5. The four-loop on-chip integrated low-dropout linear regulator according to claim 4, characterized in that, The error amplifier includes: the twenty-seventh transistor, the twenty-eighth transistor, the twenty-ninth transistor, the thirtieth transistor, and the thirty-first transistor; The source of the 27th transistor is grounded, its gate is connected to the first bias voltage, and its drain is connected to the source of the 28th transistor and the source of the 29th transistor, respectively. The gate of the 28th transistor serves as the inverting input of the error amplifier, is connected to the non-inverting input of the dual-ring Class-AB error amplifier, and is connected to the output voltage. The drain of the 28th transistor is connected to the drain of the 30th transistor as the output of the even-number error amplifier. The sources of the 30th transistor and the 31st transistor are connected to the power supply voltage, and the gate of the 30th transistor is connected to the gate of the 31st transistor, the drain of the 31st transistor, and the drain of the 29th transistor, respectively. The gate of the 29th transistor is connected to the reference voltage.

6. The four-loop on-chip integrated low-dropout linear regulator according to claim 1, characterized in that, The output of the low dropout linear regulator also includes a frequency compensation module, which is located between the gate and drain of the power transistor to provide frequency compensation so that the circuit remains stable.

7. The four-loop on-chip integrated low-dropout linear regulator according to claim 6, characterized in that, The frequency compensation module includes a compensation capacitor, one end of which is connected to the gate of the power transistor, and the other end of which is connected to the drain of the power transistor.

8. The four-loop on-chip integrated low-dropout linear regulator according to claim 1, characterized in that, The output of the low-dropout linear regulator also includes a bandgap reference module for providing the reference voltage.

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