Calibration circuit of clock signal and high bandwidth memory

Abstract

The embodiments of the present disclosure disclose a clock signal calibration circuit and a high bandwidth memory. The calibration circuit comprises an adjusting circuit, a selecting circuit, a merging circuit and a detecting circuit. The adjusting circuit is configured to receive n clock signals with sequentially increasing phases, adjust the delay of a target clock signal among the n clock signals in response to a delay control signal, and transmit the n clock signals. The selecting circuit is configured to select a reference clock signal and the target clock signal among the n clock signals. The merging circuit is configured to merge based on the phase difference between the target clock signal and the reference clock signal, and generate an included angle signal. The detecting circuit is configured to detect the duty cycle of the included angle signal, and generate a delay control signal corresponding to the target clock signal.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a clock signal calibration circuit and a high-bandwidth memory. Background Technology

[0002] High-bandwidth memory (HBM) is a high-performance memory based on 3D stacking technology. HBM is suitable for applications with high memory bandwidth requirements and can meet the needs of data-intensive applications such as artificial intelligence (AI), high-performance computing (HPC), and graphics processing.

[0003] High-bandwidth memory (HBRAM) comprises multiple stacked memory chips, enabling large-capacity, high-bit-width memory arrays. The compact and fast connection between the HBRAM stack and the processor results in higher speed, higher bandwidth, and lower power consumption. However, due to the higher operating frequency of HBRAM, the clock signals within it require higher calibration accuracy. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a clock signal calibration circuit and a high-bandwidth memory, which can eliminate deviations between multi-phase clock signals and improve calibration accuracy.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a clock signal calibration circuit, comprising: an adjustment circuit configured to receive n clock signals with sequentially increasing phases, adjust the delay of a target clock signal among the n clock signals in response to a delay control signal, and transmit the n clock signals; where n is an integer greater than 1; a selection circuit coupled to the adjustment circuit, configured to select a reference clock signal and the target clock signal from the n clock signals; a merging circuit coupled to the selection circuit, configured to merge the target clock signal and the reference clock signal based on their phase difference to generate an angle signal; and a detection circuit coupled to the merging circuit, configured to detect the duty cycle of the angle signal and generate the delay control signal corresponding to the target clock signal.

[0007] In some embodiments of this disclosure, the reference clock signal includes: a first reference clock signal and a second reference clock signal; wherein, the adjustment target phase of the target clock signal is the average phase of the first reference clock signal and the second reference clock signal.

[0008] In some embodiments of this disclosure, the selection circuit is further configured to select the first reference clock signal and the second reference clock signal from the clock signals whose phases have been determined; wherein the target clock signal corresponding to the first reference clock signal and the second reference clock signal is the unadjusted clock signal.

[0009] In some embodiments of this disclosure, n=2k, k>0; the phases of the n clock signals are sequentially 360° / n apart; the selection circuit is further configured to, in the first adjustment, select the i-th clock signal as both the first reference clock signal and the second reference clock signal, and select either the (i+n / 2)-th clock signal or the (in / 2)-th clock signal as the target clock signal; 1≤i≤n.

[0010] In some embodiments of this disclosure, the selection circuit is further configured to, in subsequent adjustments, replace one of the first reference clock signal and the second reference clock signal in the previous adjustment with the target clock signal in the previous adjustment to obtain the first reference clock signal and the second reference clock signal in the current adjustment, and select the target clock signal in the current adjustment based on the first reference clock signal and the second reference clock signal in the current adjustment, until the first reference clock signal, the target clock signal and the second reference clock signal are adjacent clock signals.

[0011] In some embodiments of this disclosure, the included angle signal includes: a first included angle signal and a second included angle signal; the merging circuit is further configured to merge based on the phase difference between the first reference clock signal and the target clock signal to generate the first included angle signal, and to merge based on the phase difference between the target clock signal and the second reference clock signal to generate the second included angle signal; wherein the pulse width of the first included angle signal is equal to the phase difference between the first reference clock signal and the target clock signal, and the pulse width of the second included angle signal is equal to the phase difference between the target clock signal and the second reference clock signal.

[0012] In some embodiments of this disclosure, the detection circuit is further configured to extract the DC component of the first included angle signal and the DC component of the second included angle signal and compare them, and output a delay control signal of corresponding level according to the comparison result; the adjustment circuit is further configured to adjust the delay of the target clock signal until the level of the delay control signal jumps.

[0013] In some embodiments of this disclosure, the adjustment circuit receives eight clock signals; the adjustment circuit includes eight numerically controlled delay lines; each numerically controlled delay line adjusts and transmits a corresponding clock signal.

[0014] This disclosure also provides a high-bandwidth memory, comprising: a base chip and multiple core chips stacked on the base chip; the base chip includes: a clock generation circuit and multiple channels; the clock generation circuit is coupled to the multiple channels; the path delays between the clock generation circuit and the multiple channels are not identical; the clock generation circuit is configured to generate n clock signals with sequentially increasing phases and transmit the n clock signals to each of the channels; n is an integer greater than 1; each of the multiple channels includes: a clock signal calibration circuit as described in the above scheme.

[0015] In some embodiments of this disclosure, the plurality of channels are arranged in a rows and b columns; a and b are both positive integers; the transmission path between the clock generation circuit and the plurality of channels includes: a main path and b branch paths connected to the main path; each branch path connects to a corresponding column of the channels.

[0016] Understandably, to address the deviation between multi-phase clock signals, the calibration circuit can select a reference clock signal and a target clock signal from the multi-phase clock signals. Then, based on the phase difference between the target clock signal and the reference clock signal, it generates an angle signal and detects the duty cycle of the angle signal to generate a delay control signal to adjust the delay of the target clock signal. This reduces or even eliminates the deviation between multi-phase clock signals, improving calibration accuracy. For applications such as high-bandwidth memories with higher operating frequencies, the calibration circuit can provide a significant improvement. Attached Figure Description

[0017] Figure 1 A schematic diagram of the structure of a high-bandwidth memory provided in an embodiment of this disclosure;

[0018] Figure 2 This is a schematic diagram of the structure of the basic chip in the high-bandwidth memory provided in the embodiments of this disclosure;

[0019] Figure 3 A schematic diagram of the calibration circuit provided in the embodiments of this disclosure;

[0020] Figure 4 A schematic diagram of the signal waveform of the calibration circuit provided in the embodiments of this disclosure;

[0021] Figure 5 This is a schematic diagram of the detection circuit in the calibration circuit provided in the embodiments of this disclosure;

[0022] Figure 6 A schematic diagram of the signal waveform of the detection circuit in the calibration circuit provided in an embodiment of this disclosure;

[0023] Figure 7 This is a schematic diagram of the structure of the numerically controlled delay line in the calibration circuit provided in the embodiments of this disclosure;

[0024] Figure 8 A schematic diagram of the signal waveform of the numerically controlled delay line in the calibration circuit provided in the embodiments of this disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0028] This disclosure provides a high-bandwidth memory (HBM), such as Figure 1 As shown, the high-bandwidth memory 10 includes a base die 01 and multiple core dies 02.

[0029] refer to Figure 1 Multiple core chips 02 are stacked on top of the base chip 01 and interconnected via through-silicon vias (TSVs) and / or micro bumps. Finally, the high-bandwidth memory 10 is connected to the processor (e.g., a graphics processing unit (GPU) or a central processing unit (CPU)) via an interposer.

[0030] Continue to refer to Figure 1The base chip 01 serves as the logic control layer and physical interface layer within the high-bandwidth memory 10. The base chip 01 is responsible for functions such as address decoding, command scheduling, data routing, and protocol conversion, as well as enabling high-speed interconnection between the high-bandwidth memory 10 and the processor.

[0031] Continue to refer to Figure 1 The core chip 02 is the data storage layer in the high-bandwidth memory 10. Each core chip 02 layer contains an independent memory array responsible for actual data storage. The core chips 02 can be stacked at high density, for example, 4 to 12 layers, with each layer having a capacity of 1 to 2 Gb, and the total capacity increasing linearly with the number of stacked layers.

[0032] In this embodiment of the disclosure, the core chip 02 may be a memory chip, such as a dynamic random access memory (DRAM). The core chip 02 may include a memory cell array and peripheral circuitry.

[0033] In this embodiment of the disclosure, the peripheral circuitry in the core chip 02 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: decoders (e.g., row decoders and column decoders), input / output (I / O) circuitry, voltage sources or generators, any portion of the functional circuitry mentioned above (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some implementations, the peripheral circuitry may be implemented using complementary metal-oxide-semiconductor (CMOS) technology, such as the aforementioned complementary metal-oxide-semiconductor (CMOS).

[0034] In this embodiment of the disclosure, the memory cell array in the core chip 02 may include any suitable type of memory cell array using transistors as switching and selection devices, such as a dynamic random access memory (DRAM) cell array, a PCM cell array, a static random access memory (SRAM) cell array, a FeRAM cell array, a resistive memory cell array, a magnetic memory cell array, or any combination thereof. Each memory cell includes a capacitor for storing data bits as positive or negative charges and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selection) access to it. In some embodiments, each DRAM cell may be a single transistor-single capacitor (1T1C) cell, a two-transistor cell (2T0C cell), etc.

[0035] In this embodiment of the disclosure, reference is made to Figure 1The high-bandwidth memory 10 has multiple channels. Each channel is an independent data path, containing complete control signals, address buses, and data buses, enabling parallel data reading and writing. Through multi-channel parallel operation, the high-bandwidth memory 10 can achieve aggregate bandwidth far exceeding that of traditional memory while reducing latency. The high-bandwidth memory 10 can use the wide interface protocol in the JEDEC standard to support multi-channel cooperative scheduling.

[0036] In this embodiment of the disclosure, combined with Figure 1 and Figure 2 The base chip 01 includes multiple channels CH0~CH15. The base chip 01 can manage the scheduling, timing synchronization and power consumption control of channels CH0~CH15. Furthermore, channels CH0~CH15 in the base chip 01 can serve as the physical layer (PHY) to enable interconnection with the outside world.

[0037] It's important to note that the Physical Layer (PHY) is a crucial interface layer in the High Bandwidth Memory (HBM) architecture, responsible for high-speed data transmission and signal processing. The PHY can include multiple interface subsystems: data interface, clock interface, control interface, and power interface. The data interface can support multiple independent channels operating in parallel; the clock interface can employ a dual-channel design (master clock + data clock) to achieve precise timing control; the control interface is the core control module, responsible for sending read / write commands, address transmission, and error handling; and the power interface provides stable power and supports voltage and temperature compensation.

[0038] In this embodiment of the disclosure, combined with Figure 1 and Figure 2 The basic chip 01 also includes a clock generation circuit 11. The clock generation circuit 11 may include a phase-locked loop (PLL) or a delay-locked loop (DLL), which can provide a phase-stable clock signal.

[0039] refer to Figure 2 The clock generation circuit 11 is coupled to multiple channels CH0~CH15. The clock generation circuit 11 is configured to generate n clock signals with sequentially increasing phases. Figure 2 The example uses 8 clock signals CLK<7:0>, and transmits n clock signals to each channel. The path delays between the clock generation circuit 11 and the multiple channels CH0~CH15 are not entirely the same.

[0040] by Figure 2For example, multiple channels CH0~CH15 are arranged in 4 rows and 4 columns. The transmission path between the clock generation circuit 11 and the multiple channels CH0~CH15 includes: one main path L1 and four branch paths L2. Among them, the four branch paths L2 are connected to the main path L1; at the same time, each branch path L2 is connected to a corresponding column of channels. For example, the first branch path L2 connects channels CH0, CH4, CH8 and CH12, the second branch path L2 connects channels CH1, CH5, CH9 and CH13, the third branch path L2 connects channels CH2, CH6, CH10 and CH14, and the fourth branch path L2 connects channels CH3, CH7, CH11 and CH15.

[0041] It should be noted that because the transmission path lengths between the multiple channels CH0~CH15 and the clock generation circuit 11 differ, the path delays between the clock generation circuit 11 and the multiple channels CH0~CH15 also differ. This can lead to mismatches in the multi-phase clock signals CLK<7:0> received by the multiple channels CH0~CH15, resulting in skew between the multi-phase clock signals CLK<7:0>. These skews ultimately affect the accuracy of the MBIST (Memory Built-In Self-Test) circuit in chip debugging (training). Furthermore, because high-bandwidth memories operate at higher frequencies, the calibration accuracy requirements between the multi-phase clock signals CLK<7:0> are also higher.

[0042] In this embodiment of the disclosure, reference is made to Figure 2 Multiple channels CH0~CH15 can be equipped with clock signal calibration circuits. These circuits adjust the delay of the multi-phase clock signal CLK<7:0>, thereby calibrating its phase. Each channel can have its own calibration circuit, or adjacent channels can share a single calibration circuit.

[0043] Understandably, setting up clock signal calibration circuits for multiple channels CH0~CH15 to calibrate the phases of the multi-phase clock signal CLK<7:0> reduces or even eliminates deviations between the multi-phase clock signals CLK<7:0>, ensuring the accuracy of the clock signal received by each channel. For high-bandwidth memories with higher operating frequencies, clock signal calibration circuits can bring significant improvements, effectively reducing the possibility of signal transmission errors.

[0044] This disclosure also provides a clock signal calibration circuit, with reference to... Figure 3The calibration circuit 20 includes: an adjustment circuit 21, a selection circuit 22, a merging circuit 23, and a detection circuit 24.

[0045] Combination Figure 2 and Figure 3 The clock generation circuit 11 generates eight clock signals CLK<7:0> with sequentially increasing phases and transmits them to multiple channels CH0~CH15. Furthermore, the adjustment circuit 21 in the calibration circuit 20 corresponding to each channel can receive the eight clock signals CLK<7:0> with sequentially increasing phases.

[0046] refer to Figure 3 The adjustment circuit 21 also receives a delay control signal DCD. The adjustment circuit 21 is configured to adjust the delay of the target clock signal mux1 among the eight clock signals CLK<7:0> in response to the delay control signal DCD, and to transmit the eight clock signals CLK<7:0>.

[0047] Continue to refer to Figure 3 The selection circuit 22 is coupled to the adjustment circuit 21. The selection circuit 22 is configured to select the reference clock signal mux0 / mux2 and the target clock signal mux1 from the eight clock signals CLK<7:0>.

[0048] Continue to refer to Figure 3 The merging circuit 23 is coupled to the selection circuit 22. The merging circuit 23 is configured to merge based on the phase difference between the target clock signal mux1 and the reference clock signals mux0 / mux2 to generate the included angle signals mckt and mckc.

[0049] Continue to refer to Figure 3 The detection circuit 24 is coupled to the parallel circuit. The detection circuit 24 is configured to detect the duty cycle of the included angle signals mckt and mckc, and generate the delay control signal DCDC corresponding to the target clock signal mux1.

[0050] In some embodiments of this disclosure, reference is made to Figure 3The adjustment circuit receives eight clock signals and includes eight numerically controlled delay lines BDL0~BDL7. Each numerically controlled delay line adjusts and transmits a corresponding clock signal. The adjustment circuit 21 transmits the eight clock signals CLK<7:0> to the selection circuit 22. The selection circuit 22 can select the target clock signal mux1, as well as the reference clock signals mux0 and mux2 from the eight clock signals CLK<7:0>. The reference clock signals mux0 and mux2 serve as references for adjusting the target clock signal mux1. Furthermore, the reference clock signals mux0, mux2, and the target clock signal mux1 are combined by the merging circuit 23 to generate angle signals mckt and mckc, where the angle signals mckt and mckc represent the phase difference between the target clock signal mux1 and the reference clock signals mux0 / mux2. Furthermore, the detection circuit 24 can detect the duty cycle of the included angle signals mckt and mckc, that is, detect the phase difference between the target clock signal mux1 and the reference clock signals mux0 / mux2, and generate a delay control signal DCDC. Then, the adjustment circuit 21 can adjust the delay of the target clock signal mux1 among the eight clock signals CLK<7:0> in response to the delay control signal DCDC. After all eight clock signals CLK<7:0> have been adjusted, they can be output from the output terminal CLK_OUT of the calibration circuit 20 to the corresponding channel.

[0051] Understandably, to address the deviation between the multi-phase clock signals CLK<7:0>, the calibration circuit 20 can select reference clock signals mux0, mux2, and target clock signal mux1 from the multi-phase clock signals CLK<7:0>. Then, based on the phase difference between the target clock signal mux1 and the reference clock signals mux0 and mux2, it generates angle signals mckt and mckc, and detects the duty cycle of the angle signals mckt and mckc to generate a delay control signal DCDC to adjust the delay of the target clock signal mux1. This reduces or even eliminates the deviation between the multi-phase clock signals CLK<7:0>, improving calibration accuracy. For applications such as high-bandwidth memories with higher operating frequencies, the calibration circuit 20 can provide a significant improvement.

[0052] For example, combining Figures 1 to 3In the base chip 01 of the high-bandwidth memory 10, the farthest distance from the clock generation circuit 11 to the physical layer PHY (containing multiple channels CH0~CH15) of the multi-phase clock signal CLK<7:0> exceeds 5000um, and the clock delay is at least 500ps. Considering the fluctuation of process parameters, this can introduce a deviation of 10ps~50ps between the clock signals. However, by using the calibration circuit 20 provided in this embodiment, the mismatch between the multi-phase clock signals CLK<7:0> can be significantly reduced, and the deviation between the multi-phase clock signals CLK<7:0> can be reduced to the adjustment accuracy of the numerically controlled delay chain (within 5ps). Therefore, the timing measurement accuracy of the high-bandwidth memory 10 test circuit can also be improved to within 5ps.

[0053] In some embodiments of this disclosure, reference is made to Figure 3 The reference clock signal includes: a first reference clock signal mux0 and a second reference clock signal mux2; wherein, the adjustment target phase of the target clock signal mux1 is the average phase of the first reference clock signal mux0 and the second reference clock signal mux2.

[0054] by Figure 4 For example, if the phase of the first reference clock signal mux0 is 0° and the phase of the second reference clock signal mux2 is 180°, then the target phase of the target clock signal mux1 needs to be adjusted to 90°. In other words, using the phases of the first and second reference clock signals mux0 and mux2 as references, the phase of the target clock signal mux1 needs to be adjusted to 90°. For instance, if the phase of the target clock signal mux1 is 87°, then the phase of the target clock signal mux1 needs to be increased by 3° to reach 90°.

[0055] It is understandable that the target phase of the target clock signal mux1 to be adjusted is the average phase of the first reference clock signal mux0 and the second reference clock signal mux2. Therefore, by simply comparing the phase difference between the target clock signal mux1 and the first reference clock signal mux0 to see if it equals the phase difference between the target clock signal mux1 and the second reference clock signal mux2, it can be determined whether the adjustment is complete. This allows for a relatively simple way to determine whether the phase of the target clock signal mux1 has been adjusted correctly, which helps simplify the circuit and improve efficiency.

[0056] In this embodiment of the present disclosure, the selection circuit 22 can select the first reference clock signal mux0, the second reference clock signal mux2, and the target clock signal mux1 from the multi-phase clock signal CLK<7:0>.

[0057] In some embodiments of this disclosure, the selection circuit 22 can be implemented by a multiplexer (MUX). For example, an 8-to-1 MUX can be used, selecting one output from eight input clock signals via three control signals S0, S1, and S2. Furthermore, three MUXs can be cascaded, with each MUX independently selecting one clock signal, thus outputting three clock signals simultaneously.

[0058] In some other embodiments of this disclosure, the selection circuit 22 can be implemented using a decoder and logic gates. For example, a 3-to-8 decoder can be used to decode the 3-bit initial control signal into 8 control signals and output them. Then, the 8 control signals and 8 clock signals can be input into the logic gates, and the output of the 8 clock signals can be controlled by the 8 control signals, thereby selecting 3 clock signals for output.

[0059] In some embodiments of this disclosure, reference is made to Figure 3 The selection circuit 22 is further configured to select a first reference clock signal mux0 and a second reference clock signal mux2 from among the eight clock signals CLK<7:0> whose phases are already determined. The target clock signal mux1 corresponding to the first reference clock signal mux0 and the second reference clock signal mux2 is an unadjusted clock signal. Thus, the unadjusted target clock signal mux1 can be adjusted based on the first reference clock signal mux0 and the second reference clock signal mux2, whose phases are already determined.

[0060] by Figure 4 For example, the phase of the first reference clock signal mux0 is 0°, the phase of the second reference clock signal mux2 is 180°, and the phases of the first reference clock signal mux0 and the second reference clock signal mux2 have been determined. Therefore, the phase of the target clock signal mux1 can be adjusted to 90° based on the first reference clock signal mux0 and the second reference clock signal mux2.

[0061] It should be noted that the clock signals with determined phases among the eight clock signals CLK<7:0> can be clock signals that have already been adjusted, or clock signals whose phases have been predetermined.

[0062] Understandably, to address the deviations between the multi-phase clock signals CLK<7:0>, the calibration circuit 20 can use the unadjusted clock signal from CLK<7:0> as the target clock signal mux1, and use the clock signal with a determined phase from CLK<7:0> as a reference to adjust the delay of the target clock signal mux1. This can reduce or even eliminate the deviations between the multi-phase clock signals CLK<7:0>, improving calibration accuracy.

[0063] In some embodiments of this disclosure, the number of clock signals n=2 k k>0; that is, the number of clock signals can be 2, 4 or 8, etc.

[0064] Simultaneously, the phases of the n clock signals differ sequentially by 360° / n. (Reference) Figure 4 Taking 8 clock signals CLK<7:0> as an example, the phases of the 8 clock signals CLK<7:0> differ by 360° / 8=45° respectively; that is, the phase of the second clock signal CLK1 is 45° larger than the phase of the first clock signal CLK0, the phase of the third clock signal CLK2 is 45° larger than the phase of the second clock signal CLK1, and so on.

[0065] refer to Figure 3 The selection circuit 22 is also configured to, in the first adjustment, select the i-th clock signal as both the first reference clock signal mux0 and the second reference clock signal mux2, and select either the (i+n / 2)-th clock signal or the (in / 2)-th clock signal as the target clock signal mux1; where 1≤i≤n.

[0066] In other words, in the first adjustment, one of the n clock signals (i.e., the i-th clock signal) can be randomly selected to serve as both the first reference clock signal mux0 and the second reference clock signal mux2. This results in the first reference clock signal mux0 and the second reference clock signal mux2 having a phase difference of 360°. Furthermore, a clock signal with a phase difference of 180° from the i-th clock signal (i.e., the (i+n / 2)-th clock signal or the (in / 2)-th clock signal) can be used as the target clock signal mux1.

[0067] For example, in the first adjustment, the first clock signal CLK0 can be selected as the first reference clock signal mux0 and the second reference clock signal mux2, which are 360° out of phase. Simultaneously, the fifth clock signal CLK4, which is 180° out of phase with the first clock signal CLK0, can be selected as the target clock signal mux1. Thus, based on the first clock signal CLK0, the delay of the fifth clock signal CLK4 can be adjusted.

[0068] Understandably, since the phase difference between each clock signal and itself is always 360°, meaning each clock signal differs from its own timing by one clock cycle, selecting one clock signal as both the first reference clock signal (mux0) and the second reference clock signal (mux2) ensures that the phase of the reference clock signals is already determined without requiring additional determination methods. This makes it relatively easy to select the first reference clock signal (mux0), the second reference clock signal (mux2), and the target clock signal (mux1) in the first adjustment, which helps simplify the circuit and improve efficiency.

[0069] In some embodiments of this disclosure, reference is made to Figure 3 The selection circuit 22 is also configured to, in subsequent adjustments, use the target clock signal mux1 from the previous adjustment to replace one of the first reference clock signal mux0 and the second reference clock signal mux2 from the previous adjustment to obtain the first reference clock signal mux0 and the second reference clock signal mux2 in the current adjustment, and select the target clock signal mux1 in the current adjustment based on the first reference clock signal mux0 and the second reference clock signal mux2 in the current adjustment, until the first reference clock signal mux0, the target clock signal mux1 and the second reference clock signal mux2 are adjacent clock signals.

[0070] For example, in the first adjustment, the first clock signal CLK0 can be selected as both the first reference clock signal mux0 and the second reference clock signal mux2, and the fifth clock signal CLK4 can be selected as the target clock signal mux1. Furthermore, in the second adjustment, the fifth clock signal CLK4 can be used as the second reference clock signal mux2, while the first clock signal CLK0 continues to be used as the first reference clock signal mux0, and the third clock signal CLK2, whose phase is between the two, can be selected as the target clock signal mux1. Furthermore, in the third adjustment, the third clock signal CLK2 can be used as the second reference clock signal mux2, while the first clock signal CLK0 continues to be used as the first reference clock signal mux0, and the second clock signal CLK1, whose phase is between the two, can be selected as the target clock signal mux1.

[0071] Since the first reference clock signal mux0 (CLK0), the target clock signal mux1 (CLK1), and the second reference clock signal mux2 (CLK2) in the third adjustment are already adjacent clock signals, no other unadjusted clock signal can be selected from among them. Therefore, in the fourth adjustment, other clock signals can be selected again. For example, in the fourth adjustment, the third clock signal CLK2 can be used as the first reference clock signal mux0, the fifth clock signal CLK4 can be used as the second reference clock signal mux2, and the fourth clock signal CLK3, whose phase is between the two, can be selected as the target clock signal mux1. This calibration completes the delay adjustment of the eight clock signals CLK<7:0>, eliminating the deviation between the multi-phase clock signals CLK<7:0>.

[0072] It is understandable that by sequentially reducing the phase difference between the first reference clock signal mux0 and the second reference clock signal mux2, fine-tuning of the target clock signal mux1 can be achieved. Simultaneously, adjustment of each clock signal in the multi-phase clock signal CLK<7:0> can be completed. This reduces or even eliminates the deviation between the multi-phase clock signals CLK<7:0>, improving calibration accuracy.

[0073] In some embodiments of this disclosure, reference is made to Figure 3 The included angle signals include: a first included angle signal mckt and a second included angle signal mckc. The merging circuit 23 is also configured to merge based on the phase difference between the first reference clock signal mux0 and the target clock signal mux1 to generate the first included angle signal mckt, and to merge based on the phase difference between the target clock signal mux1 and the second reference clock signal mux2 to generate the second included angle signal mckc.

[0074] Combination Figure 4 The pulse width of the first included-angle signal mckt is equal to the phase difference between the first reference clock signal mux0 and the target clock signal mux1, and the pulse width of the second included-angle signal mckc is equal to the phase difference between the target clock signal mux1 and the second reference clock signal mux2.

[0075] In this embodiment of the disclosure, combined with Figure 3 and Figure 4Certain logic gates can be set in the merging circuit 23 to perform certain logical operations on the first reference clock signal mux0, the target clock signal mux1, and the second reference clock signal mux2 to obtain the first included angle signal mckt and the second included angle signal mckc. For example, ANDing the inverted signals of the first reference clock signal mux0 and the target clock signal mux1 yields the first included angle signal mckt; ANDing the inverted signals of the target clock signal mux1 and the second reference clock signal mux2 yields the second included angle signal mckc.

[0076] In some embodiments of this disclosure, reference is made to Figure 3 The detection circuit 24 is further configured to extract the DC component of the first included angle signal mckt and the DC component of the second included angle signal mckc, compare them, and output a corresponding level delay control signal DCDC based on the comparison result. The adjustment circuit 21 is further configured to adjust the delay of the target clock signal mux1 until the level of the delay control signal DCDC jumps.

[0077] In this embodiment of the disclosure, reference is made to Figure 3 The level of the delay control signal DC-CDC generated by the detection circuit 24 reflects the comparison result of the DC component of the first included angle signal mckt and the DC component of the second included angle signal mckc. For example, if the DC component of the first included angle signal mckt is greater than the DC component of the second included angle signal mckc, the value of the delay control signal DC-CDC generated by the detection circuit 24 is 1 (i.e., high level), indicating that the phase difference between the first reference clock signal mux0 and the target clock signal mux1 is greater than the phase difference between the target clock signal mux1 and the second reference clock signal mux2. Correspondingly, if the DC component of the first included angle signal mckt is less than the DC component of the second included angle signal mckc, the value of the delay control signal DC-CDC generated by the detection circuit 24 is 0 (i.e., low level), indicating that the phase difference between the first reference clock signal mux0 and the target clock signal mux1 is less than the phase difference between the target clock signal mux1 and the second reference clock signal mux2.

[0078] Continue to refer to Figure 3The adjustment circuit 21 can adjust the delay of the target clock signal mux1 in response to the level of the delay control signal DCD. For example, if the delay control signal DCD is high, indicating that the phase difference between the first reference clock signal mux0 and the target clock signal mux1 is greater than the phase difference between the target clock signal mux1 and the second reference clock signal mux2, then the adjustment circuit 21 will adjust the delay of the target clock signal mux1, making the phase of the target clock signal mux1 closer to the second reference clock signal mux2, until the delay control signal DCD jumps from high to low. Conversely, if the delay control signal DCD is low, indicating that the phase difference between the first reference clock signal mux0 and the target clock signal mux1 is less than the phase difference between the target clock signal mux1 and the second reference clock signal mux2, then the adjustment circuit 21 will adjust the delay of the target clock signal mux1, making the phase of the target clock signal mux1 closer to the first reference clock signal mux0, until the delay control signal DCD jumps from low to high.

[0079] It should be noted that, in combination Figure 3 and Figure 7 Since the delay control signal DC-CDC cannot directly control the numerically controlled delay line BDL in the adjustment circuit 21, a conversion circuit 211 can be set in the adjustment circuit 21. The conversion circuit 211 can convert the delay control signal DC-CDC into a control signal for the numerically controlled delay line BDL.

[0080] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 The detection circuit 24 can use a DCM (Duty Cycle Monitor). The DCM can extract the DC component Int_flt of the first included angle signal mckt and the DC component Inc_flt of the second included angle signal mckc, and send them to comparator C1 for comparison; then, the comparison result of the output of comparator C1 is sampled by flip-flops FF1 and FF2 and output as a delay control signal DCDC.

[0081] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 The selector (mux) is configured to select the signal from the input DCM. The low-pass filter (LPF) is configured to filter the input DCM signal, suppressing high-frequency noise and preserving the effective low-frequency components.

[0082] In this embodiment of the disclosure, combined with Figure 5 and Figure 6The DCM logic control unit 241 is configured to provide a clamp signal Clamp, equalization control signals EqA / EqB, and a comparator peak signal Comp in response to the DCM module enable signal MdDCMEN, coordinating the duty cycle detection process. The clamp signal Clamp clamps the voltage to a fixed level to prevent abnormal voltage fluctuations from affecting circuit operation. The equalization control signals EqA / EqB control the equalization operation in comparator C1 after it completes comparison, ensuring that the charges at the two input terminals of comparator C1 are shared and balanced. The comparator peak signal Comp indicates the moment when comparator C1 detects that the input signal has reached its peak value.

[0083] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 DCMOSCEN is the DCM internal oscillator enable signal, used to control the start and stop of the internal oscillator, providing the DCM with an internal clock source or auxiliary clock. DCMOSC is the DCM internal oscillator output signal; when DCMOSCEN is active, this signal outputs the clock waveform generated by the oscillator.

[0084] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 By adjusting the digital delay line (BDL) in the circuit, the delay from the input terminal IN to the output terminal OUT can be determined according to the delay control signal DCDC.

[0085] In this embodiment of the disclosure, a typical implementation of the numerically controlled delay line (BDL) is to use gate delay and phase interpolator.

[0086] Gate delay describes the time offset of a signal from input to output when passing through a logic gate, including: rise delay (tpLH), fall delay (tpHL), and turn-off delay. Rise delay is the transition time from low to high level; fall delay is the transition time from high to low level; and turn-off delay is the transition time from active to high impedance state. Defining gate delays ensures that timing simulations match actual hardware behavior.

[0087] A phase interpolator is used to dynamically adjust the clock phase, achieving clock alignment and compensating for delay differences between channels. The phase interpolator generates an intermediate phase through digital control, achieving sub-picosecond phase resolution. The phase interpolator can work in conjunction with a DLL (Delay Locked Loop).

[0088] Understandably, accurate modeling of gate delays (such as tpLH / tpHL) provides an input timing reference for the phase interpolator, ensuring the reliability of clock signal phase adjustment.

[0089] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0090] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0092] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0093] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0094] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A clock signal calibration circuit, characterized in that, The calibration circuit includes: The adjustment circuit is configured to receive n clock signals with sequentially increasing phases, adjust the delay of a target clock signal among the n clock signals in response to a delay control signal, and transmit the n clock signals; n is an integer greater than 1. The selection circuit, coupled to the adjustment circuit, is configured to select a reference clock signal and the target clock signal from the n clock signals; A merging circuit, coupled to the selection circuit, is configured to merge based on the phase difference between the target clock signal and the reference clock signal to generate an angle signal; the angle signal includes: a first angle signal and a second angle signal; The detection circuit, coupled to the merging circuit, is configured to detect the duty cycle of the included angle signal and generate the delay control signal corresponding to the target clock signal, including: extracting the DC component of the first included angle signal and the DC component of the second included angle signal and comparing them, and outputting a delay control signal of the corresponding level according to the comparison result.

2. The clock signal calibration circuit according to claim 1, characterized in that, The reference clock signal includes: a first reference clock signal and a second reference clock signal; wherein, the adjustment target phase of the target clock signal is the average phase of the first reference clock signal and the second reference clock signal.

3. The clock signal calibration circuit according to claim 2, characterized in that, The selection circuit is further configured to select the first reference clock signal and the second reference clock signal from the clock signals whose phases have been determined; wherein the target clock signal corresponding to the first reference clock signal and the second reference clock signal is the unadjusted clock signal.

4. The clock signal calibration circuit according to claim 2, characterized in that, n=2 k k>0; the phases of the n clock signals differ by 360° / n sequentially; The selection circuit is further configured to, in the first adjustment, select the i-th clock signal as both the first reference clock signal and the second reference clock signal, and select either the (i+n / 2)-th clock signal or the (in / 2)-th clock signal as the target clock signal; 1≤i≤n.

5. The clock signal calibration circuit according to claim 4, characterized in that, The selection circuit is further configured to, in subsequent adjustments, use the target clock signal from the previous adjustment to replace one of the first reference clock signal and the second reference clock signal from the previous adjustment to obtain the first reference clock signal and the second reference clock signal in the current adjustment, and select the target clock signal in the current adjustment based on the first reference clock signal and the second reference clock signal in the current adjustment, until the first reference clock signal, the target clock signal, and the second reference clock signal are adjacent clock signals.

6. The clock signal calibration circuit according to claim 2, characterized in that, The merging circuit is further configured to merge based on the phase difference between the first reference clock signal and the target clock signal to generate the first included angle signal, and to merge based on the phase difference between the target clock signal and the second reference clock signal to generate the second included angle signal; wherein the pulse width of the first included angle signal is equal to the phase difference between the first reference clock signal and the target clock signal, and the pulse width of the second included angle signal is equal to the phase difference between the target clock signal and the second reference clock signal.

7. The clock signal calibration circuit according to claim 6, characterized in that, The adjustment circuit is further configured to adjust the delay of the target clock signal until the level of the delay control signal changes.

8. The clock signal calibration circuit according to claim 1, characterized in that, The adjustment circuit receives eight clock signals; The adjustment circuit includes: 8 numerically controlled delay lines; each of the numerically controlled delay lines adjusts and transmits a corresponding clock signal.

9. A high-bandwidth memory, characterized in that, The high-bandwidth memory includes: a base chip and multiple core chips stacked on the base chip; The base chip includes: a clock generation circuit and multiple channels; The clock generation circuit is coupled to the plurality of channels; the path delays between the clock generation circuit and the plurality of channels are not entirely the same. The clock generation circuit is configured to generate n clock signals with sequentially increasing phases and transmit the n clock signals to each of the channels; n is an integer greater than 1. Each of the plurality of channels includes: a clock signal calibration circuit as described in any one of claims 1 to 8.

10. The high-bandwidth memory according to claim 9, characterized in that, The multiple channels are arranged in a rows and b columns; a and b are both positive integers. The transmission path between the clock generation circuit and the plurality of channels includes: a main path and b branch paths connected to the main path; Each of the branch paths connects to a corresponding column of channels.

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