DDR memory control method, apparatus and device, and storage medium

Abstract

The invention discloses a control method, device and equipment of a DDR (Double Data Rate) memory and a storage medium. The method comprises the following steps: receiving command information sent by a user side through a DDR controller; target parameters of a transmission interface of the DDR controller are configured, and the target parameters comprise at least one of clock frequency, data bit width and burst length; and after the configuration of the target parameter is completed, sending the command information to a DDR (Double Data Rate) memory through the transmission interface so as to control the DDR memory to execute an operation corresponding to the command information. The access complexity of the DDR memory is reduced, and the access overhead is optimized.

Description

Technical Field

[0001] This invention relates to the field of DDR memory control, and more particularly to a DDR memory control method, apparatus, device, and storage medium. Background Technology

[0002] Control methods, apparatus, devices, and storage media for DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memory.

[0003] DDR memory is complex to use and incurs additional overhead. Internally, DDR uses a hierarchical BANK-ROW-COLUMN structure. To access a memory cell, its corresponding BANK-ROW must first be activated, and then a certain time must be waited before a read / write operation can be performed. There are also timing constraints for adjacent read / write operations. To access other rows within the same BANK, the current BANK must be closed first. Furthermore, to prevent data loss in DDR memory, it needs to be periodically refreshed (REF). All BANKs must be closed before each refresh. Therefore, DDR memory access is complex and incurs significant overhead. Summary of the Invention

[0004] This invention provides a control method, apparatus, device, and storage medium for DDR memory to solve the problems of high complexity and high overhead in accessing DDR memory.

[0005] According to one aspect of the present invention, a control method for a DDR memory is provided, the method comprising:

[0006] Receive command information sent by the user terminal through the DDR controller;

[0007] Configure the target parameters of the DDR controller's transmission interface, wherein the target parameters include at least one of clock frequency, data bit width, and burst length;

[0008] After configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform the operation corresponding to the command information.

[0009] According to another aspect of the present invention, a control device for a DDR memory is provided, the device comprising:

[0010] The command receiving module is used to receive command information sent by the user terminal through the DDR controller;

[0011] The parameter configuration module is used to configure the target parameters of the DDR controller transmission interface, wherein the target parameters include at least one of clock frequency, data bit width and burst length;

[0012] The control module is used to send the command information to the DDR memory through the transmission interface after the target parameters are configured, so as to control the DDR memory to perform the operation corresponding to the command information.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] At least one processor; and

[0015] A memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the DDR memory control method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the control method of the DDR memory according to any embodiment of the present invention.

[0018] The technical solution of this invention involves receiving command information sent by the user terminal through a DDR controller, enabling effective interaction between the user terminal and the DDR memory. Then, target parameters of the DDR controller's transmission interface are configured, including at least one of clock frequency, data bit width, and burst length, allowing the DDR controller to better adapt to various application requirements. Finally, after configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform operations corresponding to the command information. By flexibly configuring command information and target parameters, diverse operations on the DDR memory can be achieved, meeting the needs of different system functions. This solves the problem of high complexity and high overhead in DDR memory access, achieving the beneficial effects of reducing DDR memory access complexity and optimizing access overhead.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a control method for a DDR memory according to Embodiment 1 of the present invention;

[0022] Figure 2a This is a flowchart of a control method for a DDR memory according to Embodiment 2 of the present invention;

[0023] Figure 2b This is a schematic diagram of a DDR memory structure, representing an optional example of a control method for a DDR memory according to Embodiment 2 of the present invention.

[0024] Figure 2c This is a schematic diagram of small-capacity channel space allocation, which is an optional example of a control method for a DDR memory provided in Embodiment 2 of the present invention.

[0025] Figure 2d This is a schematic diagram of large-capacity channel space allocation, which is an optional example of a DDR memory control method provided in Embodiment 2 of the present invention.

[0026] Figure 3 This is a schematic diagram of the structure of a control device for a DDR memory according to Embodiment 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of an electronic device that implements the control method for the DDR memory according to an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] Example 1

[0031] Figure 1 This invention provides a flowchart of a seismic analysis method for buried pipelines in tunnels, as shown in Embodiment 1. This embodiment is applicable to seismic analysis of buried pipelines in tunnels. The method can be executed by a seismic analysis device for buried pipelines in tunnels, which can be implemented in hardware and / or software and can be configured in an electronic device. For example... Figure 1 As shown, the method includes:

[0032] S110: Receives command information sent by the user terminal through the DDR controller.

[0033] The DDR controller can be understood as the various parameters associated with the buried pipeline. It can also be understood as the core hardware module that manages the data interaction between DDR memory (such as DDR3) and external devices (such as CPU, FPGA, or user terminal). The user terminal refers to the device that sends command information.

[0034] Specifically, the user terminal sends command packets to the DDR controller via the bus protocol, including operation type, address information, data length, and other control signals (such as priority, caching strategy, etc.). The DDR controller parses the command packets, extracts key information, and generates internal control signals.

[0035] For example, the controller supports the following user-side commands (the 3-bit binary code corresponding to the command is in parentheses): set command, activate command, write command, read command, precharge command, and refresh command. The controller will discard any undefined encoded value of 0.

[0036] The receiving interface module includes a first receiving interface, a second receiving interface, and a third receiving interface. The third receiving interface is used to receive data read from the DDR memory. Receiving command information sent by the user terminal through the DDR controller includes:

[0037] Receive the first command information sent by the user terminal through the first receiving interface, or

[0038] The second command information sent by the user terminal is received through the second receiving interface.

[0039] The first command information can be understood as command information excluding the write command. The second command information can be understood as command information for the write command.

[0040] Specifically, the interfaces between the controller and the user module include a first receiving interface cmd_fifo, a second receiving interface wrdata_fifo, and a third receiving interface rddata_fifo. cmd_fifo is used to transmit user logic commands to the controller; wrdata_fifo is used to transmit data corresponding to write commands to the controller; and rddata_fifo is used to obtain read command data from the controller.

[0041] Optionally, the command information includes command type and address information; the command type includes at least one of initialization command, mode register setting command, activation command, write command, read command, precharge command, and refresh command; the address information includes at least one of Bank memory address, row address, and column address.

[0042] S120. Configure the target parameters of the DDR controller transmission interface, wherein the target parameters include at least one of clock frequency, data bit width and burst length.

[0043] Here, clock frequency can be understood as the reference frequency for synchronous communication between the DDR controller and the memory. Data bit width can be understood as the number of binary bits in each data transfer. Burst length refers to the number of consecutive data transfers.

[0044] Specifically, select the base clock frequency based on the memory specifications. Generate a stable clock signal using a PLL (Phase-Locked Loop) and adjust timing parameters to meet memory specifications. Select the bit width based on the physical interface of the memory chips. If using multiple memory chips, high bandwidth can be achieved through bit extension. Select the burst length based on the memory type and application scenario. Configure the burst length parameter in the Mode Register (MRS).

[0045] S130. After configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform the operation corresponding to the command information.

[0046] Specifically, the DDR controller encapsulates the commands to be executed (such as activation commands, write commands, read commands, etc.) and related address information (bank address, row address, column address). According to the DDR protocol specification, the commands and addresses are encoded to generate a signal sequence that meets transmission requirements. Using the configured transmission interface (including clock signals, command / address bus, data bus, etc.), the encoded commands and address information are sent to the DDR memory. During transmission, the timing, level, and drive strength of the signals are ensured to meet the interface requirements of the DDR memory. Upon receiving the signal from the DDR controller, the DDR memory first decodes the signal to identify the command type and address information. Based on the decoding result, the DDR memory's internal state machine or control logic begins to execute the corresponding operation. The DDR memory executes the corresponding operation according to the command type, such as activating a specified bank and row, writing or reading data, or closing an activated row. During execution, the DDR memory may feed back status information to the DDR controller (such as operation completion signals, error signals, etc.) so that the DDR controller can perform subsequent processing or adjustments.

[0047] The technical solution of this invention involves receiving command information sent by the user terminal through a DDR controller, enabling effective interaction between the user terminal and the DDR memory. Then, target parameters of the DDR controller's transmission interface are configured, including at least one of clock frequency, data bit width, and burst length, allowing the DDR controller to better adapt to various application requirements. Finally, after configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform operations corresponding to the command information. By flexibly configuring command information and target parameters, diverse operations on the DDR memory can be achieved, meeting the needs of different system functions. This solves the problem of high complexity and high overhead in DDR memory access, achieving the beneficial effects of reducing DDR memory access complexity and optimizing access overhead.

[0048] Example 2

[0049] Figure 2a This is a flowchart of a control method for a DDR memory according to Embodiment 2 of the present invention. This embodiment is a further optimization of how the command information is sent to the DDR memory through the target interface in the above embodiments. Optionally, sending the command information to the DDR memory through the target interface includes: sending the command information to the DDR memory based on a single-edge mode and an output serial-to-parallel converter.

[0050] like Figure 2a As shown, the method includes:

[0051] S210 receives command information sent by the user terminal through the DDR controller.

[0052] Optionally, the DDR controller includes a receiving interface module connected to the user terminal, a transmitting interface module connected to the DDR memory, and a state machine module connected to the receiving interface module and the transmitting interface module respectively; wherein, the state machine module includes an initialization state machine and a main state machine; the initialization state machine is a sub-state machine of the main state machine.

[0053] For example, Figure 2b This is a schematic diagram of a DDR memory structure, representing an optional example of a DDR memory control method according to Embodiment 2 of the present invention. The interfaces between the controller and the user module include a first receiving interface cmd_fifo, a second receiving interface wrdata_fifo, and a third receiving interface rddata_fifo. INIT_FSM and MAIN_FSM are the initialization state machine and the main state machine, respectively. PHY is the transmission interface.

[0054] The cascading of the DDR controller logic is limited by the operating frequency of the FPGA (Field-Programmable Gate Array Logic). The user logic runs at 200MHz, while the DDR interface clock runs at 800MHz. DDR supports an access burst of 8, meaning one read / write command corresponds to 64 bits * 8 = 512 bits of data. Both wrdata_fifo and rddata_fifo have a bit width of 512 bits. Specifically, INIT_FSM and MAIN_FSM are the initialization state machine and the main state machine, respectively. The former acts as a sub-state machine of the latter, and the main state machine's other states only run after INIT_FSM completes. Due to the 1:4 relationship between the controller logic and the DDR physical clock, four DDR commands need to be processed within one controller logic clock cycle. For INIT_FSM, since it's a relatively simple initialization sequence, a single-cycle approach is used to process only one DDR command. For MAIN_FSM, four combinational logic (state machines) are cascaded to achieve the 1:4 logic ratio.

[0055] For example, the initialization state machine transitions, with each state corresponding to the control state of a DDR signal line. The state machine is configured with two counters, init_cnt0 and init_cnt1, to control state delays and transitions. int_cnt0 increments by 4 during RESET, NOP, MRS3 and MRS0, ZQCL, and ZQCL_DONE (accumulated value is 4), and is cleared in other states. int_cnt1 increments by 4 during RESET_POST, MRS2 and MRS1, and ZQCL (accumulated value is 4), and is cleared in other states. The main state machine transition diagram is shown. The main state machine controls the low-level commands sent to the DDR. When the main state machine is in the INIT state, it uses the control commands output by the INIT state machine. In other states, it uses the outputs of this state machine. The basic commands sent to DDR include NOP (no-operation instruction), ACT (activation command), WR (WR_AP) (write instruction), RD (RD_AP) (read instruction), PRE (precharge instruction), REF (refresh instruction), MRS (mode register set instruction), RESET (reset command, only initializes the INIT state), and ZQCL (ZQ calibration long command, only in the INIT state).

[0056] It's worth noting that these basic commands must conform to the timing requirements of DDR devices. Constraints related to the INIT state are already satisfied in INIT_FSM using a delay counter. Other constraints, applicable only to the main state, are implemented using different types of timing constraint registers.

[0057] S220. Configure the target parameters of the DDR controller transmission interface, wherein the target parameters include at least one of clock frequency, data bit width and burst length.

[0058] S230. After configuring the target parameters, the command information is sent to the DDR memory based on the single-edge mode and the output serial-to-parallel converter to control the DDR memory to perform the operation corresponding to the command information.

[0059] In this context, single-edge mode can be understood as the DDR controller triggering the transmission of data or commands on a single edge of the clock signal (usually the rising or falling edge). The output serial-to-parallel converter can be understood as a circuit module that converts parallel data into serial data (or vice versa).

[0060] Specifically, command information exists in parallel form in the internal registers or bus of the DDR controller, and the output serial-to-parallel converter converts the parallel command information into a serial signal. During the conversion process, clock synchronization and phase alignment must be ensured to avoid data errors. In single-edge mode, the DDR controller triggers the transmission of serial command information on a single edge of the clock signal (such as the rising edge). After receiving the serial signal, the DDR memory restores it to parallel command information through its internal serial-to-parallel converter. The DDR memory executes corresponding operations based on the received command information, such as activating a specified bank and row, writing or reading data, and closing an activated row. During execution, the DDR memory feeds back status information (such as operation completion signals, error signals, etc.) to the DDR controller so that the DDR controller can perform subsequent processing or adjustments. The DDR controller receives the feedback signals from the DDR memory and checks whether the operation was successfully completed. If an error occurs (such as timing violation, data error, etc.), the DDR controller will take appropriate recovery measures (such as retrying the operation, reporting the error, etc.). Depending on system requirements, the DDR controller may adjust the generation and transmission strategy of command information to optimize performance.

[0061] Optionally, the step of sending the command information to the DDR memory based on single-edge mode and output serial-to-parallel converter includes:

[0062] The command information is sent to the DDR memory based on preset timing constraints, single-edge mode, and output serial-to-parallel converter.

[0063] Among them, the preset timing constraints refer to the timing rules and parameters that must be followed when the DDR controller and DDR memory communicate.

[0064] Specifically, the DDR controller checks the transmission timing of command information according to preset timing constraints (such as tCL, tRP, tRAS, etc.). This ensures that command information is sent and received within the correct clock cycle, avoiding operational failures caused by timing violations.

[0065] Understandably, DDR memory has extremely strict timing requirements; the sending of commands and addresses must follow precise timing specifications.

[0066] For example, the DDR timing constraints and the implemented register structure are as follows:

[0067] The timing constraints related to the ACTIVATE command are as follows:

[0068] (1) Adjacent ACTIVATE commands with the same target BANK must have an interval of no less than tRC (tRC = 48.75ns = 39T).

[0069] To satisfy condition (1), configure an act command saturation counter cnt_act for each bank.

[0070] When there is new

[0071] When the `act` command is executed, the `cnt_act` value of the corresponding bank is cleared to zero; otherwise, it is accumulated until it reaches saturation at `tRC-1`.

[0072] (2) The interval between adjacent ACTIVATE commands with different target banks is not less than tRRD (tRRD = max(4T, 7.5ns) = 6T).

[0073] (3) The time window of four consecutive ACTIVATE commands must be greater than tFAW (tFAW = max(40ns, 32T) = 32T).

[0074] To satisfy constraints (2) and (3), a set of four saturation counters (cnt_faw0~3) are configured. cnt_faw0~3 are used to record the times of the four most recently executed activate commands, with cnt_faw0 corresponding to the first executed activate command. The saturation values ​​of the four counters are set to tFAW-1, tFAW-tRRD-1, tFAW-2*tRRD-1, and tFAW-3*tRRD-1, respectively. When a newly executed act command is encountered, cnt_faw3 is cleared, and cnt_faw_i = cnt_faw_(i+1)+1 (i = 0~2); otherwise, cnt_faw0~3 are incremented until saturation.

[0075] (4) The interval between the PRECHARGE command and the target BANK is not less than tRP(11T).

[0076] To satisfy constraint (4), a pre-command saturation counter cnt_pre is configured for each bank. When a new precharge command is executed (including the RD_AP interval tRTP time and the WR_AP interval tWR time), the cnt_pre of the corresponding ank is cleared to zero. Otherwise, it is accumulated until it reaches tRP-1 and becomes saturated.

[0077] An act command can be executed if the following conditions are met.

[0078] (1) The cnt_act of the corresponding bank is saturated (=tRC-1)

[0079] (2)cnt_faw3>=(tRRD-1)

[0080] (3) cnt_faw0 is saturated (=tFAW-1)

[0081] (4) The corresponding bank's cnt_pre is saturated (=tRP-1)

[0082] b. For the READ (including RD_AP) and WRITE (including WR_AP) commands, the relevant constraints are:

[0083] (1) The BANK / ROW corresponding to the read / write command is in the ACTIVE state.

[0084] To meet the constraints, configure the bank_act and act_row registers for each bank.

[0085] The `bank_act` register is used to indicate whether each bank is in the `activate` state. It is set to 1 when the `activate` command is executed and cleared to 0 when the `precharge` command is executed. The `act_row` register is used to record the row address opened by the `activate` command in each bank. It is updated to the row number in the command when the `activate` command is executed.

[0086] (2) The distance to the corresponding ACT command of the BANK is not less than tRCD (active to internal r / w; 13.75ns = 11T)

[0087] This constraint can be satisfied by using the previously defined cnt_act register.

[0088] (3) For the READ command, the distance to the nearest READ command is not less than tCCD(4T); the distance to the nearest WRITE command is not less than tWR2RD=tWTR+CWL+BL / 2(8T+4T=12T).

[0089] (4) For the WRITE command, the distance to the nearest WRITE command is not less than tCCD(4T); the distance to the nearest READ command is not less than tRD2WR=RL+tCCD+2T-WL(11T+4T+2T-8T=9T)

[0090] For constraints (3) and (4), two global saturation counters, cnt_wr_all and cnt_rd_all, are set to record the times of the most recent WRITE and READ commands, respectively.

[0091] When the WRITE command is executed for any BANK, cnt_wr_all is cleared to zero; otherwise, it is incremented until it reaches tWR2RD-1, at which point it saturates.

[0092] When the READ command of any BANK is executed, cnt_rd_all is cleared to zero; otherwise, it is accumulated until it reaches tRD2WR, at which point it becomes saturated.

[0093] The READ command can be executed if the following conditions are met:

[0094] (1) The corresponding bank_act = 1; the corresponding act_row is the same as the command to be executed.

[0095] (2) The corresponding bank's cnt_act>=tRCD-1

[0096] (3)cnt_rd_all>=tCCD-1

[0097] (4) cnt_wr_all>=tWR2RD-1

[0098] The WRITE command can be executed if the following conditions are met:

[0099] (1) The corresponding bank_act = 1; the corresponding act_row is the same as the command to be executed.

[0100] (2) The corresponding bank's cnt_act>=tRCD-1

[0101] (3)cnt_wr_all>=tCCD-1

[0102] (4)cnt_rd_all>=tRD2WR-1

[0103] c. The PRECHARGE command must meet the following constraints:

[0104] (1) The distance to the ACTIVATE command of the corresponding BANK conforms to the tRAS parameter (tRASmin=35ns=28T, tRASmax=9*tREFI).

[0105] For PRECHARGE, only the tRASmin parameter is considered; the tRASmax parameter is guaranteed by the REFRESH operation. The previously defined cnt_act can be used to constrain this condition.

[0106] (1) The distance between the WRITE command and the corresponding bank is not less than tWR (15ns = 12T).

[0107] To satisfy this constraint, a saturation counter cnt_wr is set for each bank to record the time of the WRITE command. When the WRITE command is executed, the corresponding cnt_wr is cleared to zero; otherwise, it is incremented until it reaches tWR-1, at which point it saturates.

[0108] (2) The distance between the READ command and the corresponding bank is not less than tRTP({max(4CK,7.5ns)=6T}

[0109] To satisfy this constraint, a saturation counter cnt_rd is set for each bank to record the time of the READ command. When the READ command is executed, the corresponding cnt_rd is cleared to zero; otherwise, it is incremented until it reaches tRTP-1, at which point it saturates.

[0110] The PRECHARGE command can be executed if the following conditions are met.

[0111] (1) The corresponding cnt_act >= tRASmin-1. If it is a PRECHARGE ALL command, then the cnt_act of all banks must meet the condition.

[0112] (2) The cnt_wr of the corresponding bank is saturated (=tWR-1). If it is a PRECHARGE ALL command, then the cnt_wr of all banks must meet the condition.

[0113] (3) The cnt_rd of the corresponding bank is saturated (=tRD-1). If it is the PRECHARGE ALL command, then the cnt_rd of all banks must meet the condition.

[0114] d. To prevent data loss in DDR storage, a refresh (REFRESH) operation is required. For a REF operation to occur, the following conditions must be met:

[0115] (1) Before refreshing, all banks must be closed.

[0116] The previously defined bank_act and cnt_pre can be used to satisfy constraint (1).

[0117] (2) The idle time after the refresh command is not less than tRFC_min(max(110ns,88T)=88T)

[0118] Set a saturation counter cnt_ref to satisfy constraint (2). When the REF command is executed, cnt_ref is cleared to zero; otherwise, it is incremented until it reaches tRFC_min-1, at which point it saturates.

[0119] (3) The average interval between adjacent refreshes is tREFI (when the chip surface temperature Tc < 85 degrees, tREFI = 64ms / 8192 = 7.8us; when the chip surface temperature Tc > 85 degrees, tREFI = 32ms / 8192 = 3.9us).

[0120] For constraint (3), set the loop counter cnt_ref and the refresh request counter cnt_ref_req.

[0121] The loop counter range of cnt_refi is 0 to tREFI-1. When cnt_refi = tREFI-1, cnt_refreq is incremented. A refresh command from the user side can cancel one increment of cnt_refreq.

[0122] (4) At least 9 refresh commands must be given within the 9*tREFI time window, that is, the maximum interval between adjacent refreshes is approximately 9*tREFI; a maximum of 8 consecutive refresh commands can be given.

[0123] For constraint (4), the method of giving m consecutive refresh commands every m*tREFI time (m<=8) is used to satisfy it.

[0124] Each refresh corresponds to a preceding PRECHARGE ALL command. Increasing m by 1 can save tRP time overhead, but increases the command bus interrupt time of tRFC_min.

[0125] The configurable parameter 'm' can be selected based on the user's tolerance for partial command interruption time and the balance between overall overhead.

[0126] A REF command from the user side or `cnt_refreq=m` can trigger a REF operation to be executed. For a REF command to be executed, it can be executed if the following conditions are met:

[0127] (1) For all banks, bank_act = 0, and cnt_pre is saturated (= tRP-1).

[0128] (2) cnt_ref saturation (=tRFC_min-1)

[0129] e. For the MRS command, the relevant constraints are:

[0130] (1) All banks are closed.

[0131] The previously defined counters bank_act and cnt_pre can satisfy constraint (1).

[0132] (2) The interval between adjacent MRS commands shall not be less than tMRD(4T).

[0133] (3) The interval between other commands and the MRS command is not less than tMOD.

[0134] For constraints (2) and (3), set cnt_mrs. When executing the MRS command, cnt_mrs is cleared to zero; otherwise, it is accumulated until it reaches tMOD and becomes saturated.

[0135] For an MRS command to be executed, it can be executed if a series of conditions are met:

[0136] (1) When all banks_act = 0, cnt_pre is saturated (= tRP-1).

[0137] (2) cnt_mrs>=tMRD-1

[0138] Optionally, after sending the command information to the DDR memory through the target interface, the method further includes: receiving the data sent by the DDR memory based on a dual-edge mode and an input serial-to-parallel converter.

[0139] Dual-edge mode refers to the DDR controller triggering data transmission simultaneously on both the rising and falling edges of the clock signal. An input serial-to-parallel converter is a circuit module that converts high-speed serial signals into low-speed parallel signals.

[0140] Specifically, after receiving a command (such as a read command) from the DDR controller, the DDR memory reads data from the specified address according to the command requirements. The read data is converted into a serial signal by the DDR memory's output serial-to-parallel converter and sent to the DDR controller through a high-speed serial interface. In dual-edge mode, the DDR controller receives the serial data sent by the DDR memory simultaneously on both the rising and falling edges of the clock signal. Dual-edge mode requires the DDR controller to have precise timing control capabilities to ensure that data is correctly sampled on both the rising and falling edges. The DDR controller's input serial-to-parallel converter converts the received serial data into parallel data. During the conversion process, the input serial-to-parallel converter needs to recover the clock signal from the serial data and ensure the phase alignment of the parallel data to avoid data errors. The converted parallel data is stored in the DDR controller's internal registers or bus for subsequent processing. The DDR controller verifies the received parallel data to ensure its integrity and correctness. If a data error is detected (such as a CRC check failure), the DDR controller may take measures such as retrying or reporting the error. Data that passes the verification is passed to other parts of the system (such as the CPU, GPU, etc.) for processing. The DDR controller may send feedback signals to the DDR memory to indicate the data reception status (such as success or failure).

[0141] Depending on system requirements and the state of the DDR memory, the DDR controller may adjust subsequent data transfer strategies (such as adjusting the clock frequency, changing the transfer mode, etc.) to optimize performance.

[0142] Optionally, on the PHY interface, for addresses and commands, a single-edge mode is used to transmit to the DDR device, using the 1:4 mode of OSERDES; for data, a bidirectional dual-edge mode is used, with DQ and DQS implemented using the 1:8 mode of ISERDES and OSERDES.

[0143] Furthermore, by exposing the underlying commands to the user side, the user side can allocate address space reasonably according to the characteristics of specific data storage; during idle time, PRE and REF operations can be generated proactively, thereby reducing the overhead introduced by the forced operation of the underlying controller.

[0144] Optionally, multiple BANKs (e.g., 8 BANKs) of DDR can be used to reduce row switching and form a multi-BANK alternating access method, thereby reducing the PRE (precharge)-RE_ACT (reactivation) overhead introduced by cross-row access within the same BANK and making the access process more continuous.

[0145] Optionally, DDR is typically used as a multi-channel cache. Allocation strategies for different channel capacities: Figure 2c This is a schematic diagram of small-capacity channel space allocation, representing an optional example of a DDR memory control method according to Embodiment 2 of the present invention; as shown. Figure 2c As shown, for small-capacity channels (<<8kB): using an auxiliary... Figure 2c The space allocation method shown on the left ensures that read and write operations of adjacent channels are located in the same row of the same BANK or different BANKs, avoiding cross-row operations within the same BANK and achieving continuous access without additional overhead.

[0146] Figure 2d This is a schematic diagram of large-capacity channel space allocation, representing an optional example of a DDR memory control method according to Embodiment 2 of the present invention; as shown. Figure 2d As shown, high-capacity channels (>4KB): using attached... Figure 2d The address allocation method shown on the left prioritizes allocating multiple blocks of a single channel to a single line of multiple banks. If a single line is insufficient, it is then allocated to multiple lines. For banks with multiple lines, a PRE or AutoPre command is added at the end of the block read / write operation, and an ACT command for subsequent lines is added in the subsequent process. Only the overhead of the command itself is introduced, and the command latency is hidden by using the line-spanning method.

[0147] In this embodiment of the invention, the user side can proactively generate PRE (precharge) and REF (refresh) operations during idle time, reducing the overhead introduced by forced operations from the underlying controller. This helps balance the access load of the DDR memory and improve overall performance.

[0148] For example, the DDR structure is 8 (bk) * 8K (row) * 1K (col) * 64 bits. The 8 banks are relatively independent units, and each bank can only have one row in the open (ACT) state. Read and write operations can be performed directly on the open rows. The capacity of one row is 1K * 64 bits = 8KBytes. The time for a global read + write operation on all 8 banks with open rows is (8 * 1K * 1.25ns / 2) * 2 = 10.24us. Assuming tREFI = 7.8us, this time is between 1 and 2 tREFI.

[0149] When allocating addresses, access overhead is reduced by minimizing row switching and forming a multi-bank alternation method.

[0150] The technical solution of this invention transmits the command information to the DDR memory using a single-edge mode and an output serial-to-parallel converter. The single-edge mode triggers data transmission only on a single edge of the clock signal (e.g., the rising edge), avoiding the complex timing alignment and phase control problems of the dual-edge mode (rising and falling edges). Through parallel-to-serial conversion technology, multiple parallel command signals are combined into a single high-speed serial signal, reducing the number of physical connection pins between the DDR controller and the DDR memory, thus lowering hardware costs and wiring complexity. Reduced dynamic power consumption improves the reliability of data transmission.

[0151] Example 3

[0152] Figure 3 This is a schematic diagram of a control device for a DDR memory provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes a command receiving module 310, a parameter configuration module 320, and a control module 330.

[0153] The command receiving module 310 is used to receive command information sent by the user terminal through the DDR controller; the parameter configuration module 320 is used to configure the target parameters of the DDR controller transmission interface, wherein the target parameters include at least one of clock frequency, data bit width and burst length; and the control module 330 is used to send the command information to the DDR memory through the transmission interface after the target parameters are configured, so as to control the DDR memory to perform the operation corresponding to the command information.

[0154] The technical solution of this invention involves receiving command information sent by the user terminal through a DDR controller, enabling effective interaction between the user terminal and the DDR memory. Then, target parameters of the DDR controller's transmission interface are configured, including at least one of clock frequency, data bit width, and burst length, allowing the DDR controller to better adapt to various application requirements. Finally, after configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform operations corresponding to the command information. By flexibly configuring command information and target parameters, diverse operations on the DDR memory can be achieved, meeting the needs of different system functions. This solves the problem of high complexity and high overhead in DDR memory access, achieving the beneficial effects of reducing DDR memory access complexity and optimizing access overhead.

[0155] Optionally, the DDR controller includes a receiving interface module connected to the user terminal, a transmitting interface module connected to the DDR memory, and a state machine module connected to the receiving interface module and the transmitting interface module respectively; wherein, the state machine module includes an initialization state machine and a main state machine; the initialization state machine is a sub-state machine of the main state machine.

[0156] Optionally, the receiving interface module includes a first receiving interface, a second receiving interface, and a third receiving interface, wherein the third receiving interface is used to receive data read from the DDR memory; correspondingly, the command receiving module includes:

[0157] The first receiving unit is configured to receive first command information sent by the user terminal through the first receiving interface, or

[0158] The second receiving unit is used to receive the second command information sent by the user terminal through the second receiving interface.

[0159] Optionally, the command information includes command type and address information; the command type includes at least one of initialization command, mode register setting command, activation command, write command, read command, precharge command, and refresh command; the address information includes at least one of bank address, row address, and column address.

[0160] Optionally, the control module is specifically used for:

[0161] The command information is sent to the DDR memory based on single-edge mode and output serial-to-parallel converter.

[0162] Optionally, the control module is specifically used for:

[0163] The command information is sent to the DDR memory based on preset timing constraints, single-edge mode, and output serial-to-parallel converter.

[0164] Optionally, the device further includes:

[0165] The receiving module is configured to receive data sent by the DDR memory based on a dual-edge mode and an input serial-to-parallel converter after the command information is sent to the DDR memory through the target interface.

[0166] The control device for DDR memory provided in the embodiments of the present invention can execute the control and analysis method for DDR memory provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0167] Example 4

[0168] Figure 4 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0169] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0170] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0171] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the control of DDR memory.

[0172] In some embodiments, control of the method DDR memory can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method DDR memory control described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform method DDR memory control by any other suitable means (e.g., by means of firmware).

[0173] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0174] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0175] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0176] To provide interaction with a service recipient, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the service recipient; and a keyboard and pointing device (e.g., a mouse or trackball) through which the service recipient can provide input to the electronic device. Other types of devices can also be used to provide interaction with the service recipient; for example, feedback provided to the service recipient can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the service recipient can be received in any form (including voice input, speech input, or tactile input).

[0177] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., service-seeking computers with a graphical service-seeking interface or a web browser through which the service-seeking party can interact with the implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0178] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0179] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0180] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A control method for a DDR memory, characterized in that, include: Receive command information sent by the user terminal through the DDR controller; Configure the target parameters of the DDR controller's transmission interface, wherein the target parameters include at least one of clock frequency, data bit width, and burst length; After configuring the target parameters, the command information is sent to the DDR memory through the transmission interface to control the DDR memory to perform the operation corresponding to the command information.

2. The method according to claim 1, characterized in that, The DDR controller includes a receiving interface module connected to the user terminal, a transmitting interface module connected to the DDR memory, and a state machine module connected to both the receiving interface module and the transmitting interface module; wherein, the state machine module includes an initialization state machine and a main state machine; the initialization state machine is a sub-state machine of the main state machine.

3. The method according to claim 2, characterized in that, The receiving interface module includes a first receiving interface, a second receiving interface, and a third receiving interface, wherein the third receiving interface is used to receive data read from the DDR memory; The process of receiving command information sent by the user terminal through the DDR controller includes: Receive the first command information sent by the user terminal through the first receiving interface, or The second command information sent by the user terminal is received through the second receiving interface.

4. The method according to claim 1, characterized in that, The command information includes command type and address information; the command type includes at least one of initialization command, mode register setting command, activation command, write command, read command, precharge command and refresh command; the address information includes at least one of bank address, row address and column address.

5. The method according to claim 1, characterized in that, Sending the command information to the DDR memory through the target interface includes: The command information is sent to the DDR memory based on single-edge mode and output serial-to-parallel converter.

6. The method according to claim 5, characterized in that, The method of sending the command information to the DDR memory based on single-edge mode and output serial-to-parallel converter includes: The command information is sent to the DDR memory based on preset timing constraints, single-edge mode, and output serial-to-parallel converter.

7. The method according to claim 5, characterized in that, After sending the command information to the DDR memory through the target interface, the process further includes: Data sent by the DDR memory is received based on a dual-edge mode and an input serial-to-parallel converter.

8. A control device for a DDR memory, characterized in that, include: The command receiving module is used to receive command information sent by the user terminal through the DDR controller; The parameter configuration module is used to configure the target parameters of the DDR controller transmission interface, wherein the target parameters include at least one of clock frequency, data bit width and burst length; The control module is used to send the command information to the DDR memory through the transmission interface after the target parameters are configured, so as to control the DDR memory to perform the operation corresponding to the command information.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the control method of the DDR memory according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the control method for the DDR memory as described in any one of claims 1-7.

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