Data transmission method and device based on MII (Media Independent Interface)
By detecting the valid data signal status and counter value control at the MII interface receiver, the problem of low data transmission efficiency of the MII interface was solved, and efficient and stable data transmission was achieved.
Patent Information
- Application Number
- CN202510975937.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-15
- Publication Date
- 2025-10-31
AI Technical Summary
In existing technologies, the MII interface has low data transmission efficiency, especially since it needs to store half the data in the buffer before converting it into 100M frame data, resulting in latency and low efficiency.
By detecting the valid data signal status at the MII interface receiver, a pulse enable signal is generated. The counter value is used to control data sampling and parallel-to-serial conversion operations, thereby reducing latency and improving data transmission efficiency.
It achieves efficient conversion of MII interface data transmission, reduces latency, improves data transmission efficiency and stability, and lowers the error rate.
Smart Images
Figure CN120872884A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data transmission technology, and in particular to a data transmission method and apparatus based on an MII interface. Background Technology
[0002] The MII interface is an interface that provides data transmission between the MAC (Media Access Control) layer and the PHY (Physical Layer) layer. Existing technology typically sets up a data buffer at the receiving end of the MII interface to temporarily store data received by the MAC layer. When the MII interface receives data sent by the PHY layer, it checks the status of the valid data edge at the rising edge of the receive clock RX_CLK. If the valid data signal RX_DV is high, it indicates that the currently received data is valid. The data on the data signals RXD[3:0] of the MII interface's data receive line is then read and stored in the data buffer until all the required data has been received, i.e., the valid data signal RX_DV goes low. However, during data reception, the data is first stored in the buffer, and several sets of data need to be stored, typically half the buffer capacity. Then, the data is read from the buffer, which is in the 25MHz clock domain, and finally converted into 100MHz frame data, resulting in low data transmission efficiency for the MII interface.
[0003] In conclusion, improving the data transmission efficiency of the MII interface is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] In view of this, this application provides a data transmission method and apparatus based on the MII interface, which aims to improve the data transmission efficiency of the MII interface.
[0005] Firstly, this application provides a data transmission method based on the MII interface, comprising:
[0006] Detect the status of the valid data signal at the receiving end of the MII interface;
[0007] When the data valid signal is at a low level, a pulse enable signal is generated;
[0008] The counter state is determined based on the pulse enable signal, and the counter value is obtained.
[0009] When the counter value is the first count value, the data signal received by the MII interface is sampled.
[0010] When the counter value is the second count value, the sampled data signal is converted from parallel to serial to obtain serial data.
[0011] Output the serial data.
[0012] Optionally, before detecting the status of the valid data signal at the receiving end of the MII interface, the method further includes:
[0013] The target clock signal is obtained by synchronously sampling the received clock signal using a data sampling clock.
[0014] Optionally, the step of synchronously sampling the received clock signal using a data sampling clock to obtain the target clock signal includes:
[0015] The target clock data is obtained by sampling the received clock twice consecutively using the data sampling clock.
[0016] Optionally, determining the counter state and obtaining the counter value based on the pulse enable signal includes:
[0017] When the pulse enable signal is high, the counter is reset, and the counter value is the third count value;
[0018] When the pulse enable signal is at a low level, the counter increments by one in a loop to obtain the counter value.
[0019] Optionally, before determining the counter state based on the pulse enable signal and obtaining the counter value, the method further includes:
[0020] Determine the period of the data signal received by the MII interface;
[0021] Determine the ratio of the period of the data signal to the period of the data sampling clock;
[0022] The counter is set according to the ratio; the counter value includes the first count value, the second count value, and the third count value.
[0023] Optionally, when the phase of the received clock signal shifts, the phase of the pulse enable signal shifts along with the phase of the received clock signal, and the sampling position of the data signal is automatically modified.
[0024] Optionally, generating a pulse enable signal when the data valid signal is at a low level includes:
[0025] When the data valid signal is in a low-level state, the target clock signal is sampled using the data sampling clock, and a high-level pulse is generated at the rising edge of the target clock signal to generate the pulse enable signal.
[0026] Optionally, after detecting the status of the valid data signal at the MII interface receiver, the method further includes:
[0027] When the data valid signal is at a high level, the generation of the pulse enable signal is turned off.
[0028] Optionally, the clock signal frequency of the data sampling clock is 100MHz; the data signal is generated from a 25MHz clock domain.
[0029] Secondly, this application provides a data transmission device based on the MII interface, comprising:
[0030] A data valid signal receiving circuit includes an OR gate, wherein the first input of the OR gate is connected to a data valid signal, and the output of the OR gate is connected to a first selector;
[0031] A pulse enable generation circuit includes a second register and an AND gate, wherein the second input of the AND gate is connected to the output of the second register, and the output of the AND gate is connected to the second input of the OR gate;
[0032] The counter operating circuit includes a first counter, a first selector, and a third register. The second input of the first selector is connected to the output of the first counter, the output of the first selector is connected to the first input of the third register, and the output of the third register is connected to the input of the second counter.
[0033] The data signal processing circuit includes a second counter, a second selector, and a fourth register. The output of the second counter is connected to the first input of the second selector, the second input of the second selector is connected to the data signal, the output of the second selector is connected to the first input of the fourth register, and the output of the fourth register is serial data.
[0034] A serial data output circuit includes a buffer, wherein the input of the buffer is the low bit of the serial data, and the output of the buffer is 100M frame data.
[0035] The data valid signal receiving circuit is used to detect the status of the data valid signal at the receiving end of the MII interface;
[0036] The pulse enable generation circuit is used to generate a pulse enable signal when the data valid signal is at a low level.
[0037] The counter operating circuit is used to determine the counter state and obtain the counter value based on the pulse enable signal;
[0038] The data signal processing circuit is used to sample the data signal received by the MII interface when the counter value is a first count value; and to perform a parallel-to-serial conversion operation on the sampled data signal to obtain the serial data when the counter value is a second count value.
[0039] The serial data output circuit is used to output the serial data.
[0040] This application provides a data transmission method based on the MII interface. When executing the method, the state of the data valid signal at the receiving end of the MII interface is first detected. If the data valid signal is low, a pulse enable signal is generated. Then, the counter state is determined based on the pulse enable signal to obtain the counter value. When the counter value is a first count value, the data signal received by the MII interface is sampled. When the counter value is a second count value, a parallel-to-serial conversion operation is performed on the sampled data signal to obtain serial data. Finally, the serial data is output. In this way, by detecting the state of the pulse enable signal and coordinating it with the counter value, the data sampling time and the time for performing the parallel-to-serial conversion operation can be precisely controlled, thereby reducing latency and improving the data transmission efficiency of the MII interface. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 A flowchart illustrating a data transmission method based on an MII interface provided in this application embodiment;
[0043] Figure 2 A schematic diagram of a waveform and a counter value provided for an embodiment of this application;
[0044] Figure 3 A schematic diagram of another waveform and counter value provided for an embodiment of this application;
[0045] Figure 4 This is a schematic diagram of a data transmission device based on an MII interface, provided as an embodiment of this application. Detailed Implementation
[0046] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. This application provides a data transmission method and apparatus based on the MII interface, relating to the field of data transmission technology. The above are merely examples and do not limit the application field of the method and apparatus provided in this application.
[0047] The MII interface is an interface that provides data transmission between the MAC (Media Access Control) layer and the PHY (Physical Layer) layer. Existing technology typically sets up a data buffer at the receiving end of the MII interface to temporarily store data received by the MAC layer. When the MII interface receives data sent by the PHY layer, it checks the status of the valid data edge at the rising edge of the receive clock RX_CLK. If the valid data signal RX_DV is high, it indicates that the currently received data is valid. The data on the data signals RXD[3:0] of the MII interface's data receive line is then read and stored in the data buffer until all the required data has been received, i.e., the valid data signal RX_DV goes low. However, during data reception, the data is first stored in the buffer, and several sets of data need to be stored, typically half the buffer capacity. Then, the data is read from the buffer, which is in the 25MHz clock domain, and finally converted into 100MHz frame data, resulting in low data transmission efficiency for the MII interface.
[0048] The inventors, through research, proposed the technical solution of this application. First, the state of the valid data signal at the receiving end of the MII interface is detected. If the valid data signal is low, a pulse enable signal is generated. Then, the counter state is determined based on the pulse enable signal, and the counter value is obtained. When the counter value is the first count value, the data signal received by the MII interface is sampled. When the counter value is the second count value, a parallel-to-serial conversion operation is performed on the sampled data signal to obtain serial data. Finally, the serial data is output. In this way, by detecting the state of the pulse enable signal and combining it with the counter value, the data sampling time and the time for performing the parallel-to-serial conversion operation can be precisely controlled. This reduces latency and improves the data transmission efficiency of the MII interface.
[0049] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application. It should be noted that, for ease of description, only the parts related to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.
[0050] See Figure 1 , Figure 1 A flowchart of a data transmission method based on an MII interface provided in this application embodiment includes:
[0051] S101: Detects the status of the valid data signal at the receiving end of the MII interface.
[0052] First, before executing the implementation method in step S101, it is necessary to perform a synchronous sampling operation on the received clock signal using the data sampling clock to obtain the target clock signal. To avoid metastability, when the data sampling clock and the received clock are not from the same source, a synchronous sampling operation is required. Specifically, the synchronous sampling operation can be to use the data sampling clock to sample the received clock twice consecutively to obtain the target clock data. The number of samplings in the synchronous sampling operation is variable and can be determined by relevant technical personnel based on experience.
[0053] Next, the status of the data valid signal at the receiving end of the MII interface is detected. If the data valid signal is high, it indicates that data is being transmitted; if the data valid signal is low, it indicates that no data is being transmitted, meaning that the receiving end of the MII interface is in an idle state.
[0054] S102: When the data valid signal is at a low level, a pulse enable signal is generated.
[0055] When the data valid signal is at a low level, the data sampling clock is used to sample the target clock signal, which will generate a high-level pulse at the rising edge of the target clock data, thus obtaining the pulse enable signal.
[0056] In addition, when the data valid signal is at a high level, the generation of high-level pulses is turned off, so that the pulse enable signal in the current stage is always at a low level.
[0057] S103: Determine the counter state based on the pulse enable signal and obtain the counter value.
[0058] The counter value includes multiple count values and a reset value, where the reset value is one of the multiple count values. The counter values can be set based on the data signal and the sampling clock signal. Specifically, multiple counter values can be set based on the frequency / period ratio of the data signal and the sampling clock signal, and then the reset value can be determined from these multiple counter values.
[0059] When the pulse enable signal is high, the counter is reset, and the counter value is the reset value. When the pulse enable signal is low, the counter increments by one in a loop, and the counter value is the non-reset value among multiple count values.
[0060] S104: When the counter value is the first count value, sample the data signal received by the MII interface.
[0061] When the counter value is the first count value, the data signal received by the MII interface is sampled. The first count value is one of multiple count values, which is set by those skilled in the art based on experience.
[0062] S105: When the counter value is the second count value, the sampled data signal is converted from parallel to serial to obtain serial data.
[0063] When the counter value is the second count value, a parallel-to-serial conversion operation is performed on the sampled data signal. The second count value is a count value that is different from the first count value among a plurality of count values. The second count value is set by those skilled in the art based on experience.
[0064] S106: Output serial data.
[0065] The low-bit bits of the serial data obtained in step S105 are output to obtain a serial 100M frame data output.
[0066] In this embodiment, the status of the data valid signal at the receiving end of the MII interface is first detected. If the data valid signal is low, the target clock data is sampled using the data sampling clock, generating a high-level pulse at the rising edge of the target clock data (at the same moment), thus generating a pulse enable. If the data valid signal is high, the generation of the pulse enable is disabled. Then, a counter value is determined based on the pulse enable status. When the counter value is the first count value, the data signal received by the MII interface is sampled. When the counter value is the second count value, a parallel-to-serial conversion operation is performed on the sampled data signal to obtain serial data. Finally, the serial data is output. In this way, by detecting the status of the pulse enable signal and combining it with the counter value, the sampling time and the time for performing the parallel-to-serial conversion operation can be precisely controlled, thereby reducing latency and improving the data transmission efficiency of the MII interface.
[0067] Furthermore, it should be noted that in the embodiments provided in this application, when the receiving clock phase of the MII interface shifts, the pulse enable can also shift accordingly, automatically modifying the subsequent sampling position to achieve automatic shift, i.e., automatic adjustment. This not only improves the data transmission efficiency of the MII interface but also increases the stability of the MII interface data transmission.
[0068] The data transmission method based on the MII interface provided in the embodiments of this application has been introduced above. The following is an exemplary description of the data transmission method based on the MII interface in combination with specific application scenarios.
[0069] See Figure 2 , Figure 2 This is a schematic diagram of signal waveforms involved in a MII interface according to an embodiment of this application, where the left side represents the signal name and the right side represents the corresponding signal waveform. The data sampling clock is a 100MHz clock, and the data signals RXD[3:0] are generated from a 25MHz clock domain. The specific implementation is as follows:
[0070] In this embodiment, since the receiving clock RX_CLK and the data sampling clock are not from the same source, a synchronous sampling operation needs to be performed on the receiving clock RX_CLK to avoid metastability when sampling it. Specifically, the synchronous sampling operation involves sampling the receiving clock RX_CLK twice consecutively using the data sampling clock. Figure 2 As shown, by sampling the received clock RX_CLK twice using the data sampling clock, the target clock signal waveform RCK_SYN2 can be obtained. Figure 2 In the waveform RCK_SYN1, the result of one sampling is given. The number of samplings in the synchronous sampling operation is variable, usually two.
[0071] Next, the status of the data valid signal RX_DV at the MII interface receiver is detected. The RX_DV signal can be low or high. A high level indicates data transmission, while a low level indicates no data transmission, meaning the MII interface receiver is idle. Figure 2 As shown, for example, if the data valid signal RX_DV is detected to be low at time T2, then RCK_SYN2 is sampled using the data sampling clock. A high-level pulse will be generated at the rising edge of RCK_SYN2 (at the same time), thus obtaining the pulse enable signal. If RX_DV is high, then the generation of this pulse enable is turned off, that is, this pulse enable is always low during the current stage. Figure 2 The pulse enable in the middle.
[0072] In this embodiment, a 2-bit counter is also included. First, the timer needs to be set. Since the data signals RXD[3:0] are generated by a 25MHz clock domain, the period of each data signal is 40ns, while the period of the 100MHz data sampling clock is 10ns. That is, the period of each data signal RXD[3:0] is 1 / 4 of the data sampling clock period. Therefore, the counter value can be set to 0, 1, 2, and 3, a total of four values, where setting 3 is the specified reset value. Figure 2 As shown, if the pulse enable is high during time T2 to T3, the counter is reset during time T3 to T4, and the counter value is the reset value 3. After time T3, the pulse enable is low, and the counter increments by one in this stage, with the counter value cycling through 0, 1, 2, 3, 0, 1...
[0073] Next, the value of the counter is used as a condition to determine the sampling time, as follows: Figure 2 As shown, when the counter value is detected to be 0, the data signal RXD[3:0] received by MII is directly sampled using a 100M data sampling clock. At this time, the sampling position is in the middle of the data, that is, the signal is stable and the sampling result is the most accurate. If the counter value is 1, 2 or 3, sampling stops and the parallel to serial conversion operation is performed. Finally, a serial 100M frame data output is obtained.
[0074] The counter cycles every 4 periods. When the counter value is 0, the MII received data RXD[3:0] is sampled. The remaining 3 periods are used for parallel data to serial conversion. There are no extra operations in between, so the structure is simple and efficient.
[0075] In some implementations, the reset value and the counter value during sampling can also be other values, as long as the sampling position is in the middle of the data. For example, in Figure 2In the process, starting from time T3, if the counter value is displayed as 3, 0, 1, 2, 3, 0, 1... then the reset value is 3, and the counter value is 0 during sampling; if the counter value is displayed as 0, 1, 2, 3, 0, 1, 2... then the reset value is 0, and the counter value is 1 during sampling.
[0076] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the automatic shift mechanism implemented in the MII interface provided in this application embodiment. When the phase of the received clock signal shifts, the pulse enable also shifts accordingly, thereby automatically modifying the position of subsequent sampling. Figure 2 and Figure 3 When the phase of RX_CLK shifts, the corresponding synchronized RCK_SYN2 also shifts, and the rising edge of the high-level pulse enable changes from time T2 to time T5. The sampling position also changes from time T5 to time T8, thus achieving automatic shift.
[0077] In the field of industrial Ethernet, to ensure transmission efficiency and real-time performance between slave stations, there are typically high requirements for transmission latency. The traditional method involves buffering the received MII data into a register, and then reading it from the register and performing the conversion when it's half full. This process is inefficient and cumbersome, often resulting in a latency of around 235ns. The method of this invention, however, provides highly efficient and rapid conversion, typically reducing latency to around 10ns, a significant improvement over the traditional approach. Furthermore, this difference will widen as the number of slave stations and their MII interfaces increases in the transmission network.
[0078] The technical solution of this application allows for direct sampling of MII interface data and its conversion into frame data, simplifying data conversion steps, reducing data conversion latency, improving data conversion efficiency, and achieving rapid data conversion. Furthermore, the invention employs an automatic shift mechanism to ensure the integrity and accuracy of received data and reduce the error rate during data transmission.
[0079] The above describes some specific implementations of the data transmission method based on the MII interface provided in this application. Based on this, this application also provides corresponding circuit devices. The circuit devices provided in the embodiments of this application will be described below.
[0080] See Figure 4 , Figure 4 A schematic diagram of a data transmission circuit device based on an MII interface provided in this application embodiment includes:
[0081] The data valid signal receiving circuit 430 is used to detect the status of the data valid signal at the receiving end of the MII interface, including an OR gate 431, the first input of the OR gate 431 is connected to the data valid signal, and the output of the OR gate 431 is connected to the first selector 441.
[0082] A pulse enable generation circuit 420 is used to generate a pulse enable signal when the state of the data valid signal is low. It includes a second register 421 and an AND gate 422. The second input of the AND gate 422 is connected to the output of the second register 421, and the output of the AND gate 422 is connected to the second input of the OR gate 431.
[0083] The counter operating circuit 440 is used to determine the counter state and obtain the counter value according to the pulse enable signal. It includes a first counter 442, a first selector 441 and a third register 443. The second input of the first selector 441 is connected to the output of the first counter 442, the output of the first selector 441 is connected to the first input of the third register 443, and the output of the third register 443 is connected to the input of the second counter 451.
[0084] The data signal processing circuit 450 is used to sample the data signal received by the MII interface when the counter value is a first count value; and to perform a parallel-to-serial conversion operation on the sampled data signal to obtain serial data when the counter value is a second count value. The circuit includes a second counter 451, a second selector 452, and a fourth register 453. The output of the second counter 451 is connected to the first input of the second selector 452, the second input of the second selector 452 is connected to the data signal, the output of the second selector 452 is connected to the first input of the fourth register 453, and the output of the fourth register 453 is the serial data.
[0085] A serial data output circuit 460 is used to output the serial data, including a buffer 461. The input of the buffer 461 is the low bit of the serial data, and the output of the buffer 461 is 100M frame data.
[0086] Optionally, the device further includes:
[0087] The sampling clock port is used to receive the data sampling clock signal and is connected to the second input of the first register 411, the second register 421, the third register 443 and the fourth register 453;
[0088] The clock synchronization circuit 410 is used to synchronously sample the received clock signal using the data sampling clock to obtain the target clock signal. It includes a first register 411, the first input of the first register 411 is connected to the received clock signal, and the output of the first register 411 is connected to the first input of the second register 421 and the first input of the AND gate 422.
[0089] Optionally, the clock synchronization circuit 410 is specifically used for:
[0090] The target clock data is obtained by sampling the received clock twice consecutively using a data sampling clock.
[0091] Optionally, the counter operating circuit 440 is specifically used for:
[0092] When the pulse enable signal is high, the counter is reset, and the counter value is the third count value;
[0093] When the pulse enable signal is at a low level, the counter increments by one in a loop to obtain the counter value.
[0094] Optionally, the device further includes a counter setting module, which is specifically used for:
[0095] Determine the ratio of the period of the data signal to the period of the data sampling clock;
[0096] The counter is set according to the ratio; the counter value includes the first count value, the second count value, and the third count value.
[0097] Optionally, when the phase of the received clock signal shifts, the phase of the pulse enable signal shifts along with the phase of the received clock signal, and the sampling position of the data signal is automatically modified.
[0098] Optionally, the pulse enable generation circuit 420 is specifically used for:
[0099] When the data valid signal is in a low-level state, the target clock signal is sampled using the data sampling clock, and a high-level pulse is generated at the rising edge of the target clock signal to generate the pulse enable signal.
[0100] Optionally, the pulse enable generation circuit 420 is also used for:
[0101] When the data valid signal is at a high level, the generation of the pulse enable signal is turned off.
[0102] Optionally, the clock signal frequency of the data sampling clock is 100MHz; the data signal is generated from a 25MHz clock domain.
[0103] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.
[0104] The device includes a memory and a processor. The memory stores instructions or code, and the processor executes the instructions or code to cause the device to perform the method described in any embodiment of this application.
[0105] The computer storage medium stores code, and when the code is run, the device running the code implements the method described in any embodiment of this application.
[0106] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0107] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0108] It should also be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The apparatus embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0109] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A data transmission method based on an MII interface, characterized in that, include: Detect the status of the valid data signal at the receiving end of the MII interface; When the data valid signal is at a low level, a pulse enable signal is generated; The counter state is determined based on the pulse enable signal, and the counter value is obtained. When the counter value is the first count value, the data signal received by the MII interface is sampled. When the counter value is the second count value, the sampled data signal is converted from parallel to serial to obtain serial data. Output the serial data.
2. The method according to claim 1, characterized in that, Before detecting the status of the valid data signal at the receiving end of the MII interface, the method further includes: The target clock signal is obtained by synchronously sampling the received clock signal using a data sampling clock.
3. The method according to claim 2, characterized in that, The step of determining the counter state and obtaining the counter value based on the pulse enable signal includes: When the pulse enable signal is high, the counter is reset, and the counter value is the third count value; When the pulse enable signal is at a low level, the counter increments by one in a loop to obtain the counter value.
4. The method according to claim 3, characterized in that, Before determining the counter state based on the pulse enable signal and obtaining the counter value, the method further includes: Determine the ratio of the period of the data signal to the period of the data sampling clock; The counter is set according to the ratio; the counter value includes the first count value, the second count value, and the third count value.
5. The method according to claim 2, characterized in that, When the phase of the received clock signal shifts, the phase of the pulse enable signal shifts accordingly, automatically modifying the sampling position of the data signal.
6. The method according to claim 2, characterized in that, When the data valid signal is at a low level, generating a pulse enable signal includes: When the data valid signal is in a low-level state, the target clock signal is sampled using the data sampling clock, and a high-level pulse is generated at the rising edge of the target clock signal to generate the pulse enable signal.
7. The method according to claim 1, characterized in that, After detecting the status of the valid data signal at the MII interface receiver, the method further includes: When the data valid signal is at a high level, the generation of the pulse enable signal is turned off.
8. The method according to claim 2, characterized in that, The clock signal frequency of the data sampling clock is 100MHz; the data signal is generated from a 25MHz clock domain.
9. The method according to claim 2, characterized in that, The step of synchronously sampling the received clock signal using a data sampling clock to obtain the target clock signal includes: The target clock data is obtained by sampling the received clock twice consecutively using the data sampling clock.
10. A data transmission device based on an MII interface, characterized in that, include: A data valid signal receiving circuit includes an OR gate, wherein the first input of the OR gate is connected to a data valid signal, and the output of the OR gate is connected to a first selector; A pulse enable generation circuit includes a second register and an AND gate, wherein the second input of the AND gate is connected to the output of the second register, and the output of the AND gate is connected to the second input of the OR gate; The counter operating circuit includes a first counter, a first selector, and a third register. The second input of the first selector is connected to the output of the first counter, the output of the first selector is connected to the first input of the third register, and the output of the third register is connected to the input of the second counter. The data signal processing circuit includes a second counter, a second selector, and a fourth register. The output of the second counter is connected to the first input of the second selector, the second input of the second selector is connected to the data signal, the output of the second selector is connected to the first input of the fourth register, and the output of the fourth register is serial data. A serial data output circuit includes a buffer, wherein the input of the buffer is the low bit of the serial data, and the output of the buffer is 100M frame data. The data valid signal receiving circuit is used to detect the status of the data valid signal at the receiving end of the MII interface; The pulse enable generation circuit is used to generate a pulse enable signal when the data valid signal is at a low level. The counter operating circuit is used to determine the counter state and obtain the counter value based on the pulse enable signal; The data signal processing circuit is used to sample the data signal received by the MII interface when the counter value is a first count value. When the counter value is the second count value, the sampled data signal is converted from parallel to serial to obtain the serial data; The serial data output circuit is used to output the serial data.