All-electric aircraft system architecture failure rate evaluation method and system and storage medium

Abstract

The invention discloses an all-electric aircraft system architecture failure rate evaluation method and system and a storage medium, and relates to the technical field of information. The method comprises the following steps: acquiring a to-be-analyzed top event and system architecture information; establishing a path search model, wherein the path search model describes directed graphs of all devices in the system architecture; traversing all devices through an enumeration method, sequentially generating a group of device working / failure state combinations in each enumeration process, performing simulation through the path search model, and calculating the occurrence probability of the group of device working / failure state combinations through the system architecture information; transmitting energy or information through a depth-first algorithm, and performing system architecture working / failure state judgment on each group of equipment working / failure state combination according to the final output performance state according to the top event; after traversal is completed, the combination occurrence probability causing system architecture failure is accumulated, and the top event occurrence probability is obtained through calculation and serves as the system architecture failure rate. According to the scheme, the technical problems that the analysis time period needed by failure rate quantitative evaluation of a traditional reliability analysis method for a complex system architecture is too long, errors are large due to the fact that omission is prone to occurring, and migration to a similar new architecture cannot be conveniently and rapidly conducted are solved.

Description

Technical Field

[0001] This invention relates to the field of information technology, and in particular to a method, system, and storage medium for assessing the failure rate of an all-electric aircraft system architecture. Background Technology

[0002] To achieve specific functions and redundant design, all-electric aircraft often have complex interconnected system architectures. One of the main differences between different system architectures lies in their varying failure rates, making reliability analysis crucial for solution evaluation and selection. However, complex system architectures involve a large number of devices and intricate inter-device connections, making traditional reliability analysis methods difficult to apply. Therefore, there is an urgent need to develop new reliability analysis methods.

[0003] The following techniques are commonly used in existing technologies for reliability analysis:

[0004] Fault tree analysis (FBA) is a deductive analysis method that uses logic diagrams to analyze events from the top (what failure occurs) to the bottom (the cause of the failure). It shows which components of a product, external events, or combinations thereof will cause a given failure. Based on the probability of each bottom event, logic gates are used to combine these events to calculate the probability of the top event, i.e., the failure rate. FBA suffers from drawbacks, including long analysis cycles for complex system architectures, potential for incomplete analysis, and difficulties in conveniently and efficiently transferring models to compare with other alternative architectures with similar characteristics. Complex system architectures typically consist of numerous components with complex connections and often multiple redundancies. Using FBA requires including every possible failure scenario in the fault tree. Due to the vast number of failure scenarios leading to complex system failures, the number of branches in the fault tree is enormous, resulting in excessively long analysis cycles. Furthermore, while comprehensive analysis requires listing all possible failure scenarios and analyzing each one thoroughly, omissions are common in practice, especially higher-order terms. Furthermore, the research on complex system architectures often requires comparative analysis of multiple alternative system architectures. Even if there are similarities between the architectures, fault tree analysis requires repeated analysis of each alternative architecture separately, which makes it difficult to conveniently and efficiently transfer models to study new architectures, further resulting in a huge workload.

[0005] Failure Mode and Effects Analysis (FMEA) aims to analyze potential failure modes across a system in order to categorize them by severity or determine the impact of failures on the system. FMEA works from the bottom up, analyzing how each underlying failure leads to the top event. However, it cannot be used to discover complex failure modes involving multiple failure problems and is therefore not suitable for this purpose.

[0006] The key challenge and difficulty for the inventors in their prior application (2025101563026), entitled "A System Architecture Reliability Analysis Method, Apparatus, Equipment, and Medium," lies in summarizing and organizing the patterns of system architecture and describing the transmission paths using formulaic language. When the system architecture contains numerous complex logical connections such as parallel and redundant connections, the problem arises from the sheer number of possible transmission paths. To fully analyze these paths would require the workload and process of manually enumerating all possible scenarios, making it difficult to apply.

[0007] Therefore, developing a method that can efficiently process massive amounts of data, accurately simulate system behavior, and comprehensively evaluate various failure scenarios is crucial for improving the efficiency and accuracy of reliability assessments for complex system architectures. Summary of the Invention

[0008] To address the failure rate assessment problem of all-electric aircraft system architecture design schemes, this invention provides a method, system, and storage medium for all-electric aircraft system architecture failure rate assessment. The core process involves establishing a path search model and then using an enumeration method for traversal. The path search model utilizes the energy / signal transmission paths to describe the system architecture logic. Leveraging the ease of use of directed graphs, Python is chosen as the language, and parallel computation is performed using a CPU. This invention eliminates the need for analyzing and listing a massive number of failure scenarios, as is common in traditional methods. This invention solves the technical problems of traditional reliability analysis methods for quantifying failure rates in complex system architectures, such as excessively long analysis cycles, the potential for omissions leading to large errors, and the inability to easily and quickly migrate to similar new architectures.

[0009] Specifically, according to a first aspect of the technical solution of the present invention, a method for assessing the failure rate of an all-electric aircraft system architecture is provided, the method comprising:

[0010] S1: Obtain the top event and system architecture information to be analyzed;

[0011] S2: Establish a path search model, which describes a directed graph of all devices in the system architecture;

[0012] S3: All devices are traversed by enumeration. During each enumeration, a set of device working / failure state combinations is generated sequentially. The path search model is used for simulation, and the probability of occurrence of the set of device working / failure state combinations is calculated using the system architecture information.

[0013] S4: Transmit energy or information through a depth-first algorithm. Based on the top event, determine the system architecture working / failure state for each group of device working / failure state combinations according to the final output performance state.

[0014] S5: After the traversal is completed, the probability of occurrence of the combination that leads to system architecture failure is accumulated, and the probability of occurrence of the top event is calculated as the system architecture failure rate.

[0015] Furthermore, the all-electric aircraft system architecture includes one or more combinations of motors, fans, shaft connections, cables, motor controllers, busbars, batteries, and switches.

[0016] Furthermore, in S1, the top event includes the architecture, failure rate parameters of each device, and / or the failure time distribution type of each device.

[0017] Furthermore, in S2, the nodes of the directed graph represent devices, and the edges of the directed graph represent pathways between the devices.

[0018] Furthermore, in step S3, each device has two states: working and unworking, and the total number of enumeration steps is 2. n , where n is the total number of devices.

[0019] Furthermore, in S1, the system architecture information includes the failure probability of each device and the operating time of each device.

[0020] Furthermore, in step S3, calculating the probability of occurrence of the combination of working / failure states of this group of devices using the system architecture information specifically includes:

[0021] Determine the failure rate of each device under the current conditions based on the failure probability and operating time of each device;

[0022] Calculate the probability of occurrence of the combination of working / failure states for this group of devices based on the failure rate of each device under the current conditions.

[0023] Furthermore, the failure rate of each device under the current condition = failure probability of each device * operating time.

[0024] Furthermore, the probability of this combination of working / failure states occurring is equal to the product of the failure rates of each device under the current condition.

[0025] Furthermore, S3 also includes: selecting a CPU for parallel computing acceleration based on the computer conditions of the simulation.

[0026] Furthermore, the parallel computing acceleration includes: creating multiple parallel worker processes; dividing the device working / failure state combination into multiple task blocks; and processing the task blocks in parallel through the worker processes to simulate and calculate the occurrence probability of the device working / failure state combination.

[0027] Furthermore, S4 specifically includes:

[0028] For each combination of device working / failure states, energy or information is transferred using a depth-first search algorithm.

[0029] Based on the top event, a performance metric is generated to determine the performance status of the system architecture.

[0030] Determine the final output performance index for each group of device working / failure state combinations, and determine whether it exceeds the preset performance state threshold. If it does, the group of device working / failure state combinations is considered to be in the system architecture working state; otherwise, the group of device working / failure state combinations is considered to be in the failure state.

[0031] Furthermore, the performance metrics of the final output reflect the overall output capability or performance of the system architecture.

[0032] According to a second aspect of the present invention, a failure rate assessment device for an all-electric aircraft system architecture is provided. The device is used to implement the method described above, and the device comprises:

[0033] The acquisition module is used to acquire the top event and system architecture information to be analyzed;

[0034] Establish a module for building the path search model;

[0035] The traversal module is used to traverse all devices by enumeration. In each enumeration process, a set of device working / failure state combinations is generated sequentially. The path search model is used for simulation, and the probability of occurrence of the set of device working / failure state combinations is calculated using the system architecture information.

[0036] The judgment module is used to transmit energy or information through a depth-first algorithm, and based on the top event, to judge the system architecture working / failure status for each group of device working / failure state combinations according to the final output performance status.

[0037] The statistical analysis module is used to accumulate the probability of occurrence of combinations that lead to system architecture failure after traversal, and calculate the probability of occurrence of the top event as the system architecture failure rate.

[0038] According to a third aspect of the technical solution of the present invention, an electronic device is provided, the electronic device comprising:

[0039] Memory, which stores executable instructions;

[0040] A processor that executes the executable instructions in the memory to implement the method.

[0041] According to a fourth aspect of the present invention, a computer storage medium is provided, wherein a computer program is stored on the medium, and the computer program is executed by a processor to implement the method described herein.

[0042] The beneficial effects of this invention are:

[0043] This invention addresses the problem of excessively long analysis times and workloads associated with existing methods for analyzing a large number of failure combinations in complex system architectures. It utilizes path search simulation for analysis and accelerates the process through programming optimization. Regarding the incomplete analysis inherent in traditional methods, this invention eliminates the need for manual enumeration of detailed failure scenarios by defining top-level performance indicators, ensuring greater comprehensiveness. Furthermore, it addresses the difficulty of conveniently and efficiently modifying models to compare and analyze similar alternative architectures, allowing for easy and efficient migration by simply modifying the changed parts. Finally, it overcomes the difficulty of manually summarizing system architecture patterns in traditional methods by requiring only the description of the connection relationships between individual device nodes within the system architecture, making it intuitive and easy to use. Attached Figure Description

[0044] Figure 1 This is a flowchart of a failure rate assessment method for an all-electric aircraft system architecture according to the present invention.

[0045] Figure 2 This is a flowchart illustrating an embodiment of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0047] This invention addresses the technical problems of traditional reliability analysis methods for complex system architectures, such as excessively long analysis time, potential omissions leading to large errors, and inconvenience in rapid migration to similar new architectures. The invention establishes a path search model and uses enumeration for traversal, creating a model that supports intuitive, convenient, and efficient migration, thus solving these problems. The core process of establishing the path search model and then using enumeration for traversal, the application of the path search model to describe the system architecture logic based on energy / signal transmission paths, the use of Python language due to the convenience of directed graphs, and the use of CPU for parallel computation best demonstrate the innovation of this invention. This allows the invention to avoid the need for analyzing and listing a massive number of failure scenarios, as is the case with traditional methods.

[0048] First, the present invention addresses the technical problem of excessively long analysis time required for failure rate quantification assessment using traditional reliability analysis methods for complex system architectures. It significantly reduces the workload of analysis and assessment, and significantly improves efficiency. Because traditional reliability analysis methods require a massive, even prohibitive, workload to analyze each failure scenario, the present invention can significantly reduce the manual workload of analysis and analyze system architectures that are difficult to analyze using traditional methods.

[0049] Secondly, the solution of this invention can effectively ensure the accuracy of the analysis and evaluation. Traditional reliability analysis methods are prone to omissions, leading to large errors in the analysis results, especially the tendency to overlook higher-order terms. The solution of this invention only needs to specify the top-level performance requirements, without manually enumerating detailed failure scenarios. By traversing all cases through an enumeration method, it can ensure that the analysis and evaluation results are theoretical values.

[0050] Meanwhile, when it is necessary to compare and analyze multiple alternative architectures, the solution of this invention only needs to modify the changes to adapt to the research of new architectures, and can achieve convenient and efficient migration.

[0051] Finally, this method solves the problem that existing methods for describing architectures still require enumerating every possible path when there are many interconnected relationships, which is still difficult to meet the requirements in terms of workload and time consumption. It is more intuitive.

[0052] The technical solution of this invention mainly includes the following steps: inputting top events and system architecture information, establishing a path search model, judging the state based on performance, traversing by enumeration, accelerating parallel computing, and obtaining the system architecture failure rate through statistical analysis. A flowchart of the steps is shown below. Figure 1 As shown.

[0053] Here, the technical solution of the present invention is to facilitate the establishment of directed graphs in a convenient and efficient manner, using Python for modeling and numerical simulation.

[0054] Step 1: Input the top event and system architecture information. In this step, for the top event to be analyzed, the scope of system architecture analysis is limited, and the failure probability and operating time of each device involved are input.

[0055] Step Two: Establishing a Path Search Model. This step directly describes the system architecture, outlining the pathways between every pair of device nodes to reflect the possible energy transfer paths along a given route. Based on the input combinations of device operating / failure states, a depth-first search (DFS) algorithm is used to transfer energy along each node. The established path search model reflects the impact of faults and their propagation on the system performance status.

[0056] Step 3: Performance Status Judgment. In this step, the status of each path is considered, and based on the top input event, a performance index is generated to evaluate the system status. The system is then judged as operational or unresponsive according to the performance status threshold.

[0057] Step 4: Enumerate and iterate, repeating steps 2 to 3. In this step, a unique combination of equipment working / failure states is generated during each enumeration. Simulation is performed through path search, and the probability of occurrence of the combination is calculated based on the set availability probability. This step accounts for the majority of the runtime of this tool and method; the specific duration depends on the number and complexity of the devices in the system architecture.

[0058] Furthermore, step four can be accelerated through parallel computing. In this step, CPU parallel computing is selected to speed up tool processing. This step is used to reduce the time taken by step four, and is not a necessary procedure if the number of devices is small.

[0059] Step 5: Statistical analysis to obtain the top event index. In this step, after the traversal is completed, the probability of occurrence of the combinations that lead to system architecture failure is accumulated to calculate the probability of occurrence of the top event (system architecture failure rate).

[0060] Example

[0061] This invention is applied to a reliability assessment of an alternative system architecture for a distributed electric propulsion system of a certain type of all-electric aircraft. The architecture formed by the battery system, power distribution lines, and electric drive system in an all-electric aircraft is collectively referred to as the distributed electric propulsion system architecture. This alternative architecture uses two lithium batteries and two fuel cells to provide energy, driving ten sets of electric drive systems on the left and right sides through a power distribution line containing five busbars, providing the thrust required by the aircraft. To meet the climb rate and other performance indicators during the aircraft's climb phase, the power grid architecture is required to provide thrust from at least seven motors. The following describes the reliability analysis and assessment process for this alternative architecture.

[0062] To improve the reliability of the distributed electric propulsion system, this alternative architecture employs a redundant design: each lithium battery has two output switches, and each fuel cell has three output switches. Each switch supplies power to a busbar in the power grid, and each busbar receives power from two different batteries. Each busbar has two output switches, and each output switch supplies power to a separate motor controller to drive the motor.

[0063] This embodiment includes: Step 1: Inputting the top event and system architecture information; Step 2: Establishing a path search model; Step 3: Judging based on performance status; Step 4: Traversing using enumeration; Step 5: Accelerating computation through parallel processing; Step 6: Obtaining top event metrics through statistical analysis. Specifically:

[0064] Step 1: Input the top event and system architecture information. First, list the top event as "Loss of thrust from any three or fewer motors". Number each device node as 1, 2, 3, ...

[0065] Step 2: Establish a path search model. By analyzing the connection paths between nodes in the power grid architecture, the following relationships can be obtained:

[0066] (5,10),(5,19),(5,11),(6,18),(7,12),(7,17),(8,13),(8,16),(9,14),(9,15),

[0067] (1,5),(2,6),(3,8),(4,9),

[0068] (5,6),(6,5),(6,7),(7,6),(7,8),(8,7),(8,9),(9,8),(9,5),(5,9)

[0069] (21,1),(22,2),(23,3),(24,4)

[0070] Input the above relationships into the model.

[0071] Step 3: Performance status assessment. The electrical power and corresponding thrust of each motor are determined through path search, and summed to obtain the total output thrust of the distributed electric propulsion system architecture. The value can range from 0 to 10. A value greater than 7 indicates the system architecture is working; otherwise, it is considered to have failed.

[0072] Step 4: Enumeration for Traversal. Using enumeration, unique combinations of paths that are open or blocked are generated, and the probability of each combination occurring is calculated based on the probability of each edge being open or blocked. A simulation is then performed using a path search model to determine whether the system is working or not. Traversal is continued until completion.

[0073] Step 5: Parallel Computing Acceleration. Since each simulation is independent, parallel computing is used to accelerate the process. A CPU is selected for acceleration.

[0074] Step Six: Statistical Analysis to Obtain Top Event Indicators. After all cycles are completed, the experimental data is processed, and the proportion of all failures is statistically analyzed to obtain the estimated failure rate index of the distributed electric propulsion system architecture.

[0075] like Figure 2 As shown, the progress bar for this embodiment is displayed. The calculation time is 1 second on the right, the total power output by the battery is 420kW (420 people), and the system failure rate below is the blockage probability of 1.2260E-06, totaling 2. 24The simulation was divided into 524,288 groups. Specifically, the method of this invention was applied to the system architecture of the case study for verification. The architecture reliability index calculated in 1 second was 1.2260E-06. After manually enumerating some low-order failure scenarios and analyzing them over several days, the failure rate was found to be 1.2221E-06. Therefore, the correctness of the theoretical value calculated in this embodiment can be verified.

[0076] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A method for assessing the failure rate of an all-electric aircraft system architecture, characterized in that, The method includes: S1: Obtain the top event and system architecture information to be analyzed; S2: Establish a path search model, which describes a directed graph of all devices in the system architecture; S3: All devices are traversed by enumeration. During each enumeration, a set of device working / failure state combinations is generated sequentially. The path search model is used for simulation, and the probability of occurrence of the set of device working / failure state combinations is calculated using the system architecture information. S4: Transmit energy or information through a depth-first algorithm. Based on the top event, determine the system architecture working / failure state for each group of device working / failure state combinations according to the final output performance state. S5: After the traversal is completed, the probability of occurrence of the combination that leads to system architecture failure is accumulated, and the probability of occurrence of the top event is calculated as the system architecture failure rate.

2. The failure rate assessment method for all-electric aircraft system architecture according to claim 1, characterized in that, In S1, the top event includes the architecture, failure rate parameters of each device, and / or the failure time distribution type of each device.

3. The failure rate assessment method for all-electric aircraft system architecture according to claim 1, characterized in that, In step S3, each device has two states: working and unworking. The total number of enumeration steps is 2. n , where n is the total number of devices.

4. The failure rate assessment method for all-electric aircraft system architecture according to claim 1, characterized in that, In S1, the system architecture information includes the failure probability of each device and the operating time of each device.

5. The failure rate assessment method for all-electric aircraft system architecture according to claim 4, characterized in that, In step S3, calculating the probability of the occurrence of the combination of working / failure states of this group of devices using the system architecture information specifically includes: Determine the failure rate of each device under the current conditions based on the failure probability and operating time of each device; Calculate the probability of occurrence of the combination of working / failure states for this group of devices based on the failure rate of each device under the current conditions.

6. The failure rate assessment method for all-electric aircraft system architecture according to claim 5, characterized in that: The failure rate of each device under the current condition = failure probability of each device * working time; The probability of this combination of working / failure states occurring is equal to the product of the failure rates of each device under the current condition.

7. The failure rate assessment method for all-electric aircraft system architecture according to claim 1, characterized in that, The S3 further includes: selecting a CPU for parallel computing acceleration based on the computer conditions of the simulation. The parallel computing acceleration includes: creating multiple parallel worker processes; dividing the device working / failure state combination into multiple task blocks; and processing the task blocks in parallel through the worker processes to simulate and calculate the occurrence probability of the device working / failure state combination.

8. The failure rate assessment method for all-electric aircraft system architecture according to claim 1, characterized in that, S4 specifically includes: For each combination of device working / failure states, energy or information is transferred using a depth-first search algorithm. Based on the top event, a performance metric is generated to determine the performance status of the system architecture. Determine the final output performance index for each group of device working / failure state combinations, and determine whether it exceeds the preset performance state threshold. If it does, the group of device working / failure state combinations is considered to be in the system architecture working state; otherwise, the group of device working / failure state combinations is considered to be in the failure state.

9. An electronic device, characterized in that, The electronic device includes: Memory, which stores executable instructions; A processor that executes the executable instructions in the memory to implement the all-electric aircraft system architecture failure rate assessment method according to any one of claims 1 to 8.

10. A computer storage medium storing a computer program, the computer program being executed by a processor to implement the all-electric aircraft system architecture failure rate assessment method according to any one of claims 1 to 8.

Images