Model order reduction method and system for multi-port linear circuit, terminal and computer readable storage medium

Abstract

The invention discloses a model order reduction method and system for a multi-port linear circuit, a terminal and a computer readable storage medium, and the method comprises the steps: obtaining a to-be-reduced-order circuit model, carrying out the port number reduction of the to-be-reduced-order circuit model according to a port reduction strategy, and obtaining a target circuit model; a target mapping equation is constructed based on the target circuit model, a residual module and a tensor mapping structure, the tensor mapping structure is used for representing the correlation between the circuit model to be subjected to order reduction and the target circuit model, and the residual module is used for predicting corresponding output according to the input; generating a training data set according to the to-be-reduced-order circuit model, and training a residual module and a tensor mapping structure in the target mapping equation to obtain a trained target mapping equation; and generating an order reduction result according to the target circuit model and the trained target mapping equation. According to the method, the trained target mapping equation can be adopted on the basis of the target circuit model, so that the precision of the multi-port model after order reduction can be improved.

Description

Technical Field

[0001] This invention relates to the field of linear system model reduction, and more particularly to a method, system, terminal, and computer-readable storage medium for reducing the model order of a multi-port linear circuit. Background Technology

[0002] Model order reduction (MOR) techniques for linear systems have been widely applied in various stages of electronic design automation (EDA) workflows to accelerate design space exploration and optimization. However, traditional projection-based MOR methods suffer from significant efficiency bottlenecks when dealing with systems with a large number of input / output ports. Correspondingly, to alleviate the problems caused by a large number of ports, current methods include compressing the input / output matrices using Singular Value Decomposition (SVD), decoupling input / output port pairs to reduce the number of ports involved in modeling, or modeling specific inputs.

[0003] However, among the current methods to alleviate the problems caused by the large number of ports, the input-independent MOR method is difficult to balance modeling accuracy and computational resources, while the MOR method that relies entirely on specific inputs lacks flexibility and robustness, making it unable to meet the growing demand for power consumption modeling in advanced integrated circuit design, thus affecting the realization of electronic design automation.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main objective of this invention is to provide a model reduction method, system, terminal, and computer-readable storage medium for multi-port linear circuits. This invention aims to address the problem that, in existing methods for mitigating the problems caused by a large number of ports, the input-independent MOR method struggles to balance modeling accuracy and computational resources, while the MOR method that relies entirely on specific inputs lacks flexibility and robustness. Consequently, these methods fail to meet the growing demand for power consumption modeling in advanced integrated circuit design, thus affecting the realization of electronic design automation.

[0006] To achieve the above objectives, the present invention provides a model order reduction method for multi-port linear circuits, the model order reduction method for multi-port linear circuits comprising the following steps: Obtain the circuit model to be downgraded, and reduce the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model; Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input. Based on the circuit model to be reduced in order, a training dataset is generated, and the residual module and tensor mapping structure in the target mapping equation are trained based on the training dataset to obtain the trained target mapping equation. Based on the target circuit model and the trained target mapping equation, a reduced-order result is generated.

[0007] Optionally, the step of obtaining the circuit model to be downgraded, and reducing the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model, specifically includes: Obtain the circuit model to be downgraded, and perform singular value decomposition on the input and output of the circuit model to be downgraded according to the port reduction strategy to obtain the first circuit model to be downgraded after the number of ports is reduced. The first circuit model to be reduced in order is reduced according to the preset model reduction algorithm to obtain the target circuit model.

[0008] Optionally, the step of constructing the target mapping equation based on the target circuit model, residual module, and tensor mapping structure specifically includes: Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the target mapping equation is expressed as: ; in, Indicates input, This represents the residual module between high and low precision. This represents the calculation result of the residual module. Represents a tensor mapping structure. This indicates the second precision output. This indicates the first precision output.

[0009] Optionally, generating a training dataset based on the circuit model to be reduced in order specifically includes: Perform a preset number of time-domain simulations on the circuit model to be reduced in order, and obtain the second precision output obtained from each time-domain simulation; A training dataset is generated based on all time-domain simulation inputs and their corresponding second-precision outputs.

[0010] Optionally, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset to obtain the trained target mapping equation specifically includes: Based on the training dataset, the residual modules and tensor mapping structures in the target mapping equation are trained using a joint optimization approach; When the training reaches the preset requirements, the training ends, and the target mapping equation for the completed training is obtained based on the residual module and tensor mapping structure obtained from the last training.

[0011] Optionally, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset and using a joint optimization approach specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision training output. The first precision training output is then input into the target mapping equation to obtain the mapping output and residual data. Obtain the residual prediction output by the tensor mapping structure, and optimize the residual module and the tensor mapping structure based on the residual data and the residual prediction.

[0012] Optionally, the step of inputting the time-domain simulation input from the training dataset into the target circuit model to obtain a first-precision training output, and inputting the first-precision training output into the target mapping equation to obtain the mapping output and residual data, specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision output of the training; The first precision output of the training is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation; Substituting the training first precision output, second precision output, and mapping output into the target mapping equation yields the residual data.

[0013] Furthermore, to achieve the above objectives, the present invention also provides a model order reduction system for multi-port linear circuits, wherein the model order reduction system for multi-port linear circuits includes: The order reduction module is used to obtain the circuit model to be reduced in order, and reduce the number of ports of the circuit model to be reduced in order according to the port reduction strategy to obtain the target circuit model. A construction module is used to construct a target mapping equation based on the target circuit model, the residual module, and the tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input; The training module is used to generate a training dataset based on the circuit model to be reduced in order, and to train the residual module and tensor mapping structure in the target mapping equation based on the training dataset to obtain the trained target mapping equation. The result generation module is used to generate reduced-order results based on the target circuit model and the trained target mapping equation.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a terminal, wherein the terminal includes: a memory, a processor, and a model reduction program for a multi-port linear circuit stored in the memory and executable on the processor, wherein when the model reduction program for the multi-port linear circuit is executed by the processor, it implements the steps of the model reduction method for the multi-port linear circuit as described above.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a model reduction program for a multi-port linear circuit, and when the model reduction program for the multi-port linear circuit is executed by a processor, it implements the steps of the model reduction method for the multi-port linear circuit as described above.

[0016] In this invention, a circuit model to be downgraded is obtained, and the number of ports in the circuit model to be downgraded is reduced according to a port reduction strategy to obtain a target circuit model. Based on the target circuit model, residual modules, and a tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be downgraded and the target circuit model, and the residual modules are used to predict the corresponding output based on the input. A training dataset is generated based on the circuit model to be downgraded, and the residual modules and tensor mapping structure in the target mapping equation are trained based on the training dataset to obtain a trained target mapping equation. A downgraded result is generated based on the target circuit model and the trained target mapping equation. This invention reduces the port dimension of the system through a port reduction strategy, combines it with traditional MOR technology to obtain a low-precision downgraded model, and then corrects the deviation between the low-precision model and the actual system behavior based on the target mapping equation. Furthermore, the tensor mapping structure fully explores the correlation between the system in the port dimension and the time dimension, thereby achieving more accurate output prediction with limited samples, and thus obtaining a downgraded result that can output accurate results. Attached Figure Description

[0017] Figure 1 This is a flowchart of a preferred embodiment of the model order reduction method for multi-port linear circuits of the present invention; Figure 2 This is a conceptual diagram of accuracy compensation in the model order reduction method for multi-port linear circuits of this invention; Figure 3 This is an overall implementation framework diagram of the model order reduction method for multi-port linear circuits in this invention; Figure 4 This is a visualization of the predictions from tensor mapping learning in the model order reduction method for multi-port linear circuits of this invention. Figure 5 This is a structural diagram of a preferred embodiment of the model order reduction system of the multi-port linear circuit of the present invention; Figure 6 This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] Model reduction techniques for linear systems have been widely applied in various stages of electronic design automation (EDA) processes to accelerate design space exploration and optimization. A key application scenario for Model Reduction (MOR) is chip power modeling (CPM). In this scenario, the large-scale power delivery network (PDN) inside the chip is typically modeled as a large network containing resistors, inductors, and capacitors (RLC). MOR techniques are used to reduce this to a smaller equivalent model to support co-simulation analysis of the chip and its package. Currently, Krylov subspace methods based on subspaces, such as the PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm), are widely adopted as the mainstream MOR solution due to their excellent moment matching ability, efficient handling of sparse matrices, and good compression ratio. However, traditional projection-based MOR methods suffer from significant efficiency bottlenecks when dealing with systems with a large number of input / output ports. For example, the computational overhead and the size of the final reduced-order model (ROM) typically increase linearly or even faster with the number of ports. As the complexity of integrated circuit (IC) design continues to increase, especially in emerging multi-chip 3D integrated architectures, the scale of PDN nodes can reach tens of millions, and the number of ports can reach hundreds of thousands. Reduced-order modeling of such ultra-large-scale networks has become a key bottleneck in power integrity design and optimization. To alleviate the problems caused by the large number of ports, existing technologies mainly fall into two categories: one is to compress the input / output matrix through singular value decomposition (SVD) or to reduce the number of ports involved in modeling by decoupling input / output port pairs. This type of method is input-independent, and the resulting ROM can be reused for arbitrary input conditions, but it usually has a large error because it no longer strictly satisfies the moment matching conditions of the original system. The other type of method models specific inputs; even if the ROM has high accuracy and modeling efficiency, it lacks reusability and cannot cope with the complex and varied input patterns in actual designs. Therefore, among the existing methods for alleviating the problems caused by a large number of ports, the input-independent MOR method is difficult to balance modeling accuracy and computational resources, while the MOR method that relies entirely on specific inputs lacks flexibility and robustness. This makes it impossible to meet the growing demand for power consumption modeling in advanced integrated circuit design, thus affecting the realization of electronic design automation.

[0020] To address one or more of the above-mentioned problems, this invention obtains a circuit model to be reduced in order, reduces the number of ports in the circuit model to be reduced in order according to a port reduction strategy, and obtains a target circuit model; based on the target circuit model, residual modules, and tensor mapping structure, a target mapping equation is constructed; based on the circuit model to be reduced in order, a training dataset is generated, and the residual modules and tensor mapping structure in the target mapping equation are trained based on the training dataset to obtain a trained target mapping equation; based on the target circuit model and the trained target mapping equation, a reduction in order result is generated.

[0021] The preferred embodiment of the present invention describes a model reduction method for multi-port linear circuits, such as... Figure 1 As shown, the model reduction method for the multi-port linear circuit includes the following steps: Step S10: Obtain the circuit model to be downgraded, and reduce the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model.

[0022] Specifically, in this invention, for the circuit model to be reduced in order, the number of ports in the system is first reduced, and the corresponding order reduction process is performed to obtain the corresponding target circuit model, which is a low-precision circuit model.

[0023] Further, the step of obtaining the circuit model to be downgraded, and reducing the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model, specifically includes: Obtain the circuit model to be downgraded, and perform singular value decomposition on the input and output of the circuit model to be downgraded according to the port reduction strategy to obtain the first circuit model to be downgraded after the number of ports is reduced. The first circuit model to be reduced in order is reduced according to the preset model reduction algorithm to obtain the target circuit model.

[0024] Specifically, most current methods for reducing the number of ports in a system rely on complex mathematical formulas, which leads to significant implementation complexity and computational overhead. This invention employs a method based on input and output matrices. A simple port reduction method for decomposition.

[0025] In this invention, the input matrix is ​​made to... and output matrix Same, that is ,right B and L Matrix operation (Singular value decomposition). This yields the following expression: ; in, It is the left singular vector of the matrix. It is a singular value matrix. It is a right singular vector matrix. T Indicates transpose; and It is the truncated submatrix; this invention selects the preceding submatrix. r The largest singular value , This is the original number of ports, obtained through this... The truncation approximation will change the original transfer function from the original... : ; It becomes the following form: ; in, This represents the changed transfer function. Represents a complex frequency variable. , It is angular frequency. Indicates the real part. This represents the imaginary part, or the imaginary unit. The conductance matrix, composed of linear elements such as resistors and admittances, reflects the conductance relationships between nodes. This represents a capacitor matrix, which is composed of energy storage elements such as capacitors and inductors.

[0026] middle Part of, namely This becomes the new model of the present invention that needs to be reduced in order, namely the first circuit model to be reduced in order, wherein the number of ports in the middle part has been reduced from It dropped to ,in Indicates the middle The transfer function corresponding to the part. In the method of reducing the number of ports using singular value decomposition proposed in this invention, any model reduction method, such as Both can be applied to this low-port system to obtain a reduced-order model. (This order reduction model is achieved through...) go through (Or obtained by reducing the order of another model using other model reduction algorithms) After that, the original has A circuit with one port can be recovered using this formula: ; in, It is original and has The model after circuit reconstruction with only one port is shown. It is worth noting that the core model reduction process is only applied to a single port. On a system with multiple ports, computational efficiency and the final order of the explained model will be improved. And after restoration... The port model is then used in simulations to ensure port compatibility with the original circuit.

[0027] The target circuit model obtained after reducing the order of the first circuit model to be reduced using a preset model reduction method is used for subsequent processing. The preset model reduction method is selected in advance. In one embodiment of the invention, the preset model reduction method can be... .

[0028] Step S20: Based on the target circuit model, residual module, and tensor mapping structure, construct the target mapping equation, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input.

[0029] Specifically, in this invention, the compressed circuit is obviously inaccurate because it contains not only errors from model reduction but also errors from the port compression step. Since only a small portion of singular values ​​are retained, this port reduction error is particularly severe for high-port-count scenarios. To address this accuracy issue, this invention represents the original model as a high-precision model, with the corresponding solution or output serving as either the true value or high-precision data. Then, using these two different multi-precision data sets as specific representative inputs, a compensation network is trained, consisting of a residual module and a tensor mapping structure. The trained residual module can generate corresponding outputs based on each input, and the trained tensor mapping structure can represent the correlation between the circuit model to be reduced and the target circuit model, thereby allowing the target mapping equation to optimize the target circuit model output, bringing it closer to the corresponding high-precision output. This compensation network is primarily used to improve the accuracy of low-precision outputs to a high-precision level, and this improvement is achieved using a target mapping equation, which is a multi-precision mapping equation. A conceptual diagram of this accuracy compensation is shown below. Figure 2 As shown.

[0030] Furthermore, the construction of the target mapping equation based on the target circuit model, residual module, and tensor mapping structure specifically includes: Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the target mapping equation is expressed as: ; in, Indicates input, This represents the residual module between high and low precision. This represents the calculation result of the residual module. Represents a tensor mapping structure. This indicates the second precision output. This indicates the first precision output.

[0031] in, and These are the transient simulation outputs of the high-precision and low-precision models, respectively. The relationship between the input and output is determined by a mapping equation: Then, a target mapping equation can be constructed.

[0032] Step S30: Generate a training dataset based on the circuit model to be reduced in order, and train the residual module and tensor mapping structure in the target mapping equation based on the training dataset to obtain the trained target mapping equation.

[0033] Specifically, in this invention, using Defined as a high-precision dataset, Defined as a low-precision dataset, input Represents the voltage input to the circuit and current source excitation , and These are the transient simulation outputs of high-precision and low-precision models, respectively. The high-precision model is the circuit model to be reduced in order, from which the corresponding training dataset can be obtained. The training dataset is then used to train the residual modules and tensor mapping structures in the corresponding target mapping equation.

[0034] The step of generating a training dataset based on the circuit model to be reduced in order specifically includes: Perform a preset number of time-domain simulations on the circuit model to be reduced in order, and obtain the second precision output obtained from each time-domain simulation; A training dataset is generated based on all time-domain simulation inputs and their corresponding second-precision outputs.

[0035] Specifically, the corresponding training dataset is obtained through time-domain simulation, and then the residual module and tensor mapping structure are trained.

[0036] Further, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset to obtain the trained target mapping equation specifically includes: Based on the training dataset, the residual modules and tensor mapping structures in the target mapping equation are trained using a joint optimization approach; When the training reaches the preset requirements, the training ends, and the target mapping equation for the completed training is obtained based on the residual module and tensor mapping structure obtained from the last training.

[0037] The specific training process is as follows: Figure 3 As shown, this includes the training path, the prediction path, and the components in the framework scheme that require weight learning. It can be seen that this invention addresses the input... Prediction It is implemented using an ANN (Artificial Neural Network), and for arrive The prediction is performed by mapping two tensor mapping matrices.

[0038] The training ends when the corresponding training reaches the preset requirements, which are the number of training iterations or the model accuracy set in advance.

[0039] Furthermore, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset and using a joint optimization approach specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision training output. The first precision training output is then input into the target mapping equation to obtain the mapping output and residual data. Obtain the residual prediction output by the tensor mapping structure, and optimize the residual module and the tensor mapping structure based on the residual data and the residual prediction.

[0040] Specifically, in order to learn the correlation between high-precision and low-precision data, this invention proposes a tensor mapping structure component, specifically given a low-precision input tensor. ,in Represents the set of real numbers. It's the amount of data. It refers to the dimensionality of the data in each dimension. n A series of mapping matrices corresponding to tensor patterns are defined from 1 to N. After inputting a tensor, the following operations will be performed: ; This represents a tensor matrix multiplication modulo -n, where tensor matrix multiplication is expressed as: ; Represents the tensor matrix to be multiplied. i and j Let represent the magnitude of the tensor matrix, where j This indicates the corresponding modulus for which modulo-n tensor multiplication needs to be performed. i This represents the remaining modulo.

[0041] In this invention, the multi-precision tensor mapping structure is primarily used to leverage the port-to-port and time-to-time correlations between data. This is because there are correlations between port-to-port and time-to-time output responses within the same system, and utilizing these correlations can significantly improve learning ability and the efficiency of the compensation network. According to actual needs, Organized into such a three-dimensional tensor ; and These represent the number of ports and the simulation step size, respectively. This represents the batch size. In this tensor mapping, two learnable mapping matrices are introduced, where... It is responsible for the response correlation between different ports at the same point in time. It is responsible for the response correlation between different points in time on the same port. Indicates the number of ports in a high-precision circuit. The simulation time of the high-precision circuit is represented; then the mapped tensor can be calculated as: ; These are two learnable tensor mapping matrices, initialized as diagonal matrices. This is because initially, the model assumes no temporal correlation between different ports and different times. During training, the off-diagonal learnable variables gradually learn the correlation information between ports and between times. The two learnable mapping matrices are then used to... The calculation will ultimately help the overall algorithm calculate the final compensation result. This compensation result will be compared with the actual result to calculate an MSE loss (Mean Squared Error Loss). Finally, the learnable parameters of the matrix will be updated through the backpropagation process of PyTorch.

[0042] like Figure 4 As shown, a simple example explains why this mapping matrix can achieve this function; the trained matrix... It is no longer a diagonal matrix. For the given example, the low-precision output... It is The matrix, where each column represents the output of all ports at a time step. The first line and The result of multiplying the first column is the predicted output of the sample at the first time point of the first port.

[0043] Furthermore, the present invention mainly includes two learnable components: a tensor learning structure. and a residual network The residual network is implemented using a multilayer perceptron network. During training, and The parameters in the model are jointly trained to ensure that the learned mappings are consistent with the residual predictions. Specifically, the Adam optimizer is used, and the learning rate during training is set. The MSE loss is calculated using the final compensation result predicted by the overall framework and the true result to represent the overall final loss. Finally, gradient backpropagation and weight updates are performed through PyTorch's backpropagation process. Here, both the ANN and the two mapping matrices update the weight parameters through backpropagation.

[0044] The step of inputting the time-domain simulation input from the training dataset into the target circuit model to obtain the first-precision training output, and then inputting the first-precision training output into the target mapping equation to obtain the mapping output and residual data, specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision output of the training; The first precision output of the training is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation; Substituting the training first precision output, second precision output, and mapping output into the target mapping equation yields the residual data.

[0045] Specifically, given a low-precision response output First, it goes through a tensor mapping structure. Obtain the mapped output Then the residual data is passed through get( This refers to the high-precision result corresponding to the low-precision response, i.e., the simulation output obtained from the original model. That is, residual network The target output to be predicted, and the input... In this invention, a simulation encompassing port voltage or current excitation across the entire analog range needs to be organized and responded to with output. Same dimensions. Input The input needs to be fed into the residual network to predict the corresponding prediction result. .

[0046] Step S40: Generate the order reduction result based on the target circuit model and the trained target mapping equation.

[0047] After obtaining the target circuit model and the trained target mapping equation, a reduced-order result is obtained. This reduced-order result yields a low-precision result for each voltage and current source excitation input to the circuit. The accurate result is then obtained by using the trained target mapping equation.

[0048] This invention obtains a circuit model to be downgraded, reduces the number of ports in the model according to a port reduction strategy, and obtains a target circuit model. Based on the target circuit model, residual modules, and a tensor mapping structure, a target mapping equation is constructed. The tensor mapping structure represents the correlation between the circuit model to be downgraded and the target circuit model, and the residual modules predict the corresponding output based on the input. A training dataset is generated based on the circuit model to be downgraded, and the residual modules and tensor mapping structure in the target mapping equation are trained using the training dataset to obtain a trained target mapping equation. A downgraded result is generated based on the target circuit model and the trained target mapping equation. This invention reduces the port dimension of the system through a port reduction strategy, combines this with traditional MOR (Modal-Order Reduction) techniques to obtain a low-precision downgraded model, and then corrects the deviation between the low-precision model and the actual system behavior based on the target mapping equation. Furthermore, the tensor mapping structure fully exploits the correlation between the system in the port and time dimensions, thereby achieving more accurate output prediction with limited samples, resulting in a downgraded result that can output accurate results.

[0049] Furthermore, such as Figure 5 As shown, based on the above-mentioned model reduction method for multi-port linear circuits, the present invention also provides a model reduction system for multi-port linear circuits, wherein the model reduction system for multi-port linear circuits includes: The order reduction module 51 is used to obtain the circuit model to be reduced in order, and reduce the number of ports of the circuit model to be reduced in order according to the port reduction strategy to obtain the target circuit model. The construction module 52 is used to construct a target mapping equation based on the target circuit model, the residual module, and the tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input. Training module 53 is used to generate a training dataset based on the circuit model to be reduced in order, and to train the residual module and tensor mapping structure in the target mapping equation based on the training dataset to obtain the trained target mapping equation. The result generation module 54 is used to generate a reduced-order result based on the target circuit model and the trained target mapping equation.

[0050] Furthermore, such as Figure 6 As shown, based on the above-mentioned model reduction method and system for multi-port linear circuits, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 6Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0051] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Further, the memory 20 may include both internal and external storage devices. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores a model reduction program 40 for a multi-port linear circuit, which can be executed by the processor 10 to implement the model reduction method for multi-port linear circuits in this invention.

[0052] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing a model reduction method for the multi-port linear circuit.

[0053] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display 30 is used to display information on the terminal and to display a visual user interface.

[0054] In one embodiment, the processor 10 implements the steps of the above-described model reduction method for multi-port linear circuits when executing the model reduction program 40 for the multi-port linear circuit in the memory 20.

[0055] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a model reduction program for a multi-port linear circuit, and the model reduction program for the multi-port linear circuit, when executed by a processor, performs the following steps: Obtain the circuit model to be downgraded, and reduce the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model; Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input. Based on the circuit model to be reduced in order, a training dataset is generated, and the residual module and tensor mapping structure in the target mapping equation are trained based on the training dataset to obtain the trained target mapping equation. Based on the target circuit model and the trained target mapping equation, a reduced-order result is generated.

[0056] Specifically, obtaining the circuit model to be downgraded, and reducing the number of ports in the circuit model to be downgraded according to a port reduction strategy to obtain the target circuit model, includes: Obtain the circuit model to be downgraded, and perform singular value decomposition on the input and output of the circuit model to be downgraded according to the port reduction strategy to obtain the first circuit model to be downgraded after the number of ports is reduced. The first circuit model to be reduced in order is reduced according to the preset model reduction algorithm to obtain the target circuit model.

[0057] Specifically, the construction of the target mapping equation based on the target circuit model, residual module, and tensor mapping structure includes: Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the target mapping equation is expressed as: ; in, Indicates input, This represents the residual module between high and low precision. This represents the calculation result of the residual module. Represents a tensor mapping structure. This indicates the second precision output. This indicates the first precision output.

[0058] Specifically, generating the training dataset based on the circuit model to be reduced in order includes: Perform a preset number of time-domain simulations on the circuit model to be reduced in order, and obtain the second precision output obtained from each time-domain simulation; A training dataset is generated based on all time-domain simulation inputs and their corresponding second-precision outputs.

[0059] Specifically, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset to obtain the trained target mapping equation includes: Based on the training dataset, the residual modules and tensor mapping structures in the target mapping equation are trained using a joint optimization approach; When the training reaches the preset requirements, the training ends, and the target mapping equation for the completed training is obtained based on the residual module and tensor mapping structure obtained from the last training.

[0060] Specifically, the step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset and using a joint optimization method includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision training output. The first precision training output is then input into the target mapping equation to obtain the mapping output and residual data. Obtain the residual prediction output by the tensor mapping structure, and optimize the residual module and the tensor mapping structure based on the residual data and the residual prediction.

[0061] Specifically, the step of inputting the time-domain simulation input from the training dataset into the target circuit model to obtain the first-precision training output, and inputting the first-precision training output into the target mapping equation to obtain the mapping output and residual data, includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision output of the training; The first precision output of the training is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation; Substituting the training first precision output, second precision output, and mapping output into the target mapping equation yields the residual data.

[0062] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal that includes that element.

[0063] Of course, those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The computer-readable storage medium can be a memory, magnetic disk, optical disk, etc.

[0064] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for reducing the order of a multi-port linear circuit model, characterized in that, The model reduction method for the multi-port linear circuit includes: Obtain the circuit model to be downgraded, and reduce the number of ports in the circuit model to be downgraded according to the port reduction strategy to obtain the target circuit model; Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input. Based on the circuit model to be reduced in order, a training dataset is generated. Based on the training dataset, the residual module and tensor mapping structure in the target mapping equation are trained to obtain the trained target mapping equation. Based on the target circuit model and the trained target mapping equation, a reduced-order result is generated.

2. The method for reducing the order of a multi-port linear circuit model according to claim 1, characterized in that, The process of obtaining the circuit model to be downgraded, and reducing the number of ports in the circuit model to be downgraded according to the port reduction strategy, to obtain the target circuit model, specifically includes: Obtain the circuit model to be downgraded, and perform singular value decomposition on the input and output of the circuit model to be downgraded according to the port reduction strategy to obtain the first circuit model to be downgraded after the number of ports is reduced. The first circuit model to be reduced in order is reduced according to the preset model reduction algorithm to obtain the target circuit model.

3. The method for reducing the order of a multi-port linear circuit model according to claim 1, characterized in that, The construction of the target mapping equation based on the target circuit model, residual module, and tensor mapping structure specifically includes: Based on the target circuit model, residual module, and tensor mapping structure, a target mapping equation is constructed, wherein the target mapping equation is expressed as: ； in, Indicates input, This represents the residual module between high and low precision. This represents the calculation result of the residual module. This represents a tensor mapping structure. This indicates the second precision output. This indicates the first precision output.

4. The method for reducing the order of a multi-port linear circuit model according to claim 1, characterized in that, The step of generating a training dataset based on the circuit model to be reduced in order specifically includes: Perform a preset number of time-domain simulations on the circuit model to be reduced in order, and obtain the second precision output obtained from each time-domain simulation; A training dataset is generated based on all time-domain simulation inputs and their corresponding second-precision outputs.

5. The method for reducing the order of a multi-port linear circuit model according to claim 4, characterized in that, The step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset to obtain the trained target mapping equation specifically includes: Based on the training dataset, the residual modules and tensor mapping structures in the target mapping equation are trained using a joint optimization approach; When the training reaches the preset requirements, the training ends, and the target mapping equation for the completed training is obtained based on the residual module and tensor mapping structure obtained from the last training.

6. The method for reducing the order of a multi-port linear circuit model according to claim 5, characterized in that, The step of training the residual modules and tensor mapping structures in the target mapping equation based on the training dataset and using a joint optimization approach specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision training output. The first precision training output is then input into the target mapping equation to obtain the mapping output and residual data. Obtain the residual prediction output by the tensor mapping structure, and optimize the residual module and the tensor mapping structure based on the residual data and the residual prediction.

7. The method for reducing the order of a multi-port linear circuit model according to claim 6, characterized in that, The step of inputting the time-domain simulation input from the training dataset into the target circuit model to obtain the first-precision training output, and then inputting the first-precision training output into the target mapping equation to obtain the mapping output and residual data, specifically includes: The time-domain simulation input from the training dataset is input into the target circuit model to obtain the first precision output of the training; The first precision output of the training is input into the target mapping equation, and a mapping output is generated according to the tensor mapping structure in the target mapping equation; Substituting the training first precision output, second precision output, and mapping output into the target mapping equation yields the residual data.

8. A model reduction system for a multi-port linear circuit, characterized in that, The model reduction system for the multi-port linear circuit includes: The order reduction module is used to obtain the circuit model to be reduced in order, and reduce the number of ports of the circuit model to be reduced in order according to the port reduction strategy to obtain the target circuit model. A construction module is used to construct a target mapping equation based on the target circuit model, the residual module, and the tensor mapping structure, wherein the tensor mapping structure is used to represent the correlation between the circuit model to be reduced in order and the target circuit model, and the residual module is used to predict the corresponding output based on the input; The training module is used to generate a training dataset based on the circuit model to be reduced in order, and to train the residual module and tensor mapping structure in the target mapping equation based on the training dataset to obtain the trained target mapping equation. The result generation module is used to generate reduced-order results based on the target circuit model and the trained target mapping equation.

9. A terminal, characterized in that, The terminal includes: a memory, a processor, and a model reduction program for a multiport linear circuit stored in the memory and executable on the processor. When the model reduction program for the multiport linear circuit is executed by the processor, it implements the steps of the model reduction method for the multiport linear circuit as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a model reduction program for a multi-port linear circuit, which, when executed by a processor, implements the steps of the model reduction method for a multi-port linear circuit as described in any one of claims 1-7.

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