Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, a pixel circuit in the display panel comprises a driving transistor, a first compensation module and a second compensation module, the first compensation module is used for transmitting a reference signal to a first source-drain end of the driving transistor in a first time period, and the second compensation module is used for transmitting a reference signal to a second source-drain end of the driving transistor in a second time period; the second compensation module is used for controlling the second source-drain end of the driving transistor and the grid electrode of the driving transistor to form a current path in the first time period and the second time period. The driving transistor is changed from the on state at the start to the off state at the end in each of the first period and the second period, thereby improving the brightness unevenness of the display panel and the life performance of the driving transistor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display panels and their driving methods. Background Technology

[0002] AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels have advantages such as fast response speed, high contrast, and wide viewing angle.

[0003] In AMOLED display panels, the traditional pixel circuit compensates for the threshold voltage of the driving transistor by writing data signals during operation. However, for high refresh rate scenarios, the writing time of data signals is short, resulting in a lower degree of compensation for the threshold voltage of the driving transistor, which leads to uneven brightness or worse lifespan of the AMOLED display panel. Summary of the Invention

[0004] This invention provides a display panel and its driving method to improve the uneven brightness or poor lifespan of AMOLED display panels.

[0005] This invention provides a display panel including a plurality of sub-pixels. Each sub-pixel includes an electrically connected light-emitting element and a pixel circuit. The pixel circuit includes:

[0006] A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light.

[0007] The first compensation module is electrically connected to the first source-drain terminal of the driving transistor, and is used to transmit a reference signal to the first source-drain terminal of the driving transistor in a first time period, and to transmit a data signal to the first source-drain terminal of the driving transistor in a second time period after the first time period.

[0008] The second compensation module is electrically connected between the second source / drain terminal of the driving transistor and the gate of the driving transistor, and is used to control the formation of a current path between the second source / drain terminal of the driving transistor and the gate of the driving transistor during the first time period and the second time period.

[0009] The driving transistor is in the on state at the beginning of the first time period, and transitions from the on state to the off state during the first time period, so as to be in the off state at the end of the first time period.

[0010] The driving transistor is in the on state at the beginning of the second time period, and transitions from the on state to the off state during the second time period, ending in the off state at the end of the second time period.

[0011] This invention also provides a driving method for a display panel, applied to a display panel comprising a plurality of sub-pixels, each sub-pixel comprising an electrically connected light-emitting element and a pixel circuit, the pixel circuit comprising:

[0012] A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light.

[0013] The first compensation module is electrically connected to the first source-drain terminal of the driving transistor and is used for time-division transmission of reference signals and data signals.

[0014] The second compensation module is electrically connected between the second source / drain terminal of the driving transistor and the gate of the driving transistor;

[0015] The driving method for the display panel includes:

[0016] During the first time period, the reference signal is transmitted to the gate of the driving transistor through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor changes from the on state to the off state.

[0017] In the second period following the first period, the data signal is transmitted to the gate of the driving transistor through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor changes from the on state to the off state.

[0018] This invention provides a display panel and its driving method. The display panel includes multiple sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel circuit. The pixel circuit includes a driving transistor, a first compensation module, and a second compensation module. By configuring the first compensation module to transmit a reference signal to the first source-drain terminal of the driving transistor in a first time period and to transmit a data signal to the first source-drain terminal of the driving transistor in a second time period after the first time period, and configuring the second compensation module to control the formation of a current path between the second source-drain terminal of the driving transistor and the gate of the driving transistor in the first and second time periods, the driving transistor changes from an on state at the beginning to an off state at the end in each of the first and second time periods. This increases the degree of improvement on the threshold voltage of the driving transistor, thereby improving the brightness uniformity of the display panel and the lifespan performance of the driving transistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the display panel architecture provided in an embodiment of the present invention.

[0021] Figure 2 and Figure 3 This is a schematic diagram of a sub-pixel and its pixel circuit provided in an embodiment of the present invention.

[0022] Figure 4 and Figure 5 The waveform diagram shows a portion of the signals in the pixel circuit provided in an embodiment of the present invention.

[0023] Figures 6 to 7 The diagram provided as a comparative example of the present invention illustrates the change in brightness ΔL with the change in threshold voltage ΔVth for refresh rates of 120Hz and 240Hz.

[0024] Figures 8 to 9 This is a schematic diagram showing the change in brightness ΔL with the change in threshold voltage ΔVth for refresh rates of 120Hz and 240Hz, respectively, according to an embodiment of the present invention.

[0025] Figure 10 A flowchart of a display panel driving method provided in an embodiment of the present invention.

[0026] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In this document, the source and drain of a transistor are not distinguished and can be interchanged. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the attached drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] The present invention provides a display panel, which includes, but is not limited to, the following embodiments and combinations thereof.

[0031] The present invention provides a display panel 100, which includes, but is not limited to, the following embodiments and combinations thereof.

[0032] In some embodiments, combined with Figures 1 to 5As shown, the display panel 100 includes a plurality of sub-pixels Pi, each sub-pixel Pi including an electrically connected light-emitting element 01 and a pixel circuit 02. The pixel circuit 02 includes: a driving transistor T1, used to generate a driving current according to a data signal Data to drive the light-emitting element 01 to emit light; a first compensation module 20, electrically connected to the first source-drain terminal (i.e., the first node A) of the driving transistor T1, used to transmit a reference signal Vref to the first source-drain terminal of the driving transistor T1 in a first time period t1, and used to transmit a data signal Data to the first source-drain terminal of the driving transistor T1 in a second time period t2 after the first time period t1; and a second compensation module 30, electrically connected to the second source-drain terminal (i.e., the second node B) of the driving transistor T1 and the gate (i.e., the second node B) of the driving transistor T1. Between the three nodes (Q), a current path is formed between the second source / drain terminal of the driving transistor T1 and the gate of the driving transistor T1 during the first time period t1 and the second time period t2; wherein, the driving transistor T1 changes from a conducting state to a cutoff state in each of the first time period t1 and the second time period t2, which can be understood as follows: the driving transistor T1 is in a conducting state at the beginning of the first time period t1, and changes from a conducting state to a cutoff state during the first time period t1, so as to be in a cutoff state at the end of the first time period t1; and the driving transistor T1 is in a conducting state at the beginning of the second time period t2, and changes from a conducting state to a cutoff state during the second time period t2, so as to be in a cutoff state at the end of the second time period t2.

[0033] The display panel 100 can be a self-emissive display panel, that is, the display panel 100 displays images through the self-emission of the light-emitting element Di in the sub-pixel Pi.

[0034] Specifically, such as Figure 1 As shown, the display panel 100 may further include cascaded multi-stage gate driving units (forming a gate driving circuit 101); a timing controller 102, each gate driving unit being electrically connected between the timing controller 102 and a corresponding plurality of pixel circuits 02, for outputting a gate signal Gate transmitted to the corresponding plurality of pixel circuits 02; and at least one source driver 103, each source driver 103 being electrically connected between the timing controller 102 and a corresponding plurality of pixel circuits 02, for outputting the aforementioned data signal Data transmitted to the corresponding plurality of pixel circuits 02. The display panel 100 may include an electrically connected panel body 10 and a driving chip. The panel body 10 has the aforementioned gate driving circuit 101 and a plurality of sub-pixels Pi disposed on its substrate. The driving chip may include the timing controller 102 and the source driver 103.

[0035] Among them, such as Figure 1As shown here, taking the arrangement of multiple sub-pixel Pi arrays as an example, the aforementioned gate signal Gate can at least include the first gate signal Scan2. Combined with... Figures 1 to 7 As shown, each gate driving unit outputs a corresponding first gate signal Scan2 according to the first control signal provided by the timing controller 102. The multiple first gate pulses p1 in the multi-level first gate signals Scan2, which are used to turn on the multiple rows of sub-pixels Pi, can be arranged sequentially on the time axis to turn on the multiple rows of sub-pixels Pi in sequence.

[0036] The source driver 103 can generate multiple data signals Data that are output to multiple columns of sub-pixels Pi through multiple data lines according to the second control signal provided by the timing controller 102. Each data signal Data can include multiple data voltages corresponding to multiple sub-pixels Pi in the same column. When each row of sub-pixels Pi is turned on, the multiple data lines receive multiple data voltages of the multiple sub-pixels Pi located in that row, so that the multiple data voltages act on the multiple sub-pixels Pi in that row to realize the light emission of multiple light-emitting elements Di in the multiple sub-pixels Pi in that row. In this way, the light-emitting elements Di of all rows can be controlled to emit light in sequence to present a complete picture.

[0037] As discussed above, for each sub-pixel Pi, the corresponding first gate signal Scan2 can control the transmission of the corresponding data voltage in the corresponding data signal Data to that sub-pixel Pi, and the corresponding driving transistor T1 generates the corresponding driving current according to the data signal Data to drive the light-emitting element O1 to emit light of the corresponding brightness.

[0038] Specifically, the first compensation module 20 transmits the data signal Data to the first source-drain terminal (i.e., the first node A) of the driving transistor T1 in the second time period t2, and the second compensation module 30 controls the second source-drain terminal of the driving transistor T1 to form a current path between the gate of the driving transistor T1 in the second time period t2, so that the driving transistor T1 changes from the on state to the off state in the second time period t2. During this process, the threshold voltage of the driving transistor T1 is compensated.

[0039] It is important to note that, in combination Figure 4 and Figure 5As shown, when the refresh rate of the display panel 100 is high, the total scanning time of multiple rows of sub-pixels Pi is short, so the pulse width t of the first gate pulse p1 in the first gate signal Scan2 in each row of sub-pixels Pi is short. This results in a shorter duration for the data voltage in the data signal Data to act on the gate of the driving transistor T1, leading to a smaller degree of compensation for the threshold voltage of the driving transistor T1. Consequently, the threshold voltage of the subsequent driving transistor T1 has a greater impact on the driving current it generates, resulting in a larger brightness deviation of the corresponding light-emitting element O1. Furthermore, for the entire display panel 100, the difference in the threshold voltage of the driving transistor T1 in different areas is inherently large. Therefore, if it is not fully compensated, the uneven brightness of the display panel 100 or the lifespan of the driving transistor T1 will be worse.

[0040] For example Figure 6 and Figure 7 The figures show the curves illustrating the change in brightness (ΔL) of the display panel 100 at refresh rates of 120Hz and 240Hz, respectively, as a function of the change in threshold voltage (ΔVth). It can be observed that, regardless of the refresh rate, the absolute value of the brightness change (ΔL) is positively correlated with the absolute value of the threshold voltage change (ΔVth). This is illustrated by the example where the brightness change (ΔL) decreases as the threshold voltage change (ΔVth) increases. Furthermore, at higher refresh rates (e.g., 240Hz), compared to lower refresh rates (e.g., 120Hz), the absolute value of the brightness change (ΔL) is more correlated with the absolute value of the threshold voltage change (ΔVth), meaning the slope of the corresponding curve is steeper. In other words, with the same absolute value of the threshold voltage change (ΔVth), the absolute value of the brightness change (ΔL) is greater at higher refresh rates.

[0041] For example Figure 8 and Figure 9 The figures shown are schematic diagrams illustrating the changes in brightness ΔL of the display panel 100 at refresh rates of 120Hz and 240Hz, respectively, as a function of the change in threshold voltage ΔVth. It can be observed that, regardless of the refresh rate, the technical solution of this embodiment can compensate for the threshold voltage of the driving transistor T1 to a greater extent; therefore, it can be considered that... Figure 8 , Figure 9 The degree of deviation or difference in the threshold voltage has a relatively small impact on the brightness of the display panel 100, so the absolute value of the slope of the corresponding curve at the same refresh rate is reduced.

[0042] As can be seen from the above discussion, for high refresh rates, the threshold voltage of the driving transistor T1 is compensated to a greater extent through the embodiments of the present invention, which can improve the impact of the threshold voltage offset or difference on the brightness of the display panel 100 to a greater extent, and improve the uneven brightness of the display panel 100 or the lifespan of the driving transistor T1 under high refresh rates.

[0043] Understandably, in this embodiment, during the first time period t1 before the second time period t2, the first compensation module 20 transmits the reference signal Vref to the first source-drain terminal (i.e., the first node A) of the driving transistor T1, and the second compensation module 30 also controls the second source-drain terminal of the driving transistor T1 to form a current path between the gate of the driving transistor T1, so that the driving transistor T1 also changes from the on state to the off state during the first time period t1 before the second time period t2. During this process, the threshold voltage of the driving transistor T1 is also compensated.

[0044] Therefore, in this embodiment, by setting the first compensation module 20 and the second compensation module 30 to compensate for the threshold voltage of the driving transistor T1 in the first time period t1 before the second time period t2, the degree of compensation for the threshold voltage of the driving transistor T1 is increased. Therefore, the threshold voltage of the subsequent driving transistor T1 has a smaller impact on the driving current it generates. Thus, the brightness deviation of the corresponding light-emitting element 01 is smaller. Moreover, for the entire display panel 100, the difference in the threshold voltage of the driving transistor T1 in different areas is relatively large. However, when it is fully compensated, the uneven brightness of the display panel 100 and the lifespan performance of the driving transistor T1 will be improved.

[0045] In some embodiments, combined with Figures 2 to 5 As shown, the first compensation module 20 includes a first compensation transistor T4 and a data writing transistor T2, both of which are electrically connected to the first source-drain terminal (i.e., the first node A) of the driving transistor T1; the second compensation module 30 includes a second compensation transistor T3, which is electrically connected between the second source-drain terminal (i.e., the second node B) of the driving transistor T1 and the gate (i.e., the third node Q) of the driving transistor T1; wherein, the first compensation transistor T4 and the second compensation transistor T3 are turned on during the first time period t1 to transmit the reference signal Vref to the gate of the driving transistor T1, so that the driving transistor T1 changes from the on state to the off state; wherein, the data writing transistor T2 and the second compensation transistor T3 are turned on during the second time period t2 to transmit the data signal Data to the gate of the driving transistor T1, so that the driving transistor T1 changes from the on state to the off state.

[0046] Specifically, the aforementioned gate signal Gate may also include a second gate signal Scan3 and a third gate signal Scan1. The first gate signal Scan2, the second gate signal Scan3, and the third gate signal Scan1 are respectively applied to the gate of the data writing transistor T2, the gate of the first compensation transistor T4, and the gate of the second compensation transistor T3.

[0047] Combination Figures 2 to 5 As shown, during the first time period t1, the second gate pulse p2 in the second gate signal Scan3 controls the first compensation transistor T4 to turn on, and the third gate pulse p3 in the third gate signal Scan1 controls the second compensation transistor T3 to turn on. The reference signal Vref is sequentially transmitted to the first source-drain terminal (i.e., the first node A), its second source-drain terminal (i.e., the second node B), and its gate (i.e., the third node Q) of the driving transistor T1, so that the threshold voltage of the driving transistor T1 is compensated for the first time when the driving transistor T1 changes from the on state to the off state.

[0048] Combination Figures 2 to 5 As shown, in the second time period t2, the first gate pulse p1 in the first gate signal Scan2 controls the data writing transistor T2 to turn on, and the third gate pulse p3 in the third gate signal Scan1 controls the second compensation transistor T3 to turn on. The data signal Data is sequentially transmitted to the first source-drain terminal (i.e., the first node A), its second source-drain terminal (i.e., the second node B), and its gate g (i.e., the third node Q) of the driving transistor T1, so that when the driving transistor T1 changes from the on state to the off state, the threshold voltage of the driving transistor T1 is compensated for a second time.

[0049] In some embodiments, combined with Figures 2 to 5 As shown, the duration of the first time period t1 (i.e., the pulse width t' of the second gate pulse p2) is greater than the duration of the second time period t2 (i.e., the pulse width t of the first gate pulse p1). Based on the above discussion, this embodiment considers that the duration of the second time period t2 is relatively short, especially at high refresh rates, resulting in a smaller degree of second compensation for the threshold voltage of the driving transistor T1. Therefore, the duration of the first time period t1 is set to be longer, allowing for a larger degree of first compensation for the threshold voltage of the driving transistor T1. This, in turn, allows for a greater degree of compensation for the threshold voltage of the driving transistor T1, thereby improving the brightness uniformity of the display panel 100 and the lifespan of the driving transistor T1.

[0050] Furthermore, the duration of the first time period t1 (i.e., the pulse width t' of the second gate pulse p2) is greater than or equal to twice the duration of the second time period t2 (i.e., the pulse width t of the first gate pulse p1). In this embodiment, the duration of the first time period t1 is further set to be at least twice the duration of the second time period t2. Compared to a first time period t1 being less than twice the duration of the second time period t2, the compensation level of the threshold voltage of the driving transistor T1 can be significantly improved.

[0051] Furthermore, the duration of the first time period t1 (i.e., the pulse width t' of the second gate pulse p2) is equal to ten times the duration of the second time period t2 (i.e., the pulse width t of the first gate pulse p1). For example, the duration of the first time period t1 can be 20µs, and the duration of the second time period t2 can be 2µs.

[0052] In some embodiments, combined with Figures 2 to 5 As shown, the duration of the first time period t1 (i.e., the pulse width t' of the second gate pulse p2) of the display panel 100 is the same at different refresh rates, while the duration of the second time period t2 (i.e., the pulse width t of the first gate pulse p1) of the display panel 100 is different at different refresh rates.

[0053] As discussed above, when the refresh rate of the display panel 100 is high, the pulse width t of the first gate pulse p1 in the first gate signal Scan2 is short. However, considering that the reference signal Vref transmitted by the first compensation transistor T4 is independent of the refresh rate, and in order to avoid affecting the writing of the data signal Data, it is necessary to satisfy that the end time of the first time period t1 is earlier than the start time of the second time period t2. That is, by setting the start time of the first time period t1 earlier, the duration of the first time period t1 can be longer, so that the duration of the first time period t1 can be longer under different refresh rates, so as to achieve a greater degree of compensation for the threshold voltage of the driving transistor T1.

[0054] Of course, the duration of the first time period t1 can also be set to be larger when the refresh rate is higher, so as to achieve greater compensation for the threshold voltage of the driving transistor T1 at higher refresh rates. For example, as discussed above, the duration of the first time period t1 (i.e. the pulse width t' of the second gate pulse p2) can be set to be positively correlated with the duration of the second time period t2 (i.e. the pulse width t of the first gate pulse p1).

[0055] In some embodiments, such as Figure 2 and Figure 3As shown, the active layer of the driving transistor T1 is composed of oxide material. Specifically, in this embodiment, the active layer of the driving transistor T1 is composed of oxide material. On one hand, the off-state current of the driving transistor T1 is lower, meaning better leakage current control, which is beneficial for low-frequency driving and reducing static power consumption. Furthermore, the driving transistor T1, being essentially an oxide transistor, can operate at lower voltages, resulting in lower dynamic power consumption. On the other hand, the interface state density between the active layer and the gate dielectric of the driving transistor T1 is lower, reducing hysteresis caused by charge accumulation. Moreover, the threshold voltage offset under positive or negative bias stress can be smaller, thereby reducing the hysteresis effect of the driving transistor T1.

[0056] In particular, although the driving transistor T1, which is essentially an oxide transistor in this embodiment, has a short lifespan due to factors such as the stability of the material itself, the reliability of the interface and gate dielectric, and stress accumulation (that is, its threshold voltage degrades more significantly with increasing years of use), the threshold voltage of the driving transistor T1 is compensated by controlling it to change from the on state to the off state during the first time period t1 before the second time period t2 in this invention. This improves the compensation degree of the threshold voltage of the driving transistor T1 before each emission of the sub-pixel Pi, thereby improving the brightness uniformity of the display panel 100 and the lifespan performance of the driving transistor T1. As a result, the display panel 100 can achieve both low power consumption, low hysteresis effect, and avoid a short lifespan.

[0057] In some embodiments, such as Figure 2 and Figure 3 As shown, the driving transistor T1 is an N-type transistor, the first source-drain terminal (i.e., the first node A) of the driving transistor T1 is the source s of the driving transistor T1, and the second source-drain terminal (i.e., the second node B) of the driving transistor T1 is the drain d of the driving transistor T1; wherein, the amplitude of the reference signal Vref is greater than the amplitude of the data signal Data.

[0058] Based on the above discussion, in the first time period t1, the reference signal Vref is sequentially transmitted to the source s, drain d, and gate g of the driving transistor T1 until the potential of the gate g of the driving transistor T1 is close to the amplitude of the reference signal Vref. In the second time period t2 after the first time period t1, since the threshold voltage of the N-type transistor is greater than 0, in order to ensure that the data signal Data is sequentially transmitted to the source s, drain d, and gate g of the driving transistor T1, the driving transistor T1 needs to be turned on. That is, the potential of the source s of the driving transistor T1 (i.e., the amplitude of the data signal Data) needs to be less than that of the gate g of the driving transistor T1 (i.e., close to the amplitude of the reference signal Vref), which means that the amplitude of the reference signal Vref needs to be greater than the amplitude of the data signal Data.

[0059] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 02 further includes: a first switch module 40, electrically connected between the first power line and the second source-drain terminal (i.e., the second node B) of the driving transistor T1; wherein, the second compensation module 30 and the first switch module 40 are used to transmit the first power signal VDD transmitted by the first power line to the gate of the driving transistor T1 in a third time period t3 before the first time period t1; wherein, the amplitude of the first power signal VDD is greater than the amplitude of the reference signal Vref.

[0060] Specifically, the first switching module 40 may include a first switching transistor T5, for example... Figure 2 and Figure 4 As shown, during the third time period t3, the fourth gate pulse p4 in the fourth gate signal EM1 acting on the gate of the first switching transistor T5 controls the first switching transistor T5 to turn on. The first power supply signal VDD is transmitted sequentially through the first switching transistor T5 and the second compensation transistor T3 to the gate g of the driving transistor T1 until the potential of the gate g of the driving transistor T1 is equal to the amplitude of the first power supply signal VDD.

[0061] Similarly, since the threshold voltage of the N-type transistor is greater than 0, in order to ensure that the reference signal Vref can be transmitted to the gate g of the driving transistor T1 in the first time period t1 after the third time period t3, the driving transistor T1 needs to be turned on. That is, the potential of the source s of the driving transistor T1 (i.e. the amplitude of the reference signal Vref) needs to be less than the gate g of the driving transistor T1 (i.e. close to the amplitude of the first power supply signal VDD), which means that the amplitude of the first power supply signal VDD needs to be greater than the amplitude of the reference signal Vref.

[0062] Furthermore, such as Figure 2 and Figure 3 As shown, the pixel circuit 02 further includes a storage module 50, electrically connected between the gate g of the driving transistor T1 and the anode of the light-emitting element 01. Specifically, the storage module 50 may include a storage capacitor Cst, for example... Figure 2 and Figure 4 As shown, the two plates of the storage capacitor Cst can be electrically connected to the gate g of the driving transistor T1 and the anode of the light-emitting element O1, respectively, so as to maintain the stability of the potential between the two when they are in a floating state, thereby maintaining the stability of the potential of the gate g of the driving transistor T1.

[0063] In some embodiments, the driving transistor may also be a P-type transistor, with the first source-drain terminal of the driving transistor being the source and the second source-drain terminal of the driving transistor being the drain; wherein the amplitude of the reference signal Vref is less than the amplitude of the data signal Data.

[0064] By analogy with the discussion above about the driving transistor T1 being an N-type transistor, we can see that since the threshold voltage of a P-type transistor is less than 0, in the second time period t2 after the first time period t1, in order to ensure that the data signal Data can be transmitted to the gate g of the driving transistor T1, the driving transistor T1 needs to be turned on. That is, the potential of the source s of the driving transistor T1 (i.e., the amplitude of the data signal Data) needs to be greater than the gate g of the driving transistor T1 (i.e., close to the amplitude of the reference signal Vref), which means that the amplitude of the reference signal Vref needs to be less than the amplitude of the data signal Data.

[0065] In some embodiments, based on the driving transistor being a P-type transistor, the pixel circuit 02 further includes: an initialization module electrically connected to the gate of the driving transistor; wherein the initialization module is used to transmit an initialization signal to the gate of the driving transistor during a third time period before the first time period t1; wherein the amplitude of the initialization signal is less than the amplitude of the reference signal Vref.

[0066] Specifically, the initialization module may include an initialization transistor. In the third time period t3, the fifth gate pulse in the fifth gate signal acting on the gate of the initialization transistor controls the initialization transistor to turn on. The initialization signal is transmitted through the initialization transistor to the gate of the driving transistor until the potential of the gate of the driving transistor is equal to the amplitude of the initialization signal.

[0067] Similarly, since the threshold voltage of the P-type transistor is less than 0, in order to ensure that the reference signal Vref can be transmitted to the gate of the driving transistor in the first time period t1 after the third time period, the driving transistor needs to be turned on. That is, the potential of the source of the driving transistor (i.e. the amplitude of the reference signal Vref) needs to be greater than the gate of the driving transistor (i.e. close to the amplitude of the initialization signal), which means that the amplitude of the initialization signal needs to be less than the amplitude of the reference signal.

[0068] Furthermore, based on the fact that the driving transistor is a P-type transistor, the pixel circuit 02 further includes: a first switching module, electrically connected between the first power line and the first source-drain terminal of the driving transistor, for controlling the formation of a current interruption between the first power line and the first source-drain terminal of the driving transistor during the second time period t2; and a storage module, electrically connected between the gate of the driving transistor and the first power line.

[0069] Specifically, based on the fact that the driving transistor is a P-type transistor, the first switching module may include a first switching transistor. As discussed above, in the second time period t2, since the data signal Data needs to be written to the gate of the driving transistor, in order to prevent the first power signal VDD from also flowing to the gate of the driving transistor and affecting the writing of the data signal Data, this embodiment sets a first switching transistor between the first power line and the first source-drain terminal of the driving transistor T1, and controls the first switching transistor to be turned off in the second time period t2 by the sixth gate pulse in the sixth gate signal acting on the gate of the first switching transistor, so as to prevent the first power signal from being transmitted to the gate of the driving transistor.

[0070] Similarly, the storage module may include a storage capacitor, the two plates of which may be electrically connected to the gate of the driving transistor and the first power supply line, respectively, thereby maintaining the stability of the gate potential of the driving transistor.

[0071] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 02 further includes a reset module 70, electrically connected to the anode of the light-emitting element 01, for conducting during a third time period t3 before the first time period t1, to transmit a reset signal Vi-ano to the anode of the light-emitting element 01. Wherein, with Figure 2 and Figure 4 For example, the reset module 70 may include a reset transistor T7 whose gate is controlled by the seventh gate signal Scan5.

[0072] As discussed above, regardless of whether the driving transistor T1 is an N-type transistor or a P-type transistor, a reset transistor T7 can be electrically connected to the anode of the light-emitting element 01. In the third time period t3 before the first time period t1, the seventh gate pulse p7 in the seventh gate signal Scan5 acting on the gate of the reset transistor T7 controls the reset transistor T7 to turn on, and the reset signal Vi-ano is transmitted to the anode of the light-emitting element 01 to reset its potential.

[0073] Furthermore, such as Figure 2 and Figure 3 As shown, the pixel circuit 02 further includes: a second switch module 80, electrically connected between the first source / drain terminal (i.e., the first node A) of the driving transistor T1 and the light-emitting element 01, as shown. Figure 2 and Figure 4 As shown; or electrically connected between the second source / drain terminal (i.e., the second node B) of the driving transistor T1 and the light-emitting element O1, as shown. Figure 3As shown. The second switching module 80 is used to form a current path between the first source-drain terminal and the second source-drain terminal of the driving transistor T1 and the light-emitting element O1 in the fourth time period t4 after the second time period t2.

[0074] Specifically, with Figure 2 and Figure 3 For example, the second switching module 80 may include a second switching transistor T6. As discussed above, in the third time period t3 before the first time period t1, since the reset signal Vi-ano is transmitted to the anode of the light-emitting element 01 to reset its potential, in order to avoid it affecting the potential of the first source-drain terminal (i.e., the first node A) of the driving transistor T1, the second switching transistor T6 can be set between the first source-drain terminal (i.e., the first node A) or the second source-drain terminal (i.e., the second node B) of the driving transistor T1 and the light-emitting element 01. The second switching transistor T6 is controlled to be turned off in the third time period t3 by the eighth gate pulse p8 in the eighth gate signal EM2 acting on the gate of the second switching transistor T6, so as to prevent the reset signal Vi-ano from being transmitted to the first source-drain terminal of the driving transistor T1. In the fourth time period t4 after the second time period t2, the eighth gate pulse p8 in the eighth gate signal EM2 controls the second switching transistor T6 to be turned on, and at this time the first switching transistor T5 is also turned on, so as to form a current path between the first power line and the second power line used to transmit the second power signal VSS, so that the driving current can flow through the light-emitting element Di.

[0075] In some embodiments, such as Figure 2 and Figure 3 As shown, the reset module 70 includes the aforementioned reset transistor T7, and the second switch module 80 includes the aforementioned second switch transistor T6. One of the reset transistor T7 and the second switch transistor T6 is an N-type transistor, and the other is a P-type transistor. The gates of the reset transistor T7 and the second switch transistor T6 are electrically connected to the same gate signal line (for example, for transmitting the aforementioned eighth gate signal EM2).

[0076] Understandably, since the required conduction periods of the reset transistor T7 and the second switching transistor T6 do not overlap, their transistor types can be set to be different so that their conduction can be controlled only by the eighth gate signal EM2, thereby achieving time-division conduction of the two and reducing the types of gate signals.

[0077] The present invention also provides a driving method for a display panel, which is applied to a display panel. The specific architecture and circuit details of the display panel can be referred to the specific architecture and circuit details of the display panel described above. The driving method for the display panel includes, but is not limited to, the following embodiments and combinations thereof.

[0078] To better explain the working principle of the sub-pixel Pi in the above-mentioned display panel 100, the working principle of the three pixel circuits 02 is explained as follows.

[0079] Combination Figure 2 and Figure 4 As shown, taking the driving transistor T1, the second compensation transistor T3, the first compensation transistor T4, and the reset transistor T7 as N-type transistors, and the other transistors as P-type transistors, the sub-pixel Pi can have, but is not limited to, the following operating stages:

[0080] During the third time period t3, the fourth gate signal EM1 is at a low potential, the eighth gate signal EM2 is at a high potential, and the third gate signal Scan1 becomes at a high potential. The first switching transistor T5 and the second compensation transistor T3 are both turned on so that the first power supply signal VDD is transmitted to the gate g of the driving transistor T1. The reset transistor T7 is turned on so that the reset signal Vi-ano is transmitted to the anode of the light-emitting element O1 to reset its potential.

[0081] During the first time period t1, the eighth gate signal EM2 is at a high potential, the third gate signal Scan1 is at a high potential, and the second gate signal Scan3 is at a high potential. The reset transistor T7 remains on to continue resetting the potential of the anode of the light-emitting element O1. The first compensation transistor T4 is turned on to transmit the reference signal Vref to the source s of the driving transistor T1 so that the driving transistor T1 is turned on. Furthermore, the second compensation transistor T3 is also turned on to transmit the reference signal Vref to the gate g of the driving transistor T1 until the driving transistor T1 is turned off.

[0082] During the first time period t1 mentioned above, the signal VQ of the gate g of the driving transistor T1 (i.e. the signal of the third node Q) is charged to Vref+Vth+△V', where Vth is the threshold voltage of the driving transistor T1, and the duration of the reference signal Vref written to point Q is the pulse width t' of the second gate pulse p2. As can be seen from the above discussion, the pulse width t' of the second gate pulse p2 is not affected by the refresh rate of the display panel 100. Therefore, even if the refresh rate of the display panel 100 is large, the pulse width t' of the second gate pulse p2 can be set to be large so that △V' can be small.

[0083] During the second time period t2, the eighth gate signal EM2 is at a high potential, the third gate signal Scan1 is at a high potential, and the first gate signal Scan2 is at a low potential. The reset transistor T7 remains on to continue resetting the potential of the anode of the light-emitting element O1. The data writing transistor T2 is turned on to transmit the data signal Data to the source s of the driving transistor T1 so that the driving transistor T1 is turned on. Furthermore, the second compensation transistor T3 is also turned on to transmit the data signal Data to the gate g of the driving transistor T1 until the driving transistor T1 is turned off.

[0084] During the second time period t2 mentioned above, the signal VQ of the gate g of the driving transistor T1 (i.e., the signal of the third node Q) is charged to Data + Vth + ΔV”. Even though the duration for which the data signal Data is written to point Q (the pulse width t of the first gate pulse p1) is short, since the threshold voltage Vth of the driving transistor T1 has been compensated to a certain extent in the first time period t1, ΔV” can be considered to be relatively small.

[0085] During the fourth time period t4, the fourth gate signal EM1 and the eighth gate signal EM2 are at low potentials. Both the first switching transistor T5 and the second switching transistor T5 are turned on to form a current path between the first power line and the second power line, so that the driving current can flow through the light-emitting element Di, and then the light-emitting element Di emits light. The driving current is K×(Data+Vi-ano+△V”). 2 K is a positive number;

[0086] Based on the analysis of the first time period t1 to the fourth time period t4 above, it can be seen that since each sub-pixel Pi passes through the corresponding first time period t1 and second time period t2, the ΔV” in the driving current is smaller in the fourth time period t4, making the driving current closer to K×(Data+Vi-ano). 2 This means that the threshold voltage Vth of the driving transistor T1 is compensated more fully, so that the threshold voltage Vth of the driving transistor T1 has less impact on the brightness of the display panel 100 due to its lifespan.

[0087] Taking a P-type transistor as an example, the sub-pixel Pi can have, but is not limited to, the following operating stages:

[0088] In the third period, the initialization transistor is turned on so that the initialization signal is transmitted to the gate g of the driving transistor T1 to reset its potential, and the reset transistor is turned on so that the reset signal is transmitted to the anode of the light-emitting element O1 to reset its potential.

[0089] In the first phase, the third gate signal corresponds to a high potential, the second gate signal corresponds to a low potential, and the seventh gate signal corresponds to a high potential. The operating process can be referenced above regarding... Figure 2 and Figure 4 The relevant discussion states that the reference signal will also be transmitted to the gate of the driving transistor until the driving transistor is turned off;

[0090] In the second time period, which follows the first time period, the third gate signal is at a high potential, the first gate signal is at a high potential, and the seventh gate signal is at a high potential. The working process can be found in the above text regarding... Figure 2 and Figure 4 The relevant discussion is that the data signal is transmitted to the gate of the driving transistor until the driving transistor is turned off;

[0091] In the fourth period, following the second period, both the first switching transistor and the first switching transistor are turned on. Their operation can be referenced above regarding... Figure 2 and Figure 4 The relevant discussion.

[0092] Combination Figure 3 and Figure 5 As shown, taking the driving transistor T1, data writing transistor T2, second compensation transistor T3, first compensation transistor T4, and reset transistor T7 as N-type transistors, and the other transistors as P-type transistors, the sub-pixel Pi can have, but is not limited to, the following operating stages:

[0093] During the third time period t3, the fourth gate signal EM1 is at a low potential, the eighth gate signal EM2 is at a high potential, and the third gate signal Scan1 becomes high. The operating process can be referenced above regarding... Figure 2 and Figure 4 Related discussions;

[0094] During the first time period t1, the eighth gate signal EM2, the third gate signal Scan1, and the second gate signal Scan3 are all at high potentials. The operational process can be found in the previous section. Figure 2 and Figure 4 Related discussions;

[0095] During the second time period t2, the eighth gate signal EM2 is at a high potential, the third gate signal Scan1 is at a high potential, and the first gate signal Scan2 is at a low potential. The operating process can be referenced above regarding... Figure 2 and Figure 4 Related discussions;

[0096] During the fourth time period t4, the fourth gate signal EM1 and the eighth gate signal EM2 are at low potentials, and both the first switching transistor T5 and the second switching transistor T5 are turned on. Their operation process can be referred to the above section on... Figure 2 and Figure 4The relevant discussion.

[0097] in, Figure 2 and Figure 3 The differences include at least whether the gate of the reset transistor T7 and the gate of the second switching transistor T6 are acted upon by the same gate signal. Figure 2 and Figure 3 The differences include at least whether the gate of the first switching transistor T5 and the gate of the second switching transistor T6 are acted upon by the same gate signal.

[0098] In some embodiments, such as Figure 10 As shown, the driving method for the display panel includes, but is not limited to, the following steps:

[0099] S1, during the first time period, the reference signal is transmitted to the gate of the driving transistor T1 through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor T1 changes from the on state to the off state.

[0100] For specific details, please refer to the above text. Figures 2 to 5 The description of the working principle of the first time period t1;

[0101] S2, in the second time period after the first time period, the data signal is transmitted to the gate of the driving transistor through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor T1 changes from the on state to the off state.

[0102] For specific details, please refer to the above text. Figures 2 to 5 The description of the working principle of the second time period t2.

[0103] In some embodiments, the driving transistor T1 is an N-type transistor, the amplitude of the reference signal Vref is greater than the amplitude of the data signal Data, and the pixel circuit 02 further includes: a first switching module 40 electrically connected between the first power line and the second source-drain terminal of the driving transistor T1; wherein, the driving method further includes:

[0104] S3, in the third time period t3 before the first time period t1, the first power signal VDD transmitted by the first power line is transmitted to the gate of the driving transistor T1 through the second compensation module 30 and the first switch module 40. The amplitude of the first power signal VDD is greater than the amplitude of the reference signal Vref.

[0105] S3 can be located before S1, and for details, please refer to the above section on... Figure 2 , Figure 3 , Figure 4 and Figure 5 The description of the working principle of the third time period t3.

[0106] In some embodiments, the driving transistor is a P-type transistor, the amplitude of the reference signal is smaller than the amplitude of the data signal, and the pixel circuit 02 further includes: an initialization module electrically connected to the gate of the driving transistor; wherein, the driving method further includes:

[0107] S4, in the third time period before the first time period, the initialization module transmits an initialization signal to the gate of the driving transistor, and the amplitude of the initialization signal is less than the amplitude of the reference signal;

[0108] S3 can be located before S1. For details, please refer to the description of the working principle of the third time period when the driving transistor is a P-type transistor.

[0109] In some embodiments, the pixel circuit 02 further includes: a first switch module 40, electrically connected between the first power line and the second source-drain terminal of the driving transistor T1; wherein, the driving method further includes:

[0110] S5, during the second time period t2, the first switching module 40 controls the formation of a current disconnection between the first power line and the second source-drain terminal of the driving transistor T1.

[0111] S5 can be included in S2 above, and its specific details can be found in the above text. Figures 2 to 5 The description of the working principle of the second time period t2.

[0112] In some embodiments, the pixel circuit 02 further includes: a second switch module 80, electrically connected between the second source / drain terminal of the driving transistor T1 and the light-emitting element 01; wherein, the driving method further includes:

[0113] S6, in the fourth time period t4 after the second time period t2, the first switch module 40 and the second switch module 80 control the formation of a current path between the first power line and the light-emitting element 01.

[0114] S6 can be located after S2, and its specific details can be found in the above text. Figures 2 to 5 The description of the working principle of the fourth time period t4.

[0115] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel circuit, the pixel circuit including: A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light. The first compensation module is electrically connected to the first source-drain terminal of the driving transistor, and is used to transmit a reference signal to the first source-drain terminal of the driving transistor in a first time period, and to transmit a data signal to the first source-drain terminal of the driving transistor in a second time period after the first time period. The second compensation module is electrically connected between the second source / drain terminal of the driving transistor and the gate of the driving transistor, and is used to control the formation of a current path between the second source / drain terminal of the driving transistor and the gate of the driving transistor during the first time period and the second time period. The driving transistor is in the on state at the beginning of the first time period, and transitions from the on state to the off state during the first time period, so as to be in the off state at the end of the first time period. The driving transistor is in the on state at the beginning of the second time period, and transitions from the on state to the off state during the second time period, ending in the off state at the end of the second time period.

2. The display panel according to claim 1, characterized in that, The duration of the first time period is greater than the duration of the second time period.

3. The display panel according to claim 2, characterized in that, The duration of the first time period is greater than or equal to twice the duration of the second time period.

4. The display panel according to claim 3, characterized in that, The duration of the first time period is ten times the duration of the second time period.

5. The display panel according to claim 2, characterized in that, The duration of the first time period corresponding to the display panel at different refresh rates is the same, while the duration of the second time period corresponding to the display panel at different refresh rates is different.

6. The display panel according to any one of claims 1 to 5, characterized in that, The first compensation module includes a first compensation transistor and a data writing transistor, both of which are electrically connected to the first source-drain terminals of the driving transistor. The second compensation module includes a second compensation transistor, which is electrically connected between the second source / drain terminal of the driving transistor and the gate of the driving transistor. Wherein, the first compensation transistor and the second compensation transistor are used to be turned on during the first time period to transmit the reference signal to the gate of the driving transistor, so that the driving transistor changes from the on state to the off state; The data writing transistor and the second compensation transistor are turned on during the second time period to transmit the data signal to the gate of the driving transistor, so that the driving transistor changes from the on state to the off state.

7. The display panel according to claim 6, characterized in that, The active layer of the driving transistor is composed of oxides.

8. The display panel according to claim 6, characterized in that, The driving transistor is an N-type transistor, and the first source-drain terminal of the driving transistor is the source of the driving transistor, and the second source-drain terminal of the driving transistor is the drain of the driving transistor. The amplitude of the reference signal is greater than the amplitude of the data signal.

9. The display panel according to claim 8, characterized in that, The pixel circuit also includes: The first switching module is electrically connected between the first power line and the second source / drain terminal of the driving transistor; The second compensation module and the first switch module are used to transmit the first power signal transmitted by the first power line to the gate of the driving transistor during a third time period before the first time period. The amplitude of the first power signal is greater than the amplitude of the reference signal.

10. The display panel according to claim 8, characterized in that, The pixel circuit also includes: The storage module is electrically connected between the gate of the driving transistor and the anode of the light-emitting element.

11. The display panel according to any one of claims 1 to 5, characterized in that, The pixel circuit also includes: A reset module, electrically connected to the anode of the light-emitting element, is used to conduct during a third time period before the first time period to transmit a reset signal to the anode of the light-emitting element.

12. The display panel according to claim 11, characterized in that, The pixel circuit also includes: The second switching module is electrically connected between the first source-drain terminal and the second source-drain terminal of the driving transistor and the light-emitting element, and is used to form a current path between the first source-drain terminal and the second source-drain terminal of the driving transistor and the light-emitting element in a fourth time period after the second time period.

13. The display panel according to claim 12, characterized in that, The reset module includes a reset transistor, and the second switch module includes a second switch transistor; In this transistor, one of the reset transistor and the second switching transistor is an N-type transistor and the other is a P-type transistor. The gates of the reset transistor and the second switching transistor are electrically connected to the same gate signal line.

14. A driving method for a display panel, characterized in that, Applied to a display panel, the display panel includes a plurality of sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel circuit, the pixel circuit including: A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light. The first compensation module is electrically connected to the first source-drain terminal of the driving transistor and is used for time-division transmission of reference signals and data signals. The second compensation module is electrically connected between the second source / drain terminal of the driving transistor and the gate of the driving transistor; The driving method for the display panel includes: During the first time period, the reference signal is transmitted to the gate of the driving transistor through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor changes from the on state to the off state. In the second period following the first period, the data signal is transmitted to the gate of the driving transistor through the first source-drain terminal and the second source-drain terminal of the driving transistor via the first compensation module and the second compensation module, so that the driving transistor changes from the on state to the off state.

15. The driving method for a display panel according to claim 14, characterized in that, The driving transistor is an N-type transistor, the amplitude of the reference signal is greater than the amplitude of the data signal, and the pixel circuit further includes: The first switching module is electrically connected between the first power line and the second source / drain terminal of the driving transistor; The driving method for the display panel further includes: In the third period prior to the first period, the first power signal transmitted by the first power line is transmitted to the gate of the driving transistor through the second compensation module and the first switching module, and the amplitude of the first power signal is greater than the amplitude of the reference signal.

16. The driving method for a display panel according to claim 14, characterized in that, The pixel circuit also includes: The first switching module is electrically connected between the first power line and the second source / drain terminal of the driving transistor; The driving method for the display panel further includes: During the second time period, the first switching module controls the formation of a current disconnect between the first power line and the second source-drain terminal of the driving transistor.

17. The driving method for a display panel according to claim 16, characterized in that, The pixel circuit also includes: The second switching module is electrically connected between the second source / drain terminal of the driving transistor and the light-emitting element; The driving method further includes: In the fourth period following the second period, a current path is formed between the first power line and the light-emitting element by controlling the first switch module and the second switch module.

Images