Stage circuit

Abstract

The present disclosure relates to a stage circuit configured to: generate a carry signal using an auxiliary clock signal swinging between a first voltage and a second voltage, a first auxiliary power supply having the first voltage, and a second auxiliary power supply having the second voltage; and generates a scan signal using a clock signal swinging between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage, a first power supply having the third voltage, and a second power supply having the fourth voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0056256, filed on April 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of this disclosure generally relate to stage circuits and display devices and electronic devices including stage circuits. Background Technology

[0004] With the development of the information society, consumer demand for display devices for displaying images has increased in various forms. For example, display devices can be used in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart TVs.

[0005] The display device uses pixels to display images. The display device may include a scan driver to drive the pixels. The scan driver may include stage circuitry, and for each frame, the scan driver uses the stage circuitry to supply at least one scan signal to each of the scan lines.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background, and therefore the information discussed in this background section need not constitute prior art. Summary of the Invention

[0007] Some embodiments include stage circuitry that can relatively reduce power consumption and display devices that include stage circuitry.

[0008] Some embodiments also include stage circuitry and a display device including stage circuitry, which can relatively stably supply scanning signals when at least two regions of the display unit are driven at different driving frequencies.

[0009] Some embodiments also include stage circuitry capable of outputting scan signals with different polarities (or voltages) and display devices including stage circuitry.

[0010] According to some embodiments of this disclosure, the stage circuit includes: an input unit located between a first input terminal and a first node, the first input terminal being configured to receive a scan start signal or a carry signal, the input unit controlling the electrical connection between the first input terminal and the first node in response to an auxiliary clock signal input to a second input terminal; a first voltage controller connected to a first main power input terminal and a second main power input terminal, the first voltage controller controlling each of a second node, a third node, and a fourth node to have a voltage higher or lower than that of the first node; a first output unit connected to a third input terminal and the first main power input terminal, the third input terminal being configured to receive a clock signal, the first output unit outputting a first scan signal to the first output terminal in response to the voltage of each of the second node and the third node; a second output unit connected to a first auxiliary power input terminal and a second auxiliary power input terminal, the second output unit outputting a carry signal to the second output terminal in response to the voltage of each of the third node and the fourth node; and a second voltage controller connected to the first auxiliary power input terminal, the second voltage controller being connected to a second main power input terminal or a second auxiliary power input terminal, the second voltage controller being located between the first node and the third node to maintain the voltage of the third node.

[0011] According to some embodiments, the auxiliary clock signal and the clock signal may have the same period and different phases. According to some embodiments, the auxiliary clock signal may oscillate between a first voltage and a second voltage, and the clock signal may oscillate between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage.

[0012] According to some embodiments, a first auxiliary power input terminal is configured to receive an auxiliary first power supply having a first voltage, a second auxiliary power input terminal is configured to receive an auxiliary second power supply having a second voltage, a first main power input terminal is configured to receive a first power supply having a third voltage, and a second main power input terminal is configured to receive a second power supply having a fourth voltage.

[0013] According to some embodiments, the second voltage controller may include an N-type first voltage control transistor and a P-type second voltage control transistor connected in series between the first node and the third node. According to some embodiments, the gate electrode of the first voltage control transistor may be connected to a first auxiliary power input terminal, and the gate electrode of the second voltage control transistor may be connected to a second main power input terminal.

[0014] According to some embodiments, the second voltage controller may include an N-type first voltage control transistor and a P-type second voltage control transistor connected in series between the first node and the third node. According to some embodiments, the gate electrode of the first voltage control transistor may be connected to a first auxiliary power input terminal, and the gate electrode of the second voltage control transistor may be connected to a second auxiliary power input terminal.

[0015] According to some embodiments, the input unit may include a first transistor connected between a first input terminal and a first node, the first transistor including a gate electrode connected to a second input terminal.

[0016] According to some embodiments, the first output unit may include: a first scan output transistor connected between a third input terminal and a first output terminal, the first scan output transistor including a gate electrode connected to a second node; a second scan output transistor connected between the first output terminal and a first main power input terminal, the second scan output transistor including a gate electrode connected to a third node; a control transistor connected between a second node and a fourth node, the control transistor including a gate electrode connected to a second main power input terminal; and a first capacitor connected between the second node and the first output terminal.

[0017] According to some embodiments, the second output unit may include: a first carry-out output transistor connected between a first auxiliary power input terminal and a second output terminal, the first carry-out output transistor including a gate electrode connected to a fourth node; and a second carry-out output transistor connected between the second output terminal and the second auxiliary power input terminal, the second carry-out output transistor including a gate electrode connected to a third node.

[0018] According to some embodiments, the first voltage controller may include: a first control transistor connected between a first main power input terminal and a fifth node, the first control transistor including a gate electrode connected to a fourth node; a second control transistor connected between the fifth node and a second main power input terminal, the second control transistor including a gate electrode connected to a third node; a third control transistor connected between the first main power input terminal and the fourth node, the third control transistor including a gate electrode connected to the fifth node; a fourth control transistor connected between the fourth node and the second main power input terminal, the fourth control transistor including a gate electrode connected to the third node; and a second capacitor connected between the fifth node and the third node.

[0019] According to some embodiments, each of the first control transistor, the second control transistor, and the third control transistor may be a P-type transistor, and the fourth control transistor may be an N-type transistor.

[0020] According to some embodiments, the stage circuit may further include: a third output unit connected to the first main power input terminal and the second main power input terminal, the third output unit outputting a second scan signal to the third output terminal in response to the voltage of each of the third node and the fourth node.

[0021] According to some embodiments, the third output unit may include: a first output transistor connected between a first main power input terminal and a third output terminal, the first output transistor including a gate electrode connected to a fourth node; a second output transistor connected between the third output terminal and the second main power input terminal, the second output transistor including a gate electrode connected to the third node; and a third capacitor connected between the third node and the third output terminal.

[0022] According to some embodiments of this disclosure, the stage circuit includes: a first output unit configured to output a scan signal using a clock signal and a first power supply; an input unit configured to receive a scan start signal or a carry signal corresponding to an auxiliary clock signal having a voltage different from that of the clock signal; and a second output unit configured to output a carry signal using an auxiliary first power supply and an auxiliary second power supply, each of the auxiliary first power supply and the auxiliary second power supply having a voltage different from that of the first power supply.

[0023] According to some embodiments, the auxiliary clock signal and the clock signal may have the same period and different phases. According to some embodiments, the auxiliary clock signal may oscillate between a first voltage and a second voltage, and the clock signal may oscillate between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage.

[0024] According to some embodiments, the auxiliary first power supply may have a first voltage, the auxiliary second power supply may have a second voltage, and the first power supply may have a third voltage.

[0025] According to some embodiments of the present disclosure, a display device includes: a display unit including pixels positioned to be connected to scan lines and data lines; and a scan driver including stage circuitry for driving scan lines, wherein the stage circuitry uses an auxiliary clock signal oscillating between a first voltage and a second voltage, a first auxiliary power supply having a first voltage, and a second auxiliary power supply having a second voltage to generate a carry signal, and uses a clock signal oscillating between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage, a first power supply having a third voltage, and a second power supply having a fourth voltage to generate a scan signal.

[0026] According to some embodiments, when a first area of ​​a display unit is driven at a first image refresh rate and a second area of ​​the display unit is driven at a second image refresh rate lower than the first image refresh rate, the scan driver can generate a carry signal corresponding to the first image refresh rate.

[0027] According to some embodiments, the display device may further include a timing controller configured to control a scan driver. According to some embodiments, the timing controller can control whether a clock signal is supplied to output a scan signal at a second image refresh rate in the second area.

[0028] According to some embodiments, each of the stage circuits may include a first input terminal, a second input terminal, a third input terminal, a first auxiliary power input terminal, a second auxiliary power input terminal, a first main power input terminal, a second main power input terminal, a first output terminal, and a second output terminal. According to some embodiments, a scan start signal or carry signal from the previous stage circuit may be input to the first input terminal. According to some embodiments, a first auxiliary clock signal may be input to the second input terminal of the odd-numbered stage circuit, and a second auxiliary clock signal may be input to the second input terminal of the even-numbered stage circuit. According to some embodiments, a first clock signal may be input to the third input terminal of the odd-numbered stage circuit, and a second clock signal may be input to the third input terminal of the even-numbered stage circuit. According to some embodiments, a first auxiliary power supply may be input to the first auxiliary power input terminal, a second auxiliary power supply may be input to the second auxiliary power input terminal, a first power supply may be input to the first main power input terminal, and a second power supply may be input to the second main power input terminal. According to some embodiments, the first auxiliary clock signal and the second auxiliary clock signal may have the same period and different phases. According to some embodiments, the first clock signal and the second clock signal may have the same period and different phases.

[0029] According to some embodiments, each of the stage circuits may include: an input unit positioned between a first input terminal and a first node, the input unit controlling the electrical connection between the first input terminal and the first node in response to a voltage at a second input terminal; a first voltage controller connected to a first main power input terminal and a second main power input terminal, the first voltage controller controlling each of a second node, a third node, and a fourth node to have a voltage higher or lower than the voltage at the first node; a first output unit connected to a third input terminal and the first main power input terminal, the first output unit outputting a scan signal to the first output terminal in response to the voltage at each of the second and third nodes; a second output unit connected to a first auxiliary power input terminal and a second auxiliary power input terminal, the second output unit outputting a carry signal to the second output terminal in response to the voltage at each of the third and fourth nodes; and a second voltage controller connected to the first auxiliary power input terminal, the second voltage controller being connected to a second main power input terminal or a second auxiliary power input terminal, the second voltage controller being positioned between the first node and the third node to maintain the voltage at the third node.

[0030] According to some embodiments of this disclosure, an electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device includes: a display unit including pixels positioned to connect to scan lines and data lines; and a scan driver including stage circuitry for driving scan lines, wherein the stage circuitry uses an auxiliary clock signal oscillating between a first voltage and a second voltage, a first auxiliary power supply having a first voltage, and a second auxiliary power supply having a second voltage to generate a carry signal, and uses a clock signal oscillating between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage, a first power supply having a third voltage, and a second power supply having a fourth voltage to generate a scan signal. Attached Figure Description

[0031] Aspects of some embodiments according to this disclosure will now be described more fully below with reference to the accompanying drawings; however, these embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will more fully convey to those skilled in the art the scope of embodiments according to this disclosure.

[0032] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always refer to the same elements.

[0033] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0034] Figure 2 This illustrates some embodiments. Figure 1 The diagram shows various aspects of the scan driver and the transmit driver.

[0035] Figure 3 This illustrates some embodiments. Figure 1 The circuit diagrams for various aspects of the pixels shown are illustrated.

[0036] Figure 4 and Figure 5 This illustrates some embodiments. Figure 3 The waveform diagrams show various aspects of the pixel driving method.

[0037] Figure 6 This is a diagram illustrating the stage circuitry of a scan driver according to some embodiments of the present disclosure.

[0038] Figure 7 It is shown Figure 6 The diagram shows the auxiliary clock signal and the clock signal.

[0039] Figure 8A and Figure 8B This illustrates some embodiments. Figure 6 The circuit diagrams for various aspects of the stage circuit shown are illustrated.

[0040] Figure 9 and Figure 10 This illustrates some embodiments. Figure 8A and Figure 8B Waveform diagrams of various aspects of the driving method of the stage circuit shown.

[0041] Figure 11 This diagram illustrates the display of images at different refresh rates in the display unit.

[0042] Figure 12 This illustrates the supply to, according to some embodiments Figure 11 The diagram shows various aspects of the first scan signal of the display unit.

[0043] Figure 13 This illustrates some embodiments. Figure 6 The circuit diagrams for various aspects of the stage circuit shown are illustrated.

[0044] Figure 14 This illustrates some embodiments. Figure 13 Waveform diagrams of various aspects of the driving method of the stage circuit shown.

[0045] Figure 15 This is a schematic block diagram illustrating an electronic device including a display device according to an embodiment.

[0046] Figure 16 It is shown that Figure 15 The electronic device shown is a schematic diagram of an example of a smartphone.

[0047] Figure 17 It is shown that Figure 15 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0048] In the following description, aspects of some embodiments are described in more detail with reference to the accompanying drawings to enable those skilled in the art to make, use, and understand aspects of embodiments according to this disclosure. This disclosure may be implemented in various different forms and is not limited to the embodiments disclosed herein.

[0049] For clarity in describing this disclosure, parts irrelevant to the description will be omitted, and throughout the specification, the same or similar components will be identified by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar components in different figures.

[0050] Furthermore, for better understanding and ease of description, the size and thickness of each component shown in the accompanying drawings are arbitrarily depicted, but this disclosure is not limited thereto. For clarity, the thickness of certain parts and areas has been exaggerated.

[0051] In the description, the expression "equal" may mean "substantially equal." That is, it may mean equal to the degree that would be understood by a person skilled in the art to be equal. Other expressions may omit "substantially."

[0052] Some embodiments relating to functional blocks, units, and / or modules are depicted in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wiring connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or other similar hardware, the blocks, units, and / or modules are programmed and controlled using software to perform the various functions discussed in this disclosure and may optionally be driven by firmware and / or software. Furthermore, each block, each unit, and / or each module may be implemented by dedicated hardware or by a combination of dedicated hardware performing some functions of the block, unit, and / or module and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing other functions of the block, unit, and / or module. In some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically divided into two or more separate blocks, two or more separate units, and / or two or more separate modules. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically divided into more complex blocks, more complex units, and / or more complex modules.

[0053] The term "connection" between two components can include both electrical and physical connections, but this disclosure is not limited thereto. For example, the term "connection" used in a circuit diagram can mean an electrical connection, and the term "connection" used in cross-sectional and plan views can mean a physical connection.

[0054] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the “first” element discussed below may also be referred to as the “second” element without departing from the teachings of this disclosure.

[0055] Furthermore, the embodiments according to this disclosure are not limited to those disclosed below, and can be implemented in various forms. Each of the embodiments disclosed below can be implemented independently, or combined with at least other embodiments prior to implementation.

[0056] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure. Figure 2 This illustrates some embodiments. Figure 1 The diagram shows various aspects of the scan driver and the transmit driver.

[0057] Reference Figure 1 and Figure 2 The display device 100 according to some embodiments of the present disclosure may include a display unit 110 (or display panel), a timing controller 120, a scan driver 130, a data driver 140, a transmit driver 150, and a power source 160.

[0058] The display device 100 can display images at various image refresh rates (or drive frequencies or screen refresh rates) depending on the driving conditions. Image refresh rate refers to the frequency at which data signals are written to the driving transistors of pixels PX. For example, image refresh rate can also be called screen scan rate or screen refresh frequency, and represents the frequency at which the display screen reproduces the image per second.

[0059] According to some embodiments, the output frequency of the data driver 140 and / or the output frequency of the first scan driver 132 may be determined corresponding to the image refresh rate. The first scan driver 132 outputs a first scan signal (or writes a scan signal) for a horizontal line (e.g., pixels PX connected to the same scan line can be classified as a horizontal line (or pixel row)). For example, the image refresh rate used to drive the moving image may be a frequency of 60 Hz (or approximately 60 Hz) or higher (e.g., 120 Hz, 240 Hz, or 360 Hz, etc.).

[0060] For example, display device 100 may display images corresponding to various image refresh rates from 1Hz to 360Hz. However, this is merely illustrative, and display device 100 may also display images at an image refresh rate of 360Hz or higher (e.g., 480Hz).

[0061] The display device 100 can divide the display unit 110 into multiple areas according to driving conditions, and display images at different image refresh rates for these areas. For this purpose, the scan driver 130 can supply first scan signals at different output frequencies for different areas of the display unit 110. This will be referred to later. Figure 11 and Figure 12 To describe in more detail.

[0062] The display unit 110 may include a pixel PX connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, fourth scan lines SL41, SL42, ... and SL4n, data lines DL1, DL2, ... and DLm, transmit control lines EL1, EL2, ... and ELn, and power lines PL1, PL2, PL3 and PL4 (n and m are natural numbers 3 or greater).

[0063] According to some embodiments, pixel PXij is located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see...). Figure 3 It can be connected to the i-th first scan line SL1i (also called the first scan line SL1i), the i-th second scan line SL2i (also called the second scan line SL2i), the i-th third scan line SL3i (also called the third scan line SL3i), the i-th fourth scan line SL4i (also called the fourth scan line SL4i), the i-th transmit control line ELi (also called the transmit control line ELi), and the j-th data line DLj (also called the data line DLj) (i is a natural number of 1 or greater and n or less, and j is a natural number of 1 or greater and m or less).

[0064] When an activated first scan signal is supplied to the first scan lines SL11 to SL1n, pixels PX can be selected on a horizontal line basis. Pixels PX selected by the activated first scan signal can be supplied with data signals from data lines (any one of data lines DL1 to DLm) connected to the pixel PX. Pixels PX supplied with data signals can generate light with a brightness (e.g., a set or predetermined brightness) corresponding to the voltage of the data signal.

[0065] The scan driver 130 can receive a scan drive signal SCS from the timing controller 120. At least one scan start signal and a clock signal for driving the scan driver 130 can be included in the scan drive signal SCS. The scan driver 130 can generate an active first scan signal, an active second scan signal, an active third scan signal, and an active fourth scan signal while shifting the scan start signal in accordance with the clock signal.

[0066] Therefore, such as Figure 2 As shown, scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Depending on the design, at least some of scan drivers 132, 134, 136, and 138 may be integrated into a single drive circuit or a module, etc.

[0067] The first scan driver 132 can receive a first scan start signal FLM1 and generate an active first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 can sequentially supply the active first scan signal to the first scan lines SL11 to SL1n.

[0068] The second scan driver 134 can receive the second scan start signal FLM2 and generate an active second scan signal while shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 134 can sequentially supply the active second scan signal to the second scan lines SL21 to SL2n.

[0069] The third scan driver 136 can receive the third scan start signal FLM3 and generate an active third scan signal while shifting the third scan start signal FLM3 in response to a clock signal. The third scan driver 136 can sequentially supply the active third scan signal to the third scan lines SL31 to SL3n.

[0070] The fourth scan driver 138 can receive the fourth scan start signal FLM4 and generate an active fourth scan signal while shifting the fourth scan start signal FLM4 in response to a clock signal. The fourth scan driver 138 can sequentially supply the active fourth scan signal to the fourth scan lines SL41 to SL4n.

[0071] Each of the activated first scan signal, activated second scan signal, activated third scan signal, and activated fourth scan signal can be set as a gate on-voltage to turn on the transistors included in the pixel PX. According to some embodiments, such as... Figure 3 As shown, each of the activated first scan signal GW and the activated fourth scan signal GB supplied to the P-type transistor can be set to a logic low voltage. According to some embodiments, such as... Figure 3 As shown, each of the activated second scan signal GC and the activated third scan signal GI supplied to the N-type transistor can be set to a logic high level voltage.

[0072] exist Figure 2The diagram shows a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138 connected to a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, respectively. However, embodiments of this disclosure are not limited thereto. According to some embodiments, at least two scan lines (i.e., at least two of SL1, SL2, SL3, and SL4) can be driven by a single scan driver.

[0073] Data driver 140 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals required to drive data driver 140. Data driver 140 can generate a data signal based on data drive signal DCS and output data Dout. According to some embodiments, data driver 140 can generate an analog data signal based on the grayscale level of output data Dout. Data driver 140 can supply data signals in units of a horizontal time period.

[0074] Transmit driver 150 can receive transmit drive signal ECS from timing controller 120. The transmit start signal and clock signal required to drive transmit driver 150 can be included in transmit drive signal ECS. Transmit driver 150 can generate a disable transmit control signal while shifting the transmit start signal in accordance with the clock signal.

[0075] like Figure 2 As shown, the transmit driver 150 can receive a transmit start signal EFLM and generate a disable transmit control signal by shifting the transmit start signal EFLM according to a clock signal. The transmit driver 150 can sequentially supply the disable transmit control signal to transmit control lines EL1 to ELn. The disable transmit control signal can be set as a gate cutoff voltage to turn off the transistors included in the pixel PX. According to some embodiments, such as Figure 3 As shown, the disabled emit control signal EM supplied to the P-type transistor can be set to a logic high level voltage.

[0076] The timing controller 120 can receive input data Din and control signal CS from the host system via an interface. According to some embodiments, the timing controller 120 can receive the input data Din and control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. Various signals, including clock signals, can be included in the control signal CS.

[0077] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the transmit driver 150, respectively.

[0078] The timing controller 120 can rearrange the input data Din to suit the specifications of the display device 100. Furthermore, the timing controller 120 can generate output data Dout by correcting the input data Din and supply the output data Dout to the data driver 140. According to some embodiments, the timing controller 120 can correct the input data Din corresponding to optical measurement results measured during processing.

[0079] Power source 160 can generate various power supplies required to drive display device 100. According to some embodiments, power source 160 can generate a first driving power supply VDD, a second driving power supply VSS, a first initialization power supply Vint1, and a second initialization power supply Vint2.

[0080] The first driving power supply VDD can be a power supply that supplies driving current to pixel PX. The second driving power supply VSS can be a power supply that supplies driving current from pixel PX. During the period when pixel PX is set to be in the emission state, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0081] The first initialization power supply Vint1 can be a power supply used to initialize the gate electrode of the driving transistor included in each of the pixels PX. The first initialization power supply Vint1 can be set to a voltage lower than the voltage of the data signal. The second initialization power supply Vint2 can be used to initialize the light-emitting element LD included in each of the pixels PX (see...). Figure 3 The power supply for the first electrode (or anode electrode) of the LED. The second initialization power supply Vint2 can be set to the voltage that turns off the LED.

[0082] The first driving power supply VDD generated by power source 160 can be supplied to the first power line PL1, the second driving power supply VSS generated by power source 160 can be supplied to the second power line PL2, the first initialization power supply Vint1 generated by power source 160 can be supplied to the third power line PL3, and the second initialization power supply Vint2 generated by power source 160 can be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 can be commonly connected to the pixel PX, but the embodiments of this disclosure are not limited thereto.

[0083] According to some embodiments, a first power line PL1 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. According to some embodiments, a second power line PL2 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. According to some embodiments, a third power line PL3 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. According to some embodiments, a fourth power line PL4 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. That is, according to some embodiments of this disclosure, each pixel PX can be connected to any one of the multiple power lines constituting the first power line PL1, any one of the multiple power lines constituting the second power line PL2, any one of the multiple power lines constituting the third power line PL3, and any one of the multiple power lines constituting the fourth power line PL4.

[0084] According to some embodiments of this disclosure, the display device 100 may include a flat panel display device, a curved display device in which a portion of the display unit 110 is bent, a flexible display device in which a portion of the display unit 110 is folded or bent, and a stretchable display device in which a portion of the display unit 110 is expanded / contracted.

[0085] According to some embodiments of this disclosure, the display device is an apparatus for displaying moving images (e.g., video images) or still images (e.g., static images), and may include portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile computers (UMPCs). According to some embodiments of this disclosure, the display device 100 may include electronic devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices.

[0086] Figure 3 This illustrates some embodiments. Figure 1 The circuit diagrams for various aspects of the pixels are shown. Although Figure 3 Various components that may be included in a pixel are shown, but embodiments of this disclosure are not limited thereto, and according to some embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of embodiments of this disclosure. Figure 3 In the diagram, pixel PXij, located on the i-th horizontal line and the j-th vertical line, will be shown.

[0087] Reference Figure 3According to some embodiments of this disclosure, pixel PXij can be connected to corresponding scan lines SL1i, SL2i, SL3i, and SL4i, transmission control line Eli, and data line DLj. According to some embodiments, pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the i-th transmission control line Eli, and the j-th data line DLj. According to some embodiments, pixel PXij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0088] According to some embodiments of this disclosure, a pixel PXij may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0089] The light-emitting element (LD) can be connected between a first electric field line PL1 and a second electric field line PL2. According to some embodiments, the first electrode (or anode electrode) of the LD can be electrically connected to the first electric field line PL1 via a sixth transistor M26, a third node N23, a first transistor M21, a second node N22, and a fifth transistor M25, and the second electrode (or cathode electrode) of the LD can be electrically connected to the second electric field line PL2. The LD can generate light of a predetermined brightness corresponding to the amount of current supplied from the first electric field line PL1 to the second electric field line PL2 via pixel circuitry.

[0090] The light-emitting element (LD) can be an organic light-emitting diode (OLED). Alternatively, the LD can be an inorganic light-emitting diode, such as a micro LED or a quantum dot LED. Furthermore, the LD can be a device constructed from a combination of organic and inorganic materials. Figure 3 The image shows a pixel PXij comprising a single light-emitting element LD. However, according to some embodiments, a pixel PXij may comprise multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a series / parallel connection.

[0091] The pixel circuit may include a first transistor M21, a second transistor M22, a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27, and a storage capacitor Cst.

[0092] The first electrode of the first transistor M21 (or driving transistor) can be connected to the second node N22, and the second electrode of the first transistor M21 can be connected to the third node N23. Furthermore, the gate electrode of the first transistor M21 can be connected to the first node N21. Corresponding to the voltage at the first node N21, the first transistor M21 can control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD.

[0093] The second transistor M22 can be connected between the data line DLj and the second node N22. Furthermore, the gate electrode of the second transistor M22 can be electrically connected to the first scan line SL1i. When the activated first scan signal GW is supplied to the first scan line SL1i, the second transistor M22 can be turned on to electrically connect the data line DLj and the second node N22 to each other.

[0094] The first electrode of the third transistor M23 can be connected to the first node N21, and the second electrode of the third transistor M23 can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M23 can be electrically connected to the third scan line SL3i. When the activated third scan signal GI is supplied to the third scan line SL3i, the third transistor M23 can be turned on to supply the voltage of the first initialization power supply Vint1 to the first node N21.

[0095] The fourth transistor M24 can be connected between the first node N21 and the third node N23. Furthermore, the gate electrode of the fourth transistor M24 can be electrically connected to the second scan line SL2i. When the activated second scan signal GC is supplied to the second scan line SL2i, the fourth transistor M24 can be turned on to electrically connect the first node N21 and the third node N23 to each other. That is, when the fourth transistor M24 is turned on, the first transistor M21 can be connected in a diode configuration.

[0096] The first electrode of the fifth transistor M25 can be electrically connected to the first power line PL1, and the second electrode of the fifth transistor M25 can be connected to the second node N22. Furthermore, the gate electrode of the fifth transistor M25 can be electrically connected to the emitter control line ELi. When a disabled emitter control signal EM is supplied to the emitter control line ELi, the fifth transistor M25 can be turned off, and when an active emitter control signal EM is supplied to the emitter control line ELi, the fifth transistor M25 can be turned on.

[0097] The sixth transistor M26 can be connected between the third node N23 and the first electrode of the light-emitting element LD. Furthermore, the gate electrode of the sixth transistor M26 can be electrically connected to the emission control line ELi. When a disabled emission control signal EM is supplied to the emission control line ELi, the sixth transistor M26 can be turned off, and when an active emission control signal EM is supplied to the emission control line ELi, the sixth transistor M26 can be turned on.

[0098] The first electrode of the seventh transistor M27 can be connected to the first electrode of the light-emitting element LD, and the second electrode of the seventh transistor M27 can be electrically connected to the fourth power line PL4. Furthermore, the gate electrode of the seventh transistor M27 can be electrically connected to the fourth scan line SL4i. When the activated fourth scan signal GB is supplied to the fourth scan line SL4i, the seventh transistor M27 can be turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0099] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. As the residual voltage in the parasitic capacitor of the light-emitting element LD is discharged (or removed), unintentional micro-emissions can be prevented. Therefore, the black level performance of pixel PXij can be improved.

[0100] A storage capacitor Cst can be connected between the first power line PL1 and the first node N21. The storage capacitor Cst can store the voltage applied to the first node N21.

[0101] According to some embodiments, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be implemented using polysilicon semiconductor transistors. According to some embodiments, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can comprise a polysilicon semiconductor layer formed as an active layer (channel) using a low-temperature polysilicon (LTPS) process. Furthermore, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be implemented using P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage of the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 when they are turned on can have a logic low level. Because polysilicon semiconductor transistors can have a relatively high response speed, they can be used in switching elements requiring fast switching.

[0102] According to some embodiments, the third transistor M23 and the fourth transistor M24 can be formed using oxide semiconductor transistors. According to some embodiments, the third transistor M23 and the fourth transistor M24 can be implemented using N-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as the active layer. Therefore, the gate on-state voltage of the third transistor M23 and the fourth transistor M24 when they are turned on can have a logic high level.

[0103] Oxide-semiconductor (OSB) transistors can be fabricated using low-temperature processes and have a lower charge mobility than polysilicon (PSB) transistors. In other words, OSB transistors exhibit excellent cutoff current characteristics. Therefore, when implementing the third transistor M23 and the fourth transistor M24 using OSB transistors, leakage current under low-frequency drive conditions can be minimized or reduced, thereby improving display quality.

[0104] Figure 4 and Figure 5 This illustrates some embodiments. Figure 3 The waveform diagrams show various aspects of the pixel driving method.

[0105] Reference Figure 4 A frame time period can include a non-transmit time period P_NE, and the non-transmit time period P_NE can include an initialization time period P_INT, a compensation time period P_C, and a write time period P_W. The write time period P_W can be included in the compensation time period P_C.

[0106] A disabled emission control signal EM (or an emission control signal EM with a high level) can be supplied during the non-emission period P_NE. The fifth transistor M25 and the sixth transistor M26 can be turned off in response to the disabled emission control signal EM, and the pixel PXij can stop emitting light.

[0107] The active third scan signal GI can be supplied during the initialization period P_INT. When the active third scan signal GI is supplied, the third transistor M23 can be turned on, and the voltage of the first initialization power supply Vint1 of the third power line PL3 can be supplied to the first node N21.

[0108] An active second scan signal GC can be supplied during the compensation period P_C. When the active second scan signal GC is supplied, the fourth transistor M24 can be turned on, and the first transistor M21 can be connected in a diode manner.

[0109] An active first scan signal GW can be supplied during the write period P_W. When the active first scan signal GW is supplied, the second transistor M22 can be turned on, and the data signal can be provided from the j-th data line DLj to the second node N22. Because the fourth transistor M24 is turned on by the active second scan signal GC, the data signal can be transmitted from the second node N22 to the first node N21 via the first transistor M21 and the fourth transistor M24. Because the diode connection of the first transistor M21 is maintained by the turned-on fourth transistor M24, the first node N21 can have a voltage obtained by compensating for the threshold voltage of the first transistor M21 in the data signal.

[0110] Before the write phase P_W, the active fourth scan signal GB can be supplied. When the active fourth scan signal GB is supplied, the seventh transistor M27 can be turned on, and the voltage of the second initialization power supply Vint2 can be supplied to the first electrode of the light-emitting element LD.

[0111] After this, the non-emission period P_NE can end, and an active transmission control signal EM (or a transmission control signal with a low level) can be supplied. When the active transmission control signal EM is supplied, the fifth transistor M25 and the sixth transistor M26 can be turned on. When the fifth transistor M25 and the sixth transistor M26 are turned on, a current flow path can be formed through the fifth transistor M25, the first transistor M21, the sixth transistor M26, and the light-emitting element LD to the second power line PL2. Depending on the operation of the first transistor M21, a drive current corresponding to the voltage of the first node N21 can flow through the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0112] At the same time, such as Figure 5 As shown, multiple active first scan signals GW can be supplied during the compensation period P_C. Corresponding to the multiple active first scan signals GW, the data signal supplied to the data line DLj can be supplied to the second node N22. The data signal supplied to synchronize with the last active first scan signal GW supplied during the compensation period P_C can ultimately be stored in the storage capacitor Cst. That is, the period during which the active first scan signal GW is last supplied can be the write period P_W. Although multiple active first scan signals GW are supplied, the voltage corresponding to the desired data signal can be stored in the storage capacitor Cst.

[0113] Simultaneously, the fourth scan signal GB can be the first scan signal GW supplied to the previous horizontal line (i.e., the (i-1)th horizontal line). During the compensation period P_C, multiple active fourth scan signals GB can be supplied. When multiple active fourth scan signals GB are supplied, the seventh transistor M27 can supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD while simultaneously turning it on and off multiple times.

[0114] Figure 6 This is a diagram illustrating the stage circuitry of a scan driver according to some embodiments of the present disclosure. Figure 7 It is shown Figure 6 The diagram shows the auxiliary clock signal and the clock signal. Figure 6 The image will show a scan driver (e.g., first scan driver 132) for supplying the first scan signal GW.

[0115] Reference Figure 6 The first scan driver 132 may include multiple stage circuits ST1, ST2, ST3, ... and STn. Each of the stage circuits ST1 to STn may be electrically connected to any one of the first scan lines SL11, SL12, SL13, ... and SL1n.

[0116] According to some embodiments, a first-stage circuit ST1 can be electrically connected to a first scan line SL11 and supply an activated first scan signal GW1 to the first scan line SL11. A second-stage circuit ST2 can be electrically connected to a first scan line SL12 and supply an activated first scan signal GW2 to the first scan line SL12. A third-stage circuit ST3 can be electrically connected to a first scan line SL13 and supply an activated first scan signal GW3 to the first scan line SL13. An nth-stage circuit STn can be electrically connected to a first scan line SL1n and supply an activated first scan signal GWn to the first scan line SL1n.

[0117] Each of the stage circuits ST1 to STn may include a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a first power input terminal VIN1 (or a first auxiliary power input terminal), a second power input terminal VIN2 (or a second auxiliary power input terminal), a third power input terminal VIN3 (or a first main power input terminal), a fourth power input terminal VIN4 (or a second main power input terminal), a first output terminal OUT1, and a second output terminal OUT2.

[0118] The first scan start signal FLM1 or carry signal CR of the preceding stage circuit can be input to the first input terminal IN1. According to some embodiments, the first scan start signal FLM1 can be input to the first input terminal IN1 of the first stage circuit ST1. According to some embodiments, the carry signal CR of the preceding stage circuit can be input to the first input terminal IN1 of each of the second stage circuits ST2 to STn. According to some embodiments, the first carry signal CR1 output from the first stage circuit ST1 can be input to the first input terminal IN1 of the second stage circuit ST2, the second carry signal CR2 output from the second stage circuit ST2 can be input to the first input terminal IN1 of the third stage circuit ST3, the third carry signal CR3 output from the third stage circuit ST3 can be input to the first input terminal IN1 of the fourth stage circuit ST4, and the (n-1)th carry signal CRn-1 output from the (n-1)th stage circuit can be input to the first input terminal IN1 of the nth stage circuit STn.

[0119] An auxiliary first clock signal sCLK1 or an auxiliary second clock signal sCLK2 can be input to the second input terminal IN2. According to some embodiments, the auxiliary first clock signal sCLK1 can be input to the second input terminal IN2 of each of the k-th (k is an odd number) stage circuits ST1, ST3, ... According to some embodiments, the auxiliary second clock signal sCLK2 can be input to the second input terminal IN2 of each of the (k+1)-th (i.e., even number) stage circuits ST2, ..., STn.

[0120] like Figure 7 As shown, the auxiliary first clock signal sCLK1 and the auxiliary second clock signal sCLK2 can be signals with the same period but different phases. According to some embodiments, the auxiliary first clock signal sCLK1 and the auxiliary second clock signal sCLK2 can have a phase difference of 180 degrees from each other. The high voltage of the auxiliary first clock signal sCLK1 and the auxiliary second clock signal sCLK2 can be set to a first voltage V1, and the low voltage of the auxiliary first clock signal sCLK1 and the auxiliary second clock signal sCLK2 can be set to a second voltage V2.

[0121] The first clock signal CLK1 or the second clock signal CLK2 can be input to the third input terminal IN3. According to some embodiments, the first clock signal CLK1 can be input to the third input terminal IN3 of each of the k-th stage circuits ST1, ST3, ... According to some embodiments, the second clock signal CLK2 can be input to the third input terminal IN3 of each of the (k+1)-th stage circuits ST2, ... and STn.

[0122] like Figure 7As shown, the first clock signal CLK1 and the second clock signal CLK2 can be signals with the same period but different phases. According to some embodiments, the first clock signal CLK1 and the second clock signal CLK2 can have a phase difference of 180 degrees from each other. The high voltage of the first clock signal CLK1 and the second clock signal CLK2 can be set to a third voltage V3, and the low voltage of the first clock signal CLK1 and the second clock signal CLK2 can be set to a fourth voltage V4.

[0123] According to some embodiments, the third voltage V3 can be a voltage higher than the first voltage V1. According to some embodiments, the fourth voltage V4 can be a voltage lower than the second voltage V2. The voltage swing range of clock signals CLK1 and CLK2 can be set to be larger than the voltage swing range of auxiliary clock signals sCLK1 and sCLK2. According to some embodiments, auxiliary clock signals sCLK1 and sCLK2 can have a voltage swing range of -3V to 3V, and clock signals CLK1 and CLK2 can have a voltage swing range of -7V to 7V.

[0124] As described above, the first clock signal CLK1 may have a voltage swing range different from that of the auxiliary first clock signal sCLK1. Furthermore, the first clock signal CLK1 may have the same period as the auxiliary first clock signal sCLK1, but have a phase different from that of the auxiliary first clock signal sCLK1. According to some embodiments, the first clock signal CLK1 and the auxiliary first clock signal sCLK1 may have a phase difference of 180 degrees from each other.

[0125] As described above, the second clock signal CLK2 may have a voltage swing range different from that of the auxiliary second clock signal sCLK2. Furthermore, the second clock signal CLK2 may have the same period as the auxiliary second clock signal sCLK2, but a different phase than the auxiliary second clock signal sCLK2. According to some embodiments, the second clock signal CLK2 and the auxiliary second clock signal sCLK2 may have a phase difference of 180 degrees from each other.

[0126] The auxiliary first power supply sVGH can be input to the first power input terminal VIN1, and the auxiliary second power supply sVGL can be input to the second power input terminal VIN2. The auxiliary first power supply sVGH can be set to a high voltage, for example, a first voltage V1. The auxiliary second power supply sVGL can be set to a low voltage, for example, a second voltage V2.

[0127] The first power supply VGH can be input to the third power input terminal VIN3, and the second power supply VGL can be input to the fourth power input terminal VIN4. The first power supply VGH can be set to a high voltage, for example, the third voltage V3. The second power supply VGL can be set to a low voltage, for example, the fourth voltage V4.

[0128] The first scan signal GW can be output to the first output terminal OUT1. The activated first scan signal GW (i.e., low voltage) can be set to the fourth voltage V4, and the disabled first scan signal GW (i.e., high voltage) can be set to the third voltage V3.

[0129] The carry signal CR can be output to the second output terminal OUT2. The low voltage of the carry signal CR can be set to the second voltage V2, and the high voltage of the carry signal CR can be set to the first voltage V1.

[0130] According to some embodiments of this disclosure, the stage circuit ST can use auxiliary clock signals sCLK1 and sCLK2 with relatively low voltages, an auxiliary first power supply sVGH, and an auxiliary second power supply sVGL to generate an internal signal (i.e., a carry signal CR). This can reduce the power consumption used to generate the carry signal CR.

[0131] According to some embodiments of this disclosure, the stage circuit ST can use clock signals CLK1 and CLK2 with relatively high voltages, a first power supply VGH, and a second power supply VGL to generate an external signal (i.e., a first scan signal GW) for driving the pixel PX. The pixel PX can be driven stably.

[0132] Figure 8A and Figure 8B It is shown Figure 6 The circuit diagrams for various aspects of the stage circuit are shown below. Figure 8A and Figure 8B For ease of description, the first-stage circuit ST1 will be shown in the diagram.

[0133] Reference Figure 8A According to some embodiments of the present disclosure, the first-stage circuit ST1 may include an input unit 202, a first voltage controller 204, a first output unit 207, a second output unit 208, and a second voltage controller 206.

[0134] The input unit 202 can be located between the first input terminal IN1 and the first node N1, and the input unit 202 controls the electrical connection between the first input terminal IN1 and the first node N1 in accordance with the auxiliary first clock signal sCLK1 input to the second input terminal IN2. For this purpose, the input unit 202 may include a first transistor M1.

[0135] The first transistor M1 can be connected between the first input terminal IN1 and the first node N1, and the gate electrode of the first transistor M1 can be connected to the second input terminal IN2. When an auxiliary first click signal sCLK1 with a low level is input to the second input terminal IN2, the first transistor M1 can be turned on to electrically connect the first input terminal IN1 and the first node N1 to each other.

[0136] The second voltage controller 206 may be located between the first node N1 and the third node N3, and control the voltage of the third node N3 to maintain it at a voltage higher or lower than the voltage of the first node N1. For this purpose, the second voltage controller 206 may include an eleventh transistor M11 (or a first voltage control transistor) and a twelfth transistor M12 (or a second voltage control transistor).

[0137] The eleventh transistor M11 and the twelfth transistor M12 can be connected in series between the first node N1 and the third node N3. The eleventh transistor M11 can be configured as an N-type transistor, and its gate electrode can be connected to the first power input terminal VIN1. The twelfth transistor M12 can be configured as a P-type transistor, and its gate electrode can be connected to the fourth power input terminal VIN4.

[0138] When the voltage of the third node N3 is set to be higher than the voltage of the auxiliary first power supply sVGH, the eleventh transistor M11 can be turned off, and otherwise remains on. The voltage of the third node N3 can be set to be higher than the voltage of the first node N1.

[0139] When the voltage of the third node N3 is set to be lower than the voltage of the second power supply VGL, the twelfth transistor M12 can be turned off. Then, the voltage of the third node N3 can be reduced to a voltage lower than the voltage of the second power supply VGL. The voltage of the third node N3 can be set to a voltage lower than the voltage of the first node N1.

[0140] In addition, such as Figure 8B As shown, the gate electrode of the twelfth transistor M12 can be connected to the second power input terminal VIN2. When the voltage of the third node N3 is set to a voltage lower than the voltage of the auxiliary second power supply sVGL, the twelfth transistor M12 can be turned off.

[0141] Corresponding to the voltage of the first node N1, the first voltage controller 204 can control the voltage of each of the second node N2 (and the fourth node N4) and the third node N3 to be either higher or lower than the voltage of the first node N1. For this purpose, the first voltage controller 204 may include a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a second capacitor C2.

[0142] A fifth transistor M5 (or a first control transistor) can be connected between the third power input terminal VIN3 and the fifth node N5. Furthermore, the gate electrode of the fifth transistor M5 can be connected to the fourth node N4. The fifth transistor M5 can control the electrical connection between the third power input terminal VIN3 and the fifth node N5 while simultaneously turning on or off according to the voltage corresponding to the fourth node N4.

[0143] A sixth transistor M6 (or a second control transistor) can be connected between the fifth node N5 and the fourth power input terminal VIN4. Furthermore, the gate electrode of the sixth transistor M6 can be connected to the third node N3. The sixth transistor M6 can control the electrical connection between the fifth node N5 and the fourth power input terminal VIN4 while simultaneously turning on or off according to the voltage corresponding to the third node N3.

[0144] The seventh transistor M7 (or the third control transistor) can be connected between the third power input terminal VIN3 and the fourth node N4. Furthermore, the gate electrode of the seventh transistor M7 can be connected to the fifth node N5. The seventh transistor M7 can control the electrical connection between the third power input terminal VIN3 and the fourth node N4 while simultaneously turning on or off according to the voltage at the fifth node N5.

[0145] The eighth transistor M8 (or the fourth control transistor) can be connected between the fourth node N4 and the fourth power input terminal VIN4. Furthermore, the gate electrode of the eighth transistor M8 can be connected to the third node N3. The eighth transistor M8 can control the electrical connection between the fourth node N4 and the fourth power input terminal VIN4 while simultaneously turning on or off according to the voltage corresponding to the third node N3.

[0146] The second capacitor C2 can be connected between the fifth node N5 and the third node N3. The second capacitor C2 can act as a coupling capacitor and control the voltage of the third node N3 in response to the voltage change of the fourth node N4.

[0147] The first output unit 207 can output the first scan signal GW1 to the first output terminal OUT1. For this purpose, the first output unit 207 may include a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1.

[0148] The second transistor M2 (or the first scan output transistor) can be connected between the third input terminal IN3 and the first output terminal OUT1. Furthermore, the gate electrode of the second transistor M2 can be connected to the second node N2. The second transistor M2 can control the electrical connection between the third input terminal IN3 and the first output terminal OUT1 while simultaneously being turned on or off according to the voltage corresponding to the second node N2.

[0149] The third transistor M3 (or the second scan output transistor) can be connected between the first output terminal OUT1 and the third power input terminal VIN3. Furthermore, the gate electrode of the third transistor M3 can be connected to the third node N3. The third transistor M3 can control the electrical connection between the third power input terminal VIN3 and the first output terminal OUT1 while simultaneously turning on or off according to the voltage corresponding to the third node N3.

[0150] A fourth transistor M4 (or control transistor) can be connected between the fourth node N4 and the second node N2. Furthermore, the gate electrode of the fourth transistor M4 can be connected to the fourth power input terminal VIN4. When the voltage of the second node N2 is set to a voltage lower than the voltage of the second power supply VGL, the fourth transistor M4 can be turned off. Then, the voltage of the second node N2 can be reduced to a voltage lower than the voltage of the fourth node N4.

[0151] The first capacitor C1 can be connected between the second node N2 and the first output terminal OUT1. Corresponding to the voltage of the first output terminal OUT1, the first capacitor C1 can control the voltage of the second node N2 to keep the second transistor M2 stably in the conducting state.

[0152] Corresponding to the voltage of each of the third node N3 and the fourth node N4, the second output unit 208 can output the first carry signal CR1 to the second output terminal OUT2. For this purpose, the second output unit 208 may include a ninth transistor M9 and a tenth transistor M10.

[0153] The ninth transistor M9 (or the first carry-out transistor) can be connected between the first power input terminal VIN1 and the second output terminal OUT2. Furthermore, the gate electrode of the ninth transistor M9 can be connected to the fourth node N4. The ninth transistor M9 can control the electrical connection between the first power input terminal VIN1 and the second output terminal OUT2 while the voltage corresponding to the fourth node N4 is turned on or off.

[0154] The tenth transistor M10 (or the second carry-out transistor) can be connected between the second output terminal OUT2 and the second power input terminal VIN2. Furthermore, the gate electrode of the tenth transistor M10 can be connected to the third node N3. The tenth transistor M10 can control the electrical connection between the second output terminal OUT2 and the second power input terminal VIN2 while simultaneously turning on or off according to the voltage corresponding to the third node N3.

[0155] According to some embodiments, the first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 may comprise a polycrystalline silicon semiconductor layer formed as an active layer (channel) using a low-temperature polycrystalline silicon (LTPS) process. Furthermore, the first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 may be implemented using P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage of the first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, ninth transistor M9, tenth transistor M10, and twelfth transistor M12 when turned on may have a logic low level.

[0156] According to some embodiments, the eighth transistor M8 and the eleventh transistor M11 can be implemented using N-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as the active layer. Therefore, the gate on-state voltage of the eighth transistor M8 and the eleventh transistor M11 when they are turned on can have a logic high level.

[0157] Figure 9 and Figure 10 This illustrates some embodiments. Figure 8A and Figure 8B Waveform diagrams of various aspects of the driving method of the stage circuit shown.

[0158] Reference Figures 8A to 9First, at the first time t1, a first scan start signal FLM1 with a high level can be input to the first input terminal IN1. The high level of the first scan start signal FLM1 can be set to a first voltage V1, and the low level (or low voltage) of the first scan start signal FLM1 can be set to a second voltage V2. At the first time t1, an auxiliary first clock signal sCLK1 with a high level can be input to the second input terminal IN2. When the auxiliary first clock signal sCLK1 with a high level is input to the second input terminal IN2, the first transistor M1 can remain in the off state.

[0159] At the second time t2, a low-level auxiliary first clock signal sCLK1 can be input to the second input terminal IN2. When the low-level auxiliary first clock signal sCLK1 is input to the second input terminal IN2, the first transistor M1 can be turned on. When the first transistor M1 is turned on, a first scan start signal FLM1 with a first voltage V1 can be supplied to the third node N3. When the first voltage V1 is supplied to the third node N3, the eighth transistor M8 can be turned on. Furthermore, when the first voltage V1 is supplied to the third node N3, the tenth transistor M10, the sixth transistor M6, and the third transistor M3 can be turned off.

[0160] When the tenth transistor M10 is turned off, the electrical connection between the second output terminal OUT2 and the second power input terminal VIN2 is blocked. When the sixth transistor M6 is turned off, the electrical connection between the fifth node N5 and the fourth power input terminal VIN4 can be blocked. When the third transistor M3 is turned off, the electrical connection between the first output terminal OUT1 and the third power input terminal VIN3 can be blocked.

[0161] When the eighth transistor M8 is turned on, the voltage of the second power supply VGL (i.e., the fourth voltage V4) can be supplied to the fourth node N4. When the voltage of the fourth node N4 is set to the fourth voltage V4, the voltage of the second node N2 can also be set to the fourth voltage V4. When the voltage of the second node N2 is set to the fourth voltage V4, the second transistor M2 can be turned on.

[0162] When the voltage of the fourth node N4 is set to the fourth voltage V4, the fifth transistor M5 and the ninth transistor M9 can be turned on.

[0163] When the ninth transistor M9 is turned on, the first power input terminal VIN1 and the second output terminal OUT2 can be electrically connected to each other. Then, the voltage of the auxiliary first power supply sVGH (i.e., the first voltage V1) can be output to the second output terminal OUT2. The first voltage V1 output to the second output terminal OUT2 can be supplied to the next stage circuit as the first carry signal CR1.

[0164] When the fifth transistor M5 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the fifth node N5. When the third voltage V3 is supplied to the fifth node N5, the seventh transistor M7 can be turned off. Furthermore, when the third voltage V3 is supplied to the fifth node N5, the voltage of the third node N3 increases through the coupling of the second capacitor C2. According to some embodiments, the voltage of the third node N3 can increase to the fifth voltage V5. According to some embodiments, the fifth voltage V5 can be a voltage higher than the first voltage V1. According to some embodiments, the fifth voltage V5 can be a voltage higher than the third voltage V3.

[0165] Although the voltage of the third node N3 increases to the fifth voltage V5, the fifth voltage V5 of the third node N3 can be stably maintained by the second voltage controller 206. At the second time t2, the voltage of the third node N3 can be set to a voltage higher than the first voltage V1 (i.e., the fifth voltage V5), and the voltage of the fourth node N4 can be set to a voltage lower than the second voltage V2 (i.e., the fourth voltage V4).

[0166] At the third time t3, a first clock signal CLK1 with a low level can be supplied to the third input terminal IN3. The first clock signal CLK1 with a low level can also be supplied to the first output terminal OUT1 via the second transistor M2 as an activated first scan signal GW1.

[0167] When a first clock signal CLK1 with a low level is input to the first output terminal OUT1, the voltage of the second node N2 can be reduced to a voltage lower than the fourth voltage V4. The fourth voltage V4 of the fourth node N4 can be maintained by the fourth transistor M4.

[0168] At the fourth time t4, the supply of the first scan start signal FLM1 to the first input terminal IN1 can be paused (stopped), and therefore, the second voltage V2 can be supplied to the first input terminal IN1. At the fourth time t4, an auxiliary first clock signal sCLK1 with a high level can be input to the second input terminal IN2. When the auxiliary first clock signal sCLK1 with a high level is input to the second input terminal IN2, the first transistor M1 can remain in the off state.

[0169] At time t5, a low-level auxiliary first clock signal sCLK1 can be input to the second input terminal IN2. When the low-level auxiliary first clock signal sCLK1 is input to the second input terminal IN2, the first transistor M1 is turned on. When the first transistor M1 is turned on, the second voltage V2 can be supplied to the third node N3.

[0170] When the second voltage V2 is supplied to the third node N3, the eighth transistor M8 can be turned off, and the tenth transistor M10, the sixth transistor M6 and the third transistor M3 can be turned on.

[0171] When the tenth transistor M10 is turned on, the voltage of the auxiliary second power supply sVGL (i.e., the second voltage V2) can be supplied to the second output terminal OUT2. The supply of the first carry signal CR1 to the second output terminal OUT2 can be paused.

[0172] When the third transistor M3 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the first output terminal OUT1. The third voltage V3 can also be supplied to the first output terminal OUT1 as a disabled first scan signal GW1.

[0173] When the sixth transistor M6 is turned on, the voltage of the second power supply VGL (i.e., the fourth voltage V4) can be supplied to the fifth node N5. When the fourth voltage V4 is supplied to the fifth node N5, the voltage of the third node N3 can be reduced to the sixth voltage V6 by the second capacitor C2. According to some embodiments, the sixth voltage V6 can be a voltage lower than the second voltage V2. According to some embodiments, the sixth voltage V6 can be a voltage lower than the fourth voltage V4.

[0174] Although the voltage of the third node N3 is reduced to the sixth voltage V6, the sixth voltage V6 of the third node N3 can be stably maintained by the second voltage controller 206. Furthermore, when the voltage of the third node N3 is reduced to the sixth voltage V6, the third transistor M3 can stably remain in the on state, thus ensuring the stability of the drive.

[0175] When the fourth voltage V4 is supplied to the fifth node N5, the seventh transistor M7 can be turned on. When the seventh transistor M7 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the fourth node N4. Then, the voltage of the second node N2 can be set to the third voltage V3, and therefore, the second transistor M2 can be turned off.

[0176] Figures 8A to 9The diagram illustrates the operation of the first-stage circuit ST1. The circuit configuration of each of the other stage circuits ST2 through STn, excluding the first-stage circuit ST1, can be substantially the same as that of the first-stage circuit. However, the carry signal CR can be input to the first input terminal IN1 of each of the other stage circuits ST2 through STn. Furthermore, the auxiliary second clock signal sCLK2 can be input to the second input terminal IN2 of each of the even-numbered stage circuits ST2, ..., STn, and the second clock signal CLK2 can be input to the third input terminal IN3 of each of the even-numbered stage circuits ST2, ..., STn. The operation of each of the even-numbered stage circuits ST2, ..., STn can be substantially the same as that of the first-stage circuit ST1.

[0177] At the same time, Figure 9 The diagram shows multiple activated first scan signals GW1 output to the first output terminal OUT1. However, embodiments of this disclosure are not limited thereto. According to some embodiments, such as Figure 10 As shown, when the width of the first scan start signal FLM1 is controlled, an activated first scan signal GW1 can be output to the first output terminal OUT1. According to... Figure 10 The operation of stage circuit ST1 in the waveform diagram shown can be compared with that of... Figure 9 The operation of stage circuit ST1 shown in the waveform diagram is essentially the same, and a detailed description related to this will be omitted.

[0178] Figure 11 This diagram illustrates the display of images at different refresh rates in the display unit.

[0179] Reference Figure 11 An image can be displayed in a first area AA1 of the display unit 110 at a first image refresh rate, and an image can be displayed in a second area AA2 of the display unit 110 at a second image refresh rate. The first image refresh rate can be 120Hz, and a moving image can be displayed in the first area AA1. The second image refresh rate can be 10Hz, and a still image can be displayed in the second area AA2.

[0180] Scan drive 130 (see Figure 1 The activated first scan signal GW can be supplied to the first region AA1 120 times per second, and the activated first scan signal GW can be supplied to the second region AA2 10 times per second.

[0181] Figure 12 This illustrates the supply to, according to some embodiments Figure 11 The diagram shows various aspects of the first scan signal of the display unit.

[0182] Reference Figure 12 Scan drive 130 (see Figure 1 )(or Figure 2 The first scan driver 132 shown can sequentially generate carry signals CR1, CR2, ..., CRk, ..., CRn (where k is a natural number of 3 or greater and n is a natural number of less than n) corresponding to auxiliary clock signals sCLK1 and sCLK2. The scan driver 130 can generate carry signals CR1 to CRn corresponding to 120Hz. That is, the scan driver 130 can generate carry signals corresponding to the first image refresh rate.

[0183] like Figure 8A and Figure 8B As shown, carry signals CR1 to CRn can be generated by auxiliary clock signals sCLK1 and sCLK2, auxiliary first power supply sVGH, and auxiliary second power supply sVGL. The power consumption used to generate carry signals CR1 to CRn can be minimized or reduced.

[0184] The scan driver 130 can sequentially output the activated first scan signals GW1, GW2, ..., GWk to the first region AA1 at a refresh rate of 120Hz. For this purpose, the timing controller 120 can supply clock signals CLK1 and CLK2, such that the activated first scan signals GW1 to GWk are output in the first region AA1 at a first image refresh rate.

[0185] The scan driver 130 can output the activated first scan signals ..., GWn-1, and GWn to the second region AA2 at a frequency of 10Hz. For this purpose, the timing controller 120 can control whether to supply clock signals CLK1 and CLK2 so that the activated first scan signals ..., GWn-1, and GWn are output in the second region AA2 at a second image refresh rate.

[0186] According to some embodiments, when the activated first scan signals ..., GWn-1, and GWn are not supplied to the second region AA2, clock signals CLK1 and CLK2 can remain low (i.e., the fourth voltage V4) during the corresponding time periods. That is, the timing controller 120 can supply the first scan signal GW at various image refresh rates in multiple regions of the display unit 110 while controlling whether to supply clock signals CLK1 and CLK2. This can minimize or reduce the power consumption of the scan driver 130 and drive multiple regions of the display unit 110 at different image refresh rates.

[0187] Figure 13 This illustrates some embodiments. Figure 6 The circuit diagrams for various aspects of the stage circuit are shown. Although Figure 13Various components that may be included in a stage circuit are shown, but embodiments of the present disclosure are not limited thereto, and according to some embodiments, the stage circuit may include additional or fewer components without departing from the spirit and scope of embodiments of the present disclosure. Figure 13 For ease of description, the first-stage circuit ST1 will be shown in the diagram. Figure 13 In, with Figure 8A The same components shown are identified by the same reference numerals, and repeated descriptions will be omitted.

[0188] Reference Figure 13 According to some embodiments of the present disclosure, the first-stage circuit ST1 may include an input unit 202, a first voltage controller 204, a first output unit 207, a second output unit 208, a third output unit 209, and a second voltage controller 206.

[0189] Corresponding to the voltage of each of the third node N3 and the fourth node N4, the third output unit 209 can output the second scan signal GC1 to the third output terminal OUT3. For this purpose, the third output unit 209 may include a thirteenth transistor M13, a fourteenth transistor M14, and a third capacitor C3.

[0190] The thirteenth transistor M13 (or the first output transistor) can be connected between the third power input terminal VIN3 and the third output terminal OUT3. Furthermore, the gate electrode of the thirteenth transistor M13 can be connected to the fourth node N4. The thirteenth transistor M13 can control the electrical connection between the third power input terminal VIN3 and the third output terminal OUT3 while simultaneously turning on or off according to the voltage corresponding to the fourth node N4.

[0191] The fourteenth transistor M14 (or the second output transistor) can be connected between the third output terminal OUT3 and the fourth power input terminal VIN4. Furthermore, the gate electrode of the fourteenth transistor M14 can be connected to the third node N3. The fourteenth transistor M14 can control the electrical connection between the third output terminal OUT3 and the fourth power input terminal VIN4 while simultaneously turning on or off according to the voltage corresponding to the third node N3.

[0192] The third capacitor C3 can be connected between the third node N3 and the third output terminal OUT3. The third capacitor C3 can store the voltage of the third node N3.

[0193] According to some embodiments, the thirteenth transistor M13 and the fourteenth transistor M14 may comprise a polycrystalline silicon semiconductor layer formed as an active layer (channel) using a low-temperature polycrystalline silicon (LTPS) process. Furthermore, the thirteenth transistor M13 and the fourteenth transistor M14 may be implemented using P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage of the thirteenth transistor M13 and the fourteenth transistor M14 when they are turned on can have a logic low level.

[0194] Figure 14 This illustrates some embodiments. Figure 13 Waveform diagrams of various aspects of the driving method for the stage circuit shown. Figure 14 The following will provide a brief description and reference. Figure 9 The parts described are similar to or the same as the parts described.

[0195] Reference Figure 14 First, at the first time t1a, the first scan start signal FLM1 with the first voltage V1 can be input to the first input terminal IN1. At the first time t1a, the first transistor M1 can remain in the off state.

[0196] At the second time t2a, the auxiliary first clock signal sCLK1 with the second voltage V2 can be input to the second input terminal IN2, and therefore, the first transistor M1 can be turned on. When the first transistor M1 is turned on, the first voltage V1 can be supplied to the third node N3. When the first voltage V1 is supplied to the third node N3, the eighth transistor M8 can be turned on. Furthermore, when the first voltage V1 is supplied to the third node N3, the tenth transistor M10, the sixth transistor M6, the fourteenth transistor M14, and the third transistor M3 can be turned off. When the fourteenth transistor M14 is turned off, the fourth power input terminal VIN4 and the third output terminal OUT3 can be disconnected by a resistor.

[0197] When the eighth transistor M8 is turned on, the voltage of the second power supply VGL (i.e., the fourth voltage V4) can be supplied to the fourth node N4. When the voltage of the fourth node N4 is set to the fourth voltage V4, the voltage of the second node N2 can be set to the fourth voltage V4. When the voltage of the second node N2 is set to the fourth voltage V4, the second transistor M2 can be turned on.

[0198] When the voltage of the fourth node N4 is set to the fourth voltage V4, the fifth transistor M5, the ninth transistor M9, and the thirteenth transistor M13 can be turned on.

[0199] When the ninth transistor M9 is turned on, the voltage of the auxiliary first power supply sVGH (i.e., the first voltage V1) can be output to the second output terminal OUT2. The first voltage V1 output to the second output terminal OUT2 can be supplied to the next stage circuit as the first carry signal CR1.

[0200] When the fifth transistor M5 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the fifth node N5. When the third voltage V3 is supplied to the fifth node N5, the voltage of the third node N3 can be increased through the coupling of the second capacitor C2. According to some embodiments, the voltage of the third node N3 can be increased to the fifth voltage V5.

[0201] When the thirteenth transistor M13 is turned on, the third output terminal OUT3 and the third power input terminal VIN3 can be electrically connected to each other. Then, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the third output terminal OUT3. The third voltage V3 supplied to the third output terminal OUT3 can be supplied to the second scan line SL21 as the activated second scan signal GC1.

[0202] At the third time t3a, a first clock signal CLK1 with a low level can be supplied to the third input terminal IN3. The first clock signal CLK1 with a low level can also be supplied to the first output terminal OUT1 via the second transistor M2 as an activated first scan signal GW1.

[0203] When a first clock signal CLK1 with a low level is input to the first output terminal OUT1, the voltage of the second node N2 can be reduced to a voltage lower than the fourth voltage V4. The fourth voltage V4 of the fourth node N4 can be maintained by the fourth transistor M4.

[0204] At the fourth time t4a, the supply of the first scan start signal FLM1 to the first input terminal IN1 can be paused, and therefore, the second voltage V2 can be supplied to the first input terminal IN1.

[0205] At the fifth time t5a, the auxiliary first clock signal sCLK1 with the second voltage can be input to the second input terminal IN2, and therefore, the first transistor M1 can be turned on. When the first transistor M1 is turned on, the second voltage V2 can be supplied to the third node N3.

[0206] When the second voltage V2 is supplied to the third node N3, the eighth transistor M8 can be turned off, and the tenth transistor M10, the sixth transistor M6, the fourteenth transistor M14 and the third transistor M3 can be turned on.

[0207] When the third transistor M3 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the first output terminal OUT1. The third voltage V3 can also be supplied to the first output terminal OUT1 as a disabled first scan signal GW1.

[0208] When the tenth transistor M10 is turned on, the voltage of the auxiliary second power supply sVGL (i.e., the second voltage V2) can be supplied to the second output terminal OUT2. The output of the first carry signal CR1 can be paused.

[0209] When the sixth transistor M6 is turned on, the voltage of the second power supply VGL (i.e., the fourth voltage V4) can be supplied to the fifth node N5. When the fourth voltage V4 is supplied to the fifth node N5, the voltage of the third node N3 can be reduced to the sixth voltage V6 by the second capacitor C2. When the fourth voltage V4 is supplied to the fifth node N5, the seventh transistor M7 can be turned on. When the seventh transistor M7 is turned on, the voltage of the first power supply VGH (i.e., the third voltage V3) can be supplied to the fourth node N4. Then, the voltage of the second node N2 can also be set to the third voltage V3, and therefore, the second transistor M2 can be turned off.

[0210] When the fourteenth transistor M14 is turned on, the voltage of the second power supply VGL (i.e., the fourth voltage V4) can be supplied to the third output terminal OUT3. The supply of the activated second scan signal GC1 can be paused.

[0211] As mentioned above, Figure 13 The stage circuit ST1 shown can output an activated first scan signal GW1 and an activated second scan signal GC1. Simultaneously, Figure 3 The i-th third scan line SL3i shown can be set as the (i-1)-th second scan line SL2i-1, and Figure 3 The i-th fourth scan line SL4i shown can be set as the (i-1)-th first scan line SL1i-1. The stage circuit ST1 can be used to supply the scan signals for all scan lines SL1, SL2, SL3 and SL4.

[0212] Figure 15 This is a schematic block diagram illustrating an electronic device 1000 including a display device according to an embodiment. Figure 16 It is shown that Figure 15 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 17 It is shown that Figure 15 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0213] Reference Figures 15 to 17 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1The display device 100. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as Figure 16 As shown, the electronic device 1000 can be a smartphone. In an embodiment, as... Figure 17 As shown, electronic device 1000 may be a tablet computer. However, the foregoing example is illustrative, and electronic device 1000 is not necessarily limited to the foregoing example. For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, or head-mounted display device, etc.

[0214] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. Processor 1010 can be connected to other components via address buses, control buses, and data buses. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0215] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0216] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile storage devices to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include a solid-state drive (SSD), hard disk drive (HDD), or optical disc read-only memory (CD-ROM), etc.

[0217] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0218] The power source 1050 can supply the power required to operate the electronic device 1000. For example, the power source 1050 may include a power management integrated circuit (PMIC). In an embodiment, the power source 1050 can supply power to the display device 1060.

[0219] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0220] In the stage circuit according to this disclosure and the display device including the stage circuit, a low voltage is used to generate the carry signal, and a high voltage is used to generate the scan signal. Therefore, the power consumption used to generate the carry signal can be minimized or reduced.

[0221] Furthermore, in the stage circuits according to this disclosure and in the display devices including the stage circuits, different clock signals are used to generate carry signals and scan signals, and therefore, various driving methods can be applied.

[0222] Furthermore, in the stage circuit according to this disclosure and the display device including the stage circuit, a scan signal with a high voltage and a scan signal with a low voltage can be generated.

[0223] Example embodiments have been disclosed herein, and although specific terminology has been used, such terminology is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, unless specifically indicated otherwise, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1. A stage circuit, wherein, The stage circuit includes: An input unit is located between a first input terminal and a first node, wherein the first input terminal is configured to receive a scan start signal or a carry signal, and the input unit is configured to control the electrical connection between the first input terminal and the first node in response to an auxiliary clock signal input to a second input terminal. A first voltage controller is connected to a first main power input terminal and a second main power input terminal. The first voltage controller is configured to control each of the second, third, and fourth nodes to have a voltage higher or lower than that of the first node in response to the voltage of the first node. A first output unit is connected to a third input terminal and a first main power input terminal, the third input terminal being configured to receive a clock signal, and the first output unit being configured to output a first scan signal to the first output terminal in response to the voltage of each of the second node and the third node. A second output unit is connected to a first auxiliary power input terminal and a second auxiliary power input terminal, the second output unit being configured to output the carry signal to the second output terminal in response to the voltage of each of the third node and the fourth node; and A second voltage controller is connected to the first auxiliary power input terminal. The second voltage controller is also connected to the second main power input terminal or the second auxiliary power input terminal. The second voltage controller is positioned between the first node and the third node to maintain the voltage of the third node.

2. The stage circuit according to claim 1, wherein, The auxiliary clock signal and the clock signal have the same period but different phases, and The auxiliary clock signal oscillates between a first voltage and a second voltage, and the clock signal oscillates between a third voltage higher than the first voltage and a fourth voltage lower than the second voltage.

3. The stage circuit according to claim 2, wherein, The first auxiliary power input terminal is configured to receive an auxiliary first power supply having the first voltage. The second auxiliary power input terminal is configured to receive an auxiliary second power supply having the second voltage. The first main power input terminal is configured to receive a first power supply having the third voltage, and The second main power input terminal is configured to receive a second power supply having the fourth voltage.

4. The stage circuit according to claim 3, wherein, The second voltage controller includes an N-type first voltage control transistor and a P-type second voltage control transistor connected in series between the first node and the third node, and The gate electrode of the first voltage-controlled transistor is connected to the first auxiliary power input terminal, and the gate electrode of the second voltage-controlled transistor is connected to the second main power input terminal.

5. The stage circuit according to claim 3, wherein, The second voltage controller includes an N-type first voltage control transistor and a P-type second voltage control transistor connected in series between the first node and the third node, and The gate electrode of the first voltage-controlled transistor is connected to the first auxiliary power input terminal, and the gate electrode of the second voltage-controlled transistor is connected to the second auxiliary power input terminal.

6. The stage circuit according to claim 3, wherein, The input unit includes a first transistor connected between the first input terminal and the first node, the first transistor including a gate electrode connected to the second input terminal.

7. The stage circuit according to claim 3, wherein, The first output unit includes: A first scan output transistor is connected between the third input terminal and the first output terminal, and the first scan output transistor includes a gate electrode connected to the second node; A second scan output transistor is connected between the first output terminal and the first main power input terminal, and the second scan output transistor includes a gate electrode connected to the third node; A control transistor, connected between the second node and the fourth node, the control transistor including a gate electrode connected to the second main power input terminal; and A first capacitor is connected between the second node and the first output terminal.

8. The stage circuit according to claim 3, wherein, The second output unit includes: A first carry-out transistor is connected between the first auxiliary power input terminal and the second output terminal, and the first carry-out transistor includes a gate electrode connected to the fourth node; and A second carry-out transistor is connected between the second output terminal and the second auxiliary power input terminal, and the second carry-out transistor includes a gate electrode connected to the third node.

9. The stage circuit according to claim 3, wherein, The first voltage controller includes: A first control transistor is connected between the first main power input terminal and the fifth node, and the first control transistor includes a gate electrode connected to the fourth node; A second control transistor is connected between the fifth node and the second main power input terminal, and the second control transistor includes a gate electrode connected to the third node; A third control transistor is connected between the first main power input terminal and the fourth node, the third control transistor including a gate electrode connected to the fifth node; A fourth control transistor, connected between the fourth node and the second main power input terminal, the fourth control transistor including a gate electrode connected to the third node; and A second capacitor is connected between the fifth node and the third node; and Each of the first control transistor, the second control transistor, and the third control transistor is a P-type transistor, and the fourth control transistor is an N-type transistor.

10. The stage circuit according to claim 3, wherein, The stage circuit further includes: a third output unit connected to the first main power input terminal and the second main power input terminal, the third output unit being configured to output a second scan signal to the third output terminal in response to the voltage of each of the third node and the fourth node; and The third output unit includes: A first output transistor is connected between the first main power input terminal and the third output terminal, and the first output transistor includes a gate electrode connected to the fourth node; A second output transistor is connected between the third output terminal and the second main power input terminal, the second output transistor including a gate electrode connected to the third node; and A third capacitor is connected between the third node and the third output terminal.

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