Low-k interconnect dielectric by means of selective implantation

Abstract

The invention relates to a low-k interconnect dielectric by means of selective implantation. A multi-level interconnect structure is formed on a semiconductor wafer to include a conductive interconnect structure formed over an interconnect region and a capacitor-terminal structure formed over a capacitor region by selectively implanting one or more interlayer dielectric (ILD) layers over the interconnect region with a capacitance-reducing implant material, at the same time, each ILD layer over the capacitor region is protected from the capacitance reducing implant material, thereby forming a relatively low capacitance interconnect structure over the interconnect region and a relatively high capacitance capacitor over the capacitor region.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor devices. In one aspect, this disclosure relates to interconnect structures formed over a substrate. Background Technology

[0002] Modern integrated circuits (ICs) typically have conductor structures formed in multiple interlayer dielectric (ILD) layers to provide conductive interconnect levels that provide electrical connections to and from circuitry formed on the IC substrate. These conductors can be used to transmit information in the form of signals sent to and from the IC formed on the underlying substrate. Additionally, conductor structures can be formed in the ILD layers to provide other circuit elements, such as capacitor plates electrically connected to the circuitry formed on the IC substrate. After forming the circuitry on the substrate during front-end processing (FEOL), existing copper metallization techniques for semiconductor wafer fabrication form inter-level conductor structures in a series of ILD layers by patterning and etching each ILD layer to form etched openings, depositing and / or filling each etched opening with one or more conductive layers, and then applying chemical mechanical planarization (CMP) or polishing steps to remove the conductive layers from outside the etched openings. Existing manufacturing techniques that form interconnect conductor structures and capacitor-terminal structures in the same ILD layer result in increasing performance trade-offs between interconnect structures and capacitor structures formed in different regions. For example, using low-k (dielectric constant) ILD materials in advanced nodes provides improved interconnect performance by reducing parasitic capacitance between interconnect conductor structures, but this can negatively impact capacitor performance. Specifically, if the capacitor dielectric is formed of a low-k ILD material, larger capacitors are required to achieve the desired capacitance level (increasing cost in terms of area and leakage) and / or more aggressive spacing is needed (which may not always be possible and could exacerbate the risk of breakdown). These design challenges and trade-offs are exacerbated by high-performance IC manufacturing processes, where signals passing through interconnect conductors operate at very high frequencies over conductors with smaller spacing, which can lead to increased parasitic capacitance, adversely affecting the speed and power of the IC. Therefore, existing processes for manufacturing interconnects have not yet provided the cost, speed, and electrical performance required for cutting-edge IC devices that integrate both interconnects and capacitor circuitry elements in an ILD layer formed over a substrate. Further limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reading the remainder of this application with reference to the drawings and the following detailed description. Summary of the Invention

[0003] A semiconductor wafer and an associated manufacturing method are now provided, wherein IC devices and interconnect structures are formed on the semiconductor wafer. In the disclosed method, a semiconductor wafer containing a plurality of IC devices is provided. The disclosed method further includes forming interconnect structures over the plurality of IC devices on the semiconductor wafer, the interconnect structures comprising a plurality of conductive interconnect structures formed over a first region by selectively implanting implant material with varying dielectric constants into one or more interlayer dielectric (ILD) layers located over a first region but not over the one or more ILD layers located over a second region, and a plurality of capacitor-terminal structures formed over a second region, such that the one or more ILD layers located over the first region have a different dielectric constant than the one or more layers located over the second region. In selected embodiments, the interconnect structure is formed as follows: for each level of the interconnect structure, a dielectric layer having a first dielectric constant value is deposited over a semiconductor wafer covering a first region and a second region; for each level of the interconnect structure, an implantation mask is formed on the dielectric layer, the implantation mask having a defined opening that exposes the dielectric layer over the first region but not over the second region; and an implantation material with a changed dielectric constant is implanted into the dielectric layer through the defined opening of the implantation mask to form an implanted dielectric layer having a second dielectric constant value less than the first dielectric constant value. In these embodiments, the dielectric layer can be formed by depositing a layer of silicon dioxide (SiO2), silicon oxycarbide (SiOC), fluorine-doped silicon oxide (SiOF), methylsilsesquioxane (MSQ), tetraethyl silicate (TEOS), or tetraethyl fluorinated silicate (FTEOS) to a predetermined thickness. Furthermore, the implantation mask can be formed by coating, developing, and exposing a photoresist (PR) layer to form a patterned PR implantation mask on the dielectric layer. The patterned PR implantation mask has defined openings that expose the dielectric layer above a first region but not above a second region. Additionally, the implanted dielectric constant-changing implant material can be nitrogen, fluorine, argon, or xenon, which is implanted into the dielectric layer through the defined openings of the implantation mask. In selected embodiments, for each level of the interconnect structure, the dielectric constant-changing implant material is implanted into the ILD layer before the plurality of conductive interconnect structures and the plurality of capacitor-terminal structures are formed in the ILD layer. In other selected embodiments, for each level of the interconnect structure, the dielectric constant-changing implant material is implanted into the ILD layer after the plurality of conductive interconnect structures and the plurality of capacitor-terminal structures are formed in the ILD layer.In a selected embodiment, the interconnect structure is formed by selectively implanting one or more ILD layers over the plurality of first regions with a capacitance-reducing implant material while protecting the one or more ILD layers over the second regions from the capacitance-reducing implant material, thereby forming the one or more ILD layers over the first regions to have a lower dielectric constant than the one or more ILD layers formed over the second regions.

[0004] In another embodiment, an integrated circuit device and an associated method of manufacturing are provided, the integrated circuit device having one or more integrated circuit components and a multilayer interconnect structure formed on a semiconductor substrate. In the disclosed integrated circuit device, the multilayer interconnect structure includes a plurality of first metal structures formed in a first plurality of interlayer dielectric (ILD) layers and electrically coupled to at least some of the one or more IC components. In a selected embodiment, the plurality of first metal structures include a plurality of conductive metal interconnects and vias of an embedded interconnect structure in the first plurality of ILD layers. Additionally, the multilayer interconnect structure includes a plurality of second metal structures formed in a second plurality of ILD layers and electrically coupled to at least some of the one or more IC components. In a selected embodiment, the plurality of second metal structures include a plurality of capacitor-terminal embedded structures in the second plurality of ILD layers. When formed, the first plurality of ILD layers have a first concentration of a dielectric constant-changing implant material and a first dielectric constant value, and the second plurality of ILD layers have a second concentration of a dielectric constant-changing implant material and a second dielectric constant value different from the first dielectric constant value. In selected embodiments, each of the first plurality of ILD layers may include a layer of silicon dioxide (SiO2), silicon oxycarbide (SiOC), fluorine-doped silicon oxide (SiOF), methylsilsesquioxane (MSQ), tetraethyl silicate (TEOS), or tetraethyl fluorinated silicate (FTEOS) that has been implanted with an implant material that alters the dielectric constant. In selected embodiments, the implant material that alters the dielectric constant may be nitrogen, fluorine, argon, or xenon. In selected embodiments, each of the second plurality of ILD layers may include a layer of silicon dioxide (SiO2), silicon oxycarbide (SiOC), fluorine-doped silicon oxide (SiOF), methylsilsesquioxane (MSQ), tetraethyl silicate (TEOS), or tetraethyl fluorinated silicate (FTEOS) that has not yet been implanted with an implant material that alters the dielectric constant. In selected embodiments, the plurality of first metal structures form an embedded interconnect structure in the first plurality of ILD layers having a first relatively low dielectric constant value, and the plurality of second metal structures form an embedded capacitor structure in the second plurality of ILD layers having a second relatively high dielectric constant value.

[0005] In another embodiment, an integrated circuit device and an associated method for fabricating one or more integrated circuit components and multilevel interconnect structures on a semiconductor substrate are provided. In the disclosed method, a plurality of integrated circuit (IC) devices are formed on the semiconductor substrate. Furthermore, the disclosed method includes forming a planarization dielectric layer over the semiconductor substrate to cover the plurality of IC devices. In selected embodiments, the planarization dielectric layer can be formed by depositing a layer of silicon dioxide (SiO2), silicon oxycarbide (SiOC), fluorine-doped silicon oxide (SiOF), methylsilsesquioxane (MSQ), tetraethyl silicate (TEOS), or tetraethyl fluorinated silicate (FTEOS) to a predetermined thickness. In other selected embodiments, the planarization dielectric layer can be formed by depositing a dielectric layer having a first dielectric constant value covering a first region and a second region for each layer of the multilevel interconnect structure. The disclosed method further includes selectively implanting a capacitance-reducing implant material, such as nitrogen, fluorine, argon, or xenon, into a first region of a planarized dielectric layer while protecting a second region of the planarized dielectric layer from the implantation of the capacitance-reducing implant material, thereby forming a first region of a dielectric layer having a first dielectric constant value and a second region of a dielectric layer having a second dielectric constant value greater than the first dielectric constant value. In selected embodiments, the capacitance-reducing implant material can be selectively implanted by forming an implantation mask on the dielectric layer for each level of a multi-level interconnect structure, the implantation mask having a defined opening that exposes the dielectric layer above the first region but not above the second region, and implanting the capacitance-reducing implant material into the dielectric layer through the defined opening of the implantation mask to form an implanted dielectric layer having a second dielectric constant value less than the first dielectric constant value. Furthermore, the disclosed method includes forming one or more conductive structures in the first and second regions of the planarized dielectric layer. In a selected embodiment, the one or more conductive structures may be formed with a plurality of conductive interconnect structures formed in a first region of a planarized dielectric layer and a plurality of capacitor-terminal structures formed in a second region of a planarized dielectric layer. Attached Figure Description

[0006] The invention can be understood and its many objectives, features and advantages can be obtained when the following detailed description of preferred embodiments is considered in conjunction with the following figures.

[0007] Figure 1-10 Cross-sectional views are shown at different manufacturing stages of a semiconductor structure having interconnect structures and capacitor structures formed in a selectively implanted ILD layer, according to selected embodiments of the present disclosure.

[0008] Figure 11 A simplified manufacturing process flow for integrating a relatively low-k interconnect structure with a capacitor structure is shown according to a selected embodiment of the present disclosure. Detailed Implementation

[0009] A process for manufacturing an IC and the resulting IC device are described, which integrates a relatively low-k dielectric layer with a relatively high-k dielectric layer for forming interconnect structures and capacitor structures in a multi-level interconnect structure. In a selected embodiment, a low-k dielectric layer is formed at each layer of the multi-level interconnect using a selective implantation process, thereby patterning the initial dielectric layer with an implantation mask. A predetermined material (e.g., nitrogen, fluorine, argon, and / or xenon) is then implanted into exposed portions of the initial dielectric layer in the interconnect region at a specified implantation dose and energy to form a relatively low-k dielectric layer in the interconnect region, while leaving a protected initial dielectric layer as a relatively high-k dielectric layer in the capacitor region. In a selected embodiment, after material implantation at each level using any suitable damascene process, conductive metal / via structures and capacitor structures are formed (e.g., patterned using copper or aluminum metallization). The damascene process etches patterned openings in the implanted relatively low-k dielectric layer and the protected relatively high-k dielectric layer, then fills the etched openings with one or more conductive layers, followed by the deposition of another dielectric layer. In these embodiments, the concentration of the implant material and the implantation energy are controlled or limited to prevent or reduce any impact on the patterning etching of the dielectric layer, but any suitable etching optimization can be applied to simultaneously process the etching of the implanted and unimplanted areas. In other embodiments, the conductive metal and via connectors are formed prior to selective material implantation. In these embodiments, the concentration and implantation energy are controlled to reduce or eliminate any impact on the conductive metal and via connectors, but one or more implantation optimization processes can be used. For example, if nitrogen is used as the implant in the copper via or metal layer, any resulting copper nitride can be decomposed by applying a controlled thermal process (e.g., annealing at ~250°C).

[0010] This disclosure describes an improved IC structure and manufacturing method for forming a multi-level interconnect structure, which integrates a relatively low-k dielectric layer in the interconnect region with a relatively high-k dielectric layer in the capacitor region as part of or after the back-end process (BEOL) to address various problems in this art, whereby the various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art after reading the remainder of this application with reference to the drawings and the detailed embodiments provided herein. Various illustrative embodiments of the invention will now be described in detail with reference to the accompanying drawings. While various details are set forth in the following description, it should be understood that the invention can be practiced without these specific details, and many implementation-specific decisions can be made with respect to the invention described herein to achieve specific objectives of the device designer, such as compliance with process-technology requirements or design-related constraints that will vary from implementation to implementation. While this development effort may be complex and time-consuming, it is merely routine work for those of ordinary skill in the art who will benefit from this disclosure. For example, selected aspects are depicted with reference to simplified cross-sectional views of a semiconductor device, but not every device feature or geometry is included so as not to limit or obscure the invention. Such descriptions and representations are used by those skilled in the art to describe and convey the essence of their work to others skilled in the art. It should also be noted that throughout this specific embodiment, some elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. Furthermore, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the embodiments of this disclosure. Additionally, reference numerals have been repeated between figures to denote corresponding or similar elements. Furthermore, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings; however, it should be understood that in practice, for example, when the described etching process is applied at different rates to different materials, or when the described deposition or growth process generates layers based on the underlying material, the actual profile or size of the device layers will be non-linear.

[0011] Now refer to Figure 1-11 Various illustrative embodiments of the invention are described in detail. Furthermore, although specific example materials, thicknesses, and processes are described herein, those skilled in the art will recognize that other materials, thicknesses, and processes having similar properties or characteristics can be substituted without loss of functionality. It should be noted that throughout this specific embodiment, certain material layers will be deposited and removed to form a semiconductor structure. Unless specific procedures for processing such layers or specific thicknesses of such layers are detailed below, it will be contemplated that conventional techniques known to those skilled in the art will be used to deposit, remove, form, or otherwise process such layers at appropriate thicknesses. Such details are well-known and are not to be considered necessary to teach those skilled in the art how to make or use the invention.

[0012] To improve the understanding of selected embodiments of this disclosure, reference is now made to... Figure 1-10 It shows cross-sectional views at different manufacturing stages of a semiconductor structure having interconnect structures formed using selective implantation of dielectric layers to integrate relatively low-k dielectric layers with relatively high-k dielectric layers in a multi-level interconnect structure. Specifically, Figure 1 A portion of a semiconductor structure 1 is shown in cross-section, the semiconductor structure 1 having one or more interlayer dielectric (ILD) layers ILD0 14, ILD1 16 and an optional first etch-stop layer (ESL) 15 formed over a semiconductor substrate 10, wherein one or more IC devices or elements 13 are fabricated using FEOL wafer fabrication steps. As will be understood, the FEOL IC device or element 13 may include one or more transistors, resistors, capacitors, diodes or other semiconductor components formed on or in the semiconductor substrate using any suitable semiconductor material or combination of materials (e.g., gallium arsenide, gallium nitride, silicon germanium, semiconductor-on-insulator (SOI), strained semiconductor-on-insulator (SSOI), silicon, single-crystal silicon, etc.). As depicted, transistors may be formed over interconnect regions 11 and may include gates formed over source / drain (S / D) regions of a channel. Adjacent to interconnect regions 11 is a capacitor region 12, over which capacitor elements may be formed. As depicted, interconnect region 11 and capacitor region 12 are separated from each other by isolation region (ISO), and represent portions therein of the interconnect structure forming interconnect elements and capacitor elements. To protect the IC components, the initial insulating layer ILD0 14 can be formed using any suitable insulating material. For example, a planarized tetraethyl boron phosphosilicate (BPTEOS) layer can form all or part of the initial interlayer dielectric (ILDO) layer 14, which provides gettering functionality to help protect the IC components and control field leakage between semiconductor transistors.

[0013] After the initial ILD layer is formed, an ESL 15 (e.g., SiN, SiC, SiCN, SiON, SiCON, etc.) may optionally be deposited to a predetermined thickness across the entire surface of the semiconductor structure 1 to serve as a substrate for forming the initial metal (M1) interconnect layer. On the ESL 15, a bottom ILD layer 16 is formed to a predetermined thickness across the entire surface of the semiconductor structure using a suitable deposition dielectric material (e.g., SiO2, SiOC, SiOF, methylsilsesquioxane (MSQ) or other suitable dielectric material). In selected embodiments, the bottom ILD layer 16 may be formed of any dielectric material suitable for capacitor structure formation, including but not limited to tetraethyl orthosilicate (TEOS), tetraethyl orthosilicate fluorinated silicate (FTEOS), or other dielectric materials having a dielectric constant k that is at least as high as that of silicon dioxide (SiO2), which is 3.9. Dielectric materials with k > 3.9 are referred to as “high” k dielectrics, while dielectric materials with k < 3.9 are defined as “low” k dielectrics. In some embodiments, the dielectric layer may be deposited to a thickness greater than the final desired thickness and then etched back or planarized to improve thickness uniformity on the semiconductor wafer.

[0014] Figure 2 This illustrates the process after forming a first patterned implantation mask layer 17 on a semiconductor structure according to a selected embodiment of the present disclosure. Figure 1 The subsequent fabrication of semiconductor structure 2. Although any suitable mask patterning process can be used, a first implanted photoresist (PR) mask 17 can be formed on the first ILD1 layer 16 by sequentially depositing, patterning, etching, and / or developing a PR layer made of any material suitable for photolithography. As depicted, the first patterned photoresist implanted mask layer 17 includes a defined opening 17A that exposes the underlying first ILD1 layer 16 at a predetermined interconnect region 11 to form a multi-level interconnect structure.

[0015] Figure 3 The illustration shows, according to a selected embodiment of the present disclosure, the selective implantation of exposed portions of the ILD layer 16 using one or more implantation processes 18 to form a low-k or very low-k implanted ILD1 layer 19. Figure 2 The subsequent processing of semiconductor structure 3. In selected implantation embodiments, the implanted ILD1 layer 19 can be formed by implanting selected materials at a predetermined implantation energy and dopant concentration to disrupt the structural properties of ILD layer 16, thereby reducing the dielectric constant of the implanted ILD1 layer 19. Example implantation materials include, but are not limited to, nitrogen, fluorine, argon, or xenon. Implantation effects can include increased porosity, decreased polarizability, or decreased film density. For example, nitrogen can be implanted into the ILD layer 16 formed with MSQ at a predetermined implantation energy and dopant concentration (e.g., N = 1E15 atoms / cm² at an energy of 20 keV).2 The resulting implanted ILD1 layer 19 initially has a low k dielectric constant (e.g., k = 2.1), which can be further reduced to approximately 2.03-2.04 by applying heat treatment after implantation. Furthermore, predetermined implantation energies and dopant concentrations (e.g., F = 1E14 keV / cm² at an energy of 40 keV) are achieved by co-implanting fluorine and nitrogen into the ILD layer 16 formed using MSQ. 2 The resulting implanted ILD1 layer 19 initially has a low k dielectric constant (e.g., k = 1.68), which can be reduced to approximately 1.6 by applying heat treatment. Furthermore, by increasing the implantation energy and concentration of fluorine and nitrogen co-implanted into the ILD layer 16 (e.g., F = 1E14 keV / cm at an energy of 40 keV), the dielectric constant can be further reduced. 2 The resulting implanted ILD1 layer 19 has a low k dielectric constant (e.g., k = 1.51), but this value can be slightly increased or decreased by applying heat treatment after implantation.

[0016] In other embodiments, approximately 1E14-1E15 atoms / cm 2 The implantable material dosage of the implanted ILD layer 16 formed with MSQ will produce approximately 1E18-1E19 atoms / cm under typical implantation conditions. 3 The concentration of MSQ molecules was increased from 1.5E21 atoms / cm³. 3 (Without pores) reduced to 1.05E21 atoms / cm 3 (30% of the holes). The resulting implantation dose will be <~1% by volume, which is unlikely to significantly affect the etching rate or sidewall profile of the implanted MSQ ILD layer 19 during subsequent mounting processing. Alternatively, any etching chemistry or rate used during mounting processing can be optimized as needed to account for the nature of the changes in MSQ ILD 19 caused by implantation.

[0017] In other embodiments, the ILD layer 16 formed of silicon dioxide is approximately 1E16 to 5E16 cm. -2 Implanting a dose of 300 keV xenon will cause the formation and thermal evolution of bubbles or cavities in silica. These bubbles or cavities will persist even after annealing at 1100 °C, while Xe will strongly desorb at this temperature, resulting in an extremely low k dielectric constant (k) value of less than 1.6.

[0018] In other embodiments, the use of a triple implantation process to implant fluorine with increased implantation energy and implantation material dosage in the silicon dioxide ILD layer 16 will result in the formation of an implanted ILD1 layer 19 with a smaller dielectric constant (k) value (e.g., k = 2.9).

[0019] Figure 4 This illustrates the process after the first patterned implantation mask layer 17 has been removed or stripped from the semiconductor structure to expose the unimplanted ILD1 layer 16. Figure 3 The subsequent fabrication of semiconductor structure 4. While any suitable resist stripping process can be used, the example process can remove the first patterned implantation mask layer 17 by using a plasma-based ashing process and / or wet etching chemistry, which selectively removes the first patterned implantation mask layer 17 without etching the underlying ILD1 layers 16, 19. At this point in the fabrication process, the selectively implanted ILD1 layer 19 has a relatively low dielectric constant value k1, and the unimplanted ILD1 layer 16 has a relatively high dielectric constant value k2>k1.

[0020] Figure 5 This illustrates the selective formation of conductive metal structures M0 and capacitor structures C0 in the underlying ILD1 layers 16 and 19 by sequentially depositing, planarizing, patterning, and / or etching any suitable conductive material (e.g., aluminum, copper, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium, titanium nitride, etc., and combinations thereof) to fill etched openings in the underlying ILD1 layers 16 and 19. Figure 4 The subsequent processing of semiconductor structure 5. For example, each constituent interconnect conductor layer M0 may be formed over interconnect region 11 in an etched opening formed in the implanted relatively low-k dielectric layer 19 using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), focused ion beam (FIB) deposition, electron beam induced deposition (EBID), microchemical vapor deposition, laser focused deposition, laser focused atomic deposition, or any other suitable global or local deposition technique, or any combination thereof, to achieve a predetermined final thickness. Similarly, each constituent capacitor-end layer C0 may be formed over capacitor region 12 in an etched opening formed in the unimplanted relatively high-k dielectric layer 16 using any suitable global or local deposition technique. While the specific arrangement, construction, and connection of the different interconnect and capacitor-end layers M0, C0 are not critical, each layer can be constructed in the underlying ILD1 layers 16, 19 using a damascene process, wherein the conductive layers M0, C0 are deposited in openings formed in the underlying ILD1 layers 16, 19, followed by polishing or etching back. Although not illustrated, it should be understood that any suitable process for depositing, planarizing, patterning, and / or etching any suitable conductive material can be used to selectively form the initial via structure V0 in the initial insulating layer ILD0 14. For example, the conductive layers V0, M0, C0 can be formed simultaneously using a dual damascene patterning process, or sequentially using a single damascene patterning process.

[0021] Figure 6 The illustration shows, according to a selected embodiment of the present disclosure, the sequential deposition (optionally) of a second ESL 20 and a second ILD2 layer 21 over a semiconductor structure 6, followed by the selective application of one or more implantation processes 23 using a second patterned implantation mask layer 22 to form a low-k or very low-k implanted ILD2 layer 24 over the interconnect region 11. Figure 5 The subsequent processing of the semiconductor structure 6. As described above, a second ILD2 layer 21 can be formed on the second ESL 20 using any suitable dielectric material, the second ILD2 layer 21 being deposited to a predetermined thickness across the entire surface of the semiconductor structure 6. In selected embodiments, the second ILD2 layer 21 can be formed from any dielectric material suitable for capacitor-structure formation. On the second ILD2 layer 21, a second patterned implantation mask layer 22 can be formed, for example, by depositing, patterning, etching, and / or developing a photoresist (PR) layer with defined openings 22A that expose the underlying second ILD2 layer 21 at designated interconnect regions 11 to form a multilevel interconnect structure. In the case of forming the second patterned implantation mask layer 22, the exposed portions of the second ILD2 layer 21 are selectively implanted with a suitable implantation material (e.g., nitrogen, fluorine, argon, or xenon) using implantation process(s)23 at controlled implantation energies and doses to form a low-k or very low-k implanted ILD2 layer 24.

[0022] Figure 7 This illustrates the selective formation of conductive via structure V1 25 in interconnect region 11. Figure 6 The subsequent processing of semiconductor structure 7. After stripping or removing the second patterned implantation mask layer 22, a conductive via structure V1 25 can be formed in the implanted ILD2 layer 24 using a single damascene patterning process by sequentially depositing, planarizing, patterning, and / or etching any suitable conductive material to fill the etched via openings in the underlying ILD2 layer 24. As will be understood, the conductive via structure V1 25 can be formed simultaneously with the conductive layers M1, C1 described below using a dual damascene patterning process. For example, each via conductor layer V1 25 can be formed using a damascene process in the etched openings formed in the implanted relatively low-k dielectric layer 24 and the second ESL 20 above the interconnect region 11, wherein the via conductor layer V1 25 is deposited in the openings formed in the underlying ILD2 layer 24 and ESL 20, and then polished or etched back.

[0023] Figure 8The illustration shows, according to a selected embodiment of the present disclosure, the sequential deposition (optional) of a third ESL 26 and a third ILD3 layer 27 over a semiconductor structure 8, followed by the selective application of one or more implantation processes 29 using a third patterned implantation mask layer 28 to form a low-k or very low-k implanted ILD3 layer 30 over an interconnect region 11. Figure 7 Subsequent fabrication of the semiconductor structure 8. As described above, a third ILD3 layer 27 can be formed on the third ESL 26 using any suitable dielectric material, the third ILD3 layer 27 being deposited to a predetermined thickness across the entire surface of the semiconductor structure 8. In selected embodiments, the third ILD3 layer 27 can be formed using any dielectric material suitable for capacitor structure formation. On the third ILD3 layer 27, a third patterned implantation mask layer 28 can be formed, for example, by depositing, patterning, etching, and / or developing a photoresist (PR) layer with defined openings 28A that expose the underlying third ILD3 layer 27 at designated interconnect regions 11 to form a multilevel interconnect structure. In the case of forming the third patterned implantation mask layer 23, the exposed portions of the third ILD3 layer 27 are selectively implanted with a suitable implantation material (e.g., nitrogen, fluorine, argon, or xenon) using implantation process(s)29 at controlled implantation energies and doses to form a low-k or very low-k implanted ILD2 layer 24.

[0024] Figure 9 This is shown after peeling or removing the third patterned implant mask layer 28. Figure 8 The subsequent fabrication of semiconductor structure 9. While any suitable resist stripping process can be used, the example process can remove the third patterned implantation mask layer 28 by using a plasma-based ashing process and / or wet etching chemistry, which selectively removes the third patterned implantation mask layer 28 without etching the underlying ILD3 layers 27, 30. At this point in the fabrication process, the selectively implanted ILD3 layer 30 has a relatively low dielectric constant value k1, and the unimplanted ILD3 layer 27 has a relatively high dielectric constant value k2>k1.

[0025] Figure 10 This illustrates the selective formation of the conductive metal structure M1 and the capacitor structure C1 in the third ILD3 layers 27, 30 by sequentially depositing, planarizing, patterning, and / or etching any suitable conductive material to fill the etched openings in the underlying ILD3 layers 27, 30. Figure 9The subsequent fabrication of the semiconductor structure 10. For example, each constituent interconnect conductor layer M1 can be formed over the interconnect region 11 in an etched opening formed in the implanted relatively low-k dielectric layer 30 to achieve a predetermined final thickness using any other suitable deposition or local deposition technique. In a similar manner, each constituent capacitor-end layer C1 can be formed over the capacitor region 12 in an etched opening formed in the unimplanted relatively high-k dielectric layer 27 using any suitable deposition or local deposition technique. While the specific arrangement, construction, and connection of the different interconnect and capacitor-end layer M1, C1 are not critical, each layer can be constructed in the underlying third ILD3 layers 27, 30 using a damascene process, wherein the conductive layers M1, C1 are deposited in openings formed in the underlying third ILD3 layers 27, 30, and then polished or etched back.

[0026] exist Figure 10 In the depicted example, the capacitor structure C0 formed in the bottom ILD1 layer 16 can form a first monolayer capacitor, which is composed of staggered capacitor plate layers, including an outermost pair of capacitor structures C0 forming the first capacitor plate 101. This outermost pair of capacitor structures C0 is staggered with the central capacitor structure C0 forming the second capacitor plate 102, separated by the capacitor dielectric ILD layer 16. Similarly, the capacitor structure C1 formed in the topmost ILD2 layer 27 can form a second monolayer capacitor, which is composed of staggered capacitor plate layers, including an outermost pair of capacitor structures C1 forming the first capacitor plate 103. This outermost pair of capacitor structures C1 is staggered with the central capacitor structure C1 forming the second capacitor plate 104, separated by the capacitor dielectric ILD layer 27. Although this example shows the first and second monolayer capacitors forming parallel aligned capacitor fingers, it should be understood that the first and second monolayer capacitors can form capacitor fingers arranged orthogonally to each other. In an alternative embodiment, the capacitor-end layers C0, C1 can form individual ends of the capacitor structure. In other embodiments, two consecutive dielectric layers can be implanted together using an implant with a higher energy level than that used for implanting a single dielectric layer. In these embodiments, dual damascene patterning and metallization can then be used together to form interconnect metal and via features. In other embodiments, each dielectric layer can be implanted individually over the interconnect region, and dual damascene patterning and metallization can be used together to form the interconnect metal and via layers.

[0027] Now go to Figure 11A simplified process flow 200-209 for manufacturing a semiconductor wafer according to a selected embodiment of the present disclosure is shown, the semiconductor wafer having a lower k dielectric layer and a higher k dielectric layer for forming interconnect structures and capacitor structures in a multi-level interconnect structure. Although a selected embodiment of the semiconductor wafer manufacturing method is described with reference to the example BEOL manufacturing process, those skilled in the art will understand that the sequence of steps shown can be used for any suitable stage of a device manufacturing process and can be modified, reduced, or expanded according to the disclosure of this disclosure. Therefore, it should be understood that the method of this disclosure can be considered as... Figure 11 The sequence of steps described in the diagram is the sequence of steps identified, but these steps can also be executed in parallel, in a different order, or as a combination of independent operations.

[0028] Following the commencement of the disclosed manufacturing method (step 200), one or more FEOL processing steps 201 are performed to fabricate a wafer substrate having IC elements (e.g., transistors, capacitors, resistors, diodes, etc.) connected to a multi-level interconnect structure and one or more capacitor structures formed in multiple ILD layers. Overall, FEOL processing is the first part of IC fabrication in which individual components (transistors, capacitors, resistors, etc.) are formed in the semiconductor, and generally covers all steps up to (but not including) the deposition of interconnect layers.

[0029] At step 202, an initial interlayer dielectric (ILD) layer is formed over the IC device on the wafer substrate. In an example embodiment, the initial ILD layer can be formed by depositing a dielectric material to a predetermined final thickness using CVD, PECVD, PVD, ALD, FIB deposition, EBID, microchemical vapor deposition, laser focused deposition, laser focused atomic deposition, or any other suitable global or local deposition technique, or any combination thereof. Furthermore, the dielectric material can include, but is not limited to, SiO2, SiOC, SiOF, MSQ, TEOS, FTEOS, or other dielectric materials having a dielectric constant k that is at least as high as that of silicon dioxide (SiO2).

[0030] At step 203, an implantation mask is patterned on the ILD layer to expose the ILD layer in a designated interconnect region and protect the ILD layer in a designated capacitor region. In a selected embodiment, the implantation mask can be formed by depositing or coating a wafer substrate with a photoresist layer, which is then developed and exposed to transfer the pattern from the mask to the wafer, such that the implantation mask protects the ILD layer located in the capacitor region and has an opening defined to expose the ILD layer located in the interconnect region of the wafer substrate.

[0031] At step 204, a portion of the ILD layer exposed by the implantation mask above the interconnect region is selectively implanted to form a lower k ILD layer. In an example embodiment, the implantation process and the implantation power and dosage of the material are controlled to selectively implant selected implantation materials (e.g., nitrogen, fluorine, argon, or xenon) into the exposed portion of the ILD layer above the designated interconnect region, but not into the protected portion of the ILD layer above the designated capacitor region. As a result of changing the structure and density of the implanted ILD layer, the implantation will reduce the capacitance of the ILD layer in the interconnect region compared to the capacitance of the ILD layer in the capacitor region, thereby enabling the formation of capacitors with higher capacitance and reducing the capacitance between conductive metal / via structures in a multi-level interconnect structure.

[0032] At step 205, the implantation mask is removed from the wafer substrate. Depending on the material used to form the implantation mask, one or more appropriate etching processes can be applied to selectively remove the implantation mask. For example, an ash / piranha process can be used to strip a patterned photoresist implantation mask, but other resist removal processes can be used.

[0033] At step 206, interconnect openings can be selectively etched in the lower k ILD layer and any capacitor openings can be selectively etched in the ILD layer. For example, interconnect openings and capacitor openings can be formed simultaneously or sequentially using any suitable mask etching process, such as by forming a patterned photoresist layer as an etching mask, and then applying one or more anisotropic etching processes to etch the openings into the exposed portions of the underlying ILD layer.

[0034] At step 207, interconnect conductor structures and capacitor-end structures are formed in the interconnect openings and capacitor openings. In an example embodiment, one or more conductive layers can be formed to fill the interconnect openings and capacitor openings by sequentially depositing one or more conductive metal layers (e.g., barrier liner layers, seed layers, and electroplated copper layers), planarizing the deposited conductive metal layers, and then patterning and etching the conductive metal layers to define the desired interconnect conductor structures and capacitor-end structures in the underlying ILD layer.

[0035] At step 208, the manufacturing method determines whether the final layer of the capacitor structure has been completed. If not (detecting the negative result of step 208), the method returns to step 202 to form the next ILD layer over the wafer substrate, and repeats steps 202-208 to selectively implant the next ILD layer and form interconnect conductor structures in the implanted portion of the next ILD layer over the interconnect region, and form capacitor-terminal structures in the unimplanted portion of the next ILD layer over the capacitor region. Thus, manufacturing steps 202-208 are iteratively repeated until the wafer substrate has a completed multilevel interconnect with a (very) low kILD layer formed over the interconnect region and a completed capacitor with a relatively high kILD layer formed over the capacitor region, including first and second plate conductor layers separated by dielectric capacitor layers with unimplanted ILD layers. In selected embodiments, the completed capacitor may be a metal-oxide-metal (MOM) capacitor, an edge capacitor, or other high-capacitance capacitor providing critical functionality for analog / precision circuits. When the last layer of the multi-level structure has been completed (a positive result of step 208), the method ends (step 209). As will be understood, an additional metallization layer (not shown) may exist, formed above the last capacitor layer of the low-k and high-k ILD layers in which no distinction is needed, for example when the top metallization layer is formed before the manufacturing process ends at step 209.

[0036] As described above, metallization is performed after selective implantation of the ILD layer in the interconnect region. In these cases, the concentration of implanted material in the ILD layer is low enough that it is unlikely to fundamentally affect subsequent etching of the implanted ILD layer, but some etching optimization may be required to simultaneously etch the implanted and unimplanted regions. As will be understood, manufacturing steps 201-209 can be adjusted, reordered, or combined in a different sequence. For example, manufacturing steps 206-207 can be combined into a combined metallization manufacturing step using any suitable technique for manufacturing interconnect structures and capacitor-end structures. Alternatively, or in an alternative, selective implantation steps 203-204 can occur after the interconnect structures and capacitor-end structures are formed in the ILD layer. For example, nitrogen can be selectively implanted into the ILD layer where copper interconnect structures and capacitor structures have previously been formed. In this example, the resulting Cu3N formed in the copper interconnect structures and capacitor structures can be removed by applying a heat treatment (e.g., annealing at 250°C) that decomposes the Cu3N formed in the copper interconnect structures and capacitor structures.

[0037] Although process steps 200-209 are for performing damascene patterning after selective dielectric implantation, those skilled in the art will understand that the manufacturing process can be adapted, modified, and / or changed to be used with other interconnect manufacturing processes such as aluminum patterning, implantation after metallization, simultaneous implantation of two consecutive dielectric layers, dual damascene patterning and metallization processes, and separate implantation of dielectric layers over interconnect regions and interconnect metals.

[0038] As described above, this disclosure provides a mechanism for integrating relatively low-k dielectric ILD interconnect layers with relatively high-k dielectric capacitor ILD layers by selectively implanting interconnect regions of each ILD layer with appropriate implant material, energy, and dosage, such that low-capacitance multilevel interconnects and higher-capacitance capacitor elements are integrated in the same fabrication sequence. The disclosed process can be used with porous organic low-k dielectrics used in advanced technologies, such that interconnect capacitors are prevented from receiving ILD implants to maintain a high dielectric constant in these regions, while interconnect regions receive ILD implants to reduce the dielectric constant in the interconnect regions.

[0039] While the exemplary embodiments described herein are directed to various semiconductor and IC device structures and methods of manufacturing thereof, the invention is not necessarily limited to illustrative examples applicable to a wide variety of semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are illustrative only and should not be considered as limiting the invention, as the invention can be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the specific forms stated, but rather is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the broadest form of the invention.

[0040] The benefits, other advantages, and solutions to the problem have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to the problem, and any elements that may cause any benefit, advantage, or solution to appear or become more apparent should not be construed as essential, necessary, or fundamental features or elements of any or all claims. As used herein, the term "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A method for manufacturing an integrated circuit (IC) device, characterized in that, include: Provide semiconductor wafers containing multiple IC devices; as well as An interconnect structure is formed over the plurality of IC devices on the semiconductor wafer. The interconnect structure includes a plurality of conductive interconnect structures formed over the first region by selectively implanting an implant material with a different dielectric constant into one or more interlayer dielectric (ILD) layers located over the first region but not into the one or more ILD layers located over the second region, and a plurality of capacitor-terminal structures formed over the second region, such that the one or more ILD layers located over the first region have a different dielectric constant than the one or more layers located over the second region.

2. The method according to claim 1, characterized in that, Forming the interconnect structure includes: For each level of the interconnect structure, a dielectric layer having a first dielectric constant value is deposited over the semiconductor wafer, covering the first region and the second region; For each level of the interconnect structure, an implantation mask is formed on the dielectric layer, the implantation mask having a defined opening that exposes the dielectric layer above the first region but not above the second region; and The dielectric constant-modified implant material is implanted into the dielectric layer through the defined opening of the implantation mask to form an implanted dielectric layer having a second dielectric constant value that is less than the first dielectric constant value.

3. The method according to claim 1, characterized in that, Forming the interconnect structure includes selectively implanting one or more ILD layers over the plurality of first regions with an implant material that alters the dielectric constant, while protecting the one or more ILD layers over the second regions from the effects of the implant material that alters the dielectric constant, thereby forming the one or more ILD layers over the first regions to have a lower dielectric constant value than the one or more ILD layers formed over the second regions.

4. The method according to claim 1, characterized in that, Before or after selective implantation of each of the one or more ILD layers, the plurality of conductive interconnect structures and the plurality of capacitor-terminal structures are formed in each of the one or more ILD layers.

5. An integrated circuit (IC) device, characterized in that, include: A semiconductor substrate that includes one or more IC components; as well as A multi-level interconnect structure formed on the semiconductor substrate, the multi-level interconnect structure comprising: A plurality of first metal structures formed in a plurality of first interlayer dielectric (ILD) layers and electrically coupled to at least some of the one or more IC components, and Multiple second metal structures are formed in a second plurality of ILD layers and electrically coupled to at least some of the IC components in the one or more IC components; The first plurality of ILD layers include an implant material with a first concentration of altered dielectric constant and have a first dielectric constant value, and the second plurality of ILD layers include an implant material with a second concentration of altered dielectric constant and have a second dielectric constant value different from the first dielectric constant value.

6. The integrated circuit device according to claim 5, characterized in that, The plurality of first metal structures include a plurality of conductive metal interconnects and vias in the embedded interconnect structures of the first plurality of ILD layers, and wherein the plurality of second metal structures include a plurality of capacitor-end embedded structures in the second plurality of ILD layers.

7. The integrated circuit device according to claim 5, characterized in that, The plurality of first metal structures form an embedded interconnect structure in the plurality of ILD layers having a first relatively low dielectric constant value, and wherein the plurality of second metal structures form an embedded capacitor structure in the plurality of ILD layers having a second relatively high dielectric constant value.

8. A method, characterized in that, include: Multiple integrated circuit (IC) devices are formed on a semiconductor substrate; A dielectric layer is formed over the semiconductor substrate to cover the plurality of IC devices; Selectively implanting a capacitance-reducing implant material into a first region of the dielectric layer, while protecting a second region of the dielectric layer from the effects of the implantation of the capacitance-reducing implant material, thereby forming a first region of the dielectric layer having a first dielectric constant value and a second region of the dielectric layer having a second dielectric constant value greater than the first dielectric constant value; as well as One or more conductive structures are formed in the first and second regions of the dielectric layer.

9. The method according to claim 8, characterized in that... Forming the dielectric layer includes depositing a dielectric layer with a first dielectric constant value covering the first region and the second region for each layer of the multi-level interconnect structure; and Selective implantation of the capacitance-reducing implant material includes: For each level of the multi-level interconnect structure, an implantation mask is formed on the dielectric layer. The implantation mask has a defined opening that exposes the dielectric layer above the first region but not above the second region. The capacitance-reducing implant material is implanted into the dielectric layer through the defined opening of the implantation mask to form an implanted dielectric layer having a second dielectric constant value that is less than the first dielectric constant value.

10. The method according to claim 9, characterized in that, Depositing the dielectric layer includes depositing a layer of silicon dioxide (SiO2), silicon oxycarbide (SiOC), fluorine-doped silicon oxycarbide (SiOF), methylsilsesquioxane (MSQ), tetraethyl silicate (TEOS), or tetraethyl fluorinated silicate (FTEOS) to a predetermined thickness.

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