Cutting method of semiconductor structure and chip unit

Abstract

The invention relates to the technical field of semiconductors, and relates to a cutting method of a semiconductor structure and chip units, the semiconductor structure comprises a substrate and a device layer located on the substrate, and the device layer comprises a plurality of chip units and cutting areas located between every two adjacent chip units. The cutting area comprises a dielectric layer and a conductive structure embedded in the dielectric layer, and the cutting method comprises the following steps: cutting the cutting area to form a cutting channel; in the direction perpendicular to the surface of the substrate, cutting the channel to penetrate through the dielectric layer and the conductive structure, and exposing the substrate; plasma etching is carried out on a part of the substrate located at the bottom of the cutting channel to form a segmentation groove; and removing the substrate at the bottom of the segmentation groove. According to the cutting method, residues can be reduced, and the yield of the chip units can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for cutting a semiconductor structure and a chip unit. Background Technology

[0002] In semiconductor manufacturing, multiple chip units are typically manufactured together. In the subsequent packaging stage, these chip units need to be cut and separated to form individual chip units. However, the cutting process generates a large amount of residue, resulting in a low yield of the final chip units.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a method for cutting a semiconductor structure and a chip unit, which can reduce residue and improve the yield of the chip unit.

[0005] According to one aspect of this disclosure, a method for dicing a semiconductor structure is provided, the semiconductor structure including a substrate and a device layer located on the substrate, the device layer including a plurality of chip cells and a dicing region located between two adjacent chip cells, the dicing region including a dielectric layer and a conductive structure, the dicing method comprising:

[0006] The cutting area is cut to form a cutting channel; in a direction perpendicular to the surface of the substrate, the cutting channel penetrates the dielectric layer and the conductive structure, and exposes the substrate;

[0007] The portion of the substrate located at the bottom of the cutting channel is subjected to plasma etching to form a slit groove;

[0008] Remove the substrate located at the bottom of the dividing groove.

[0009] In one exemplary embodiment of this disclosure, the cutting method further includes, prior to plasma etching of the portion of the substrate located at the bottom of the cutting trench:

[0010] A filling layer is formed within the dicing channel, the filling layer being located on the substrate and covering the surface of the conductive structure exposed on the sidewall of the dicing channel;

[0011] The plasma etching of the portion of the substrate located at the bottom of the cutting trench includes:

[0012] A mask layer is formed on the side of the dielectric layer and the filler layer away from the substrate. The mask layer includes a mask region, and the orthographic projection of the mask region on the substrate lies within the orthographic projection of the filler layer on the substrate.

[0013] The filler layer and the substrate located directly below the filler layer are etched in the mask area to form the dividing groove.

[0014] In one exemplary embodiment of this disclosure, cutting the cutting area includes:

[0015] The cutting area is cut using laser cutting technology.

[0016] In one exemplary embodiment of this disclosure, the cutting method further includes, before removing the substrate located at the bottom of the dividing groove:

[0017] An adhesive layer is formed on the surface of the dielectric layer away from the substrate, and the orthographic projection of the dividing groove on the substrate is within the orthographic projection of the adhesive layer on the substrate.

[0018] In one exemplary embodiment of this disclosure, removing the substrate located at the bottom of the dividing groove includes:

[0019] The substrate is ground until the remaining substrate at the bottom of the dividing groove is removed.

[0020] In one exemplary embodiment of this disclosure, the cutting method further includes:

[0021] A fixing portion is formed on the side of the substrate away from the dielectric layer, the substrate is fixed on the fixing portion, and the orthographic projection of the dividing groove on the substrate is within the orthographic projection of the fixing portion on the substrate;

[0022] Remove the adhesive layer;

[0023] Clean the surfaces of the dividing groove and the medium layer.

[0024] In one exemplary embodiment of this disclosure, the cutting method further includes, before cleaning the surfaces of the dividing groove and the medium layer:

[0025] The surface of the medium layer is ground.

[0026] In one exemplary embodiment of this disclosure, the dividing groove is located in the central region of the cutting area, and the ratio of the width of the dividing groove to the width of the cutting area is 1:2.5 to 1:4.

[0027] In one exemplary embodiment of this disclosure, there are multiple device layers, which are bonded to each other along a direction perpendicular to the substrate, and the dicing regions in different device layers are aligned and distributed; the dicing channels penetrate each dielectric layer and each conductive structure in each device layer.

[0028] According to one aspect of this disclosure, a chip cell is provided, the chip cell being cut using a semiconductor structure cutting method as described in any of the preceding claims.

[0029] The semiconductor structure cutting method and chip unit disclosed herein, by cutting only the cutting area and not the substrate, avoids the generation of a large amount of molten debris and particles caused by large-area substrate ablation during the cutting process. Compared with the traditional method of laser cutting the entire semiconductor structure, the cutting process of this disclosure generates relatively fewer impurities, thus effectively controlling the amount of impurities generated at the cutting stage. Simultaneously, this disclosure uses plasma etching to form the dividing grooves on the exposed substrate. Compared with other cutting or etching methods, plasma etching generates fewer impurities, further reducing the impurities generated throughout the entire cutting process. Finally, the substrate at the bottom of the dividing grooves is removed, completing the separation of the chip unit. Throughout the process, the combination of cutting and plasma etching effectively reduces the number of impurities, significantly improves the product yield of the final chip unit, and solves the problem of low yield caused by excessive cutting residue in the prior art.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0033] Figure 2 This is a flowchart of a semiconductor structure cutting method according to an embodiment of the present disclosure.

[0034] Figure 3 This is a schematic diagram of cutting a channel in one embodiment of the present disclosure.

[0035] Figure 4 This is a schematic diagram of a dividing groove in one embodiment of the present disclosure.

[0036] Figure 5 This is a schematic diagram of the filling layer in one embodiment of the present disclosure.

[0037] Figure 6 This is a schematic diagram of the mask layer in an embodiment of this disclosure.

[0038] Figure 7 This is a schematic diagram of the structure after removing the remaining substrate at the bottom of the dividing groove in an embodiment of this disclosure.

[0039] Figure 8 This is a schematic diagram of the adhesive layer in an embodiment of this disclosure.

[0040] Figure 9 This is a schematic diagram of the fixing part and the adhesive layer in an embodiment of this disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1. Substrate; 2. Device layer; 21. Chip unit; 211. Wiring layer; 2111. Conductive layer; 2112. Probe pad; 2113. Connector block; 212. Bonding section; 213. Redundant bonding section; 214. Through-silicon via; 22. Cleavage area; 221. Dielectric layer; 2211. First dielectric layer; 2212. Second dielectric layer; 2213. Third dielectric layer; 222. Conductive structure; 201. Cleavage channel; 202. Dividing groove; 3. Filler layer; 4. Mask layer; 41. Mask area; 5. Adhesive layer; 6. Fixing section; 7. Protective layer. Detailed Implementation

[0043] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0044] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0045] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0046] With the continuous advancement of semiconductor technology, especially in advanced packaging fields such as high-bandwidth memory and system-in-package (SoC), the requirements for dicing processes are becoming increasingly stringent. Traditional dicing methods generate more impurities during dicing, resulting in lower yields for individual chip units. Simultaneously, the retention of conductive structures (e.g., alignment marks or test pads) on the diced area directly affects the bonding alignment quality of the chip on the wafer, which is crucial for achieving precise bonding of chip units on the wafer.

[0047] Furthermore, as semiconductor manufacturing moves towards smaller sizes and higher densities, traditional methods struggle to effectively isolate and protect the conductive structures on the cut area during the cutting process. This can lead to damage to the surface of the cut chip unit, affecting its performance in subsequent packaging.

[0048] Based on this, embodiments of this disclosure provide a method for cutting a semiconductor structure, such as... Figure 1 As shown, the semiconductor structure may include a substrate 1 and a device layer 2 located on the substrate 1. The device layer 2 may include multiple chip cells 21 and a dicing region 22 located between two adjacent chip cells 21. Each chip cell 21 may include a wiring layer 211, which may include multiple conductive layers 2111 stacked along a direction perpendicular to the substrate and probe pads 2112 on the topmost conductive layer 2111. Adjacent conductive layers 2111 can be connected together by connecting blocks 2113. In this disclosure, the probe pads 2112 can be electrically led out through the bonding portion 212. In subsequent bonding processes, the bonding portion 212 can be bonded to other structures with conductive functions, thereby realizing signal transmission in the chip cell 21.

[0049] In some embodiments of this disclosure, the chip unit 21 may further include a redundant bonding portion 213, which may be distributed side-by-side with the bonding portion 212. During subsequent processing, the redundant bonding portion 213 can dissipate heat or balance structural stress. In this disclosure, the bottommost conductive layer 2111 can be connected to word lines, bit lines, or capacitors via through-silicon vias 214 (TSVs). The diced region 22 may include a dielectric layer 221 and a conductive structure 222. The dielectric layer 221 may be a single-layer film structure or a composite film structure composed of multiple film layers.

[0050] For example, the dielectric layer 221 may include a first dielectric layer 2211, a second dielectric layer 2212, and a third dielectric layer 2213 stacked from bottom to top along a direction perpendicular to the substrate 1, and the conductive structure 222 may be embedded in the first dielectric layer 2211. In some embodiments of this disclosure, the first dielectric layer 2211 and the second dielectric layer 2212 are made of different materials, and the first dielectric layer 2211 and the third dielectric layer 2213 are made of different materials. For example, the first dielectric layer 2211 and the third dielectric layer 2213 may be made of silicon oxide, and the second dielectric layer 2212 may be made of silicon nitride. The conductive structure 222 may be a wiring layer, a test pad, or an alignment mark disposed in the dicing area 22, etc., and the specific structure and type of the conductive structure 222 are not specifically limited herein.

[0051] In one exemplary embodiment of this disclosure, the thickness of the dielectric layer 221 is less than the thickness of the substrate 1. For example, the ratio of the thickness of the dielectric layer 221 to the thickness of the substrate 1 is 1:5 to 1:20. For example, the ratio of the thickness of the dielectric layer 221 to the thickness of the substrate 1 can be 1:5, 1:10, 1:15 or 1:20. Of course, the ratio of the thickness of the dielectric layer 221 to the thickness of the substrate 1 can also be other values, which are not specifically limited here.

[0052] In one exemplary embodiment of this disclosure, the number of device layers 2 can be one or more, for example, two, three, four, or five layers. It should be noted that when there are multiple device layers 2, they can be stacked and distributed along a direction perpendicular to the substrate 1, and adjacent device layers 2 are bonded to each other in this direction, with the cut regions 22 in different device layers 2 aligned. For example, adjacent device layers 2 can be bonded together by bump bonding, fusion bonding, or hybrid bonding, and no specific limitation is made here regarding the bonding method of each device layer 2.

[0053] like Figure 2 As shown, the cutting method of this disclosure may include steps S110-S130, wherein:

[0054] Step S110: The cutting area is cut to form a cutting channel; in a direction perpendicular to the surface of the substrate, the cutting channel penetrates the dielectric layer and the conductive structure, and exposes the substrate.

[0055] Step S120: Plasma etching is performed on a portion of the substrate located at the bottom of the cutting trench to form a segmentation groove;

[0056] Step S130: Remove the substrate located at the bottom of the sizing trench.

[0057] The semiconductor structure cutting method disclosed herein only laser-cuts the cutting area 22 in the device layer 2, without laser-cutting the substrate 1. This avoids the large-area ablation of the substrate 1 during laser cutting, which would generate a large amount of molten debris and particles. Compared to the traditional method of laser cutting the entire semiconductor structure, the cutting process of this disclosure generates relatively fewer impurities, thus effectively controlling the amount of impurities generated during the cutting stage. Simultaneously, this disclosure uses plasma etching to form a dividing groove on the exposed substrate 1. Compared to other cutting or etching methods, plasma etching generates fewer impurities, further reducing the impurities generated throughout the entire cutting process. Finally, the substrate 1 at the bottom of the dividing groove is removed, completing the separation of the chip unit 21. Throughout the process, the combination of cutting and plasma etching effectively reduces the number of impurities, significantly improving the yield of the final chip unit 21 and solving the problem of low yield due to excessive cutting residue in existing technologies.

[0058] The following provides a detailed description of each step and specific details of the semiconductor structure cutting method disclosed herein:

[0059] like Figure 2 As shown, in step S110, the cutting area 22 is cut to form a cutting channel 201; in a direction perpendicular to the surface of the substrate 1, the cutting channel 201 penetrates the dielectric layer 221 and the conductive structure 222, and exposes the substrate 1.

[0060] Laser cutting technology can be used to cut the cutting area 22. For example... Figure 3 As shown, a protective layer 7 can be formed on the semiconductor structure before cutting. The material of the protective layer 7 can be silicon oxide. The protective layer 7 can protect the surface of the semiconductor structure from damage. A laser cutting process can be used to cut the dielectric layer 221 and the conductive structure 222 located within the dielectric layer 221 simultaneously, thereby forming a cutting channel 201 that exposes the surface of the substrate 1. That is, the cutting channel 201 can penetrate the dielectric layer 221 and the conductive structure 222. It should be noted that, in order to ensure that the surface of the substrate 1 at the bottom of the cutting channel 201 can be fully exposed to facilitate subsequent etching of the substrate 1, a preliminary cut can be made on the surface of the substrate 1 during the laser cutting process. That is, the bottom of the cutting channel 201 can extend into the substrate 1. The depth of the cutting channel 201 is related to the thickness of the dielectric layer 221 and the conductive structure 222. For example, when the thickness of the dielectric layer 221 is 10 micrometers, the depth of the cutting channel 201 can be greater than or equal to 10 micrometers; for example, the depth of the cutting channel 201 can be 10 micrometers, 10.5 micrometers, 11 micrometers, 11.5 micrometers or 12 micrometers.

[0061] In one exemplary embodiment of this disclosure, the cutting area 22 may be annular or strip-shaped, and the corresponding cutting channel 201 may also be annular or strip-shaped. For example, when the chip unit 21 to be cut is located in the middle region of the device layer 2, the cutting channel 201 is annular and may surround the outer periphery of the chip unit 21; when the chip unit 21 to be cut is located in the edge region of the device layer 2, the cutting channel 201 may be strip-shaped and located on at least one side of the chip unit 21.

[0062] In one exemplary embodiment of this disclosure, the cutting channel 201 may be located in the central region of the cutting area 22, so that the remaining conductive structures 222 on both sides of the cutting channel 201 after cutting can be uniformly distributed on the outer periphery of different chip units 21. In some embodiments of this disclosure, the ratio of the width of the cutting channel 201 to the width of the cutting area 22 may be 1:1.5 to 1:4.5. For example, the ratio of the width of the cutting channel 201 to the width of the cutting area 22 may be 1:1.5, 1:2, 1:2.5, 1:3, 1:3.5, 1:4, or 1:4.5, etc. For example, the width of the cutting channel 201 may be 80 micrometers, and the width of the cutting area 22 may be 220 micrometers.

[0063] It should be noted that when there are multiple device layers 2, during the dicing process, the dielectric layer 221 and conductive structure 222 in the dicing area 22 of multiple device layers 2 can be diced until the surface of the substrate 1 is exposed (i.e., the dicing trench 201 can penetrate each dielectric layer 221 and each conductive structure 222 in each device layer 2). Furthermore, when there are multiple device layers 2, the depth of the formed dicing trench 201 is greater than the depth of the dicing trench 201 formed when there is only one device layer 2. At this time, the depth of the dicing trench 201 is approximately tens of micrometers, which is less than the depth of the dicing trench 201 formed when the entire chip unit 21 is diced using only laser dicing in the prior art. Compared to the prior art, the laser dicing in this disclosure produces fewer impurities or residues, and will not affect the yield of the final diced chip unit 21.

[0064] It should be noted that, in this embodiment of the present disclosure, since the thickness of the dielectric layer 221 and conductive structure 222 cut during the laser cutting process is small (for example, the total thickness of the dielectric layer 221 and conductive structure 222 is 10 μm), the particles and residues generated during the cutting process are relatively few, and will hardly affect the yield of the final cut chip unit 21.

[0065] like Figure 2 As shown, in step S120, a portion of the substrate 1 located at the bottom of the cutting channel 201 is subjected to plasma etching to form a dividing groove 202.

[0066] like Figure 4As shown, the depth of the dividing groove 202 can be 10 to 16 times the depth of the cutting channel 201. For example, the depth of the dividing groove 202 can be 10, 12, 14, 15, or 16 times the depth of the cutting channel 201. Of course, other ratios are also possible, which will not be listed here. In some embodiments of this disclosure, the depth of the cutting channel 201 can be 10 micrometers, and the depth of the dividing groove 202 can be 100 micrometers; or, the depth of the cutting channel 201 can be 10 micrometers, and the depth of the dividing groove 202 can be 120 micrometers; or, the depth of the cutting channel 201 can be 10 micrometers, and the depth of the dividing groove 202 can be 140 micrometers; or, the depth of the cutting channel 201 can be 10 micrometers, and the depth of the dividing groove 202 can be 150 micrometers; or, the depth of the cutting channel 201 can be 10 micrometers, and the depth of the dividing groove 202 can be 160 micrometers.

[0067] In this disclosure, the dividing groove 202 is mainly formed on the basis of the cutting channel 201 by plasma etching. Compared with other cutting or etching methods, plasma etching introduces fewer impurities, which can further reduce the impurities generated in the entire cutting process. This can significantly reduce the impurities in the final chip unit 21 and improve the yield of the chip unit 21.

[0068] In one exemplary embodiment of this disclosure, such as Figure 5 As shown, before performing plasma etching on a portion of the substrate 1 located at the bottom of the cutting channel 201, a filling layer 3 can also be formed in the cutting channel 201. The filling layer 3 is located on the substrate 1 and covers the surface of the exposed conductive structure 222 on the sidewall of the cutting channel 201.

[0069] In one exemplary embodiment of this disclosure, the material of the filling layer 3 may be an insulating material, for example, silicon oxide. The filling layer 3 may fill the dicing channel 201, and the surface of the filling layer 3 away from the substrate 1 is flush with the surface of the dielectric layer 221. The filling material may be deposited on the dielectric layer 221 having the dicing channel 201 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition until the dicing channel 201 is completely filled. Subsequently, the filling material on top of the dielectric layer 221 may be removed by chemical mechanical polishing or etching, and the filling material in the dicing channel 201 may be flush with the surface of the dielectric layer 221 (when a protective layer 7 is formed on the surface of the dielectric layer 221, the top surface of the filling layer 3 may be etched to be flush with the top surface of the protective layer 3). The remaining filling material in the dicing channel 201 may be used as the filling layer 3.

[0070] When a filling layer 3 is formed within the cutting channel 201, plasma etching of the portion of substrate 1 located at the bottom of the cutting channel 201 may include steps S210 and S220, wherein:

[0071] In step S210, a mask layer 4 is formed on the side of the dielectric layer 221 and the filling layer 3 away from the substrate 1. The mask layer 4 includes a mask region 41, and the orthogonal projection of the mask region 41 on the substrate 1 is located within the orthogonal projection of the filling layer 3 on the substrate 1.

[0072] For example, the material of mask layer 4 can be photoresist, such as... Figure 6 As shown, a mask layer 4 can be formed on the surface of the structure jointly formed by the dielectric layer 221 and the filler layer 3 by spin coating or other methods. The mask layer 4 can then be exposed and developed to form a mask area 41. The mask area 41 can expose the surface of the filler layer 3, and the width of the mask area 41 is smaller than the width of the filler layer 3; that is, the remaining mask layer 4 after development can cover the edge area of ​​the filler layer 3.

[0073] In some embodiments of this disclosure, the mask region 41 may be located in the central region of the cutting region 22 and may be symmetrically distributed along the centerline of the cutting region 22 in the width direction. In the width direction of the cutting region 22, the width of the mask region 41 may be smaller than the width of the cutting region 22; for example, in the width direction of the cutting region 22, the ratio of the width of the mask region 41 to the width of the cutting region 22 may be 1:2.5 to 1:4.

[0074] In step S220, the filling layer 3 and the substrate 1 located directly below the filling layer 3 are etched in the mask area 41 to form a segmentation groove 202.

[0075] Plasma etching can be performed on the fill layer 3 and the substrate 1 located directly below the fill layer 3 in the mask region 41 to form the segmentation groove 202. Please refer to [link to documentation]. Figure 4 As shown. During plasma etching, since the remaining mask layer 4 after development covers the edge area of ​​the fill layer 3, the edge area of ​​the fill layer 3 will not be etched away under the protection of the mask layer 4. That is, during the etching of the fill layer 3, the fill layer 3 on the sidewall of the cutting channel 201 will not be etched away. In the subsequent etching of the substrate 1, the fill layer 3 can protect the sidewall of the conductive structure 222 located in the dielectric layer 221, which can reduce the probability of the conductive structure 222 being damaged by etching and help to further improve the product yield.

[0076] It should be noted that when the mask area 41 is located in the central region of the cutting area 22, and the ratio of the width of the mask area 41 to the width of the cutting area 22 in the width direction of the cutting area 22 is 1:2.5 to 1:4, the etched dividing groove 202 is located in the central region of the cutting area 22, and the ratio of the width of the dividing groove 202 to the width of the cutting area 22 is 1:2.5 to 1:4. For example, in the width direction of the cutting area 22, the ratio of the width of the dividing groove 202 to the width of the cutting area 22 can be 1:2.5, 1:3, 1:3.5, or 1:4. In some embodiments of this disclosure, when the width of the cutting area 22 is 200 micrometers to 230 micrometers, the width of the cutting channel 201 can be 70 micrometers to 90 micrometers, and the width of the dividing groove 202 can be 50 micrometers to 70 micrometers.

[0077] It should be noted that when the material of the protective layer 7 is the same as that of the fill layer 3 (for example, both the protective layer 7 and the fill layer 3 are made of silicon oxide), the protective layer 7 located on top of the dielectric layer 221 may be removed simultaneously during the etching of the fill layer 3. In this disclosure, the mask layer 4 can be removed after the segmentation trench 202 is formed.

[0078] like Figure 2 As shown, in step S130, the substrate 1 located at the bottom of the dividing groove 202 is removed.

[0079] like Figure 7 As shown, after the dividing groove 202 is formed, the remaining substrate 1 at the bottom of the dividing groove 202 can be removed, thereby making each chip unit 21 completely divided. That is, after removing the substrate 1 at the bottom of the dividing groove 202, the cutting of the semiconductor structure can be considered to be completed.

[0080] In one exemplary embodiment of this disclosure, such as Figure 8 As shown, before removing the substrate 1 located at the bottom of the partition groove 202 (i.e., before performing step S130), an adhesive layer 5 can be formed on the surface of the dielectric layer 221 away from the substrate 1. The orthographic projection of the partition groove 202 on the substrate 1 is within the orthographic projection of the adhesive layer 5 on the substrate 1. The chip cells 21 on both sides of the partition groove 202 can be fixed together by the adhesive layer 5 to prevent the separated chip cells 21 from separating or shifting due to stress during subsequent processes. In the subsequent process of removing the substrate 1 at the bottom of the partition groove 202, the adhesive layer 5 can protect the surface of the chip cells 21 to prevent the chip cells 21 from directly contacting the equipment during subsequent processes (e.g., cleaning, transportation, polishing, or film application), which helps reduce the probability of the chip cells 21 being scratched or contaminated. At the same time, the adhesive layer 5 can also provide physical support to the entire array of chip cells 21 that has been partitioned by the partition groove 202 and whose structural strength has been reduced, which can reduce the risk of semiconductor structure breakage, warping, or deformation during subsequent processes (e.g., polishing to remove the substrate 1) or transportation.

[0081] In one exemplary embodiment of this disclosure, the adhesive layer 5 can cover the entire surface of the dielectric layer 221, that is, the adhesive layer 5 can cover each chip cell 21 and each cutting area 22 between each chip cell 21. The adhesive layer 5 can bridge across the dividing groove 202, thereby firmly bonding and fixing the chip cells 21 on both sides of the dividing groove 202 together, which can prevent the chip cells 21 from scattering or mixing after the substrate 1 at the bottom of the dividing groove 202 is removed.

[0082] In one exemplary embodiment of this disclosure, the adhesive layer 5 may be made of an adhesive material, such as an encapsulating tape. The adhesive layer 5 can be fixed to the surface of the dielectric layer 221 away from the substrate 1 by lamination.

[0083] In one exemplary embodiment of this disclosure, removing the substrate 1 located at the bottom of the sizing trench 202 (i.e., step S130) may include: grinding the substrate 1 until the remaining substrate 1 at the bottom of the sizing trench 202 is completely removed. For example, after forming the adhesive layer 5, the semiconductor structure including the adhesive layer 5 can be flipped so that the substrate 1 faces upward and the adhesive layer 5 faces downward. A chemical mechanical polishing process can be used to grind the substrate 1, and the grinding process can at least completely remove the substrate 1 located at the bottom of the sizing trench 202.

[0084] In some embodiments of this disclosure, after removing the substrate 1 located at the bottom of the dividing groove 202, the surface of the substrate 1 can be further polished to achieve the required thickness, thereby allowing precise control over the overall dimensions of the final package. For example, the thickness of the remaining substrate 1 after polishing can be 100 micrometers to 130 micrometers, such as 100 micrometers, 110 micrometers, 120 micrometers, or 130 micrometers. Simultaneously, after polishing, the total thickness of the remaining substrate 1 and the dielectric layer 221 can be 110 micrometers to 140 micrometers; for example, the total thickness of the remaining substrate 1 and the dielectric layer 221 after polishing can be 110 micrometers, 120 micrometers, 130 micrometers, or 140 micrometers.

[0085] In one exemplary embodiment of this disclosure, the semiconductor structure cutting method of this disclosure may further include steps S310-S330, wherein:

[0086] In step S310, a fixing portion 6 is formed on the side of the substrate 1 away from the dielectric layer 221. The substrate 1 is fixed on the fixing portion 6, and the orthographic projection of the dividing groove 202 on the substrate 1 falls within the orthographic projection of the fixing portion 6 on the substrate 1. Figure 9 As shown.

[0087] In one exemplary embodiment of this disclosure, the fixing part 6 may be a fixing frame. For example, it may be a metal frame or a plastic frame. After removing the substrate 1 located at the bottom of the slitting groove 202, the fixing part 6 may be formed on the side of the remaining substrate 1 away from the dielectric layer 221. In this process, the fixing part 6 may cover the surfaces of all substrates 1 separated by the slitting groove 202. For example, the surfaces of all the separated substrates 1 away from the dielectric layer 221 may be bonded to the fixing part 6 by adhesive tape. That is, the substrates 1 located on both sides of the slitting groove 202 can be fixed together by the fixing part 6. The setting of the fixing part 6 can provide physical support for subsequent process steps and ensure that the chip cell 21 will not shift, vibrate, or scatter after the adhesive layer 5 is removed. This can reduce the probability of chip cell 21 mixing or damage and facilitate subsequent chip cell 21 picking.

[0088] Step S320: Remove adhesive layer 5.

[0089] After the fixing part 6 is formed, the adhesive layer 5 can be removed. In some embodiments of this disclosure, the adhesive layer 5 can be a release layer, which can be directly peeled off from the surface of the dielectric layer 221. During the peeling process, the adhesive layer 5 can remove impurities or particles that adhere to the surface of the dielectric layer 221 during laser cutting. This can reduce the content of impurities finally attached to the chip unit 21, thereby improving the yield of the chip unit 21. In other embodiments of this disclosure, the adhesive layer 5 can be removed by chemical etching, laser peeling, or mechanical polishing. It should be noted that an appropriate removal method can be selected according to the material of the adhesive layer 5. The selection principle is: as long as the adhesive layer 5 can be removed without affecting the performance of other surrounding structures (e.g., chip unit 21, dielectric layer 221, and conductive structure 222, etc.), the removal method of the first adhesive layer 5 is not specifically limited here. For the structure after step S320 in this disclosure, please refer to Figure 7 As shown.

[0090] Step S330: Clean the surfaces of the dividing groove 202 and the medium layer 221.

[0091] After removing the adhesive layer 5, the surfaces of the dicing groove 202 and the dielectric layer 221 can be cleaned to remove any remaining fragments of the adhesive layer 5, abrasive particles, and impurities or particles generated during the cutting process. This further reduces residual impurities in the chip unit 21 and improves its yield. For example, a wet cleaning method can be used to clean the dicing groove 202, the dielectric layer 221, and the chip unit 21. For instance, deionized water rinsing, ultrasonic cleaning, plasma cleaning, or chemical cleaning with a specialized cleaning agent can be used to clean the chip unit 21, the dielectric layer 221, and the dicing groove 201. It should be noted that the cleaning process can be performed once or multiple times; no specific limitation is made here.

[0092] It should be noted that during the cleaning process, the fixing part 6 can support each chip unit 21, which can reduce the probability of each chip unit 21 collapsing due to the liquid tension in the cleaning agent, thus reducing the probability of chip mixing.

[0093] In one exemplary embodiment of this disclosure, before cleaning the surfaces of the dividing groove 202 and the dielectric layer 221 (i.e., before performing step S330), the surface of the dielectric layer 221 may also be chemically mechanically polished. Polishing removes impurities adhering to the surface of the dielectric layer 221 during laser cutting and precisely controls the thickness of the dielectric layer 221.

[0094] In one exemplary embodiment of this disclosure, after cleaning the dividing groove 202, the dielectric layer 221 and the chip unit 21, the fixing part 6 can be removed to obtain an independent chip unit 21.

[0095] It should be noted that although the steps of the semiconductor structure dicing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0096] This disclosure also provides a chip unit 21, which can be cut by the semiconductor structure cutting method in any of the above embodiments. Compared with the prior art, the beneficial effects of the chip unit 21 provided by this disclosure are the same as the beneficial effects of the semiconductor structure cutting method provided in the above example embodiments (e.g., the chip unit 21 has a high product yield), and will not be described in detail here.

[0097] The chip unit 21 disclosed herein may include a wiring layer 211, which may include a plurality of conductive layers 2111 stacked along a direction perpendicular to the substrate and probe pads 2112 on the topmost conductive layer 2111. Adjacent conductive layers 2111 may be connected together by connecting blocks 2113. In this disclosure, the probe pads 2112 can be electrically led out through the bonding portion 212. In subsequent bonding processes, the bonding portion 212 can be bonded to other structures with conductive functions, thereby realizing signal transmission in the chip unit 21.

[0098] In some embodiments of this disclosure, the chip unit 21 may further include a redundant bonding portion 213, which may be distributed side-by-side with the bonding portion 212. During subsequent processing, the redundant bonding portion 213 can be used to dissipate heat or balance structural stress. In this disclosure, the bottommost conductive layer 2111 can be connected to word lines, bit lines, or capacitors via a through-silicon via 214 (TSV).

[0099] The chip cell 21 disclosed herein has fewer residual impurities on its surface, resulting in a lower product yield. Tests have shown that the yield of the chip cell 21 disclosed herein is greater than 20%, which is significantly higher than the yield of existing technologies with yields below 5%. The chip cell 21 formed using the semiconductor structure dicing method of this disclosure exhibits a higher yield.

[0100] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for dicing a semiconductor structure, the semiconductor structure comprising a substrate and a device layer located on the substrate, the device layer comprising a plurality of chip cells and a dicing region located between two adjacent chip cells, the dicing region comprising a dielectric layer and a conductive structure, characterized in that, The cutting method includes: The cutting area is cut to form a cutting channel; in a direction perpendicular to the surface of the substrate, the cutting channel penetrates the dielectric layer and the conductive structure, and exposes the substrate; The portion of the substrate located at the bottom of the cutting channel is subjected to plasma etching to form a slit groove; Remove the substrate located at the bottom of the dividing groove.

2. The cutting method according to claim 1, characterized in that, Prior to plasma etching of the portion of the substrate located at the bottom of the cutting trench, the cutting method further includes: A filling layer is formed within the dicing channel, the filling layer being located on the substrate and covering the surface of the conductive structure exposed on the sidewall of the dicing channel; The plasma etching of the portion of the substrate located at the bottom of the cutting trench includes: A mask layer is formed on the side of the dielectric layer and the filler layer away from the substrate. The mask layer includes a mask region, and the orthographic projection of the mask region on the substrate lies within the orthographic projection of the filler layer on the substrate. The filler layer and the substrate located directly below the filler layer are etched in the mask area to form the dividing groove.

3. The cutting method according to claim 1, characterized in that, The cutting of the cutting area includes: The cutting area is cut using laser cutting technology.

4. The cutting method according to claim 1, characterized in that, Before removing the substrate located at the bottom of the slitting groove, the cutting method further includes: An adhesive layer is formed on the surface of the dielectric layer away from the substrate, and the orthographic projection of the dividing groove on the substrate is within the orthographic projection of the adhesive layer on the substrate.

5. The cutting method according to claim 4, characterized in that, The removal of the substrate located at the bottom of the dividing groove includes: The substrate is ground until the remaining substrate at the bottom of the dividing groove is removed.

6. The cutting method according to claim 5, characterized in that, The cutting method further includes: A fixing portion is formed on the side of the substrate away from the dielectric layer, the substrate is fixed on the fixing portion, and the orthographic projection of the dividing groove on the substrate is within the orthographic projection of the fixing portion on the substrate; Remove the adhesive layer; Clean the surfaces of the dividing groove and the medium layer.

7. The cutting method according to claim 6, characterized in that, Before cleaning the surfaces of the dividing groove and the medium layer, the cutting method further includes: The surface of the medium layer is ground.

8. The cutting method according to claim 1, characterized in that, The dividing groove is located in the central region of the cutting area, and the ratio of the width of the dividing groove to the width of the cutting area is 1:2.5 to 1:

4.

9. The cutting method according to any one of claims 1-8, characterized in that, The number of device layers is multiple, and the multiple device layers are bonded to each other along a direction perpendicular to the substrate, and the dicing regions in different device layers are aligned and distributed; the dicing channels penetrate each dielectric layer and each conductive structure in each device layer.

10. A chip unit, characterized in that, The chip unit is cut using the semiconductor structure cutting method described in any one of claims 1-9.

Images