Chip packaging structure and electronic equipment

Abstract

The invention relates to the technical field of chip packaging, and provides a chip packaging structure and electronic equipment. The chip packaging structure comprises a frame, a power chip and a plastic package body, the frame comprises a plurality of pins, each pin is provided with a first reference surface, a second reference surface and a welding surface, the welding surface is located between the first reference surface and the second reference surface, and the welding surface and the first reference surface form a step surface; the power chip is pasted on the second reference surface of the pin, and the power chip is connected with the welding surface through a bonding wire; the space formed by the power chip and the pins and the periphery of the power chip are filled with plastic packaging bodies. According to the invention, the power chip is pasted on the second reference surface of the base pin, and the power chip is connected with the welding surface of the base pin through the welding wire, so that the connection between the base pin and the power chip is realized, the length of the welding wire can be greatly shortened, the parasitism is reduced, and the stability and reliability of an electronic system are improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a chip packaging structure and electronic device. Background Technology

[0002] In the field of integrated circuit packaging technology, wire bonding is a widely used and relatively mature packaging method. It plays a crucial role in ensuring stable chip performance and achieving reliable connections between the chip and external circuits. Currently, common wire bonding structures include... Figure 1 As shown, a copper frame structure is adopted, in which a single base island 1 is set in the middle to support the chip. The back of the copper base island 1 exposes the plastic package, which serves as a heat dissipation channel to ensure that the heat generated by the chip 2 during operation can be effectively dissipated, avoiding the impact of excessive temperature on the performance and lifespan of the chip 2. At the same time, pins 3 are distributed on both sides of the copper frame. The chip is connected to these pins 3 by soldering copper wires 4, thereby realizing the electrical connection with external circuits.

[0003] The existing wire bonding packaging process generally involves mounting the chip on the front of the frame, then connecting the chip's surface pads to the frame pins using a wire bonding process, and finally encapsulating and protecting the entire structure with molding compound. However, because the chip's surface pads need to be connected to the frame pins via a relatively long wire bonding path, the electrical signals need to travel a long distance during transmission, leading to an increase in parasitic parameters (including parasitic resistance, parasitic capacitance, and parasitic inductance), which affects the stability and reliability of the electronic system. Summary of the Invention

[0004] This invention provides a chip packaging structure and electronic device to solve the problems of long transmission distance and large parasitics in the existing chip packaging structure, which affect the stability and reliability of the electronic system.

[0005] This invention provides a chip packaging structure, comprising: a frame including a plurality of pins, each pin having a first reference surface, a second reference surface, and a soldering surface, the soldering surface being located between the first reference surface and the second reference surface, the soldering surface forming a stepped surface with the first reference surface; a power chip, the power chip being attached to the second reference surface of the pins, the power chip being connected to the soldering surface via wire bonding; and a molding compound, the molding compound filling the space formed by the power chip and the pins and the outer periphery of the power chip.

[0006] According to a chip packaging structure provided by the present invention, the frame further includes a base island, a plurality of pins are disposed on the outer periphery of the base island, the base island is used to support the power chip, and the space enclosed by the base island, the power chip and the pins is filled with the molding compound.

[0007] According to a chip packaging structure provided by the present invention, a driver chip is further included. The driver chip is attached to the power chip. The driver chip and the pin are located on the same side of the power chip. The driver chip and the power chip are connected by the bonding wire. The space formed by the driver chip, the power chip and the pin is filled with the encapsulant.

[0008] According to a chip packaging structure provided by the present invention, the frame further includes a heat sink, a plurality of pins are disposed on the outer periphery of the heat sink, the heat sink and the pins are disposed on the same side of the power chip, and the space enclosed by the heat sink, the power chip and the heat sink is filled with the molding compound.

[0009] According to a chip packaging structure provided by the present invention, the heat sink includes heat-dissipating ceramic.

[0010] According to a chip packaging structure provided by the present invention, the power chip is attached to one side of the pin and a protective layer is provided. The protective layer is etched with a plurality of soldering positions, which are used to solder the bonding wire.

[0011] The present invention also provides an electronic device, including a chip packaging structure as described in any of the preceding claims, and a circuit board, wherein the first reference surface is connected to the circuit board.

[0012] An electronic device according to the present invention further includes a conductive element disposed between the circuit board and the first reference surface.

[0013] An electronic device according to the present invention further includes a heat sink, which is disposed on the side of the power chip away from the second reference surface, and the heat sink covers the power chip and the molding compound.

[0014] An electronic device according to the present invention further includes a heat-conducting component disposed between the power chip and the heat sink.

[0015] The chip packaging structure and electronic device provided by this invention connect the pin and the power chip by attaching a power chip to the second reference surface of the pin and connecting the power chip to the soldering surface of the pin via bonding wires. By filling the space between the power chip and the pin and the periphery of the power chip with a molding compound, the pin, power chip, and bonding wires are fixed together to form a single unit. Embodiments of this invention can significantly shorten the length of the bonding wires, reduce parasitics, and improve the stability and reliability of the electronic system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a chip packaging structure in the prior art.

[0018] Figure 2 This is a top view of the chip packaging structure of Embodiment 1 provided by the present invention.

[0019] Figure 3 This is a cross-sectional view of the chip packaging structure without the filling plastic encapsulation provided in Embodiment 1 of the present invention.

[0020] Figure 4 This is one of the cross-sectional views of the chip packaging structure provided in Embodiment 1 of the present invention.

[0021] Figure 5 This is the second cross-sectional view of the chip packaging structure provided in Embodiment 1 of the present invention.

[0022] Figure 6 This is a top view of the frame of Embodiment 1 provided by the present invention.

[0023] Figure 7 This invention provides Figure 6 Cross-sectional view of the middle frame.

[0024] Figure 8 This is a schematic diagram of attaching the power chip to the pin in Embodiment 1 of the present invention.

[0025] Figure 9 This is a top view of the chip packaging structure of Embodiment 2 provided by the present invention.

[0026] Figure 10 This is a cross-sectional view of the unfilled plastic encapsulation structure of the chip packaging structure provided in Embodiment 2 of the present invention.

[0027] Figure 11 This is one of the cross-sectional views of the chip packaging structure provided in Embodiment 2 of the present invention.

[0028] Figure 12 This is the second cross-sectional view of the chip packaging structure provided in Embodiment 2 of the present invention.

[0029] Figure 13 This is a top view of the chip packaging structure of Embodiment 3 provided by the present invention.

[0030] Figure 14This is a cross-sectional view of the unfilled plastic encapsulation structure of Embodiment 3 provided by the present invention.

[0031] Figure 15 This is one of the cross-sectional views of the chip packaging structure provided in Embodiment 3 of the present invention.

[0032] Figure 16 This is the second cross-sectional view of the chip packaging structure of Embodiment 3 provided by the present invention.

[0033] Figure 17 This is a top view of the chip packaging structure of Embodiment 4 provided by the present invention.

[0034] Figure 18 This is a cross-sectional view of the unfilled plastic encapsulation structure of Embodiment 4 provided by the present invention.

[0035] Figure 19 This is one of the cross-sectional views of the chip packaging structure in Embodiment 4 of the present invention.

[0036] Figure 20 This is the second cross-sectional view of the chip packaging structure of Embodiment 4 provided by the present invention.

[0037] Figure 21 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0038] Figure label: 10. Pin; 11. First reference plane; 12. Second reference plane; 13. Welding surface; 20. Power chip; 21. Protective layer; 22. Soldering position; 30. Molded enclosure; 40. Wire bonding; 50. Adhesive component; 60. Base island; 70. Driver chip; 80. Heat sink; 90. Circuit board; 100. Conductive component; 110. Heat sink; 120. Thermally conductive component. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0040] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0041] In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0044] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. Additionally, examples of various specific processes and materials are provided in this invention; however, those skilled in the art will recognize the applicability of other processes and / or the use of other materials.

[0045] The following is combined Figures 2-21 This invention describes the chip packaging structure and electronic device.

[0046] The chip packaging structure provided in this embodiment of the invention includes a frame, a power chip 20, and a molding compound 30. The frame includes multiple pins 10, each pin 10 having a first reference surface 11, a second reference surface 12, and a soldering surface 13. The soldering surface 13 is located between the first reference surface 11 and the second reference surface 12, and forms a stepped surface with the first reference surface 11. The power chip 20 is attached to the second reference surface 12 of the pin 10, and the power chip 20 is connected to the soldering surface 13 via bonding wires 40. The space formed by the power chip 20 and the pins 10, as well as the outer periphery of the power chip 20, is filled with the molding compound 30.

[0047] The frame of this invention can be fabricated using etching and stamping processes. For example... Figure 6 and Figure 7 As shown, the frame includes multiple pins 10, each pin 10 having a first reference surface 11, a second reference surface 12, and a soldering surface 13, with a stepped surface formed between the first reference surface 11 and the soldering surface 13. The power chip 20 can be attached to the second reference surface 12 via an adhesive attachment 50. In actual operation, as... Figure 8 As shown, pin 10 can be reversed to facilitate the mounting of power chip 20. The mounting component 50 is an insulating component and can be DAF (Dielectric Aerated Fiber). DAF is a chip mounting film with high thermal conductivity, low stress, and insulating properties. It can be cured and bonded by heating and pressurizing. The mounting component 50 can also be other non-conductive mounting components. After mounting, reverse pin 10 and power chip 20, as shown... Figure 3 As shown, the power chip 20 is connected to the soldering surface 13 of the pin 10 via a bonding wire 40, thereby achieving the connection between the pin 10 and the power chip 20, significantly shortening the length of the bonding wire 40 and reducing parasitics. Furthermore, the soldered power chip 20, bonding wire 40, and pin 10 are encapsulated, thus forming a single unit. Figure 4 As shown, the power chip 20 is surrounded by a molding compound 30, and the space formed by the power chip 20 and the pin 10 is also filled with the molding compound 30. It should be noted that after molding with the molding compound 30, the effective area can be cut according to the actual situation.

[0048] The embodiments of this invention are not only applicable to DFN (Dual Flat No-lead), a common semiconductor package type, which belongs to leadless flat packages, such as... Figure 2 and Figure 4 As shown. This embodiment of the invention is also applicable to leaded packages, such as... Figure 5 As shown.

[0049] The chip packaging structure provided in this embodiment of the invention connects the pin 10 and the power chip 20 by attaching the power chip 20 to the second reference surface 12 of the pin 10 and connecting the power chip 20 to the soldering surface 13 of the pin 10 via bonding wires 40. By filling the space between the power chip 20 and the pin 10 and the periphery of the power chip 20 with a molding compound 30, the pin 10, the power chip 20, and the bonding wires 40 are fixed together to form a single unit. This embodiment of the invention can significantly shorten the length of the bonding wires 40, reduce parasitics, and improve the stability and reliability of the electronic system.

[0050] In some embodiments of the present invention, the frame further includes a base island 60, with a plurality of pins 10 disposed on the outer periphery of the base island 60. The base island 60 is used to support the power chip 20, and the space enclosed by the base island 60, the power chip 20, and the pins 10 is filled with a plastic encapsulation 30.

[0051] The frame includes a base island 60 and multiple pins 10, with the pins 10 located on the outer periphery of the base island 60. It should be noted that the thickness of the base island 60 is the same as the thickness of the pins 10. In the actual packaging process, the pins 10 and the base island 60 can be reversed to facilitate the attachment of the power chip 20. The power chip 20 can be attached to the second reference surface 12 and the base island 60 via the adhesive component 50. The base island 60 can support the power chip 20, improving its stability. The adhesive component 50 is an insulating component and can be DAF (die-mount film). DAF has high thermal conductivity, low stress, and insulating properties, and can be cured and bonded by heating and pressurizing. The adhesive component 50 can also be other non-conductive adhesive components. After attachment, the power chip 20, pins 10, and base island 60 can be reversed, such as... Figure 10 As shown, the power chip 20 is connected to the pin 10 via bonding wire 40, thereby achieving the connection between pin 10 and power chip 20. This significantly shortens the length of bonding wire 40 and reduces parasitics. Furthermore, the soldered power chip 20, pin 10, bonding wire 40, and base island 60 are encapsulated, thus forming a single unit. Figure 11 As shown, the power chip 20 is surrounded by a molding compound 30, and the space formed by the power chip 20, the base island 60, and the pins 10 is also filled with the molding compound 30. It should be noted that after molding with the molding compound 30, the effective area can be cut according to actual needs. Furthermore, the heat from the power chip 20 can also be transferred to the outside through the base island 60, achieving heat dissipation. In one embodiment, the side of the base island 60 furthest from the power chip 20 is at least partially exposed to the outside of the molding compound 30, resulting in good heat dissipation.

[0052] The embodiments of this invention are not only applicable to DFN (Dual Flat No-lead), a common semiconductor package type, which belongs to leadless flat packages, such as... Figure 9 and Figure 11 As shown. This embodiment of the invention is also applicable to leaded packages, such as... Figure 12 As shown.

[0053] In some embodiments of the present invention, the chip packaging structure further includes a driver chip 70, which is attached to the power chip 20. The driver chip 70 and the pin 10 are located on the same side of the power chip 20. The driver chip 70 and the power chip 20 are connected by a bonding wire 40. The space formed by the driver chip 70, the power chip 20 and the pin 10 is filled with the plastic encapsulation body 30.

[0054] like Figure 13 As shown, the driver chip 70 and power chip 20 are stacked, and the driver chip 70 can be attached to the power chip 20 using the adhesive piece 50. In actual operation, pin 10 can be flipped to facilitate attaching the side of the power chip 20 with the driver chip 70 to the second reference surface 12 of pin 10. After attachment, pin 10, power chip 20, and driver chip 70 are reversed, as shown... Figure 14 As shown, the power chip 20 near the pin is connected to the soldering surface 13 of the pin 10 via bonding wire 40, thereby achieving the connection between the pin 10 and the power chip 20, greatly shortening the length of bonding wire 40 and reducing parasitics. It should be noted that the power chip 20 and the driver chip 70 also need to be connected via bonding wire 40, which can be completed before or after the power chip 20 is pasted onto the second reference surface 12 of the pin 10. Furthermore, the soldered power chip 20, driver chip 70, bonding wire 40, and pin 10 are encapsulated, thereby forming a single unit. Figure 15 As shown, the power chip 20 is surrounded by a molding compound 30, and the space formed by the power chip 20, the driver chip 70, and the pin 10 is also filled with a molding compound 30. It should be noted that after molding with the molding compound 30, the effective area can be cut according to the actual situation.

[0055] The embodiments of this invention are not only applicable to DFN (Dual Flat No-lead), a common semiconductor package type, which belongs to leadless flat packages, such as... Figure 13 and Figure 15 As shown. This embodiment of the invention is also applicable to leaded packages, such as... Figure 16 As shown.

[0056] In some embodiments of the present invention, the frame further includes a heat sink 80, a plurality of pins 10 are disposed on the outer periphery of the heat sink 80, the heat sink 80 and the pins 10 are disposed on the same side of the power chip 20, and the space enclosed by the heat sink 80, the power chip 20 and the heat sink 80 is filled with the encapsulated body 30.

[0057] like Figure 17 As shown, the frame includes pins 10 and a heatsink 80, which dissipates heat from the power chip 20. In the actual packaging process, pins 10 and the heatsink 80 can be reversed to facilitate the bonding of the power chip 20 to the second reference surface 12 of pins 10. Contact between the power chip 20 and the heatsink 80 helps dissipate heat from the power chip 20. After bonding, pins 10, the heatsink 80, and pins 10 are flipped over, as shown... Figure 18 As shown, the power chip 20 near the pin is connected to the soldering surface 13 of the pin 10 via bonding wire 40, thereby achieving the connection between the pin 10 and the power chip 20, significantly shortening the length of bonding wire 40 and reducing parasitics. Furthermore, the soldered power chip 20, bonding wire 40, pin 10, and heat sink 80 are encapsulated, thus forming a single unit. Figure 19 As shown, the power chip 20 is surrounded by a molding compound 30, and the space formed by the power chip 20, pin 10, and heat sink 80 is also filled with molding compound 30. It should be noted that after molding with the molding compound 30, the effective area can be cut according to the actual situation.

[0058] It should be noted that the thickness of the heat sink 80 can be adjusted according to actual needs. In one embodiment, the side of the heat sink 80 away from the power chip 20 is flush with the molding compound 30, and the heat from the power chip 20 can be transferred to the outside through the heat sink 80, resulting in good heat dissipation.

[0059] The embodiments of this invention are not only applicable to DFN (Dual Flat No-lead), a common semiconductor package type, which belongs to leadless flat packages, such as... Figure 17 and Figure 19 As shown. This embodiment of the invention is also applicable to leaded packages, such as... Figure 20 As shown.

[0060] The heat sink 80 in this embodiment of the invention includes heat-dissipating ceramic.

[0061] In some embodiments of the present invention, a protective layer 21 is provided on one side of the power chip 20 attached to the pin 10 to protect the power chip 20. The protective layer 21 may have multiple soldering positions 22, such as... Figure 3 As shown, soldering is used to solder the bonding wire 40 to connect the power chip 20 to the pin 10, and to connect the power chip 20 to the driver chip 70. The number of soldering positions 22 in this embodiment is not specifically limited and can be set according to actual needs. In one embodiment, the soldering positions 22 are located on the protective layer 21 near the pin 10, which can shorten the length of the bonding wire between the power chip 20 and the pin 10 and reduce parasitic defects.

[0062] In this embodiment of the invention, the bonding wire 40 can be a copper bonding wire 40.

[0063] This invention also provides an electronic device, including the chip packaging structure as described in any of the above embodiments.

[0064] The electronic device provided in this embodiment of the invention also includes a circuit board 90 (PCB), which is located on the side of the pin 10 away from the power chip 20, and the circuit board 90 is connected to the first reference surface 11 of the pin 10.

[0065] In some embodiments of the present invention, the electronic device further includes a conductive element 100, which is disposed between the first reference surface 11 and the circuit board 90 to enhance conductivity and improve the stability of electronic device transmission.

[0066] In some embodiments of the present invention, such as Figure 21 As shown, the electronic device also includes a heat sink 110, which is located on the side of the power chip 20 away from the second reference surface 12. The heat sink 110 covers the power chip 20 and the molding compound 30, and can dissipate heat from the chip package structure.

[0067] In some embodiments of the present invention, the electronic device further includes a heat-conducting element 120 disposed between the power chip 20 and the heat sink 110, which can accelerate the heat dissipation of the chip package structure and enhance the heat dissipation effect of the chip package structure. In one embodiment, the heat-conducting element 120 covers the power chip 20 and the plastic encapsulation 30 located on the outer periphery of the power chip 20. The heat sink 80 may be a filling medium.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: The frame includes multiple pins, each pin having a first reference surface, a second reference surface, and a welding surface, the welding surface being located between the first reference surface and the second reference surface, and the welding surface forming a stepped surface with the first reference surface; A power chip is attached to the second reference surface of the pin, and the power chip is connected to the bonding surface by a bonding wire; The encapsulation is filled within the space formed by the power chip and the pins, as well as around the outer periphery of the power chip.

2. The chip packaging structure according to claim 1, characterized in that, The frame also includes a base island, with a plurality of pins disposed on the outer periphery of the base island. The base island is used to support the power chip, and the space enclosed by the base island, the power chip, and the pins is filled with the encapsulation.

3. The chip packaging structure according to claim 1, characterized in that, It also includes a driver chip, which is attached to the power chip. The driver chip and the pin are located on the same side of the power chip. The driver chip and the power chip are connected by the bonding wire. The space formed by the driver chip, the power chip and the pin is filled with the encapsulation.

4. The chip packaging structure according to claim 1, characterized in that, The frame also includes a heat sink, with a plurality of pins disposed on the outer periphery of the heat sink. The heat sink and the pins are disposed on the same side of the power chip. The space enclosed by the heat sink, the power chip, and the heat sink is filled with the encapsulation.

5. The chip packaging structure according to claim 4, characterized in that, The heat sink includes heat-dissipating ceramic.

6. The chip packaging structure according to claim 1, characterized in that, The power chip is attached to one side of the pin and has a protective layer. The protective layer is etched with multiple soldering positions, which are used to solder the bonding wire.

7. An electronic device, characterized in that, The device includes the chip packaging structure as described in any one of claims 1 to 6, and further includes a circuit board, wherein the first reference surface is connected to the circuit board.

8. The electronic device according to claim 7, characterized in that, It also includes a conductive element disposed between the circuit board and the first reference surface.

9. The electronic device according to claim 7, characterized in that, It also includes a heat sink, which is located on the side of the power chip away from the second reference surface, and the heat sink covers the power chip and the molding compound.

10. The electronic device according to claim 9, characterized in that, It also includes a heat-conducting component, which is disposed between the power chip and the heat sink.

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