Chip packaging structure and packaging method

Abstract

The invention discloses a chip packaging structure and a packaging method, the chip packaging structure comprises a substrate, a chip and a circuit layer which are respectively arranged on two sides of the substrate along the thickness direction, a first metal convex block and a first filling layer, the first metal convex block is electrically connected with the chip, the substrate comprises a through hole, and the through hole is communicated with the circuit layer. The first metal bumps penetrate through the through holes and are electrically connected with the circuit layer, and the filling layer is at least filled between the first metal bumps and the through holes, so that accurate positioning between the chip and the substrate is facilitated, and the binding force between the chip and the substrate is enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and testing, and more particularly to a chip packaging structure and packaging method. Background Technology

[0002] In existing technologies, chip packaging structures include chips, substrates, and metal bumps. The chips are electrically connected to the substrate via the metal bumps. Misalignment and positioning errors can occur between individual chips and the substrate during subsequent packaging processes. When a chip packaging structure involves multiple chips electrically connected to the substrate, it is necessary to control the relative positions of the multiple chips to the substrate to ensure accurate positioning and electrical connection of the chips via the metal bumps and substrate. Summary of the Invention

[0003] One of the objectives of this invention is to provide a chip packaging structure to solve the technical problem of relative positional misalignment between the chip and the substrate during the packaging process in the prior art.

[0004] One of the objectives of this invention is to provide a chip packaging method.

[0005] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging structure, including a substrate, a chip and a circuit layer respectively located on both sides of the substrate along its thickness direction, a first metal bump, and a first fill layer. The first metal bump is electrically connected to the chip. The substrate includes a through hole. The first metal bump passes through the through hole and is electrically connected to the circuit layer. The fill layer at least fills the space between the first metal bump and the through hole.

[0006] As a further improvement of one embodiment of the present invention, the filling layer extends between the substrate and the circuit layer.

[0007] As a further improvement of one embodiment of the present invention, the filling layer exposes the first metal bump.

[0008] As a further improvement of one embodiment of the present invention, the circuit layer is formed on the surface of the filler layer and the surface of the first metal bump.

[0009] As a further improvement of one embodiment of the present invention, the chip includes chip pads formed on its surface, and the first metal bump is formed on the chip pads.

[0010] As a further improvement of one embodiment of the present invention, the chip includes a dielectric film formed on its surface, the dielectric film exposing the chip pads.

[0011] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a bonding layer for bonding the chip and the substrate.

[0012] As a further improvement of one embodiment of the present invention, the chip includes a first chip and a second chip arranged in a horizontal direction, the first chip and the second chip being connected to the same substrate.

[0013] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging method, comprising the following steps: A chip is provided, and a first metal bump is formed on the chip pads of the chip; A substrate is provided, and through-holes are formed on the substrate; The chip and the substrate are connected, with the first metal bump located inside the through-hole; A filler layer is formed, which at least fills the space between the first metal bump and the through hole; A circuit layer is formed on the side of the substrate opposite to the chip, and the first metal bump passes through the via and is electrically connected to the circuit layer.

[0014] As a further improvement of one embodiment of the present invention, the fabrication of the first metal bump on the chip pad includes: fabricating a dielectric film on the surface of the chip where the chip pad is disposed, the dielectric film exposing the chip pad.

[0015] As a further improvement to one embodiment of the present invention, the fabrication of the first metal bump on the chip pad includes: A photoresist layer is fabricated on the dielectric film; The photoresist layer is patterned to form openings that expose the chip pads; A first metal bump is made in the opening; Remove the photoresist layer. As a further improvement of one embodiment of the present invention, a substrate is provided, wherein forming a through-hole on the substrate includes: forming a bonding layer on one side of the substrate, wherein the through-hole penetrates the substrate and the bonding layer.

[0016] As a further improvement of one embodiment of the present invention, before fabricating through-holes in the substrate, a carrier plate is provided, wherein the carrier plate and the substrate are bonded together by a release layer, the bonding layer being located on the side of the substrate opposite to the carrier plate. As a further improvement of one embodiment of the present invention, connecting the chip and the substrate includes: bonding the chip and the substrate through the bonding layer, wherein the first metal bump protrudes to the release layer.

[0017] As a further improvement to one embodiment of the present invention, the step includes: removing the peeling layer and the carrier plate. As a further improvement of one embodiment of the present invention, the fabrication of the filling layer includes: filling the side of the substrate away from the chip with a molding compound, wherein the molding compound enters from the surface of the substrate between the first metal bump and the through hole.

[0018] As a further improvement of one embodiment of the present invention, the fabrication of the filler layer includes: grinding the molding material to expose the first metal bump. As a further improvement of one embodiment of the present invention, the fabrication of a circuit layer on the side of the substrate opposite to the chip includes: A metal interconnect layer is fabricated, the metal interconnect layer being connected to the first metal bump; A dielectric layer is fabricated, which covers the metal interconnect layer.

[0019] As a further improvement to one embodiment of the present invention, the method includes the step of: forming a second metal bump on the side of the circuit layer away from the chip, wherein the second metal bump is electrically connected to the circuit layer. As a further improvement to one embodiment of the present invention, the method includes the steps of: providing a first chip and a second chip, wherein the first chip and the second chip are electrically connected to the same side of the same substrate via a first metal bump.

[0020] Compared with the prior art, the present invention provides a chip packaging structure in which the first metal bump passes through the through hole and is electrically connected to the circuit layer. The first metal bump and the through hole have accurate positioning function, which is beneficial to the accurate positioning between the chip and the substrate and prevents relative displacement. The filling layer fills at least between the first metal bump and the through hole, further strengthening the bonding force between the first metal bump and the through hole, thereby strengthening the bonding force between the chip and the substrate. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a chip packaging method according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the chip packaging structure in the first embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram illustrating the steps of providing a chip in the first embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the steps for providing a substrate in the first embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of the steps for connecting the chip and the substrate in the first embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram of the steps for making the filling layer in the first embodiment of the present invention.

[0027] Figure 7 This is a schematic diagram of the fabrication of the circuit layer and the second metal bump in the first embodiment of the present invention.

[0028] Figure 8-10 This is a schematic diagram illustrating the specific steps involved in fabricating the circuit layer in the first embodiment of the present invention.

[0029] Figure 11 This is a schematic diagram of the chip packaging structure in the second embodiment of the present invention.

[0030] Figure 12 This is a schematic diagram illustrating the steps of providing a chip in the second embodiment of the present invention.

[0031] Figure 13 This is a schematic diagram of the steps for providing a substrate in the second embodiment of the present invention.

[0032] Figure 14 This is a schematic diagram of the steps for connecting the chip and the substrate in the second embodiment of the present invention.

[0033] Figure 15 This is a schematic diagram of the steps for making the filling layer in the second embodiment of the present invention.

[0034] Figure 16 This is a schematic diagram of the fabrication of the circuit layer and the second metal bump in the second embodiment of the present invention.

[0035] Figure 17-20 This is a schematic diagram illustrating the specific steps involved in fabricating the circuit layer in the second embodiment of the present invention. Detailed Implementation

[0036] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0037] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0039] Please see Figure 2 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present invention. The chip packaging structure 100 includes a substrate 10, a chip 20 and a circuit layer 30 respectively located on both sides of the substrate 10 along its thickness direction, and a first metal bump 40. The first metal bump 40 is electrically connected to the chip 20. The substrate 10 includes a through hole 11, and the first metal bump 40 passes through the through hole 11 and is electrically connected to the circuit layer 30.

[0040] Thus, the first metal bump 40 and the through hole 11 are pre-positioned and matched, which can avoid the relative positional offset between the chip 20 and the substrate 10 during the subsequent packaging process; the chip 20 and the circuit layer 30 are located on opposite sides of the substrate 10, and the chip 20 is electrically connected to the circuit layer 30 through the first metal bump 40 to connect the chip 20 to the external circuit.

[0041] The chip 20 includes chip pads 21 formed on its surface, and the first metal bump 40 is formed on the chip pads 21. Specifically, the chip 20 includes a functional surface 23, the chip pads 21 are formed on the functional surface 23, and the first metal bump 40 is electrically connected to the chip pads 21, thereby electrically connecting to the chip 20.

[0042] In one embodiment, the first metal bump 40 may be a copper pillar.

[0043] In one embodiment, due to the special packaging process of this application, the first metal bump 40 includes a narrow bump 41 and a wide bump 42. The diameter of the narrow bump 41 should be equal to the opening diameter of the dielectric film 22, and the diameter of the wide bump 42 is larger than the diameter of the narrow bump 41. The narrow bump 41 is located inside the opening of the dielectric film 22 and is used to contact the chip pad 21. The wide bump 42 covers the dielectric film 22 extending to the surface of the chip pad 21 and is used to pass through the via 11 and electrically connect to the circuit layer 30.

[0044] The chip 20 includes a dielectric film 22 formed on its surface, which exposes the chip pads 21. Only the chip pads 21 exposed to the dielectric film 22 can be further electrically connected to the first metal bump 40. In a specific embodiment, the dielectric film 22 extends to the edge surface of the chip pads 21, and the edge of the first metal bump 40 covers the dielectric film 22 to completely cover the exposed portion of the chip pads 21, preventing other structures from contacting the chip pads 21 and affecting the electrical connection function between the first metal bump 40 and the chip pads 21.

[0045] The dielectric film 22 is formed on the functional surface 23, which is equivalent to the insulating layer between the functional surface 23 of the chip 20 and the substrate 10. The dielectric film 22 is usually made of insulating materials, such as silicon dioxide or silicon nitride. These materials have high insulation resistance and breakdown voltage, and have good isolation and insulation effects.

[0046] The wiring layer 30 includes multiple wiring layers, each of which includes a metal layer 31 and a dielectric layer 32. The metal layer 31 may be a copper wire layer. Metal interconnection is achieved between the multiple metal layers 31, and the multiple dielectric layers 32 enclose the metal layers 31. A first metal bump 40 passes through the via 11 and is electrically connected to the metal layers 31 to achieve metal interconnection.

[0047] The dielectric layer 32 between the circuit layers 30 is usually made of insulating material, such as silicon dioxide or silicon nitride, with high insulation resistance and breakdown voltage. It can effectively isolate adjacent metal layers 31 and prevent electrical signal interference and short circuits between them.

[0048] The chip packaging structure 100 includes a bonding layer 50 for bonding the chip 20 and the substrate 10. Specifically, the bonding layer 50 bonds the dielectric film 22 on the surface of the chip 20 and the surface of the substrate 10, and the bonding layer 50 may be a bonding adhesive.

[0049] The chip packaging structure 100 includes a filling layer 60, which fills at least between the first metal bump 40 and the through hole 11 to strengthen the bonding force between the first metal bump 40 and the through hole 11.

[0050] The filler layer 60 fills the surface of the dielectric film 22 without contacting the first pad 21, and does not affect the electrical contact between the first pad 21 and the first metal bump 40.

[0051] The substrate 10 includes a first side and a second side opposite to each other. The chip 20 and the bonding layer 60 are formed on the first side, and the circuit layer 30 is formed on the second side. A first metal bump 40 extends from the first side to the second side to connect the metal layer 31 of the circuit layer 30.

[0052] The filler layer 60 extends between the substrate 10 and the circuit layer 30, serving as an insulating layer. The filler layer 60 includes an integrally formed annular portion 61 and a horizontal portion 62. The annular portion 61 fills the annular gap between the first metal bump 40 and the through-hole 11, not only strengthening the bond but also mitigating thermal stress between the first metal bump 40 and the through-hole 11. One end of the annular portion 61, away from the horizontal portion 62, connects to the surface of the dielectric film 22 without connecting to the first pad 21, thus not affecting the electrical connection function. The horizontal portion 62 is formed on the second side of the substrate, isolating the substrate 10 and the circuit layer 30, preventing dielectric transfer between them and mitigating thermal stress.

[0053] The filler layer 60 exposes the first metal bump 40, and the exposed surface of the first metal bump 40 is used to achieve an electrical connection with the metal layer 31.

[0054] The circuit layer 30 is formed on the surface of the filler layer 60 and the surface of the first metal bump 40. The circuit layer 30 is formed on the surface of the horizontal portion 61, and the surface of the first metal bump 40 is at least partially connected to the metal layer 31.

[0055] The chip package structure 100 includes a second metal bump 70 formed on the side of the circuit layer 30 opposite to the substrate 10, the second metal bump 70 being electrically connected to the circuit board. The second metal bump 70 may be a solder ball.

[0056] The wiring layer 30 includes at least a first wiring layer 301 and a second wiring layer 302 formed by stacking. The first wiring layer 301 connects the first metal bump 40 and the horizontal portion 62. The metal layer 32 of the second wiring layer 302 connects the second metal bump 70.

[0057] The chip packaging structure 100 includes a molding layer 80 formed on the first side of the substrate 10 and the outer periphery of the chip 20 for protecting the chip 20.

[0058] The chip packaging structure 100 includes a plastic backplate 90 formed on the surface of the plastic encapsulation layer 80 away from the chip, which can be formed as a heat dissipation backplate.

[0059] Combination Figure 2 As shown, in the first embodiment of this application, the chip packaging structure 100 includes a single chip 20, which is connected to the circuit board through a first metal bump 40 and a circuit layer 30.

[0060] Combination Figure 11As shown, in the second embodiment of this application, the difference from the first embodiment is that the chip 20 includes a first chip 201 and a second chip 202 arranged in a horizontal direction. The first chip 201 and the second chip 202 are connected to the same substrate 10, so as to realize the simultaneous packaging of multiple chips.

[0061] In one embodiment, the first chip 201 and the second chip 202 may be different chips; the first chip 201 may be a logic operation chip, and the second chip 202 may be a memory chip. In other embodiments, the first chip 201 and the second chip 202 may be the same chip.

[0062] A first chip 201 and a second chip 202 are simultaneously disposed on a first side of a substrate 10. The first chip 201 includes a functional surface 23, chip pads 21 formed on the functional surface 23, and a dielectric film 22. The second chip 202 includes a functional surface 23, chip pads 21 formed on the functional surface 23, and a dielectric film 22.

[0063] The first metal bump 40 is formed on the chip pad 21 of the first chip 201 and the chip pad 21 of the second chip 202. When the first chip 201 and the second chip 202 are simultaneously connected to the first side of the same substrate 10, the first metal bump 40 extends through the through hole 11 to the second side of the substrate 10. This is beneficial for the planar control of each functional surface 23 being on the same horizontal plane during multi-chip packaging, and is beneficial for the alignment and cooperation between each chip 20 and the substrate 10 during multi-chip packaging, saving alignment time, reducing alignment correction, and improving packaging efficiency.

[0064] This application provides a chip packaging method for fabricating a chip packaging structure 100, combined with... Figure 1 As shown, it includes the following steps: S1: Provide chip 20, and fabricate first metal bumps 40 on chip pads 21 of chip 20; combine Figure 3 As shown, the first metal bump 40 can be a copper pillar, which is made by electroplating.

[0065] Combination Figure 3 As shown, in the first embodiment of this application, the chip 20 includes providing a single chip formed by cutting, fabricating a first metal bump 40 on the single chip 20, and then bonding it to the substrate 10 to form a chip-level package.

[0066] In the second embodiment of this application, the chip 20 includes providing a first chip 201 and a second chip 202, and first metal bumps 40 are formed on the chip pads 21 of the first chip 201 and the chip pads 21 of the second chip 202, respectively. The first chip 201 and the second chip 202 are electrically connected to the same side of the same substrate 10 through the first metal bumps 40.

[0067] Combination Figure 11 As shown, multiple chips are provided, each chip 20 can be selected as a different type of chip, and a first metal bump 40 is made on each chip 20.

[0068] In other embodiments, the chip 20 may be a wafer integrated with a plurality of chips 20, and a first metal bump 40 may be formed on the wafer. The substrate 10 may be a wafer-level substrate 10, and through holes 11 may be formed on the wafer-level substrate 10. After the wafer integrated with the chips 20 and the wafer-level substrate 10 are connected, a wafer-level packaging structure is realized. After the wafer-level packaging structure is formed, it is then cut into a single chip packaging structure.

[0069] Fabricating the first metal bump 40 on the chip pad 21 includes: fabricating a dielectric film 22 on the surface of the chip pad 21 on the chip 20, the dielectric film 22 exposing the chip pad 21 to facilitate the fabrication of the first metal bump 40. The fabricated dielectric film 22 extends to the edge surface of the chip pad 21, and the opening of the dielectric film 22 exposes a portion of the chip pad 21.

[0070] The process of fabricating the first metal bump 40 on the chip pad 21 includes: fabricating a photoresist layer on the dielectric film 22, patterning the photoresist layer to form an opening that exposes the chip pad 21, fabricating the first metal bump 40 in the opening, and removing the photoresist layer to obtain the first metal bump 40 protruding from the surface of the dielectric film 22.

[0071] Specifically, since the dielectric film 22 extends to the edge surface of the chip pad 21, the diameter of the opening formed by the dielectric film 22 for exposing the chip pad 21 is smaller than the diameter of the chip pad 21. The opening diameter of the photoresist layer is equal to the diameter of the chip pad 21. Therefore, the dielectric film 22 extending to the edge surface of the chip pad 21 is also exposed within the opening of the photoresist layer.

[0072] Therefore, the first metal bump 40 includes a narrow bump 41 and a wide bump 42. The diameter of the narrow bump 41 should be equal to the opening diameter of the dielectric film 22, and the diameter of the wide bump 42 should be equal to the opening diameter of the photoresist layer. The narrow bump 41 is located inside the opening of the dielectric film 22 and is used to contact the chip pad 21. The wide bump 42 covers the dielectric film 22 extending to the surface of the chip pad 21 and is used to pass through the via 11 and electrically connect to the circuit layer 30.

[0073] Combination Figure 3 , 12 As shown, in the first and second embodiments of this application, the fabrication of the first metal bump 40 also includes: fabricating a dielectric film 22 for each chip 20, patterning the dielectric film 22 to expose the chip pad 21, and forming the first metal bump 40 on the chip pad 21.

[0074] S2: A substrate 10 is provided, and a through-hole 11 is formed on the substrate 10. The substrate 10 may be a silicon wafer, glass, or ceramic. The through-hole 11 may be formed by chemical etching, laser cutting, or mechanical cutting. It is understood that the diameter of the through-hole 11 should be slightly larger than the diameter of the first metal bump 40 to facilitate the subsequent insertion and mating of the first metal bump 40 and the through-hole 11.

[0075] Combination Figure 4 As shown, a substrate 10 is provided, and a through-hole 11 is formed on the substrate 10, including: forming a bonding layer 50 on one side of the substrate 10, the through-hole 11 penetrating the substrate 10 and the bonding layer 50. The bonding layer 50 is formed on a first side of the substrate 10 for subsequent bonding connection with the chip 20, and the bonding layer 50 may be a bonding adhesive formed by coating.

[0076] Before fabricating the through-hole 11 on the substrate 10, a carrier plate 200 is provided. The carrier plate 200 and the substrate 10 are bonded together by a release layer 300, wherein the bonding layer 50 is located on the side of the substrate 10 opposite to the carrier plate 200. In other words, the carrier plate 200 is disposed on the second side of the substrate 10 to support the substrate 10 and facilitate operation on the first side of the substrate 10.

[0077] In the process of fabricating the through-hole 11, in order to further protect and support the substrate 10, a carrier plate 200 can be provided in advance, and the substrate 10 can be temporarily bonded to the carrier plate 200 so as to facilitate the fabrication of the bonding layer 50 and the through-hole 11 on the substrate 10.

[0078] Combination Figure 4 , 13 As shown, in the first and second embodiments of this application, a substrate 10 is provided, and the through hole 11 is formed on the substrate 10. Specifically, this includes: providing a carrier plate 200, and bonding the carrier plate 200 and the substrate 10 together through a release layer 300; forming a bonding layer 50 and a through hole 11 on the side of the substrate 10 away from the carrier plate 200, with the through hole 11 penetrating the bonding layer 50 and the substrate 10.

[0079] S3: Connecting the chip 20 and the substrate 10, the first metal bump 40 is located within the through hole 11; combining Figure 5 As shown, in the first embodiment, the first metal bump 40 of the chip 20 is inserted into the through hole 11, and the chip 20 and the substrate 10 are pre-positioned and fitted.

[0080] The connection between the chip 20 and the substrate 10 includes: bonding the chip 20 and the substrate 10 together through the bonding layer 50, with the first metal bump 50 protruding into the release layer 300. The bonding layer 50 is pre-formed on the surface of the first side of the substrate 10. After the first metal bump 40 is inserted into the through-hole 11, the dielectric film 22 on the functional surface 23 of the chip 20 is bonded to the bonding layer 50. At this time, the carrier plate 200 on the second side of the substrate 10 has not yet been debonded, and the first metal bump 40 protrudes into the release layer 300.

[0081] Combination Figure 14 As shown, in the second embodiment, the difference from the first embodiment is that: connecting the chip 20 and the substrate 10 includes: connecting the first chip 201 and the second chip 202 to the same substrate 10, wherein the first metal bump 40 of the first chip 201 is correspondingly engaged with the through hole 11, and the first metal bump 40 of the second chip 202 is correspondingly engaged with the through hole 11.

[0082] It is understandable that the height of the first metal bump 40 should be configured such that it passes through the substrate 10 and protrudes from the surface of the second side of the substrate 10, so as to facilitate subsequent electrical connection with the circuit layer 30.

[0083] Combination Figure 5 As shown, after connecting the chip 20 and the substrate 10, the substrate 10 includes a first side of the molding substrate 10 and the chip 20, forming a molding layer 80.

[0084] After connecting the chip 20 and the substrate 10, the process includes providing a molding backplate 90, which is molding the molding backplate 90 onto the side of the chip 20 facing away from the substrate 10. In other words, a molding layer 80 is formed between the molding backplate 90 and the chip 20. In other embodiments, the molding backplate 90 may also be a heat dissipation backplate.

[0085] Combination Figure 5 , 14 As shown, in the first and second embodiments of this application, the pre-formed chip 20 and the first metal bump 40, and the substrate 10 and the carrier plate 200 are bonded together, and a molding compound 80 is formed on the first side of the substrate 10, or a molding compound 80 and a molding compound backplate 90 are formed.

[0086] Combination Figure 6 , 15 As shown, it can be understood that in the first and second embodiments of this application, the chip packaging method includes the steps of: removing the release layer 300 and the carrier 200, unbonding the substrate 10 and the carrier 200, and exposing the second side of the substrate 10, so as to facilitate the subsequent fabrication of the fill layer 60 and the circuit layer 30 on the second side of the substrate 10.

[0087] S4: Fabricate a filler layer 60, which fills at least between the first metal bump 40 and the through hole 11 to enhance the bonding force between the chip 20 and the substrate 10.

[0088] Fabricating the filler layer 60 includes filling the side of the substrate 10 away from the chip 20 with a molding compound, the molding compound entering from the surface of the substrate 10 between the first metal bump 40 and the through hole 11.

[0089] A molding compound is formed on the second side surface of the substrate 10 to form a horizontal portion 62, and the molding compound enters the gap between the first metal bump 40 and the through hole 11 to form an annular portion 61.

[0090] The annular portion 61 fills the annular gap between the first metal bump 40 and the through-hole 11, and further fills the surface of the dielectric film 22. This can improve the thermal stress phenomenon between the first metal bump 40 and the through-hole 11 without affecting the electrical connection between the first metal bump 40 and the chip pad 21. The horizontal portion 62 is used to insulate and isolate the substrate 10 and the circuit layer 30, preventing dielectric transmission between them and improving thermal stress.

[0091] Fabricating the filler layer 60 includes grinding the molding material to expose the first metal bump 40. If the initial horizontal portion 62 covers the surface of the first metal bump 40, the horizontal portion 62 can be treated by grinding and polishing to expose the first metal bump 40.

[0092] Combination Figure 6 , 15 As shown, in the first and second embodiments of this application, the second side of the substrate 10 is facing upward, the bonding carrier 200 is unbonded to expose the second side surface of the substrate 10 and the first metal bump 40, and a molding compound is filled into the second side surface of the substrate 10. The molding compound is then ground to obtain the filling layer 60.

[0093] Thus, the substrate 10 first forms a bonding layer 50, a bonding connection chip 20, and a molding compound layer 80 and / or a molding compound backplane 90 on its first side. Then, it is flipped to the second side of the substrate 10, where the bonding carrier 200 is debonded and a filler layer 60 is formed. The circuit layer 30 and the second metal bump 70 are then formed. This optimizes the packaging process and improves packaging efficiency.

[0094] S5: A circuit layer 30 is formed on the side of the substrate 10 opposite to the chip 20, and the first metal bump 40 passes through the through-hole 11 and is electrically connected to the circuit layer 30. Figure 7 , 16 As shown, a circuit layer 30 is formed on the surface of the horizontal portion 62 and the first metal bump 40. The first metal bump 40 is connected to a metal layer 31 of the circuit layer 30. The metal layer 31 is used to connect to the circuit board, thereby electrically connecting the chip 20 to the circuit board.

[0095] Fabricating a circuit layer 30 on the side of the substrate 10 away from the chip 20 includes: fabricating a metal layer 31, the metal layer 31 being connected to the first metal bump 40; and fabricating a dielectric layer 32, the dielectric layer 32 covering the metal layer 31, wherein the metal layer 31 is preferably copper.

[0096] The circuit layer 30 includes at least a first wiring layer 301 and a second wiring layer 302 formed by stacking. Both the first wiring layer 301 and the second wiring layer 302 include a metal layer 31 and a dielectric layer 32.

[0097] Combination Figure 8 As shown, in the first embodiment of this application, the fabrication of the first wiring layer 301 includes: coating photoresist, patterning photoresist, electroplating metal, and removing photoresist to obtain the metal layer 31 of the first wiring layer 301.

[0098] Combination Figure 8 As shown, after the metal layer 31 of the first wiring layer 301 is fabricated, a dielectric material is coated and the dielectric material is patterned to obtain the dielectric layer 32 of the first wiring layer 301.

[0099] Combination Figure 9 As shown, after the first wiring layer 301 is fabricated, the second wiring layer 302 is fabricated. Fabricating the second wiring layer 302 includes: coating the surface of the first wiring layer 301 with photoresist, patterning the photoresist, electroplating metal, and removing the photoresist to obtain the metal layer 31 of the second wiring layer 302.

[0100] Combination Figure 9 As shown, after fabricating the metal layer 31 of the second wiring layer 302, the process includes coating a dielectric material and patterning the dielectric material to obtain the dielectric layer 32 of the second wiring layer 302. This completes the fabrication of the first layer 301 and the second wiring layer 302. In other embodiments, when the circuit layer 30 includes more wiring layers, the above method is used to repeat the steps sequentially to obtain a circuit layer 30 with more wiring layers.

[0101] Combination Figure 17-20 As shown, in the second embodiment of this application, since multiple chips 20 are connected to the same side of the substrate 10 at the same time, the integrated circuit is more complex than in the first embodiment. The circuit layer 30 includes more wiring layers, and the metal layer 31 and dielectric layer 32 need to be fabricated repeatedly.

[0102] S6: A second metal bump 70 is formed on the side of the circuit layer 30 opposite to the chip 10, and the second metal bump 70 is electrically connected to the circuit layer 30. Figure 10 , 16As shown in the first and second embodiments of this application, the exposed metal layer 31 is used to form a second metal bump 70, which is used to electrically connect the circuit layer 30 and the circuit board. The second metal bump 70 is preferably a solder ball.

[0103] The beneficial effects of the present invention are as follows: the first metal bump 40 passes through the through hole 11 and is electrically connected to the circuit layer 30. The first metal bump 30 and the through hole 11 are pre-fitted, so that the chip 20 and the substrate 20 can be accurately positioned before packaging. This is beneficial for accurate positioning between the chip 20 and the substrate 10 and prevents the chip 20 from shifting relative to the substrate 10 during the packaging process. The annular portion 61 fills the space between the first metal bump 40 and the through hole 11, strengthening the bonding force between the first metal bump 40 and the through hole 11, thereby strengthening the bonding force between the chip 20 and the substrate 10. The horizontal portion 62 is used to insulate and isolate the substrate 10 and the circuit layer 30, preventing dielectric transmission between the two and improving thermal stress.

[0104] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0105] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0106] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that, The device includes a substrate, a chip and a circuit layer located on both sides of the substrate along its thickness direction, a first metal bump, and a first fill layer. The first metal bump is electrically connected to the chip. The substrate includes a through-hole. The first metal bump passes through the through-hole and is electrically connected to the circuit layer. The fill layer fills at least between the first metal bump and the through-hole.

2. The chip packaging structure according to claim 1, characterized in that, The filler layer extends between the substrate and the circuit layer.

3. The chip packaging structure according to claim 2, characterized in that, The filler layer exposes the first metal bump.

4. The chip packaging structure according to claim 2, characterized in that, The circuit layer is formed on the surface of the filler layer and the surface of the first metal bump.

5. The chip packaging structure according to claim 1, characterized in that, The chip includes chip pads formed on its surface, and the first metal bump is formed on the chip pads.

6. The chip packaging structure according to claim 5, characterized in that, The chip includes a dielectric film formed on its surface, the dielectric film exposing the chip pads.

7. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure includes a bonding layer for bonding the chip and the substrate.

8. The chip packaging structure according to claim 1, characterized in that, The chip includes a first chip and a second chip arranged in a horizontal direction, and the first chip and the second chip are connected to the same substrate.

9. A chip packaging method, characterized in that, Includes the following steps: A chip is provided, and a first metal bump is formed on the chip pads of the chip; A substrate is provided, and through-holes are formed on the substrate; The chip and the substrate are connected, with the first metal bump located inside the through-hole; A filler layer is formed, which at least fills the space between the first metal bump and the through hole; A circuit layer is formed on the side of the substrate opposite to the chip, and the first metal bump passes through the via and is electrically connected to the circuit layer.

10. The chip packaging method according to claim 9, characterized in that, The process of creating a first metal bump on the chip pad includes: creating a dielectric film on the surface of the chip where the chip pad is located, the dielectric film exposing the chip pad.

11. The chip packaging method according to claim 10, characterized in that, The process of creating the first metal bump on the chip pad includes: A photoresist layer is fabricated on the dielectric film; The photoresist layer is patterned to form openings that expose the chip pads; A first metal bump is made in the opening; Remove the photoresist layer.

12. The chip packaging method according to claim 9, characterized in that, A substrate is provided, and a through-hole is formed on the substrate by: forming a bonding layer on one side of the substrate, wherein the through-hole penetrates the substrate and the bonding layer.

13. The chip packaging method according to claim 12, characterized in that, Before fabricating through-holes in the substrate, the method includes: providing a carrier plate, wherein the carrier plate and the substrate are bonded together by a release layer, the bonding layer being located on the side of the substrate opposite to the carrier plate.

14. The chip packaging method according to claim 13, characterized in that, Connecting the chip and the substrate includes: bonding the chip and the substrate through the bonding layer, wherein the first metal bump protrudes to the release layer.

15. The chip packaging method according to claim 14, characterized in that, The steps include: removing the peeling layer and the carrier plate.

16. The chip packaging method according to claim 9, characterized in that, Fabricating the filler layer includes filling the side of the substrate away from the chip with a molding compound, the molding compound entering from the surface of the substrate between the first metal bump and the via.

17. The chip packaging method according to claim 16, characterized in that, Creating the filler layer includes grinding the molding material to expose the first metal bump.

18. The chip packaging method according to claim 9, characterized in that, Fabricating a circuit layer on the side of the substrate opposite to the chip includes: A metal interconnect layer is fabricated, the metal interconnect layer being connected to the first metal bump; A dielectric layer is fabricated, which covers the metal interconnect layer.

19. The chip packaging method according to claim 9, characterized in that, The steps include: fabricating a second metal bump on the side of the circuit layer away from the chip, wherein the second metal bump is electrically connected to the circuit layer.

20. The chip packaging method according to claim 9, characterized in that, The steps include: providing a first chip and a second chip, wherein the first chip and the second chip are electrically connected to the same side of the same substrate via a first metal bump.

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