Current sensing implementation for common drain back-to-back power switch in vertical FET technology

Abstract

A current sensing implementation for a common drain back-to-back power switch in vertical FET technology is disclosed. Techniques for load current sensing in a common drain power FET switch are described. In an exemplary embodiment, a power field effect transistor (FET) device includes a back-to-back power FET connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to draw a sense current through the first replica FET using a sense voltage from the second replica FET.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Indian Provisional Application No. 202411034337, filed on April 30, 2024. The entire contents of the above application are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to the field of power transmission devices and systems and methods for controlling power transmission devices. Background Technology

[0004] Various electronic devices (e.g., smartphones, tablets, laptops, hubs, chargers, adapters, etc.) can be configured according to the Universal Serial Bus (USB) power delivery protocol defined in various revisions of the USB Power Delivery (USB-PD) specification for wired charging via a USB Type-C (USB-C) connector. For example, in some applications, the electronic device can be configured as a power-consuming device to receive power via a USB-C connector (e.g., a laptop computer for charging its own battery), while in other applications, the electronic device can be configured as a power-generating device (e.g., a laptop computer) to supply power to another device connected to it (e.g., a smartphone) via a USB-C connector. The USB-PD specification allows the power-generating device and the power-consuming device to dynamically negotiate various power levels, such as 5V (volts) at 3A (amperes), 15V at 3A, 20V at 3A, 12V at 5A, 20V at 5A, 48V at 5A, etc.

[0005] However, power delivery and control are challenging in USB and other technologies that require accurate power levels (e.g., voltage and / or current) and stringent overvoltage and / or overcurrent protection. Attached Figure Description

[0006] The present disclosure is illustrated by way of example and not limitation in the figures in the accompanying drawings.

[0007] Figure 1 A circuit block diagram of an apparatus for load current sensing in a common-drain power field-effect transistor (FET) device according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A circuit block diagram of another device for load current sensing in a common-drain power FET device, according to some embodiments of the present disclosure, is shown.

[0009] Figure 3A circuit block diagram of another device for load current sensing in a common-drain power FET device, according to some embodiments of the present disclosure, is shown.

[0010] Figure 4 An exemplary structure of a vertical field-effect transistor (FET) according to some embodiments of the present invention is shown.

[0011] Figure 5 This is a block diagram illustrating an integrated circuit (IC) controller that can be configured with a power FET semiconductor device in the power path of a power supply device and / or a power consumer device, according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram illustrating a system-in-package (SiP) comprising an IC controller and a power FET semiconductor device within a single package, according to some embodiments of the present disclosure. Detailed Implementation

[0013] The following description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to better understand embodiments of the various techniques described herein for load current sensing and current limiting in common-drain power FET switches implemented in vertical FET technology. However, it will be apparent to those skilled in the art that at least some embodiments can be implemented without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in a simple block diagram format to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of the invention.

[0014] References to "embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" indicate that a particular feature, structure, step, operation, or characteristic described in connection with one or more embodiments is included in at least one embodiment of the invention. Furthermore, descriptions of the phrases "embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" appearing throughout the specification do not necessarily refer to the same one or more embodiments.

[0015] This description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate embodiments according to exemplary models. These embodiments (which may also be referred to herein as "examples") have been described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0016] This document describes various embodiments of current sensing and current limiting techniques in power FET devices for a variety of USB-enabled electronic devices. Examples of such USB-enabled electronic devices include, but are not limited to, personal computers (e.g., laptops, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, etc.), mobile communication devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, pocket PCs, etc.), audio / video / data recording and / or playback devices (e.g., cameras, voice recorders, handheld scanners, etc.), and other similar electronic devices that can use a USB-C connector for battery charging and / or power delivery.

[0017] Some USB-enabled electronic devices may conform to specific revisions and / or versions of the USB-PD specification. The USB-PD specification defines a standard protocol designed to provide more flexible power delivery and data communication over a single USB-C cable via a USB-C port, enabling the maximum functionality of USB-enabled devices. The USB-PD specification also describes the architecture, protocols, power delivery behavior, parameters, and wiring required to manage power delivery over a USB-C cable at up to 100W (or higher, up to 240W, in the case of Extended Power Range (or EPR)). According to the USB-PD specification, devices with USB-C ports (e.g., USB-enabled devices) can negotiate greater current and / or higher or lower voltage over a USB-C cable than allowed in older USB specifications (e.g., such as the USB 2.0 specification, USB Battery Charging Specification versions 1.1 / 1.2, etc.). For example, the USB-PD specification defines a protocol for negotiating a power delivery agreement (PD agreement) between a pair of USB-enabled devices. The PD protocol can specify both the power level and the direction of power transfer that can be adapted by two devices, and can be dynamically renegotiated (e.g., without the device being unplugged) based on the request of either device and / or in response to various events and conditions (e.g., power function swapping, data function swapping, hard reset, power failure, etc.). According to the USB-PD specification, electronic devices are typically configured to deliver power to another device via a power path configured on the USB VBUS line. Devices providing power are typically referred to as (or include) a "power supply device" (or power source), and devices consuming power are typically referred to as (or include) a "power-consuming device" (or power consumer). In some embodiments, a USB-PD power supply can be configured to draw power from a direct current (DC) source and may include a DC-DC converter. In other embodiments, a USB-PD power supply can be configured to draw power from an alternating current (AC) power adapter or from another AC source.

[0018] In USB-enabled and other technologies that require accurate power levels (e.g., voltage and / or current) and stringent overvoltage and / or overcurrent protection, power delivery and its control are often challenging. Electronic devices are typically configured to deliver power via field-effect transistors (FETs) or other similar switching devices. In some cases, FETs can become susceptible to electrical damage (e.g., overcurrent damage, overvoltage damage, overheating damage, reverse current damage, etc.) due to one or more electrical faults, for example, that may occur in a USB-C connector system. Power delivery IC controllers in such technologies often struggle to meet the conflicting requirements of accurate power levels, protection, and efficiency in high-current (e.g., 3A or above) implementations and applications.

[0019] Electronic devices typically use power transfer circuits (power paths) to transfer power to / from the device. In other electronic components, a power path may include one or more power FETs coupled in series in the circuit path to operate as a switch (e.g., as an "on" / "off" switch). In some important characteristics, power FETs differ from FETs and other types of transistor switching devices used in other non-power transfer applications. As a discrete semiconductor switching device, a power FET can carry a large current between its source and drain when it is "on"; it can have a low resistance from its source to its drain when it is "on"; and it can withstand a high voltage from its source to its drain when it is "off". For example, a power FET can be characterized as being able to carry currents ranging from several hundred milliamps (e.g., 500-900 mA) to several amps (e.g., 3-5 A or higher) and withstand voltages ranging from 12 V to 40 V (or higher) from its source to its drain. For example, the resistance between the source and drain of a power FET device may be very small in order to prevent, for example, power losses on the device. The examples, implementations, and embodiments disclosed herein may use different types of FETs, such as metal-oxide FETs (MOSFETs), nFETs (e.g., N-type MOSFETs), pFETs (e.g., P-type MOSFETs), etc.

[0020] Vertical FETs represent a relatively recent advancement in FET design. They offer several advantages over traditional lateral FET designs, such as higher current density, improved thermal performance, smaller device size, and higher die area efficiency. These advantages make vertical FETs advantageous for high-density integrated circuits. However, vertical FETs present additional challenges in current sensing.

[0021] In some conventional implementations, load current is sensed by a sensing resistor implemented in series with a power FET. However, this technique typically results in high power loss due to the presence of the sensing resistor in the load path, which is undesirable for applications such as USB Type-C power delivery chips.

[0022] Another method for sensing current in a dual-power FET device involves using a replica FET fabricated in the same integrated circuit die. The power FET device is configured such that the current through the replica FET is a mirror image of the current through the power FET at a known ratio, determined by the size ratio between the power FET and the smaller replica FET. This ratio may be referred to as k. ILIS It represents the load current I. L It is the sensing current I S k ILIS times, IL =k ILIS ×I S In some embodiments, a typical k ILIS The ratio can be approximately 3000. In this way, a much smaller sensed current through the replica FET can be measured and processed to provide the load current through the power FET. However, conventional circuitry for implementing this current sensing method requires the drain node of the main power FET to be separate from its replica. Separating the drain nodes of the power FET and replica FET using a lateral FET is relatively easy, but it is difficult with a vertical FET. If dual power FETs are implemented in vertical FET technology, conventional current sensing methods would require various process technology changes. For example, process technology changes are needed to separate the drain terminals of the main power FET and replica FET and / or enable access to the common drain terminal of the vertical power FET (e.g., the back-side metallization of each die, etc.). However, the costs associated with such technology changes can be prohibitive.

[0023] To address these and other shortcomings of conventional current sensing in power FET devices, the techniques described herein provide a current sensing technique for common-drain dual power FET devices with vertical FETs. The power FET device according to embodiments includes dual power FETs arranged in series and sharing a common drain node (i.e., back-to-back). The power FET device also includes at least two replica FETs fabricated within the same die, wherein the drain of each replica FET is coupled to the common drain node of the two power FETs. One of the replica FETs (referred to herein as the current-sensing FET) is used to provide a sense current representing the load current flowing through the power FET device, while the other replica FET (referred herein as the voltage-sensing FET) is used to provide a sense voltage representing the voltage at the common drain node. The current-sensing FET and the voltage-sensing FET are coupled to a current-sensing circuit configured to measure a sense current proportional to the load current flowing through the power FET. The current-sensing circuit uses the sense voltage from the voltage-sensing FET (i.e., the voltage at the common drain node) to draw the sense current through the current-sensing FET. More specifically, the sensed voltage at the common drain node is used to generate a voltage across the current-sensing FET that matches the source-to-drain voltage drop across the corresponding power FET. In this way, the current-sensing FET generates a voltage at an appropriate K position relative to the corresponding power FET. ILIS Ratio of current.

[0024] The sensed current can then be used in various ways, such as for overcurrent fault prevention and other applications. For example, the sensed current can be digitized and processed (e.g., by an IC controller) and used by firmware to manage or interrupt the load current. In some embodiments, the sensed current can be received by a current-limiting circuit that uses the sensed current to limit the load current to or below a maximum current level.

[0025] In some embodiments, the techniques described herein provide for implementing such power FET devices in vertical FET technology, thereby improving power efficiency while allowing for higher current delivery and control compared to lateral FETs. However, it should be understood that while the disclosed techniques may be particularly suitable for power FET devices comprising back-to-back vertical FETs with a common drain, the disclosed techniques are not limited to such embodiments. For example, the disclosed techniques can also be used in lateral FET and FET devices employing a single power FET instead of dual power FETs.

[0026] In some embodiments, the techniques described herein also allow for the implementation of such power FET devices as well as IC controller dies in SiP packages or dual-chip modules. In some USB-enabled embodiments, the techniques described herein conform to a common footprint definition, making such embodiments easily designable by manufacturers into a variety of electronic devices, such as laptops and notebooks.

[0027] Figure 1 A circuit block diagram of a device 100 for load current sensing in a common-drain power FET device 102 is shown according to some exemplary embodiments of the present disclosure. The device 100 may include a power FET device 102 and a current sensing circuit 104. In some embodiments, the power FET device 102 and the current sensing circuit 104 may be instantiated on a separate die and encapsulated in a single chip carrier package as a system-in-package (SiP) device.

[0028] The power FET device 102 is a power switch instantiated on a single die, comprising two power FETs 106A and 106B and corresponding replica FETs 108A and 108B. The gates of the power FET 106A and replica FET 108B may have separate gate terminals. However, in some embodiments, the gate of the power FET 106A is internally connected to the gate of the replica FET 108A, such that both FETs are controlled by a common signal applied to a first common gate terminal. Similarly, the gate of the power FET 106B may be internally connected to the gate of the replica FET 108B, such that both FETs are controlled by a common signal applied to a second common gate terminal.

[0029] According to the technology described herein, power FETs 106 are arranged back-to-back within power FET device 102, therefore, during operation, as depicted, the load current I... L The bus voltage VBUS flows to load 112. Furthermore, power FET 106 is drain-connected to share a common drain node 120. Diode 130 represents a body diode (also called a host diode) that can be incorporated into the structure of the respective FET. Power FET device 102 is depicted operating in power delivery mode. However, power FET device 102 can also be configured to operate in power receiving mode, in which case the current through power FETs 106A and 106B will be relative to... Figure 1 In the opposite direction shown.

[0030] The replica FETs 108 are area-scaled versions of the power FETs 106. Although not shown, the replica FETs may also include corresponding body diodes. The drains of the two replica FETs 108 are also coupled to the same common drain node 120 as the two power FETs 106. Therefore, all four FETs in the power FET device 102 share a common drain. The common drain node 120 can be accessed by fabricating the replica FETs in linear mode or using a simple contact mask. The voltage at the common drain 120 may be referred to herein as V. DRAIN .

[0031] During operation, the gates 110A and 110B of power FET 106 are controlled by a gate driver (not shown) to turn on power FET 106, thereby connecting the bus voltage VBUS to load 112 to supply current to load 112. In some embodiments, the magnitude of the bus voltage can be determined according to the power delivery conventions described above. Additionally, the corresponding gates 110C and 110D of replica FET 108 are activated by a gate driver to achieve current sensing. Figure 1 In the exemplary embodiment shown, the connection between the current sensing circuit 104 and the two replica FETs 108 enables replica FET 108A to be configured as a current sensing FET and replica FET 108B to be configured as a voltage sensing FET.

[0032] like Figure 1As shown, the source terminal of replica FET 108B (voltage sensing FET) is coupled to the non-inverting input of operational amplifier 114. Operational amplifier 114 is configured as a closed-loop amplifier, comprising operational amplifier 114, transistor 116 (e.g., FET), and a voltage divider consisting of two resistors 118 having equal resistance R. The resistance R of resistors 118 may be several times larger than the resistance of power FET 106 (e.g., 500 ohms or greater). The inverting input of operational amplifier 114 is coupled to first replica FET 108A (current sensing FET) via the voltage divider (i.e., between resistors 118).

[0033] The sensed voltage received at the non-inverting input of operational amplifier 114 is equal to (or nearly equal to) the voltage level V at the common drain node 120 between power FETs 106. DRAIN To achieve balance, the inverting input of operational amplifier 114 becomes equal to the non-inverting input. Therefore, the sensed voltage V... DRAIN The resistors 118 in the voltage divider are connected to the node. As a result, the source-to-drain voltage drop across the replica FET 108A will be equal to (or nearly equal to) the source-to-drain voltage drop across the power FET 106A, but with opposite polarity. Therefore, the current I through the replica FET 108A... L / N will be relative to the load current I through the power FET 106A. L In the appropriate K ILIS Ratio. Furthermore, since the resistance R provided by resistor 118 is several times larger than the source-to-drain resistance of the power FET 106A, the source-to-drain current through transistor 116 will be approximately equal to the sensed current I. L / N.

[0034] In some embodiments, the sensing resistor 122(R) S It can be coupled between the output of transistor 116 and ground to sense the current I. L / N is converted to voltage. The voltage (R) across the sensing resistor 122 is... S The detected load current I can be digitized and processed using an analog-to-digital converter (not shown). L The value of the detected load current. For example, this value can be used in the feedback loop of the control bus voltage (VBUS) and / or gate driver (not shown) to change or limit the load current or maintain the load current at a specified level.

[0035] It should be understood that Figure 1 The circuit depicted is an example of current sensing technology according to an embodiment, and various modifications can be made without departing from the scope of the claims. Regarding Figure 2and Figure 3 Additional embodiments of this technology are further described.

[0036] Figure 2 A circuit block diagram of a load current sensing device 200 for a common-drain power FET device 202 is shown, according to some exemplary embodiments of the present disclosure. Figure 2 The circuit shown is similar to Figure 1 The circuitry differs in that the power FET device 202 includes an additional pair of replica FETs 208A and 208B. For example... Figure 1 As shown, the replica FETs 108A, 108B, 208A and 208B are area-scaled versions of the power FETs 106A and 106B, respectively, and the drains of all four replica FETs 108A, 108B, 208A and 208B are coupled to the same common drain node 120 as the two power FETs 106A and 106B.

[0037] exist Figure 2 In the example shown, the gates of replica FETs 208A and 208B can each have separate gate terminals 110E and 110F, respectively. However, in some embodiments, the gate of power FET 106A is internally connected to the gates of replica FETs 108A and 208A, such that they share a common gate terminal. Similarly, the gate of power FET 106B can be internally connected to the gates of replica FETs 108B and 208B, such that they share a common gate terminal.

[0038] Current sensing, based on the above regarding Figure 1 They operate on the same principle as described, the difference being that the sensed voltage is provided by replica FET 208A instead of replica FET 108B. Replica FETs 108B and 208B are used for sensing the load current I. L It may not be necessary, but can be used for other purposes, such as current mirroring applications. During operation, the duplicate FETs 108B and 208B can be coupled to other circuitry (not shown), such as additional current sensing circuitry, or can be coupled to ground via appropriate resistors.

[0039] The power FET device 202 can also be configured to operate in a power receiving mode, in which case the current through the power FETs 106A and 106B will be relative to... Figure 2The directions shown are in opposite directions. If the power FET device 202 operates in power receive mode, current sensing can be implemented on opposite sides of the power FET device 202 using replica FETs 108B and 208B. Therefore, when operating in power receive mode, an additional current sensing circuit 104 can be coupled to the replica FETs 108B and 208B to be used.

[0040] Figure 3 A circuit block diagram of a load current sensing device 300 for a common-drain power FET device 302 is shown, according to some exemplary embodiments of the present disclosure. Figure 3 The circuit shown is similar to Figure 2 The circuitry includes additional replicas of FETs 208A and 208B. Additionally, in... Figure 3 In the example shown, the gate of power FET 106A is internally connected to the gates of replica FET 108A and replica FET 208A, such that they share a common gate terminal 310A. Similarly, the gate of power FET 106B is internally connected to the gates of replica FET 108B and replica FET 208B, such that they share a common gate terminal 310B. For simplicity, the conductive connections between the corresponding gates are not shown. For the purposes of this specification, power FET 106A may be referred to as input power FET 106A, and power FET 106B may be referred to as output power FET 106B.

[0041] Figure 3 The diagram also shows a gate driver 312 comprising two current sources. One current source is coupled to gate terminal 310A to provide a gate signal to the input power FET 106A and its corresponding replicas FETs 108A and 208A. The other current source is coupled to gate terminal 310B to provide a gate signal to the output power FET 106B and its corresponding replicas FETs 108B and 208B.

[0042] Current sensing, based on the above regarding Figure 1 and Figure 2 The circuit operates on the same principle as described, except that the current sensing circuit 304 includes a current mirror circuit 316, which causes the source-to-drain current through transistor 116 to be replicated to two or more outputs, thus sensing the current I. L / N can be used for multiple purposes. For example, one output of the current mirror circuit 316 can be coupled to a device for sensing the current I. L / N is converted into the sensing resistor 122(R) as described above. S ).Apart from Figure 3In addition to the output shown, the current mirror circuit 316 may also have any appropriate number of additional outputs to provide sensing current to other components.

[0043] The different outputs of the current mirror circuit 316 provide sensing current I to the current limiting circuit 314. L / N. The current limiting circuit 314 will limit the load current I through power FETs 106A and 106B. L The current limit is set to a value specified for the specific application. For example, in USB-enabled applications, this current limit is dynamically determined by a PD agreement established between the power supply and the power consumer. In such applications, the current limit can be determined using appropriate firmware control and / or programmable circuitry (e.g., circuitry with a controllable current source).

[0044] The current limiting circuit 314 can be implemented using any suitable circuit. Figure 3 In the example shown, the current limiting circuit 314 includes a comparator 318 and a current limiting transistor 320 (e.g., a FET), the current limiting transistor 320 being coupled to the gate terminal 310B of the output power FET 106B. The comparator 318 converts the received sensed current I... L / N is compared with a reference current representing a specified current limit value. When comparator 318 detects that the current limit value is exceeded, comparator 318 applies a control signal to the gate of current-limiting transistor 320. Activation of current-limiting transistor 320 causes a portion of the current from gate driver 312 to be shunted to ground, which reduces the amount of current supplied to gate terminal 310B. This, in turn, increases the resistance of output power FET 106B and limits the load current IL to a specified maximum current level. In this way, current-limiting circuit 314 can limit the current through output power FET 106B, which also effectively limits the current through power FET device 102.

[0045] The current-limiting configuration described above has significant advantages related to the electrical characteristics of most FETs. Specifically, when the gate signal applied to the FET decreases sufficiently to significantly increase the FET's resistance, the FET no longer operates in the linear region. As a result, the ratio of the current through the FET to any associated replica FET will change, meaning the ratio of load current to sense current will deviate from the expected K... ILIIS The ratio. This deviation is difficult to characterize and compensate for. However, in the described embodiment, the load current is controlled by controlling only the resistor of the output power FET 106B. The resistor of the input power FET 106A is not affected by the current limiting circuit 314. Therefore, the sensed current through the replica FET 108A will be in an appropriate ratio compared to the current through the input power FET 106A, regardless of the state of the current limiting circuit 314.

[0046] In this way, the technique described herein utilizes the inherent sensing accuracy and control when performing current sensing of the input power FET 106A using the replica FETs 108A and 208A, even when the load current is limited by the current-limiting circuit 314, the replica FETs 108A and 208A continue to operate in the linear region. On the other hand, the technique described herein also enables control of the load current through the power FET device 102 by controlling the resistance of the output power FET 106B without affecting the accuracy of current sensing.

[0047] The power FET device 302 can also be configured to operate in power receiving mode, in which case the current through power FETs 106A and 106B will be relative to... Figure 3 In the opposite direction shown. If the power FET device 302 operates in power-receiving mode, the current sensing and current limiting operations can be interchanged on the power FET device 302. In other words, current sensing can be implemented using replica FETs 108B and 208B, and current limiting can be implemented using power FET 106A. Therefore, an additional current sensing circuit 304 can be coupled to power FET 106B and replica FETs 108B, 208B, and an additional current limiting circuit 314 can be coupled to the gate drive of power FET 106A for operation in power-receiving mode.

[0048] Figure 4 An exemplary structure of a vertical FET 400 according to some embodiments is shown. Figure 4 The vertical FET 400 shown can be referred to as a trench MOSFET. However, the current technology can be applied to any type of vertical FET, including vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), etc. Furthermore, embodiments of the disclosed technology are not limited to these. Figure 4 The specific arrangement shown is provided only as one example of vertical FET technology that may benefit from the disclosed technology.

[0049] like Figure 4As shown, source 402 and gate 404 are disposed on the top surface of vertical FET 400, and drain 406 is disposed on the bottom surface of vertical FET 400 on the opposite side of the bulk semiconductor substrate compared to source 402 and gate 404. As indicated by arrow 419, the direction of current is perpendicular from source 402 to drain 406. Typically, any additional vertical FETs fabricated in the same die will be oriented in a similar manner to drain 406 on the bottom surface. Since drain 406 is on the same semiconductor layer as the drain of any adjacent vertical FET, fabricating two or more vertical FETs sharing a common connection / drain is relatively simple and cost-effective. Compared to lateral FETs, such as Figure 4 The depicted vertical FET uses significantly less lateral area. Therefore, such a vertical FET may be well-suited for integrated circuit applications that benefit from higher circuit density.

[0050] Figure 5 This is a block diagram illustrating an IC controller 500 that can be configured as a USB-PD controller according to some embodiments, and power FET semiconductor devices on the power path of the power supply and / or power consumption device. The IC controller 500 may include a peripheral subsystem 510, which includes components for USB-PD power delivery. The peripheral subsystem 510 may include a peripheral interconnect 511, which includes a clock module and a peripheral clock (PCLK) 512 for providing clock signals to the various components of the peripheral subsystem 510. The peripheral interconnect 511 may be a peripheral bus, such as a single-level or multi-level Advanced High-Performance Bus (AHB), and may provide a data and control interface between the peripheral subsystem 510, the CPU subsystem 530, and the system resource 540. The peripheral interconnect 511 may include controller circuitry, such as a Direct Memory Access (DMA) controller, which can be programmed to transfer data between peripheral blocks without input, control, or burden from the CPU subsystem 530.

[0051] Peripheral interconnects 511 can be used to couple components of the peripheral subsystem 510 to other components of the IC controller 500. Coupled to peripheral interconnects 511 can be multiple general purpose input / output (GPIO) 515s for transmitting and receiving signals. GPIO 515s may include circuitry configured to implement various functions, such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single multiplexing, etc. Other functions may also be implemented by GPIO 515s. One or more timer / counter / pulse width modulator (TCPWM) 517s may also be coupled to the peripheral interconnects and include circuitry for implementing timing circuitry (timers), counters, pulse width modulator (PWM) decoders, and other digital functions that can operate on I / O signals and provide digital signals to system components of the IC controller 500. The peripheral subsystem 510 may also include one or more serial communication blocks (SCBs) 519 for implementing serial communication interfaces, such as internal integrated circuits (I2C), serial peripheral interfaces (SPI), universal asynchronous receivers / transmitters (UART), controller area networks (CAN), clock extended peripheral interfaces (CXPI), etc.

[0052] The peripheral subsystem 510 may include a USB power delivery subsystem 520 coupled to a peripheral interconnect, and includes a set of USB-PD modules 521 for USB power delivery. The USB-PD modules 521 may be coupled to the peripheral interconnect 511 via a USB-PD interconnect 523. The USB-PD module 521 may include: an analog-to-digital converter (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line according to PD conventions; a high-voltage (HV) regulator for converting the power supply voltage into a precise voltage (e.g., 3.5-5V) to power the IC controller 500; a high-side or low-side current sensing amplifier (LSCSA) for accurately measuring the load current; an overvoltage protection (OVP) module and an overcurrent protection (OCP) module for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field-effect transistors (FETs) used in USB power delivery in a power supply and / or power consumption device configuration; and a communication channel PHY (CC BB PHY) module for supporting communication on the USB-C communication channel (CC) line. The USB-PD module 521 may also include a charger detection module for determining the presence of a charging circuit and coupled to the IC controller 500, and a VBUS discharge module for controlling the voltage discharge on the VBUS line. The discharge control module can be configured to couple to a power node or an output (consumer) node on the VBUS line and discharge the voltage on the VBUS line to a desired voltage level (i.e., the voltage level negotiated in the PD protocol). The USB power delivery subsystem 520 may also include pads 527 for external connections and electrostatic discharge (ESD) protection circuitry 529, which may be required for the Type-C port. The USB-PD module 521 may also include a bidirectional communication module for supporting bidirectional communication with another controller.

[0053] GPIO 515, TCPWM 517, and SCB 519 can be coupled to input / output (I / O) subsystem 550, which may include a high-speed (HS) I / O matrix 551 coupled to multiple GPIO 553. GPIO 515, TCPWM 517, and SCB 519 can be coupled to GPIO 553 through the HS I / O matrix 551.

[0054] The IC controller 500 may also include a central processing unit (CPU) subsystem 530 for processing commands, storing program information, and data. The CPU subsystem 530 may include one or more processing units 531 for executing instructions and reading from and writing to memory locations from multiple memories. The processing unit 531 may be a processor suitable for operation in an integrated circuit (IC) or system-on-a-chip (SOC) device. In some embodiments, the processing unit 531 may be optimized for low-power operation employing extended clock gating. In this embodiment, various internal control circuitry may be implemented for processing unit operation in various power states. For example, the processing unit 531 may include a wake-up interrupt controller (WIC) configured to wake the processing unit from a sleep state, thereby allowing power to be turned off when the IC or SOC is in a sleep state. The CPU subsystem 530 may include one or more memories, including flash memory 533 and static random access memory (SRAM) 535, and read-only memory (ROM) 537. The flash memory 533 may be a non-volatile memory (NAND flash memory, NOR flash memory, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 533 may include a read accelerator and may improve access time by being integrated within CPU subsystem 530. SRAM 535 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 531. ROM 537 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of IC controller 500. SRAM 535 and ROM 537 may have associated control circuitry. Processing unit 531 and memory may be coupled to system interconnect 539 to route signals to and from various components of CPU subsystem 530 to other blocks or modules of IC controller 500. System interconnect 539 may be implemented as a system bus, such as a single-level or multi-level AHB. System interconnect 539 may be configured as an interface to couple various components of CPU subsystem 530 to each other. System interconnect 539 may be coupled to peripheral interconnect 511 to provide signal paths between components of CPU subsystem 530 and peripheral subsystem 510.

[0055] The IC controller 500 may also include multiple system resources 540, including a power module 541, a clock module 543, a reset module 545, and a test module 547. The power module 541 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REFs), and a power system (PWRSYS) module. In some embodiments, the power module 541 may include circuitry that allows the IC controller 500 to draw power from and / or supply power to an external source at different voltage and / or current levels and supports controller operation in different power states (e.g., active, low power, or sleep). In various embodiments, more power states can be implemented because the IC controller 500 suppresses operation to achieve desired power consumption or output. The clock module 543 may include a clock control module, a watchdog timer (WDT), an internal low-speed oscillator (ILO), and an internal master oscillator (IMO). The reset module 545 may include a reset control module and an external reset (XRES) module. Test module 547 may include modules for controlling and entering test modes, as well as test control modules for analog and digital functions (digital test and analog DFT).

[0056] In some embodiments, the IC controller 500 may be implemented in a monolithic (e.g., a single) semiconductor die. According to the techniques described herein, in some embodiments, the IC controller 500 die is disposed together with a power FET semiconductor die in a single package as a SiP or a single multi-chip module. As previously described, the power FET die includes two back-to-back power FETs with a connected / common drain and a corresponding replica FET for sensing load current at the common drain. In such embodiments, according to the techniques described herein, the peripheral subsystem 510 of the IC controller 500 includes one or more gate drivers (e.g., Figure 3 The gate driver 312 (in the IC controller 500) is coupled (via a corresponding terminal) to the FET of the power FET die to control the power FET in the power supply or power consumption configuration herein, and to activate a replica FET for current sensing and / or voltage sensing operations. Additionally, the peripheral subsystem 510 of the IC controller 500 may include... Figure 3 The current limiting circuit 314 and about Figures 1 to 3 Any current sensing circuits 104, 304 described. For example, the gate driver 312, the current limiting circuit 314, and the current sensing circuits 104, 304 may be components of the USB-PD module 521.

[0057] Figure 6This is a block diagram illustrating a system-in-package (SiP) 600 including an IC controller 500 and a power FET device 602 housed in a single package, according to some embodiments. The power FET device 602 may be as described above regarding... Figures 1 to 3 Any of the power FET devices 102, 202, and 302 described herein. According to the techniques described herein, within the SiP 600, various terminals of the IC controller 500 are coupled to terminals of the power FET device 602 via multiple metal wires (or buses). As shown, multiple pins of the SiP 600 may be coupled to other components of the power path 604. In various embodiments, the power path 604 may be a power supply device power path (e.g., for supplying power to a user device) or a user device power path (e.g., for receiving power from a power supply device).

[0058] In the above description, some technical details can be presented based on the algorithms and symbolic representations of operations performed via firmware and / or within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to those skilled in the art. Algorithms are, and generally are, conceived herein as a self-consistent sequence of steps leading to a desired result. These steps are those that require physical manipulation of physical quantities. Typically, though not always necessary, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has been shown that, primarily for general reasons, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0059] However, it should be remembered that all these terms and similar terms will be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, as is apparent from the above discussion, it should be understood that throughout the specification, discussions using terms such as “determine,” “allocate,” “dynamically allocate,” “redistribute,” “ignore,” “reassign,” “detect,” “execute,” “polling,” “register,” and “monitor” refer to the actions and processes of a device or similar electronic system that manipulate and transform data representing physical (e.g., electronic) quantities in the system’s registers and memories into other data similarly represented as physical quantities in the system’s memory or registers.

[0060] The terms “example” or “exemplary” are used herein to indicate that something is used as an example, instance, or illustration. Any aspect or design described herein as an “example” or “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present concepts in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or clearly understood from the context, “X includes A or B” is intended to indicate any natural inclusion substitution. That is, if X includes A, X includes B, or X includes both A and B, then “X includes A or B” is satisfied in any of the foregoing instances. Furthermore, the article “a” used in this application and the appended claims should generally be interpreted as meaning “one or more” unless otherwise stated or clearly indicated from the context to the singular form. Additionally, unless so described, the use of the terms “example” or “an example” or “an embodiment” or “an embodiment” throughout the text is not intended to represent the same example or embodiment.

[0061] The embodiments described herein may also relate to means for performing the operations described herein. Such means may be specifically constructed for the intended purpose (e.g., application-specific integrated circuit, ASIC), or may be an integrated circuit (IC) comprising a CPU subsystem capable of executing instructions stored as firmware in a non-transitory computer-readable storage medium. Such non-transitory computer-readable storage media may include, but is not limited to, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered as including a single medium storing one or more sets of instructions. The term "computer-readable medium" should also be considered as including any medium capable of storing, encoding, or carrying a set of instructions for execution by a means and causing the means to perform any one or more methods of this embodiment.

[0062] The foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., in order to provide a good understanding of several embodiments of the present disclosure. It should be understood that the foregoing description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description. Therefore, the scope of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A power field-effect transistor (FET) device instantiated on a first die, the power FET device comprising: First power FET; A second power FET is arranged back-to-back with the first power FET, wherein the first power FET and the second power FET are connected to a common drain node within the first die; A first replica FET, coupled to the common drain node, is configured to provide a sense current representing the load current flowing through the power FET device; and A second replica FET, coupled to the common drain node and configured to provide a sense voltage representing the voltage of the common drain node; and A current sensing circuit coupled to the first replica FET and the second replica FET, and configured to draw the sensed current through the first replica FET using the sensed voltage from the second replica FET.

2. The apparatus of claim 1, further comprising a current limiting circuit coupled to the current sensing circuit and configured to: Receive the sensed current from the current sensing circuit; A control signal is generated based on the sensed current; and The control signal is provided to the second power FET to control the load current flowing through the power FET device.

3. The apparatus according to claim 2, wherein, The current sensing circuit and the current limiting circuit are included in an integrated circuit (IC) controller instantiated on the second die.

4. The apparatus according to claim 3, wherein, The IC controller is configured as a Universal Serial Bus Power Delivery (USB-PD) controller.

5. The apparatus according to claim 3, wherein, The power FET device and the IC controller are housed within a single semiconductor package as a system-in-package (SiP).

6. The apparatus according to claim 1, wherein, The current sensing circuit is configured as follows: The voltage supplied by the second replica FET at the common drain node is detected; and A second voltage is generated to be applied to the source terminal of the first replica FET to match the drain-to-source voltage drop on the first power FET, thereby generating the sense current.

7. The apparatus according to claim 6, wherein, The second voltage on the first replica FET has the opposite polarity to that on the first power FET.

8. The apparatus according to claim 1, wherein, The current sensing circuit includes an operational amplifier configured as a closed-loop amplifier, wherein the sensed voltage is coupled to the non-inverting input of the operational amplifier, and wherein the inverting input of the operational amplifier is coupled to the first replica FET via a voltage divider.

9. The apparatus according to claim 1, wherein, The power FET device further includes: A third replica FET, coupled to the common drain node and configured to provide an additional sense voltage representing the voltage of the common drain node; and A fourth replica FET is coupled to the common drain node and configured to provide additional sensing current.

10. The apparatus according to claim 9, wherein, The first replica FET, the second replica FET, and the first power FET share a common first gate terminal, and the third replica FET, the fourth replica FET, and the second power FET share a common second gate terminal.

11. The apparatus according to claim 1, wherein, The first power FET and the second power FET are vertical FETs.

12. A power field-effect transistor (FET) device, comprising: A first power FET and a second power FET are arranged in series and electrically coupled through a common drain node, wherein the first power FET and the second power FET are configured to deliver an output current to a load in response to a first gate drive signal coupled to the first power FET through a first gate terminal of the power FET device and a second gate drive signal coupled to the second power FET through a second gate terminal of the power FET device; A first replica FET is used to provide a sensing current proportional to the output current; and A second replica FET is provided to provide a sensing voltage corresponding to the voltage of the common drain node, wherein the drains of the first replica FET and the second replica FET are coupled to the common drain node.

13. The power FET device according to claim 12, wherein, The gates of the first replica FET and the second replica FET are conductively coupled to the first gate terminal of the first power FET.

14. The power FET device of claim 12, further comprising a third replica FET and a fourth replica FET, wherein, The drains of the third and fourth replica FETs are coupled to the common drain node, and the gates of the third and fourth replica FETs are conductively coupled to the second gate terminal of the second power FET.

15. The power FET device according to claim 12, wherein, The first power FET and the second power FET are vertical FETs.

16. The power FET device of claim 12, wherein, The power FET device is instantiated on a first die, which is disposed within a semiconductor package as a system-in-package (SiP), wherein the semiconductor package further includes an integrated circuit (IC) controller instantiated on a second die.

17. The power FET device of claim 16, wherein, The integrated circuit (IC) controller also includes: A current sensing circuit is used to receive the sensed current; and A current limiting circuit is used to limit the output current to a specified value.

18. The power FET device of claim 17, wherein, The current limiting circuit is configured as follows: Receive the sensed current from the current sensing circuit; A control signal is generated based on the sensed current; and The control signal is provided to the second power FET to control the output current flowing through the power FET device.

19. The power FET device of claim 17, wherein, The current sensing circuit is configured as follows: The voltage supplied by the first replica FET at the common drain node is detected; and Generate a second voltage with the same magnitude as the voltage at the common drain node; The second voltage is applied to the first replica FET to generate the sensing current, wherein the second voltage on the first replica FET has the opposite polarity to that of the first power FET.

20. The power FET device of claim 16, wherein, The IC controller is configured as a Universal Serial Bus Power Delivery (USB-PD) controller.

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