Wide-range speed control method of high-voltage frequency converter and sampling and conditioning circuit

Abstract

The application provides a wide-range speed regulation control method and a sampling and conditioning circuit of a high-voltage frequency converter, and belongs to the technical field of high-voltage frequency converters.The application divides a working frequency range into three intervals by setting a frequency boundary threshold, adopts a three-phase acquisition unit to perform real-time sampling on the output voltage of the high-voltage frequency converter, performs a multi-path phase calculation strategy based on the frequency range, adopts an integral circuit to cooperate with 90-degree leading phase compensation when the frequency is high, adopts a low-pass filter circuit to perform non-lag processing when the frequency is low, adopts a smooth switching algorithm to weight and fuse two kinds of signals when the frequency is medium, adopts an adaptive PID control algorithm to perform feedback regulation, applies double-layer game to realize the coordinated balance of energy consumption and precision, and transmits the optimized control parameters to a driving port to realize wide-range speed regulation control, so that the technical problem that the high-voltage frequency converter is difficult to simultaneously ensure phase precision and speed regulation control stability in a wide frequency range is solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-voltage frequency converters, and particularly relates to a wide-range speed control method for a high-voltage frequency converter and a sampling and conditioning circuit. BACKGROUND

[0002] As a core device of industrial motor drive systems, high-voltage frequency converters are widely used in the speed control of high-power AC motors in heavy industrial fields such as petrochemical, steel, and power. Traditional high-voltage frequency converter speed control methods mainly use constant voltage-to-frequency ratio control strategies and vector control technologies to achieve precise control of motor speed by adjusting output frequency and voltage amplitude. They play an important role in various industrial production lines, fan and pump systems, and compressor drives. However, traditional technologies have significant defects when faced with wide frequency range speed control requirements, especially in high-frequency and low-frequency operating conditions. The phase detection accuracy is severely degraded, the 90-degree phase lag introduced by the integral circuit causes the control system to respond with a lag, and the signal amplitude attenuation and noise interference at low frequencies make the phase detection accuracy insufficient. There is a lack of effective signal processing strategies in the medium frequency transition region, and traditional single control strategies cannot dynamically balance energy consumption optimization and control accuracy. In existing technologies, due to the lack of adaptive signal processing mechanisms and multi-objective coordinated optimization strategies for different frequency ranges, the phase detection error accumulates severely when the high-voltage frequency converter operates in a wide frequency range, resulting in a decrease in speed control accuracy and deterioration of system stability. That is, there is a technical problem in existing technologies that high-voltage frequency converters cannot simultaneously ensure phase accuracy and speed control stability in a wide frequency range. SUMMARY

[0003] Therefore, the application provides a wide-range speed control method for a high-voltage frequency converter and a sampling and conditioning circuit, which can solve the technical problem in existing technologies that high-voltage frequency converters cannot simultaneously ensure phase accuracy and speed control stability in a wide frequency range.

[0004] The application is implemented as follows: The first aspect of the application provides a wide-range speed control method for a high-voltage frequency converter, which includes: setting speed control parameters of the high-voltage frequency converter, including target speed range, frequency boundary threshold and , phase compensation coefficient, and control accuracy requirement, establishing a set of initial state parameters for speed control; using a three-phase acquisition unit to perform real-time sampling on the output voltage of the high-voltage frequency converter to obtain digitized voltage signals; based on different ranges of the output frequency of the high-voltage frequency converter, a multi-path phase calculation strategy is executed, when the output frequency is greater than the frequency boundary threshold , high-frequency sampling signals output by the integral circuit are used and a 90-degree leading phase compensation operation is performed in the DSP calculation unit, when the output frequency is less than the frequency boundary threshold The low-frequency sampling signal output by the low-pass filter circuit is used for non-lagging phase calculation when the output frequency is between and The output results of the integral circuit and the low-pass filter circuit are weighted and fused by using a smooth switching algorithm when the output frequency is between and A convex optimization solving model for minimizing the speed error is established, the wide-range speed regulation control problem is converted into a parameter optimization problem under multiple constraint conditions, the Lagrange multiplier method is used to solve the optimal frequency adjustment and phase correction, adaptive feedback adjustment is performed based on the deviation between the target speed and the actual speed, and the adaptive PID control algorithm is used to calculate the frequency adjustment and the phase correction, the double-layer game coordination optimization model is applied to coordinate the system parameters, and the optimal control parameters output by the game coordination optimization model are transmitted to the drive port of the high-voltage frequency converter.

[0005] In the step of setting the speed regulation control parameters of the high-voltage frequency converter, 5 Hz is set, 2 Hz is set.

[0006] The three-phase acquisition unit includes three unit acquisition circuits with the same structure, each unit acquisition circuit converts the high voltage output by the high-voltage frequency converter into a digital signal through the cooperation of a sampling voltage dividing circuit, an anti-common-mode differential operational amplifier, an integral circuit, a low-pass filter circuit and an AD analog-to-digital conversion chip, and simultaneously outputs a high-frequency sampling signal and a low-frequency sampling signal.

[0007] The AD analog-to-digital conversion chip transmits the digitized high-frequency sampling signal and the low-frequency sampling signal to the DSP calculation unit through an SPI bus, and the DSP calculation unit calculates the phase information of the high-voltage frequency converter under high-frequency voltage, low-frequency voltage or medium-frequency voltage according to the signals from the AD analog-to-digital conversion chip.

[0008] The smooth switching algorithm is used to process the medium-frequency voltage signal between the frequency boundary threshold and , the output results of the integral circuit and the low-pass filter circuit are weighted and fused to calculate the medium-frequency voltage phase, and the weighting coefficients are dynamically determined according to the relative position of the current output frequency and the frequency boundary threshold and .

[0009] The convex optimization solving model is used to minimize the deviation between the target speed and the actual speed, the constraint conditions include the frequency change rate constraint, the phase change constraint, the power limitation constraint and the system stability constraint, the input includes the target speed, the actual speed, the frequency adjustment, the phase correction and the system power parameter, and the output is the optimal frequency adjustment and the phase correction that satisfy all the constraint conditions.

[0010] The frequency of the high-frequency sampling signal is the same as the frequency of the high-frequency voltage output by the high-voltage frequency converter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage frequency converter by 90 degrees.

[0011] The double-layer game coordination optimization model comprises an upper-layer energy consumption optimization model and a lower-layer precision optimization model, a target function of the upper-layer energy consumption optimization model is constituted by adding an exponential weighting term of system total power consumption and a logarithmic penalty term of switching loss, combining a product term of harmonic current and reciprocal of system efficiency, and finally adding an energy consumption precision coupling term, and a target function of the lower-layer precision optimization model is constituted by adding a product term of reciprocal of control precision standard deviation and reciprocal of response time, an exponential weighting term of stability index and robustness index, and finally subtracting the energy consumption precision coupling term.

[0012] The energy consumption precision coupling term is used to describe the mutual restraint relationship between energy consumption optimization and precision optimization, and the input comprises system total power consumption, control precision standard deviation, frequency adjustment amount, phase correction amount and load change rate, and the output is a coupling coefficient reflecting the trade-off strength between the two optimization targets.

[0013] The 90-degree leading phase compensation operation is used to offset the inherent 90-degree phase lag effect of the integral circuit, and ensure that the DSP calculation unit obtains accurate high-frequency voltage phase information.

[0014] The adaptive PID control algorithm dynamically adjusts proportional gain, integral gain and differential gain parameters according to the current frequency range and load conditions, the input comprises speed error, frequency range identifier and load characteristic parameters, and the output is the frequency adjustment amount and the phase correction amount.

[0015] The game equilibrium is used to find a stable state in which the upper-layer energy consumption optimization model and the lower-layer precision optimization model reach optimal solutions at the same time, and the coordination balance of energy consumption minimization and precision maximization is realized through iterative solution. The double-layer game coordination optimization model realizes the dynamic balance of system power consumption minimization and control precision maximization in a wide frequency range through the coordination mechanism of upper-layer energy consumption optimization and lower-layer precision optimization. The multi-path phase calculation strategy eliminates the technical defects of insufficient phase detection precision of the traditional single processing strategy in a wide frequency range by using different signal processing paths and phase compensation methods for different frequency ranges.

[0016] The second aspect of the application also provides a sampling and conditioning circuit for wide-range speed regulation control of the high-voltage frequency converter in the above method, the circuit comprising a high-voltage frequency converter, an AC motor and a load, the output end of the high-voltage frequency converter, the AC motor and the load being connected in sequence, characterized in that it further comprises a three-phase acquisition unit and a DSP calculation unit, the three-phase acquisition unit comprising three unit acquisition circuits of the same structure, each unit acquisition circuit comprising a sampling voltage division circuit, an anti-common-mode differential operational amplifier, an integration circuit, a low-pass filter circuit and an AD analog-to-digital conversion chip; the voltage output end of the high-voltage frequency converter is further connected to the input of the anti-common-mode differential operational amplifier through the sampling voltage division circuit, the output of the anti-common-mode differential operational amplifier is connected to the input of the integration circuit and the low-pass filter circuit, the output of the integration circuit and the low-pass filter circuit is connected to the input of the AD analog-to-digital conversion chip, and the output of the AD analog-to-digital conversion chip is connected to the input of the DSP calculation unit; the output of the DSP calculation unit is connected to the drive port of the high-voltage frequency converter; the anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage frequency converter through the sampling voltage division circuit; the integration circuit and the low-pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the voltage frequency of the high-voltage frequency converter through the anti-common-mode differential operational amplifier, respectively, and send them to the DSP calculation unit for calculation through the AD analog-to-digital conversion chip; the DSP calculation unit calculates the phase of the high-voltage frequency converter under high-frequency voltage, low-frequency voltage or medium-frequency voltage according to the signals from the AD analog-to-digital conversion chip.

[0017] The application effectively solves the problems of insufficient phase detection precision and single control strategy in the traditional technology by constructing a wide-range speed regulation control method based on a frequency adaptive multi-path phase calculation strategy and a double-layer game coordination optimization model. The application adopts a differentiated signal processing strategy of integral circuit high-frequency sampling with 90-degree leading phase compensation, low-pass filter circuit low-frequency sampling without lag processing and smooth switching algorithm weighted fusion for three different frequency ranges of high frequency, low frequency and medium frequency, eliminates the adverse effects of frequency change on phase detection precision, realizes accurate calculation of frequency adjustment and phase correction through a convex optimization solving model and an adaptive PID control algorithm, and reaches a dynamic balance between minimizing system power consumption and maximizing control precision through a double-layer game coordination mechanism composed of an upper-layer energy consumption optimization model and a lower-layer precision optimization model. In summary, the application solves the technical problem of difficulty in simultaneously ensuring phase precision and speed regulation control stability of a high-voltage frequency converter in a wide frequency range through the technical means of multi-path adaptive phase processing and game coordination optimization. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The flowchart of the method of the application.

[0019] Figure 2 is a block connection structure schematic diagram of example 2.

[0020] Figure 3 is a block connection structure schematic diagram of one unit acquisition circuit, high-voltage frequency converter, AC motor, load and DSP calculation unit in example 2.

[0021] Figure 4 is a circuit structure schematic diagram in example 2.

[0022] Figure 5 is a magnitude-frequency response characteristic diagram of a three-phase acquisition unit in example 3 at different frequencies.

[0023] Figure 6 is a comparison diagram of phase compensation effect in example 3.

[0024] Figure 7 is a test result diagram of speed control accuracy in example 3.

[0025] Figure 8 is a convergence process diagram of game optimization algorithm in example 3.

[0026] Figure 9 is a system overall performance evaluation result diagram in example 3.

[0027] The reference signs in the drawings are explained as follows: 1, common-mode rejection differential operational amplifier; 2, integral circuit; 3, low-pass filter circuit; 4, AD analog-digital conversion chip; 5, DSP calculation unit; 6, high-voltage frequency converter; 7, AC motor; 8, load; 9, sampling voltage division circuit; 10, three-phase acquisition unit; 11, unit acquisition circuit. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0029] As shown in Figure 1 , it is a flow chart of a wide-range speed control method of a high-voltage frequency converter provided by the first aspect of the present application, and the method comprises the following steps:

[0030] S01, setting the speed control parameters of the high-voltage frequency converter, including the target speed range, the frequency boundary threshold ω1 and ω2, the phase compensation coefficient and the control accuracy requirement, establishing the initial state parameter set of the speed control, wherein ω1 is set to 5 Hz and ω2 is set to 2 Hz;

[0031] S02, the output voltage of the high-voltage frequency converter is sampled in real time by a three-phase acquisition unit, the three-phase acquisition unit includes three unit acquisition circuits with the same structure, each unit acquisition circuit includes a sampling voltage dividing circuit, an anti-common-mode differential operational amplifier, an integration circuit, a low-pass filter circuit and an AD analog-to-digital conversion chip, the sampling voltage dividing circuit converts the high voltage output by the high-voltage frequency converter into a low voltage signal and sends it to the input end of the anti-common-mode differential operational amplifier, and the anti-common-mode differential operational amplifier processes the sampling signal and simultaneously sends it to the integration circuit and the low-pass filter circuit;

[0032] S03, a multi-path phase calculation strategy is executed based on different ranges of the output frequency of the high-voltage frequency converter, when the output frequency is greater than the frequency boundary threshold ω1, the high-frequency sampling signal output by the integration circuit is used and a 90-degree leading phase compensation operation is performed in the DSP calculation unit, when the output frequency is less than the frequency boundary threshold ω2, the low-frequency sampling signal output by the low-pass filter circuit is used for no-lag phase calculation, and when the output frequency is between ω1 and ω2, a smooth switching algorithm is used to weight and fuse the output results of the integration circuit and the low-pass filter circuit;

[0033] S04, a convex optimization solving model for minimizing speed error is established, the wide-range speed control problem is converted into a parameter optimization problem under multiple constraint conditions, the optimal frequency adjustment and phase correction are solved by using the Lagrange multiplier method, and accurate speed control of the high-voltage frequency converter in a wide frequency range is realized;

[0034] S05, adaptive feedback adjustment is performed based on the deviation between the target speed and the actual speed, the frequency adjustment and the phase correction are calculated by using the adaptive PID control algorithm, and the driving parameters of the high-voltage frequency converter are dynamically updated to reduce the speed error;

[0035] S06, a double-layer game coordination optimization model is applied to coordinate the system parameters, the upper energy consumption optimization model optimizes the frequency adjustment strategy by a combination function of exponential weighted sum and logarithmic penalty with the goal of minimizing the total system power consumption, the lower precision optimization model optimizes the phase compensation parameters by a product type objective function with the goal of maximizing the control precision, and the coordination and balance of energy consumption and precision are realized through game equilibrium;

[0036] S07, the optimal control parameters output by the game coordination optimization model are transmitted to the driving port of the high-voltage frequency converter, wide-range speed control of the alternating current motor is realized, and the output state is continuously monitored for closed-loop adjustment to maintain stable operation of the system.

[0037] The smooth switching algorithm is used to process the medium frequency voltage signal between the frequency boundary thresholds ω1 and ω2, the medium frequency voltage phase is calculated by weighting and fusing the output results of the integration circuit and the low-pass filter circuit, and the weighting coefficients are dynamically determined according to the relative positions of the current output frequency and the frequency boundary thresholds ω1 and ω2.

[0038] The objective function of the convex optimization solution model is used to minimize the deviation between the target speed and the actual speed, the constraint conditions include the frequency change rate constraint, the phase change constraint, the power limit constraint and the system stability constraint, the inputs include the target speed, the actual speed, the frequency adjustment amount, the phase correction amount and the system power parameters, and the output is the optimal frequency adjustment amount and the phase correction amount that meet all the constraint conditions.

[0039] The adaptive PID control algorithm dynamically adjusts the proportional gain, integral gain and derivative gain parameters according to the current frequency range and load conditions, the inputs include the speed error, the frequency range identifier and the load characteristic parameters, and the output is the frequency adjustment amount and the phase correction amount.

[0040] The double-layer game coordination optimization model includes an upper-layer energy consumption optimization model and a lower-layer precision optimization model, the objective function of the upper-layer energy consumption optimization model is composed of an exponential weighting term of the total system power consumption, a logarithmic penalty term of the switching loss, a product term of the harmonic current and the reciprocal of the system efficiency, and finally an energy consumption precision coupling term, and the objective function of the lower-layer precision optimization model is composed of a product term of the reciprocal of the control precision standard deviation and the reciprocal of the response time, an exponential weighting term of the stability index and the robustness index, and finally a subtraction of the energy consumption precision coupling term.

[0041] The energy consumption precision coupling term is used to describe the mutual restraint relationship between energy consumption optimization and precision optimization, the inputs include the total system power consumption, the control precision standard deviation, the frequency adjustment amount, the phase correction amount and the load change rate, and the output is a coupling coefficient reflecting the trade-off strength between the two optimization objectives.

[0042] The game equilibrium is used to find a stable state where the upper-layer energy consumption optimization model and the lower-layer precision optimization model reach the optimal solution at the same time, and the coordination balance between energy consumption minimization and precision maximization is achieved through iterative solution.

[0043] The frequency of the high-frequency sampling signal is the same as the frequency of the high-frequency voltage output by the high-voltage frequency converter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage frequency converter by 90 degrees.

[0044] The frequency of the low-frequency sampling signal is the same as the frequency of the low-frequency voltage output by the high-voltage frequency converter, and the phase of the low-frequency sampling signal has no lag phenomenon.

[0045] The 90-degree leading phase compensation operation is used to offset the inherent 90-degree phase lag effect of the integral circuit, ensuring that the DSP calculation unit obtains accurate high-frequency voltage phase information.

[0046] The specific implementation of step S01 is to first determine the target speed range according to the load characteristics and process requirements, and usually set the speed ratio of the highest speed to the lowest speed to be more than 100 to 1 to meet the wide range speed regulation requirement. Then set the frequency boundary threshold ω1 to 5 Hz and ω2 to 2 Hz, which are used to distinguish the processing methods of high frequency, medium frequency and low frequency voltage signals, wherein signals above 5 Hz are processed by an integral circuit, and signals below 2 Hz are processed by a low-pass filter circuit. Then configure the phase compensation coefficient, usually set to a value between 0.8 and 1.2, which is used to correct the 90-degree phase lag introduced by the integral circuit. Finally, set the control accuracy requirement, the speed accuracy error is controlled within 0.1% of the target speed, and establish the initial state parameter set of the speed regulation control containing the parameters. The purpose of the step is to provide basic parameter configuration for subsequent wide range speed regulation control, and ensure that the system has accurate control reference under different working conditions.

[0047] The specific implementation of step S02 is to synchronously sample the three-phase output voltage of the high-voltage frequency converter through the three-phase acquisition unit. Each unit acquisition circuit first reduces the kilovolt-level voltage output by the high-voltage frequency converter to a volt-level low voltage signal through a voltage dividing network composed of a sixth voltage dividing resistor R6 and a seventh voltage dividing resistor R7 by a sampling voltage dividing circuit. The sixth voltage dividing resistor R6 is usually selected to have a megohm-level resistance value, and the seventh voltage dividing resistor R7 is selected to have a kilohm-level resistance value, and the voltage dividing ratio is set to be between 1000 to 1 and 10000 to 1. The reduced signal enters the anti-common-mode differential operational amplifier, which is composed of a first operational amplifier U1, a bidirectional TVS diode DZ1 and a first resistor R1, wherein the bidirectional TVS diode DZ1 is used for overvoltage protection, the first resistor R1 is used for current limiting, and the first operational amplifier U1 amplifies the differential signal and suppresses common-mode interference. The signal output by the anti-common-mode differential operational amplifier is sent to the integral circuit and the low-pass filter circuit at the same time. The integral circuit is composed of a second operational amplifier U2, a second resistor R2, a third resistor R3 and a first capacitor C1 to form an inverting integrator structure, and the low-pass filter circuit is composed of a third operational amplifier U3, a fourth resistor R4, a fifth resistor R5 and a second capacitor C2 to form an active low-pass filter structure. The step uses the principle of analog signal processing to realize linear transformation and filtering processing of the signal through the virtual short and virtual open characteristics of the operational amplifier. The relevance of the circuit design is to provide different processing paths for signals of different frequency ranges.

[0048] The specific implementation of step S03 is to perform a segmented phase calculation strategy according to the numerical range of the output frequency of the high-voltage frequency converter. When it is detected that the output frequency is greater than the frequency boundary threshold ω1, i.e., 5 Hz, the DSP calculation unit selects the high-frequency sampling signal output by the integration circuit as the processing object. Due to the transfer function characteristics of the integration circuit, the output signal lags behind the input signal by 90 degrees, so the DSP calculation unit performs a 90-degree lead compensation operation on the phase information output by the integration circuit to obtain the true high-frequency voltage phase. When it is detected that the output frequency is less than the frequency boundary threshold ω2, i.e., 2 Hz, the DSP calculation unit selects the low-frequency sampling signal output by the low-pass filter circuit. Since the phase response of the low-pass filter circuit is close to zero degrees in the low-frequency range, the phase information of the signal is directly used for calculation. When the output frequency is in the medium frequency range of 2 Hz to 5 Hz, a smooth switching algorithm is used to weight and fuse the outputs of the integration circuit and the low-pass filter circuit. The weighting coefficient is determined according to the distance between the current frequency and the boundary frequency in a linear interpolation manner. The step uses a segmented processing principle to avoid the performance limitations of a single processing method in the full frequency range by frequency segmentation, ensuring accurate phase information in a wide frequency range.

[0049] The specific implementation of step S04 is to model the wide-range speed regulation control problem as a convex optimization problem under multiple constraint conditions. The input parameters include the target speed, the actual speed, the current frequency, the current phase, and the load torque. The output parameters are the optimal frequency adjustment and the phase correction. First, a target function is constructed with the sum of the squares of the speed error as the main term. Penalty terms for the frequency change rate and the phase change rate are added to avoid drastic changes in control. The constraint conditions include the frequency change rate constraint, which is usually limited to a change speed of not more than 1 Hz per second, the phase change constraint, which is limited to a change amplitude of not more than 5 degrees per control period, the power limit constraint, which ensures that the output power does not exceed 110% of the rated power of the frequency converter, and the stability constraint, which ensures the convergence of the system through the Lyapunov function. The Lagrange multiplier method is used to convert the constrained optimization problem into an unconstrained optimization problem, and the gradient descent algorithm is used to iteratively solve the optimal solution. The step uses convex optimization theory to ensure the uniqueness and stability of the solution using the global optimality of convex functions. The relevance to speed regulation control is that the complex multivariable control problem is converted into a standard mathematical optimization problem.

[0050] The specific implementation of step S05 is to realize closed-loop feedback control based on the deviation amount of the target speed and the actual speed, the input parameters include the speed error, the time integral of the speed error and the time differential of the speed error, and the output parameters are the frequency adjustment amount and the phase correction amount. First, the speed error is calculated as a proportional control item, then the time integral of the speed error is calculated as an integral control item to eliminate the steady-state error, and then the time differential of the speed error is calculated as a differential control item to improve the dynamic response. The adaptive PID control algorithm dynamically adjusts three gain parameters according to the current frequency range and the load change. In the high frequency range, the proportional gain is increased to improve the response speed, in the low frequency range, the integral gain is increased to reduce the steady-state error, and in the load mutation, the differential gain is increased to suppress the overshoot. The adjustment of the gain parameters adopts the fuzzy logic control principle, and the inference is carried out according to the preset fuzzy rule base and membership function. The step adopts the PID control principle in the classical control theory, and realizes online adjustment of parameters combined with the adaptive control idea. The relevance to the wide-range speed regulation lies in providing differentiated control strategies for different frequency ranges and load conditions.

[0051] The specific implementation of step S06 is to construct a double-layer game structure of the upper energy consumption optimization model and the lower precision optimization model. The input parameters of the upper model include the system total power consumption, the switching loss, the harmonic current, the system efficiency and the energy consumption precision coupling item, and the output parameter is the optimal frequency adjustment strategy. The input parameters of the lower model include the control precision standard deviation, the response time, the stability index, the robustness index and the energy consumption precision coupling item, and the output parameter is the optimal phase compensation parameter. The upper model adopts a combination function structure of exponential weighting and logarithmic penalty, amplifies the influence of power consumption change through an exponential function, and smoothes the fluctuation of switching loss through a logarithmic function. The final objective function is a nonlinear combination of each item. The lower model adopts a product type objective function structure, and multiplies the reciprocals of the precision related indexes to realize multi-objective collaborative optimization. The game solution adopts the Nash equilibrium theory, and finds a stable solution that makes both parties optimal through an iterative algorithm. The step adopts the game theory principle, and models the energy consumption optimization and the precision optimization as a competitive and cooperative relationship. The relevance to the wide-range speed regulation control lies in realizing multi-objective coordinated optimization of system performance.

[0052] The specific implementation of step S07 is to convert the optimal control parameters output by the game coordination optimization model into PWM driving signals through a digital signal processor, drive the power switching devices of the high-voltage frequency converter to generate the required three-phase alternating voltage. First, the optimal frequency adjustment amount is converted into a carrier frequency parameter, and a reference signal corresponding to the frequency is generated through a sine wave modulation algorithm. Then, the optimal phase correction amount is converted into a phase offset parameter, and a 120-degree phase difference and a phase correction amount are respectively applied to the three-phase reference signals. Next, the space vector pulse width modulation technology is used to convert the reference signals into driving pulse sequences of the switching devices, and the duty cycle of the driving signals is dynamically adjusted according to the voltage amplitude requirement. At the same time, the state monitoring module is started to continuously collect the operating parameters of the motor such as speed, current and temperature, and compare them with the target values to form new control deviations. When the detected deviation exceeds the preset threshold, the aforementioned control steps are re-executed to form a closed-loop regulation. The step uses the pulse width modulation principle and closed-loop control theory to realize accurate control of voltage and frequency through the high-frequency on-off of the switching devices. The relevance to wide-range speed regulation lies in converting digital control instructions into analog voltage output to drive the motor to run.

[0053] The key technical ideas of the method of the application include a multi-path phase calculation strategy, a double-layer game coordination optimization, and an adaptive circuit signal processing. The multi-path phase calculation strategy uses a segmented processing method of integrating circuit processing high-frequency signals, low-pass filter circuit processing low-frequency signals, and smooth switching algorithm processing medium-frequency signals, which has a high-precision technical effect in the full frequency range compared to the traditional single filter method, solves the technical problems of insufficient precision in the extremely low frequency range and slow response in the extremely high frequency range of the traditional method, and realizes the technical advantage of expanding the frequency range by more than 100 times. The double-layer game coordination optimization uses the competitive and cooperative mechanism of the upper energy consumption model and the lower precision model, which has the technical effect of multi-objective coordination and balance compared to the traditional single-objective optimization method, avoids the performance compromise problem caused by the mutual restriction of energy consumption and precision in the traditional method, and realizes the technical advantage of optimizing the overall performance of the system. The adaptive circuit signal processing uses analog signal preprocessing of anti-common-mode differential operational amplifier, integrating circuit and low-pass filter circuit, which has the technical effects of high signal-to-noise ratio and strong real-time compared to the traditional pure digital processing method, reduces the quantization error and delay problem in digital sampling, and improves the weak signal detection capability and fast response characteristics. The synergistic effect of the three key technical ideas lies in that the multi-path phase calculation provides accurate state information for game optimization, the game optimization provides optimal parameter configuration for adaptive control, and the adaptive circuit processing provides high-quality signal source for phase calculation, forming a positive cycle of information flow and mutual promotion of performance, which realizes the synergistic effect of the system level compared to the traditional independent design method, and simultaneously achieves the technical targets of high-precision control and low-energy consumption operation in a wide frequency range.

[0054] In addition, the second aspect of the present application provides a specific embodiment of the sampling and conditioning circuit, which is that the three-phase output voltage of the high-voltage frequency converter is synchronously sampled and processed by a three-phase acquisition unit, the three-phase acquisition unit includes three unit acquisition circuits which are completely identical in structure, each unit acquisition circuit corresponds to one phase output of the high-voltage frequency converter, and the independent sampling and signal conditioning of the A-phase, B-phase and C-phase voltage are realized. Each unit acquisition circuit internally integrates key functional modules such as a sampling and dividing circuit, a common-mode rejection differential operational amplifier, an integration circuit, a low-pass filter circuit and an AD analog-to-digital conversion chip, and through the organic combination of analog signal processing and digital conversion, the frequency and phase information of the output voltage of the high-voltage frequency converter are accurately extracted.

[0055] The specific embodiment of the sampling and dividing circuit is that a resistance dividing network is used to reduce the kilovolt-level output voltage of the high-voltage frequency converter to a voltage level suitable for subsequent circuit processing, one end of the sixth dividing resistor R6 is directly connected to the voltage output end of the high-voltage frequency converter and is connected to the input end of the alternating current motor at the same time, forming a voltage sampling point, the other end of the sixth dividing resistor R6 is connected to one end of the seventh dividing resistor R7, constituting a dividing node, the node is connected to the input end of the common-mode rejection differential operational amplifier at the same time, and the other end of the seventh dividing resistor R7 is grounded, forming a complete dividing loop. The sixth dividing resistor R6 is usually selected as a high-resistance resistor of the order of megohm, and the typical value is 10MΩ to 100MΩ, so as to ensure that the influence on the output current of the high-voltage frequency converter is minimized, the seventh dividing resistor R7 is selected as a resistor of the order of kilohm, and the typical value is 10kΩ to 100kΩ, through reasonable resistance ratio design, a dividing ratio of 1000:1 to 10000:1 is realized, and the kilovolt-level high voltage is safely and reliably converted into a low-voltage signal below 5V.

[0056] The specific embodiment of the anti-common-mode differential operational amplifier is to realize differential amplification of signals and common-mode interference suppression by using high-precision differential amplifier and protection circuit. The first operational amplifier U1 uses a differential amplifier chip, such as AD629AR chip, which has the characteristics of high input impedance, low offset voltage and strong common-mode suppression capability. The bidirectional TVS diode DZ1 is connected in parallel with the first resistor R1 between the inverting input terminal and the non-inverting input terminal of the first operational amplifier U1, forming an input protection network. The bidirectional TVS diode DZ1 selects a device with a breakdown voltage of 6V to 15V for clamping overvoltage signals to prevent electrostatic discharge and transient overvoltage from damaging the operational amplifier. The first resistor R1 selects a current-limiting resistor of 1kΩ to 10kΩ to cooperate with the TVS diode to limit fault current. The output terminal of the first operational amplifier U1 is connected to the input terminals of the integration circuit and the low-pass filter circuit at the same time, realizing the signal distribution function of one-way input and double-way output. The anti-common-mode differential operational amplifier amplifies the differential signal provided by the sampling and dividing circuit, and reverses the polarity of the signal at the same time, that is, the output signal is 180 degrees out of phase with the input signal, providing a standardized signal interface for the subsequent circuit.

[0057] The specific embodiment of the integration circuit is to realize the integration operation of the input signal by using an active integrator structure, which is used to process high-frequency voltage signals. One end of the second resistor R2 is connected to the output terminal of the anti-common-mode differential operational amplifier as the input resistor of the integration circuit. The other end of the second resistor R2 is connected to the inverting input terminal of the second operational amplifier U2, forming a virtual ground node. The first capacitor C1 and the third resistor R3 are connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier U2, forming an integration feedback network. The first capacitor C1 is an integration capacitor, and its capacitance determines the integration time constant. The typical value is 0.1μF to 1μF. The third resistor R3 is a discharge resistor that prevents the output saturation of the operational amplifier caused by the input bias current. Its resistance is usually 1MΩ to 10MΩ. The non-inverting input terminal of the second operational amplifier U2 is connected to the analog ground, ensuring that the operational amplifier works in the linear region. The second operational amplifier U2 uses a low-noise and high-precision operational amplifier, such as OP284ES chip. The output terminal of the integration circuit is directly connected to the input channel of the AD analog-to-digital conversion chip. The integration circuit has an amplitude-frequency characteristic of -20dB per decade and a constant phase characteristic of -90 degrees in the frequency domain, which is particularly suitable for processing high-frequency signals and can provide a stable phase reference while maintaining the signal amplitude.

[0058] The specific embodiment of the low-pass filter circuit is to realize selective amplification of low-frequency signals and effective suppression of high-frequency interference by using an active low-pass filter structure, which is used for processing low-frequency voltage signals. One end of the fifth resistor R5 is connected to the output end of the anti-common-mode differential operational amplifier, and receives the same input signal in parallel with the integration circuit. The other end of the fifth resistor R5 is connected to the inverting input end of the third operational amplifier U3, serving as the input resistance of the filter circuit. The second capacitor C2 is connected in parallel with the fourth resistor R4 between the inverting input end and the output end of the third operational amplifier U3, constituting a feedback network of the low-pass filter. The second capacitor C2 is a filter capacitor, and its capacitance value and the resistance value of the fourth resistor R4 together determine the cutoff frequency of the filter. By reasonable design, the cutoff frequency is located between 2Hz and 5Hz, ensuring good pass performance of low-frequency signals and effective suppression of high-frequency noise. The fourth resistor R4 is a feedback resistor, which determines the passband gain of the filter. The resistance ratio of the fourth resistor R4 and the fifth resistor R5 determines the amplification factor. The non-inverting input end of the third operational amplifier U3 is connected to the analog ground, and the same type of operational amplifier chip as the integration circuit is used to ensure the consistency and comparability of the two signal processing paths. The output end of the low-pass filter circuit is connected to another input channel of the AD analog-to-digital conversion chip. The filter circuit has a flat amplitude-frequency response and a phase response close to zero below the designed cutoff frequency, which is particularly suitable for precise processing of very low-frequency signals.

[0059] The specific embodiment of the AD analog-to-digital conversion chip is to realize the conversion of analog signals to digital signals by using a high-precision analog-to-digital converter with multiple channels and synchronous sampling. The AD analog-to-digital conversion chip selects AD7606 type chip, which has 16-bit resolution, 8 differential input channels, synchronous sampling, and SPI interface. The output signals of the integration circuit and the low-pass filter circuit are connected to different input channels of the AD analog-to-digital conversion chip, ensuring the time reference consistency of the two signals through synchronous sampling. The sampling frequency is set to 10kHz to 100kHz, meeting the Nyquist theorem requirements for signal sampling in a wide frequency range. The AD analog-to-digital conversion chip integrates input buffer, sample-and-hold circuit, successive approximation type analog-to-digital converter, and digital interface circuit, which can convert analog voltage signals to 16-bit digital quantities with conversion accuracy of 0.0015%, meeting the requirements of high-precision phase detection. The AD analog-to-digital conversion chip communicates data with the DSP computing unit through the SPI bus. The SPI interface includes chip select signal CS, clock signal SCLK, master out slave in signal MISO, and master in slave out signal MOSI. The data transmission rate can reach 20Mbps, ensuring real-time requirements.

[0060] The specific embodiment of the DSP computing unit is to realize the phase calculation and the execution of the control algorithm by using a high-performance digital signal processor. The DSP computing unit selects a TMS320F28377S type DSP chip, which has a working frequency of 200MHz, a dual-core CPU architecture and a rich peripheral interface. The DSP computing unit receives digitized sampling data from an AD analog-to-digital conversion chip through an SPI interface, executes a corresponding phase calculation algorithm according to the output frequency range of the current high-voltage frequency converter, adopts integral circuit data and executes 90-degree lead compensation when the frequency is greater than 5Hz, directly adopts low-pass filter circuit data when the frequency is less than 2Hz, and adopts a smooth switching algorithm for data fusion processing when the frequency is between 2Hz and 5Hz. The output of the DSP computing unit is connected to the control port of the high-voltage frequency converter through a driving interface, and the output signal includes a frequency control instruction, a phase control instruction and an amplitude control instruction, which provides accurate vector control parameters for the high-voltage frequency converter and realizes the technical goal of wide-range speed regulation control. Through the organic combination of analog signal processing and digital signal processing, the high-precision detection of the output voltage frequency and phase of the high-voltage frequency converter is realized, and a reliable technical foundation is provided for accurate speed regulation control in a wide frequency range.

[0061] Specifically, the principle of the present application is that the present application can solve the fundamental principle of the high-voltage frequency converter wide frequency range phase accuracy and speed stability problem lies in the establishment of the frequency adaptive multi-path signal processing mechanism and multi-objective coordination optimization framework. The reason why the traditional technology performs poorly in a wide frequency range is mainly because a single signal processing path and a fixed control strategy are adopted, which cannot adapt to the significant difference in signal characteristics at different frequencies. The present application divides the entire working frequency range into high, low and medium frequency intervals by setting the frequency boundary thresholds ω1 and ω2, adopts different processing strategies for the signal characteristics of each interval, uses the high-frequency response characteristics of the integration circuit to obtain accurate amplitude information in the high-frequency region, and at the same time, performs 90-degree leading phase compensation through the DSP calculation unit to offset the inherent phase lag of the integration circuit, adopts a low-pass filter circuit in the low-frequency region to suppress high-frequency noise interference and maintain the phase lag-free characteristic, and through the smooth switching algorithm, the two signal processing results are dynamically weighted and fused in the medium frequency transition region, avoiding signal mutation when the frequency switches. At the control strategy level, the present application constructs a convex optimization solving model with the minimum speed error as the target, converts the complex wide-range speed control problem into a parameter optimization problem under multiple constraint conditions, solves the optimal solution through the Lagrange multiplier method, ensures the global optimality of the control parameters, and the adaptive PID control algorithm dynamically adjusts the control parameters according to the current frequency range and load conditions, enhancing the adaptive ability of the system. The design concept of the double-layer game coordination optimization model is to regard energy optimization and precision optimization as two game subjects that restrict and depend on each other, the upper model optimizes the frequency adjustment strategy through the combination function of the exponential weighted sum and the logarithmic penalty to minimize the system power consumption, the lower model optimizes the phase compensation parameters through the product type target function to maximize the control precision, and the energy precision coupling term between the two models realizes information interaction and constraint transmission, and the game equilibrium mechanism ensures that the two optimization targets can always maintain the optimal coordinated balance state under the dynamic changing working conditions, which theoretically guarantees that the system can meet the requirements of phase accuracy and speed stability in any frequency range.

[0062] A specific embodiment 1 of the method provided by the present application is provided below, and the specific implementation of each step in the embodiment 1 is described in detail as follows.

[0063] In this embodiment, the specific implementation of step S01 is the same as described above, and will not be described in detail here.

[0064] The specific implementation of step S02 is to sample the output voltage of the high-voltage frequency converter by the three-phase acquisition unit, and the voltage division ratio calculation formula of the sampling voltage division circuit is as follows:

[0065] ;

[0066] In the formula, is a voltage division ratio; is a sixth voltage division resistor resistance value; is a seventh voltage division resistor resistance value.

[0067] The output voltage of the common-mode rejection differential operational amplifier is represented as:

[0068] ;

[0069] In the formula, is the output voltage of the common-mode rejection differential operational amplifier; is a magnification, which is usually set to 10-50; is a non-inverted input voltage; is an inverted input voltage.

[0070] The transfer function of the integration circuit is:

[0071] ;

[0072] In the formula, is the transfer function of the integration circuit in the Laplace domain; is a Laplace operator; is a second resistor resistance value, typically 10kΩ-100kΩ; is a first capacitor capacitance value, typically 0.1μF-1μF.

[0073] The transfer function of the low-pass filter circuit is:

[0074] ;

[0075] In the formula, is the transfer function of the low-pass filter circuit; is a fourth resistor resistance value; is a fifth resistor resistance value; is a second capacitor capacitance value.

[0076] The parameter acquisition method is: The experimental measurement method is adopted, and a digital multimeter is used to measure the resistance value in a power-off state; The same method is adopted; The output voltage ratio is determined by inputting a standard signal from a signal generator and measuring the output voltage ratio; and It is obtained by measuring the capacitance tester.

[0077] The specific implementation of step S03 is to perform segmented phase calculation according to the output frequency of the high-voltage frequency converter, and the phase fusion formula of the smooth switching algorithm is as follows:

[0078] ;

[0079] In the formula, The phase of the intermediate frequency voltage; This refers to the phase information of the output signal of the integrator circuit after it is 90 degrees ahead of the DSP computing unit. This refers to the phase information of the output signal of the low-pass filter circuit. This is the current output frequency; The high-frequency boundary threshold is set to 5Hz; The low-frequency boundary threshold is set to 2Hz.

[0080] The high-frequency phase compensation formula is:

[0081] ;

[0082] In the formula, The compensated high-frequency phase; This represents the original phase output by the integrator circuit.

[0083] The low-frequency phase can be directly expressed using the formula:

[0084] ;

[0085] In the formula, Low-frequency phase; This is the output phase of the low-pass filter circuit.

[0086] The parameter acquisition method is as follows: The frequency domain peak value is obtained by sampling through an AD analog-to-digital converter chip and then calculating it using a fast Fourier transform. and The instantaneous phase is obtained by calculating the Hilbert transform.

[0087] The specific implementation of step S04 is to establish a convex optimization solution model, and the objective function is expressed as:

[0088] ;

[0089] In the formula, The objective function value; This represents the number of sampling points; For the first The target rotational speed at each sampling point; For the first The actual rotational speed at each sampling point; For the first Frequency adjustment amount per sampling point; For the first Phase correction amount per sampling point; The weighting coefficient is adjusted for frequency, with a typical value of 0.01 to 0.1; The phase correction weight coefficient is typically 0.005-0.05.

[0090] The constraint matrix is represented as:

[0091] ;

[0092] In the formula, is the equality constraint coefficient matrix; is the inequality constraint coefficient matrix; is the equality constraint right end vector; is the inequality constraint right end vector; is the frequency adjustment vector; is the phase correction vector.

[0093] The Lagrange function is:

[0094] ;

[0095] In the formula, is the Lagrange function; is the Lagrange multiplier vector; is the constraint coefficient matrix; is the decision variable vector; is the constraint right end vector.

[0096] The parameter acquisition method is: It is set by the upper computer and obtained through the communication interface; It is obtained by measuring the rotating speed through the encoder and through filtering processing; and The optimal value is determined through system identification experiment.

[0097] The specific implementation of step S05 is to use an adaptive PID control algorithm, and the PID controller output formula is:

[0098] ;

[0099] In the formula, is the output of the controller at time ; is the proportional gain; is the integral gain; is the differential gain; is the rotating speed error at time ; is the rotating speed error at time .

[0100] The adaptive gain adjustment formula is:

[0101] ;

[0102] ;

[0103] ;

[0104] wherein, 、 、 is a base gain parameter; 、 、 is an adaptive adjustment coefficient, and a typical value range is 0.1-0.5; is a current output frequency.

[0105] The rotation speed error calculation formula is:

[0106] ;

[0107] wherein, is a reference rotation speed; is a measured rotation speed.

[0108] The parameter acquisition method is: 、 、 obtained through a step response experiment debugging; obtained by a speed regulation instruction calculation; obtained by real-time measurement through a rotation speed sensor.

[0109] The specific implementation of step S06 is to construct a double-layer game coordination optimization model. The objective function of the upper-layer energy consumption optimization model is:

[0110] ;

[0111] wherein, is the upper-layer model objective function; is the total power consumption of the system; is the switching loss change amount; is the effective value of the harmonic current; is the system efficiency; is the energy consumption accuracy coupling term; 、 、 is a weight coefficient, and a typical value range is 0.1-1.0; is an exponential adjustment coefficient, and a typical value is 0.01-0.1.

[0112] The objective function of the lower-layer accuracy optimization model is:

[0113] ;

[0114] wherein, is the lower model objective function; is the control accuracy standard deviation; is the system response time; is the stability index; is the robustness index; , , , is the weight coefficient, and a typical value range is 0.1-2.0.

[0115] The energy consumption accuracy coupling term calculation formula is:

[0116] ;

[0117] In the formula, , , is the coupling coefficient; is the frequency adjustment amplitude; is the phase correction amplitude; is the load change rate.

[0118] The game equilibrium condition is:

[0119] ;

[0120] In the formula, is the upper decision variable; is the lower decision variable; is the gradient operator.

[0121] The parameter acquisition method is: obtained by real-time measurement through a power sensor; obtained by calculating the speed deviation of the last 100 control cycles; obtained by step response test measurement; the coupling coefficient is determined by multi-objective optimization experiment calibration.

[0122] The specific implementation of step S07 is the same as the foregoing, and will not be described in detail here.

[0123] It should be noted that the anti-common-mode differential operational amplifier formula Based on the differential amplification principle of the operational amplifier, through the protection network of the bidirectional TVS diode and the current limiting resistor, the differential amplification of the voltage signal after voltage division and the common-mode interference suppression are realized. Compared with the traditional single-ended amplification mode, the circuit design has stronger anti-interference ability, can effectively suppress the electromagnetic interference and common-mode noise generated during the operation of the high-voltage frequency converter, improve the signal-to-noise ratio, and ensure that stable and reliable voltage sampling signals can be obtained in a complex electromagnetic environment, laying a foundation for the precision guarantee of wide-range speed control.

[0124] Integral circuit transfer function The frequency domain characteristics of an ideal integrator are embodied, the amplitude-frequency response attenuates with increasing frequency, and the phase-frequency response is fixedly lagged by 90 degrees. The integral circuit plays a role of frequency adaptive filtering in wide range speed control of high voltage frequency converter, has good tracking performance for high frequency signals, compared with a traditional fixed cutoff frequency filter, can maintain high signal amplitude and stable phase relationship in a high frequency band, solves the problem of detection precision decline caused by serious signal attenuation in a high frequency band in a traditional method, and realizes accurate extraction of phase information in a high frequency band.

[0125] Low pass filter circuit transfer function A standard form of a first-order active low pass filter is constituted, the cutoff frequency is determined by the product of resistance and capacitance, and the gain in the passband is determined by the resistance ratio. The low pass filter circuit is designed for low frequency signals, has better low frequency selectivity and noise suppression capability than traditional wideband filters, can effectively filter out high frequency interference and noise, maintain the integrity and phase accuracy of low frequency signals, and solve the technical problem that signals are weak and susceptible to interference in an extremely low frequency band in a traditional method, thereby providing a reliable signal processing basis for low speed disc turning and other application scenarios.

[0126] Smooth switching algorithm formula The linear interpolation principle is adopted to realize smooth transition of the output results of the integral circuit and the low pass filter circuit in a medium frequency band. The algorithm avoids the phase jump problem at the switching point in the traditional segmented control method through continuous change of the weighting coefficient, can significantly reduce oscillation and instability of the control system compared with the hard switching mode, ensures the continuity and smoothness of the phase information in the entire wide frequency range, and solves the problems of control precision decline and system oscillation caused by switching mutation in the traditional multi-path signal processing.

[0127] High frequency phase compensation formula Based on the inherent 90-degree phase lag characteristic of the integral circuit, the phase delay of the analog integral circuit is offset through phase advance compensation in the digital domain. The compensation strategy has the advantages of high precision, flexible adjustment and good temperature stability compared with the traditional hardware phase correction method, avoids the influence of analog circuit parameter drift on phase accuracy, realizes accurate recovery of high frequency phase information, and provides a reliable phase reference for accurate vector control of the high voltage frequency converter in a high frequency working state.

[0128] Convex optimization objective function A quadratic objective function including a speed error main term and a control quantity penalty term is constructed to meet the basic requirements of convex optimization. The objective function design can consider control accuracy and control smoothness at the same time compared with the traditional single-objective optimization method, and the coordination and balance between multiple objectives can be achieved through reasonable setting of weight coefficients, avoiding system oscillation and actuator wear caused by sharp changes in control quantity in traditional methods, and improving the stability of wide-range speed control and the service life of equipment.

[0129] PID controller formula Combined with the adaptive gain adjustment mechanism, the dynamic optimization of control parameters with frequency and load conditions is realized. The adaptive gain formula adjusts the three gain parameters through the power function relationship of frequency, which can maintain good control performance in a wide frequency range compared with the traditional fixed parameter PID controller, solve the contradiction problem of slow response in low frequency band and serious overshoot in high frequency band, and realize high-precision speed control in full frequency band.

[0130] The double-layer game model realizes the global optimization of system performance through the competitive and cooperative mechanism of the upper energy consumption optimization function and the lower precision optimization function The exponential term in the upper function amplifies the influence of switching loss change, the logarithmic term smoothly processes the fluctuation of harmonic current, and the product term embodies the mutual restraint relationship between power consumption and efficiency. The product term in the lower function optimizes the accuracy and response speed at the same time, and the exponential term strengthens the importance of stability and robustness. The coupling term describes the nonlinear mutual influence between energy consumption and accuracy through the power function relationship, which can more accurately reflect the complex correlation between various performance indicators in the actual system compared with the traditional linear weighted multi-objective optimization method, realize the coordination and balance between energy consumption minimization and control accuracy maximization, and significantly improve the comprehensive performance of wide-range speed control of high-voltage frequency converters.

[0131] A specific embodiment 2 of the high-voltage frequency converter is provided below, as shown in Figures 2-4 Fig. 2, which includes a high-voltage frequency converter 6, an AC motor 7, a load 8, a three-phase acquisition unit 10 and a DSP calculation unit 5. The output of the high-voltage frequency converter 6, the AC motor 7 and the load 8 are connected in sequence.

[0132] The high-voltage frequency converter 6 is a three-phase output. The three-phase acquisition unit 10 comprises three unit acquisition circuits 11 which are the same in structure, each of which is connected to one phase of the three-phase output of the high-voltage frequency converter 6, and each of which comprises an anti-common-mode differential operational amplifier 1, an integration circuit 2, a low-pass filter circuit 3 and an AD analog-digital conversion chip 4.

[0133] The voltage output end of the high-voltage frequency converter 6 is also connected to the input of the anti-common-mode differential operational amplifier 1 through the sampling voltage division circuit 9, the output of the anti-common-mode differential operational amplifier 1 is connected to the input of the integration circuit 2 and the low-pass filter circuit 3 respectively, the output of the integration circuit 2 and the low-pass filter circuit 3 is connected to the input of the AD analog-digital conversion chip 4 respectively, and the output of the AD analog-digital conversion chip 4 is connected to the DSP calculation unit 5; the output of the DSP calculation unit 5 is connected to the driving port of the high-voltage frequency converter 6.

[0134] The anti-common-mode differential operational amplifier 1 of each unit acquisition circuit comprises a bidirectional TVS diode DZ1, a first resistor R1 and a first operational amplifier U1, the bidirectional TVS diode DZ1 and the first resistor R1 are connected in parallel between the inverting input end and the non-inverting input end of the first operational amplifier U1, and the output of the first operational amplifier U1 of the anti-common-mode differential operational amplifier 1 is connected to the input of the integration circuit 2 and the low-pass filter circuit 3 respectively. The first operational amplifier U1 can be a chip with the model AD629AR produced by Analog Devices Inc.

[0135] The integration circuit 2 of each unit acquisition circuit comprises a second operational amplifier U2, a second resistor R2, a third resistor R3 and a first capacitor C1, one end of the second resistor R2 is connected to the anti-common-mode differential operational amplifier, the other end of the second resistor R2 is connected to the inverting input end of the second operational amplifier U2, the first capacitor C1 and the third resistor R3 are connected in parallel between the inverting input end of the second operational amplifier U2 and the output end of the second operational amplifier U2, the non-inverting input end of the second operational amplifier U2 is connected to an analog ground, and the output end of the second operational amplifier U2 is connected to the AD analog-digital conversion chip 4.

[0136] The low pass filter circuit 3 of each unit acquisition circuit comprises a third operational amplifier U3, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2, one end of the fifth resistor R5 is connected with the anti-common-mode differential operational amplifier, the other end of the fifth resistor R5 is connected with the inverting input terminal of the third operational amplifier U3, the second capacitor C2 is connected in parallel with the fourth resistor R4 between the inverting input terminal of the third operational amplifier U3 and the output terminal of the third operational amplifier U3, the non-inverting input terminal of the third operational amplifier U3 is connected with the analog ground, and the output terminal of the third operational amplifier U3 is connected with the AD analog-digital conversion chip 4.

[0137] The frequency output by the integration circuit 2 is the same as the frequency output by the low pass filter circuit 3, but the phase is different.

[0138] The AD analog-digital conversion chip of each unit acquisition circuit transmits data to the DSP computing unit through the SPI bus.

[0139] The sampling voltage dividing circuit of each unit acquisition circuit comprises a sixth voltage dividing resistor R6 and a seventh voltage dividing resistor R7, one end of the sixth voltage dividing resistor R6 is connected with the output terminal of the high-voltage frequency converter and the AC motor respectively, the other end of the sixth voltage dividing resistor R6 is connected with the anti-common-mode differential operational amplifier and one end of the seventh voltage dividing resistor R7 respectively, and the other end of the seventh voltage dividing resistor R7 is connected with the ground. The sampling voltage dividing circuit samples the output voltage of the high-voltage frequency converter, converts the high voltage into low voltage, and then sends the low voltage into the input of the corresponding anti-common-mode differential operational amplifier.

[0140] The second operational amplifier U2 and the third operational amplifier U3 can be the amplifiers produced by Analog Devices Inc., model OP284ES. The AD analog-digital conversion chip 4 can be the chip produced by Analog Devices Inc., model AD7606. The DSP computing unit 5 can be the chip produced by Texas Instruments Inc., model TMS6747.

[0141] The anti-common-mode differential operational amplifier 1 multiplies the sampling signal of the sampling voltage dividing circuit 9 by-1, and then sends the signal to the integration circuit 2 and the low pass filter circuit 3. In this way, the output of the subsequent integration circuit 2 and low pass filter circuit 3 is also opposite in polarity to the input, and finally a positive number is obtained, which is convenient for subsequent DSP processing.

[0142] The anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage frequency converter through the sampling voltage dividing circuit; the integration circuit and the low pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the voltage frequency of the high-voltage frequency converter 6 respectively through the anti-common-mode differential operational amplifier, and send the signals to the DSP computing unit for calculation through the AD analog-digital conversion chip.

[0143] The DSP computing unit calculates the phase of the high-voltage frequency converter under high-frequency voltage, low-frequency voltage or medium-frequency voltage according to the signal from the AD analog-digital conversion chip.

[0144] The frequency and phase information of the output voltage of the high-voltage frequency converter obtained by the DSP computing unit can provide accurate information for subsequent vector control, ensuring that high-precision control can be achieved in a wide frequency range.

[0145] Specifically, when the frequency output by the high-voltage frequency converter is high-frequency voltage greater than ω1, the integral circuit 2 converts the sampled high-frequency voltage signal into a high-frequency sampling signal, which is output to the AD analog-digital conversion chip for analog-digital conversion and then sent to the DSP computing unit, and the DSP computing unit calculates the phase of the high-frequency voltage output by the high-voltage frequency converter according to the high-frequency sampling signal; wherein ω1=5Hz.

[0146] The frequency of the high-frequency sampling signal output by the integral circuit is the same as the frequency of the high-frequency voltage output by the high-voltage frequency converter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage frequency converter by 90°, so the actual phase of the high-frequency voltage output by the high-voltage frequency converter is the phase of the high-frequency sampling signal plus 90° in advance, which is completed in the DSP computing unit.

[0147] When the frequency output by the high-voltage frequency converter is low-frequency voltage less than ω2, the low-pass filter circuit converts the sampled low-frequency voltage signal into a low-frequency sampling signal, which is output to the AD analog-digital conversion chip for analog-digital conversion and then sent to the DSP computing unit, and the DSP computing unit calculates the phase of the low-frequency voltage output by the high-voltage frequency converter according to the low-frequency sampling signal; wherein ω2=2Hz. The amplitude of the low-frequency sampling signal generated after sampling by the low-pass filter circuit is amplified, the frequency of the low-frequency sampling signal is the same as the frequency of the low-frequency voltage output by the high-voltage frequency converter, and the phase of the low-frequency sampling signal has no lag.

[0148] The frequency of the high-frequency sampling signal output by the integral circuit is the same as the frequency of the low-frequency sampling signal output by the low-pass filter circuit, which is ω.

[0149] When the frequency output by the high-voltage frequency converter is medium-frequency voltage between ω1 and ω2, the sampling results of the low-pass filter circuit and the integral circuit are used simultaneously, and at this time, the DSP computing unit calculates the phase of the medium-frequency voltage according to the following formula by means of smooth switching:

[0150] Medium-frequency voltage phase=a1(ω-ω1) / (ω2-ω1)+a2(ω2-ω) / (ω2-ω1),

[0151] Wherein a1 is the phase information of the output signal of the integral circuit after leading 90° in the DSP calculation unit, and a2 is the phase information of the output signal of the low-pass filter circuit.

[0152] In order to better understand and implement the present application, the following provides an embodiment 3 of a specific application scenario of the present application: a 6kV high-voltage frequency converter drives an asynchronous motor with a rated power of 5MW, and it is required to realize full-range accurate speed control from 0.1Hz extremely low frequency turning to 150Hz high frequency test. The research team first sets the speed control parameters, determines the target speed range as 3rpm to 9000rpm, and sets the frequency boundary threshold 5Hz, 2Hz, the phase compensation coefficient is set as 0.9, and the control accuracy requirement is set as within 0.05% of the target speed. The established initial state parameter set of the speed control contains 15 core parameters, covering various aspects such as frequency control, phase adjustment, power limitation and stability guarantee.

[0153] In the design and implementation of the three-phase acquisition unit, the research team configures an independent unit acquisition circuit for each phase output of the high-voltage frequency converter. The sampling voltage division circuit uses a sixth voltage division resistor R6 with a high-precision resistance of 22MΩ and a seventh voltage division resistor R7 with a precision resistance of 47kΩ to realize a voltage division ratio of about 470:1, safely reducing the 6kV high voltage to below 12.8V. The anti-common-mode differential operational amplifier selects the AD629AR chip, and the amplification multiple is set to 15, cooperating with a 6.8V breakdown voltage bidirectional TVS diode and a 2.2kΩ current limiting resistor to form an input protection network. The integral circuit uses an OP284ES operational amplifier, the second resistor R2 is selected as 33kΩ, the first capacitor C1 is selected as 0.47μF, and the third resistor R3 is selected as 4.7MΩ, forming an integrator with a time constant of 15.5ms. The low-pass filter circuit also uses an OP284ES operational amplifier, the fifth resistor R5 is 33kΩ, the fourth resistor R4 is 100kΩ, and the second capacitor C2 is 2.2μF, forming a first-order low-pass filter with a cutoff frequency of 0.72Hz. The AD analog-to-digital conversion chip selects AD7606, and the sampling frequency is set to 50kHz with a resolution of 16 bits.

[0154] In the implementation process of the segmented phase calculation strategy, the research team executes the multi-path phase calculation algorithm through the DSP calculation unit TMS320F28377S. When it is detected that the output frequency of the high-voltage frequency converter is higher than 5Hz, the system automatically selects the integral circuit channel, and performs a 90° leading compensation operation on the obtained phase information in the DSP, and the compensation formula is The item ensures the accuracy of the high-frequency phase information. When the output frequency is lower than 2 Hz, the system switches to the low-pass filter circuit channel, directly adopts the phase information output by the low-pass filter circuit channel, and avoids the phase distortion of the low-frequency range. In the medium frequency range of 2 Hz to 5 Hz, the smooth switching algorithm dynamically calculates the weighting coefficient according to the current frequency value, realizes the smooth transition of the signals of the two channels, and effectively avoids the phase jump phenomenon at the switching point.

[0155] The implementation of the convex optimization solution model adopts a sliding window containing 180 sampling points, and the frequency adjustment weight coefficient in the objective function is 0.05, and the phase correction weight coefficient 0.02. The constraint conditions include that the frequency change rate is limited within 0.5 Hz per second, the phase change is limited within 2 degrees per control period, and the power is limited within 105% of the rated power. The iterative calculation of the Lagrange multiplier method is completed within each control period, and the calculation time is controlled within 2 ms, meeting the requirements of real-time control. The convergence criterion of the optimization calculation is set to be that the change rate of the objective function is less than or the number of iterations exceeds 50 times.

[0156] In the implementation of the adaptive PID control algorithm, the basic gain parameter is set to =1.2, =0.8, =0.15, and the adaptive adjustment coefficient =0.3, =0.25, =0.35. The controller adjusts the gain parameters in real time according to the current frequency range and the load change. When the frequency is 0.1 Hz, the proportional gain is automatically adjusted to 2.8, and the integral gain is adjusted to 3.2. When the frequency is 100 Hz, the proportional gain is adjusted to 0.6, and the differential gain is adjusted to 0.8. The calculation accuracy of the speed error reaches 0.1 rpm, and the integral term adopts the anti-integral saturation algorithm to prevent the integrator from being saturated.

[0157] In the implementation process of the double-layer game coordination optimization model, the weight coefficient of the upper-layer energy consumption optimization model is set to =0.6, =0.3, =0.4, and the exponential adjustment coefficient =0.08. The weight coefficient of the lower-layer precision optimization model is set to =1.5, =1.2, =0.4, =0.6. The coupling coefficients of the energy consumption and precision coupling term are =0.03, =0.008, =0.25. The iterative solution of the game equilibrium uses an alternate optimization algorithm, each round of iteration contains two stages of upper model optimization and lower model optimization, and the convergence condition is set to be that the change rate of the objective function in the last three rounds of iteration is less than 0.1%.

[0158] The key control parameters in the implementation process are shown in Table 1:

[0159] Table 1 Key parameters of wide-range speed control of high-voltage frequency converter

[0160]

[0161] In the system debugging stage, the research team tested the control performance of different frequency bands in detail. Figure 5 The amplitude-frequency response characteristics of the three-phase acquisition unit at different frequencies are shown, which clearly shows the excellent performance of the integral circuit and the low-pass filter circuit in their respective applicable frequency bands. Figure 6 The comparison of phase compensation effect is depicted, which verifies the effectiveness of the 90-degree lead compensation algorithm in the high frequency band. The test results of speed control accuracy are shown in Figure 7 , which shows the control accuracy advantage of the method in the whole frequency range. The convergence process of the game optimization algorithm is shown in Figure 8 , which reflects the fast convergence characteristics of the double-layer game model. The overall performance evaluation results of the system are shown in Figure 9 , which comprehensively shows the coordination effect of energy optimization and accuracy improvement.

[0162] The test data show that in the extremely low frequency 0.1Hz turning stage, the speed control accuracy reaches ±0.02rpm, and the speed fluctuation rate is reduced to within 0.8%, which is significantly improved compared with the ±0.5rpm accuracy and 3.5% fluctuation rate of the traditional method. In the intermediate frequency 2.5Hz transition stage, the smooth switching algorithm effectively avoids the ±15 degree phase jump caused by the traditional hard switching method, and realizes the smooth transition with a phase continuity error less than ±0.5 degrees. In the high frequency 100Hz test stage, the phase lag compensation reduces the 12 degree lag of the traditional method to within ±1 degree, and the frequency response speed is improved to 90% within 50ms, which is more than 60% shorter than the response time of the traditional method.

[0163] The game optimization model shows good self-adaptability in actual operation, the total power consumption is reduced by 8.5% compared with a single target optimization method, and the control accuracy is improved by more than 40%. The introduction of the energy consumption accuracy coupling term enables the system to maintain a relatively low power consumption level under high-precision control, avoiding the contradiction between accuracy and energy consumption in traditional methods. The dynamic response of the system is excellent when the load suddenly changes. During the process of the load suddenly changing from 20% rated power to 80% rated power, the speed overshoot is controlled within 2%, and the regulation time is shortened to 1.5 seconds, showing excellent robustness and fast response capability.

[0164] The technical progress brought by the traditional speed control means mainly embodies three aspects of principle breakthroughs. Firstly, the multi-path phase calculation strategy breaks through the frequency domain limitation of the traditional single filter method. Through the division and cooperation of the integral circuit and the low-pass filter circuit, the signal strength is maintained at high frequencies by using the frequency tracking characteristics of the integral circuit, the signal-to-noise ratio is improved at low frequencies by using the noise suppression ability of the low-pass filter circuit, and seamless connection is realized at medium frequencies by using the smooth switching algorithm, which fundamentally solves the problem of uneven performance in a wide frequency domain in the traditional method. Secondly, the double-layer game coordination optimization breaks through the limitation of the traditional linear weighted multi-objective optimization. Through the competition and cooperation mechanism of the upper and lower models and the introduction of the nonlinear coupling term, the complex correlation between energy consumption and accuracy in the actual system is more accurately described, the global optimal solution is realized instead of the local optimal solution, and the overall performance decline caused by the mutual restriction of various performance indicators in the traditional method is avoided. Finally, the adaptive circuit signal processing breaks through the precision bottleneck of the traditional digital processing method. Through the high-precision signal preprocessing of the analog circuit combined with the flexible calculation of the digital algorithm, accurate detection of weak signals is ensured and high-speed execution of complex algorithms is realized, providing high-quality signal basis and strong computing power support for wide-range speed control.

[0165] It should be noted that the variables involved in the present application are explained in detail as shown in Tables 2 and 3.

[0166] Table 2 Variable explanation table (first part)

[0167]

[0168] Table 3 Variable explanation table (second part)

[0169]

[0170] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A wide-range speed control method of a high-voltage frequency converter, characterized by, The three-phase acquisition unit comprises three unit acquisition circuits with the same structure. Setting the speed control parameters of high-voltage frequency converter, including target speed range, frequency boundary threshold and , phase compensation coefficient and control accuracy requirement, establishing the initial state parameter set of speed control; using three-phase acquisition unit to sample the output voltage of high-voltage frequency converter in real time, obtaining digitized voltage signal; based on different ranges of high-voltage frequency converter output frequency, executing multi-path phase calculation strategy, when output frequency is greater than frequency boundary threshold , using high-frequency sampling signal output by integral circuit and executing 90-degree leading phase compensation operation in DSP calculation unit, when output frequency is less than frequency boundary threshold , using low-frequency sampling signal output by low-pass filter circuit to perform non-lagging phase calculation, when output frequency is between and , using smooth switching algorithm to weight and fuse the output results of integral circuit and low-pass filter circuit; establishing convex optimization solving model of minimum speed error, converting wide-range speed control problem into parameter optimization problem under multiple constraint conditions, using Lagrange multiplier method to solve optimal frequency adjustment and phase correction; executing adaptive feedback adjustment based on deviation between target speed and actual speed, using adaptive PID control algorithm to calculate frequency adjustment and phase correction; applying double-layer game coordination optimization model to coordinate system parameters; transmitting optimal control parameters output by game coordination optimization model to driving port of high-voltage frequency converter.

2. The method of claim 1, wherein, In the step of setting the speed control parameters of the high-voltage frequency converter, 5 Hz is set, 2 Hz is set.

3. The method of claim 2, wherein, The AD analog-digital conversion chip transmits the digitized high-frequency sampling signal and low-frequency sampling signal to the DSP calculation unit through an SPI bus.

4. The method of claim 3, wherein, The convex optimization solving model comprises a target function for minimizing the deviation between the target rotating speed and the actual rotating speed, constraint conditions including a frequency change rate constraint, a phase change constraint, a power limit constraint and a system stability constraint, and inputs including the target rotating speed, the actual rotating speed, the frequency adjustment amount, the phase correction amount and system power parameters, and the output is the optimal frequency adjustment amount and phase correction amount satisfying all the constraint conditions.

5. The method of claim 4, wherein, The smooth switching algorithm, in particular for processing intermediate frequency voltage signals between frequency boundary thresholds to The output results of the weighted fusion integration circuit and the low-pass filter circuit are fused to calculate the intermediate frequency voltage phase, and the weighting coefficient is dynamically determined according to the relative position of the current output frequency and the frequency boundary thresholds and .

6. The method of claim 5, wherein, The frequency of the high-frequency sampling signal is the same as the frequency of the high-frequency voltage output by the high-voltage frequency converter, and the phase of the high-frequency sampling signal lags behind the phase of the high-frequency voltage output by the high-voltage frequency converter by 90 degrees.

7. The method of claim 6, wherein, The double-layer game coordination optimization model comprises an upper-layer energy consumption optimization model and a lower-layer precision optimization model.

8. The method of claim 7, wherein, The energy consumption precision coupling term is used to describe the mutual restraint relationship between energy consumption optimization and precision optimization, and the inputs include the system total power consumption, the control precision standard deviation, the frequency adjustment amount, the phase correction amount and the load change rate, and the output is a coupling coefficient reflecting the trade-off strength between the two optimization objectives.

9. The method of claim 8, wherein, ​ 10. A sampling and conditioning circuit for wide range speed control of a high voltage frequency converter, characterized by The circuit comprises a high-voltage frequency converter, an alternating current motor and a load, the output end of the high-voltage frequency converter, the alternating current motor and the load are connected in sequence, characterized in that it further comprises a three-phase acquisition unit and a DSP calculation unit, the three-phase acquisition unit comprises three unit acquisition circuits which are the same in structure, each unit acquisition circuit comprises a sampling voltage division circuit, an anti-common-mode differential operational amplifier, an integration circuit, a low-pass filter circuit and an AD analog-digital conversion chip; the voltage output end of the high-voltage frequency converter is further connected with the input of the anti-common-mode differential operational amplifier through the sampling voltage division circuit, the output of the anti-common-mode differential operational amplifier is connected with the input of the integration circuit and the low-pass filter circuit respectively, the output of the integration circuit and the low-pass filter circuit is connected with the input of the AD analog-digital conversion chip, and the output of the AD analog-digital conversion chip is connected with the input of the DSP calculation unit; the output of the DSP calculation unit is connected with the drive port of the high-voltage frequency converter; the anti-common-mode differential operational amplifier samples the voltage frequency of the high-voltage frequency converter through the sampling voltage division circuit; the integration circuit and the low-pass filter circuit obtain the high-frequency voltage signal and the low-frequency voltage signal of the voltage frequency of the high-voltage frequency converter respectively through the anti-common-mode differential operational amplifier, and send the signals to the DSP calculation unit for calculation through the AD analog-digital conversion chip; the DSP calculation unit calculates the phase of the high-voltage frequency converter under the high-frequency voltage, the low-frequency voltage or the medium-frequency voltage according to the signals from the AD analog-digital conversion chip.

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