Gate drive circuit capable of preventing surge

Abstract

A grid driving circuit capable of preventing surge is used for providing soft start current to a grid of a power switch in a soft start period so as to softly start the power switch, and comprises a first current mirror circuit used for mirroring reference current according to a mirroring proportion so as to generate mirroring output current, and a second current mirror circuit used for mirroring reference current according to a mirroring proportion, wherein the soft start current is generated according to the mirror image output current; the path switch is coupled to a signal path between the mirror output current and the soft start current, and the path switch is used for turning off the signal path when the power switch is turned off; wherein in a preset time period in the soft start time period, the mirror image proportion of the first current mirror circuit is reduced, so that the surge of the path switch caused when the soft start time period is switched to be conducted is compensated, and the surge of the soft start current in the soft start time period is further avoided.

Description

Technical Field

[0001] This invention relates to a gate drive circuit, and more particularly to a gate drive circuit that can prevent surges. Background Technology

[0002] Figure 1 This is a circuit diagram showing a known gate drive circuit. Figure 1 The gate drive circuit shown uses a current mirror to limit the gate drive initiation current, achieving a soft-start effect. However, when the path switch Sp switches, the voltage at node A fluctuates, causing the voltage at node B to increase, which in turn increases the mirrored output current Imr. Because the size ratio of transistors MP1 and MP2 is large, for example, 1:50, the mirrored output current Imr is amplified by a factor of 10, contradicting the original intention of limiting the current.

[0003] In view of this, the present invention addresses the shortcomings of the prior art by proposing a gate drive circuit that can prevent surges. Summary of the Invention

[0004] In one viewpoint, the present invention provides a gate driving circuit for providing a soft-start current to a gate of a power switch during a soft-start period to soft-start the power switch. The gate driving circuit includes: a first current mirror circuit for mirroring a reference current according to a mirror ratio to generate a mirrored output current, wherein the soft-start current is generated according to the mirrored output current; and a path switch coupled to a signal path between the mirrored output current and the soft-start current, the path switch being used to turn off the signal path when the power switch is turned off; wherein during a preset period within the soft-start period, the mirror ratio of the first current mirror circuit is reduced, thereby compensating for the surge caused by the path switch switching on during the soft-start period, and thus preventing the soft-start current from surging during the soft-start period.

[0005] In one embodiment, the gate drive circuit further includes a second current mirror circuit for mirroring the mirrored output current to generate the soft-start current, wherein the path switch is coupled between the first current mirror circuit and the second current mirror circuit.

[0006] In one embodiment, the first current mirror circuit includes: a plurality of bias transistors for generating a bias voltage at a bias node based on the reference current; and a mirror transistor whose gate is biased by the bias voltage for generating the mirrored output current based on the bias voltage; wherein, during the preset time period, the mirror ratio is reduced by adjusting the number of the plurality of bias transistors electrically connected to the reference current.

[0007] In one embodiment, the plurality of bias transistors includes a first bias transistor and a second bias transistor, wherein the gate of the first bias transistor and the gate of the second bias transistor are coupled to the bias node, wherein the gate and drain of the first bias transistor are electrically connected to each other, and wherein the first current mirror circuit further includes: an adjustment switch coupled between the gate and drain of the second bias transistor for conducting the gate and drain of the second bias transistor during the preset time period, thereby reducing the mirror ratio.

[0008] In one embodiment, the first current mirror circuit further includes: a bias stacked transistor connected in series with the first bias transistor for adjusting the voltage at the drain of the first bias transistor; and a mirror stacked transistor connected in series with the mirror transistor for adjusting the voltage at the drain of the mirror transistor.

[0009] In one embodiment, the gate and drain of the bias stacked transistor are electrically connected to each other, and the gate of the bias stacked transistor is electrically connected to the gate of the mirror stacked transistor.

[0010] In one embodiment, the first current mirror circuit further includes: a bias-side amplifier for amplifying the voltage of the drain of the first bias transistor to generate a bias-side amplified voltage to control the gate of the bias stacked transistor, thereby adjusting the voltage of the drain of the first bias transistor; and a mirror-side amplifier for amplifying the voltage of the drain of the mirror transistor to generate a mirror-side amplified voltage to control the gate of the mirror stacked transistor, thereby adjusting the voltage of the drain of the mirror transistor.

[0011] In one embodiment, the bias-side amplifier includes a bias-side amplifying transistor, the gate and drain of which are respectively coupled to the drain of the first bias transistor and the gate of the bias stacked transistor, thereby adjusting the voltage of the drain of the first bias transistor to be close to a turn-on threshold of the bias-side amplifying transistor; and the mirror-side amplifier includes a mirror-side amplifying transistor, the gate and drain of which are respectively coupled to the drain of the mirror transistor and the gate of the mirror stacked transistor, thereby adjusting the voltage of the drain of the mirror transistor to be close to a turn-on threshold of the mirror-side amplifying transistor.

[0012] In one embodiment, the gate drive circuit further includes a pulse generator for detecting the moment when a drive input signal becomes enabled to generate an adjustment pulse, wherein the width of the adjustment pulse corresponds to the preset time period, and wherein the adjustment pulse is used to control the adjustment switch.

[0013] In one embodiment, the width of the adjustment pulse is positively correlated with the bandwidth of the bias-side amplifier and / or the bandwidth of the mirror-side amplifier.

[0014] The advantage of this invention is that the gate drive circuit of this invention can avoid the surge phenomenon of soft-start current, thereby ensuring that the rise time of the power switch control signal is not too short, thus achieving the effect of soft start.

[0015] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0016] Figure 1 This is a circuit diagram showing a known gate drive circuit.

[0017] Figure 2 This is a circuit diagram of a display gate driving circuit according to an embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram of a gate driving circuit according to another embodiment of the present invention.

[0019] Figure 4 This is a circuit diagram of a gate driving circuit according to another embodiment of the present invention.

[0020] Figure 5 This is a circuit diagram of a gate driving circuit according to another embodiment of the present invention.

[0021] Figure 6 This is a circuit diagram of a gate driving circuit according to another embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the signal waveforms of the gate drive circuit according to an embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram of the signal waveforms of the relevant signals of a known gate drive circuit.

[0024] Figure 9 This is a schematic diagram of the signal waveforms of the gate drive circuit according to an embodiment of the present invention.

[0025] Explanation of symbols in the diagram

[0026] 10: Current Mirror Circuit

[0027] 11: Bias-side amplifier

[0028] 12: Mirror-side amplifier

[0029] 13: Pulse Generator

[0030] 20: Current Mirror Circuit

[0031] 30: Gate drive circuit

[0032] A, B: Nodes

[0033] Ia: Source current

[0034] Imr: Mirror output current

[0035] Iref: Reference current

[0036] Iss: Soft-start current

[0037] MP1, MP2: Transistors

[0038] Nb: Offset node

[0039] Ps: Signal path

[0040] QA1: Bias-side amplification transistor

[0041] QA2: Mirror-side amplification transistor

[0042] Qb1, Qb2: Bias transistors

[0043] Qbc: Biased Stacked Transistor

[0044] Qm: Mirror transistor

[0045] Qmc: Mirror-mounted transistor

[0046] Rm: Mirror ratio

[0047] Sa: Adjustment switch

[0048] Sp: Path switch

[0049] Spw: Drive input signal

[0050] Spwr: Power Switch

[0051] Ta: Preset Time Period

[0052] Tss: Soft boot period

[0053] Vab: Bias-side amplified voltage

[0054] Vam mirror side amplification voltage

[0055] Vb: Bias voltage

[0056] Vdb, Vdm: Voltage

[0057] Vds1, Vds2: Drain-source voltages

[0058] VG: Power switch control signal

[0059] Vin: Input voltage

[0060] Vout: Output voltage

[0061] Vsc: Adjust pulse

[0062] Vsp: Path switch control signal Detailed Implementation

[0063] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0064] Figure 2 This is a circuit diagram of a display gate driving circuit according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the signal waveforms of relevant signals of the gate driving circuit according to an embodiment of the present invention. Please also refer to... Figure 2 and Figure 7 The gate drive circuit 30 of the present invention is used to provide a soft-start current Iss to the gate of the power switch Spwr during the soft-start period Tss, so as to soft-start the power switch Spwr. The power switch Spwr may be, for example, a Figure 2 The step-down converter circuit shown includes a lower bridge switch. The gate drive circuit 30 includes a current mirror circuit 10, a path switch Sp, a current mirror circuit 20, and a pulse generator 13. The current mirror circuit 10 mirrors the reference current Iref according to the mirror ratio Rm to generate a mirrored output current Imr, and the soft-start current Iss is generated based on the mirrored output current Imr. The path switch Sp is coupled to the signal path Ps between the mirrored output current Imr and the soft-start current Iss, and the path switch Sp is used to turn off the signal path Ps when the power switch Spwr is turned off.

[0065] Please refer to the following at the same time Figure 2 and Figure 7 During a preset time period Ta within the soft-start period Tss, the gate drive circuit reduces the mirroring ratio Rm of the current mirror circuit 10, thereby compensating for the surge caused by the path switch Sp turning on during the soft-start period Tss, and thus preventing the soft-start current Iss from spikeing during the soft-start period Tss. The current mirror circuit 20 mirrors the output current Imr to generate the soft-start current Iss, wherein the path switch Sp is coupled between the current mirror circuit 10 and the current mirror circuit 20. The pulse generator 13 detects the moment when the drive input signal Spw turns on to generate an adjustment pulse Vsc. In one embodiment, the width of the adjustment pulse Vsc corresponds to the preset time period Ta.

[0066] Figure 8This is a schematic diagram showing the signal waveforms of relevant signals from a known gate drive circuit. The soft-start current Iss and the power switch control signal VG are displayed on... Figure 8 middle. Figure 8 The dotted line in the upper middle figure represents the soft-start current Iss when the control target value is -60mA, while the solid line in the upper figure represents the soft-start current Iss when the control target value is -30mA. Figure 8 In the lower diagram, the dotted line represents the power switch control signal VG with a target control value of -60mA, while the solid line represents the power switch control signal VG with a target control value of -30mA. Please also refer to... Figure 1 and Figure 8 During the soft-start period, the conduction of the path switch Sp causes a surge in the mirror output current Imr, which in turn causes a surge in the soft-start current Iss. In particular, the soft-start current Iss, with a control target value of -60mA, almost shifts to -160mA, resulting in an excessively short rise time for the power switch control signal VG. For example... Figure 8 As shown in the figure below, the rise time of the power switch control signal VG when the control target value is -60mA is approximately 50ns, and the rise time of the power switch control signal VG when the control target value is -30mA is approximately 140ns, thus failing to achieve the expected soft-start effect.

[0067] Figure 3 This is a circuit diagram of a display gate driving circuit according to another embodiment of the present invention. This embodiment corresponds to... Figure 2 In one specific embodiment, the current mirror circuit 10 includes multiple bias transistors Qb1 and Qb2 and a mirror transistor Qm. The mirror transistor Qm generates a bias voltage Vb at the bias node Nb based on the reference current Iref. The gate of the mirror transistor Qm is biased by the bias voltage Vb to generate a mirrored output current Imr. In this embodiment, the gate drive circuit reduces the mirror ratio Rm by adjusting the number of bias transistors Qb1 and Qb2 electrically connected to the reference current Iref during a preset time period Ta. The gates of bias transistors Qb1 and Qb2 are coupled to the bias node Nb, and the gate and drain of bias transistor Qb1 are electrically connected to each other. Figure 3 As shown, the current mirror circuit 10 also includes an adjustment switch Sa, which is coupled between the gate and drain of the bias transistor Qb2, to conduct the gate and drain of the bias transistor Qb2 during a preset time period Ta, thereby reducing the mirror ratio Rm. The adjustment pulse Vsc is used to control the adjustment switch Sa.

[0068] Figure 7This is a schematic diagram of the signal waveforms of relevant signals of the gate drive circuit according to an embodiment of the present invention. The drive input signal Spw, adjustment pulse Vsc, power switch control signal VG, and path switch control signal Vsp are displayed on... Figure 7 In order to reduce the impact of surges, the present invention switches the adjustment pulse Vsc to the enable level during a preset time period Ta, and turns on the adjustment switch Sa, so that the bias transistor Qb2 and the bias transistor Qb1 are connected in parallel, thereby making the equivalent size of the bias transistor Qb2 and the bias transistor Qb1 twice that of the mirror transistor Qm, thereby reducing the mirror ratio Rm and reducing the mirror output current Imr to 1 / 2·Iref, thus avoiding surges in the soft-start current Iss.

[0069] Please refer to the following: Figure 7 and Figure 3 After a preset time period Ta, the adjustment pulse Vsc switches to the prohibition level, so that the adjustment switch Sa is not turned on. This causes the mirror output current Imr to return to 1 times the reference current Iref, and thus maintains it at the preset target value (such as -60mA, -30mA). In this way, the rise time of the power switch control signal VG can also reach the preset target value, thus achieving soft start.

[0070] Figure 4 This is a circuit diagram of a gate driving circuit according to another embodiment of the present invention. This embodiment is similar to... Figure 3 The embodiments differ in that, as Figure 4 As shown, the current mirror circuit 10 also includes a bias stacked transistor Qbc and a mirror stacked transistor Qmc. The bias stacked transistor Qbc is connected in series with the bias transistor Qb1 to adjust the drain voltage Vdb of the bias transistor Qb1. The mirror stacked transistor Qmc is connected in series with the mirror transistor Qm to adjust the drain voltage Vdm of the mirror transistor Qm. The gate and drain of the bias stacked transistor Qbc are electrically connected to each other, and the gate of the bias stacked transistor Qbc is electrically connected to the gate of the mirror stacked transistor Qmc. Through the bias stacked transistor Qbc and the mirror stacked transistor Qmc, the on-resistance Rds can be made closer to infinity, thereby making the equivalent output impedance of the current mirror circuit 10 closer to infinity, and making the current mirroring ratio of the current mirror circuit 10 closer to a preset value.

[0071] Figure 5 This is a circuit diagram of a display gate driving circuit according to another embodiment of the present invention. This embodiment is similar to... Figure 4 The embodiments differ in that, as Figure 5As shown, the current mirror circuit 10 also includes a bias-side amplifier 11 and a mirror-side amplifier 12. The bias-side amplifier 11 amplifies the drain voltage Vdb of the bias transistor Qb1 to generate a bias-side amplified voltage Vab, which controls the gate of the bias stacked transistor Qbc, thereby adjusting the drain voltage Vdb of the bias transistor Qb1 and locking the drain-source voltage Vds1 of the bias transistor Qb1. The mirror-side amplifier 12 amplifies the drain voltage Vdm of the mirror transistor Qm to generate a mirror-side amplified voltage Vam, which controls the gate of the mirror stacked transistor Qmc, thereby adjusting the drain voltage Vdm of the mirror transistor Qm and locking the drain-source voltage Vds2 of the mirror transistor Qm. This allows the equivalent output impedance of the current mirror circuit 10 to approach infinity, and the current mirroring ratio of the current mirror circuit 10 to approach a preset value.

[0072] Figure 6 This is a circuit diagram of a display gate driving circuit according to another embodiment of the present invention. This embodiment corresponds to... Figure 5 In one specific embodiment, the bias-side amplifier 11 includes a bias-side amplifying transistor QA1. The gate and drain of the bias-side amplifying transistor QA1 are coupled to the drain of the bias transistor Qb1 and the gate of the bias stacked transistor Qbc, respectively. This adjusts the drain voltage Vdb of the bias transistor Qb1 to near the turn-on threshold of the bias-side amplifying transistor QA1, thus locking the drain-source voltage Vds1 of the bias transistor Qb1. The mirror-side amplifier 12 includes a mirror-side amplifying transistor QA2. The gate and drain of the mirror-side amplifying transistor QA2 are coupled to the drain of the mirror transistor Qm and the gate of the mirror stacked transistor Qmc, respectively. This adjusts the drain voltage Vdm of the mirror transistor Qm to near the turn-on threshold of the mirror-side amplifying transistor QA2, thus locking the drain-source voltage Vds2 of the mirror transistor Qm.

[0073] In one embodiment, please also refer to Figure 5 and Figure 7 The width of the pulse Vsc is adjusted to be positively correlated with the bandwidth of the bias-side amplifier 11 and / or the bandwidth of the mirror-side amplifier 12.

[0074] Figure 9 This is a schematic diagram of signal waveforms for the gate drive circuit according to an embodiment of the present invention. The soft-start current Iss and the power switch control signal VG are shown in [the diagram / image / etc.]. Figure 9 middle. Figure 9 The dotted line in the upper middle figure represents the soft-start current Iss when the control target value is -60mA, while the solid line in the upper figure represents the soft-start current Iss when the control target value is -30mA. Figure 9In the lower diagram, the dotted line represents the power switch control signal VG with a target control value of -60mA, while the solid line represents the power switch control signal VG with a target control value of -30mA. Figure 9 As shown, the soft-start current Iss generated by the gate drive circuit of the present invention can be controlled to be quite close to the control target value, for example... Figure 9 The soft-start current Iss at -60mA and -30mA, as shown in the figure above, are very close to the control target values ​​of -60mA and -30mA, respectively. Neither current generates unwanted surges due to the switching of the switch Sp. Therefore, the rise time of the power switch control signal VG is not too short to achieve the required rise time for soft start. For example, as shown... Figure 9 As shown in the figure below, the rise time of the power switch control signal VG when the control target value is -60mA is approximately 100ns, and the rise time of the power switch control signal VG when the control target value is -30mA is approximately 200ns, both of which meet the rise time length required for the corresponding soft start.

[0075] In summary, the gate drive circuit of the present invention can avoid the surge phenomenon of soft-start current, thereby ensuring that the rise time of the power switch control signal is not too short, thus achieving the effect of soft start.

[0076] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A gate drive circuit for providing a soft-start current to a gate of a power switch during a soft-start period to soft-start the power switch, the gate drive circuit comprising: A first current mirror circuit is used to mirror a reference current according to a mirror ratio to generate a mirror output current, wherein the soft-start current is generated according to the mirror output current. as well as A path switch is coupled to a signal path between the mirror output current and the soft-start current, the path switch being used to shut off the signal path when the power switch is turned off; During a preset period within the soft-start period, the mirror ratio of the first current mirror circuit is reduced to compensate for the surge caused when the path switch turns on during the soft-start period, thereby preventing the soft-start current from surging during the soft-start period.

2. The gate driving circuit as described in claim 1, wherein, It also includes a second current mirror circuit for mirroring the mirrored output current to generate the soft-start current, wherein the path switch is coupled between the first current mirror circuit and the second current mirror circuit.

3. The gate driving circuit as described in claim 1, wherein, The first current mirror circuit includes: Multiple bias transistors are used to generate a bias voltage at a bias node based on the reference current; and A mirror transistor, the gate of which is biased by the bias voltage, is used to generate the mirror output current according to the bias voltage; During the preset time period, the mirror ratio is reduced by adjusting the number of the plurality of bias transistors electrically connected to the reference current.

4. The gate driving circuit as described in claim 3, wherein, The plurality of bias transistors includes a first bias transistor and a second bias transistor, wherein the gate of the first bias transistor and the gate of the second bias transistor are coupled to the bias node, wherein the gate and drain of the first bias transistor are electrically connected to each other, and wherein the first current mirror circuit further includes: An adjustment switch is coupled between the gate and drain of the second bias transistor to conduct the gate and drain of the second bias transistor during the preset time period, thereby reducing the mirror ratio.

5. The gate driving circuit as described in claim 4, wherein, The first current mirror circuit also includes: A bias stacked transistor, connected in series with the first bias transistor, is used to adjust the voltage at the drain of the first bias transistor; and A mirror-mounted transistor is connected in series with the mirror transistor to regulate the drain voltage of the mirror transistor.

6. The gate driving circuit as described in claim 5, wherein, The gate and drain of the bias stacked transistor are electrically connected to each other, and the gate of the bias stacked transistor is electrically connected to the gate of the mirror stacked transistor.

7. The gate drive circuit as described in claim 5, wherein, The first current mirror circuit also includes: A bias-side amplifier is used to amplify the voltage at the drain of the first bias transistor to generate a bias-side amplified voltage to control the gate of the bias stacked transistor, thereby adjusting the voltage at the drain of the first bias transistor; and A mirror-side amplifier is used to amplify the voltage at the drain of the mirror transistor to generate a mirror-side amplified voltage to control the gate of the mirror-overlay transistor, thereby adjusting the voltage at the drain of the mirror transistor.

8. The gate drive circuit as claimed in claim 7, wherein: The bias-side amplifier includes a bias-side amplifying transistor, the gate and drain of which are respectively coupled to the drain of the first bias transistor and the gate of the bias-overlay transistor, thereby adjusting the voltage of the drain of the first bias transistor to be close to a turn-on threshold of the bias-side amplifying transistor. as well as The mirror-side amplifier includes a mirror-side amplifying transistor, the gate and drain of which are respectively coupled to the drain of the mirror transistor and the gate of the mirror-overlay transistor, thereby adjusting the voltage of the drain of the mirror transistor to be close to a turn-on threshold of the mirror-side amplifying transistor.

9. The gate driving circuit as claimed in claim 7, wherein, It also includes a pulse generator for detecting the moment when a drive input signal becomes enabled to generate an adjustment pulse, wherein the width of the adjustment pulse corresponds to the preset time period, and wherein the adjustment pulse is used to control the adjustment switch.

10. The gate driving circuit as claimed in claim 9, wherein, The width of the adjustment pulse is positively correlated with the bandwidth of the bias-side amplifier and / or the bandwidth of the mirror-side amplifier.

Images