Over-current protection circuit for depletion type GaN device

Abstract

The invention discloses an overcurrent protection circuit for a depletion type GaN device. The overcurrent protection circuit comprises a clamping network, a voltage following network, a copying network, a comparison network and a Si power tube which are connected in sequence. The depletion type GaN device is not directly subjected to current limiting, the Si power tube is connected to the source electrode of the depletion type GaN device, the reference current and the copy current are compared, negative feedback is formed, the maximum load current of the Si power tube is limited, and therefore over-current protection of the depletion type GaN device is achieved. Therefore, the problem of normally open characteristic of overcurrent protection of a traditional depletion type GaN device is avoided, and on the basis of ensuring high-precision current limiting and quick response, the circuit structure can be greatly simplified, and the circuit cost is effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of gallium nitride power device technology, specifically relating to the design of an overcurrent protection circuit for depletion-type GaN devices. Background Technology

[0002] GaN power devices all have a maximum drain-source current limit. When the load is too large or a punch-through or short circuit occurs, the drain-source current will exceed the device's rated limit. Transient load steps, load overloads, and current spikes during startup are common overcurrent phenomena in power devices, and all of these situations can damage GaN devices. Therefore, in order to reduce the risk of drain-source current overcurrent and enhance the reliability of the drive system, overcurrent protection is required for depletion-mode GaN devices.

[0003] In the existing technology, normally open devices need to be continuously turned off by negative voltage, and overcurrent protection needs to quickly apply a larger negative voltage when a fault occurs. Therefore, higher requirements are placed on the transient output capability of the driver chip, resulting in a complex driver circuit. Summary of the Invention

[0004] The purpose of this invention is to solve the problem of complex overcurrent protection circuit structure in existing GaN devices, and to propose an overcurrent protection circuit for depletion-type GaN devices.

[0005] The technical solution of the present invention is: an overcurrent protection circuit for a depletion-type GaN device, comprising a clamping network, a voltage follower network, a replication network, a comparator network and a Si power transistor connected in sequence, wherein the source of the Si power transistor is grounded, its gate is connected to the power supply VDD, and its drain is connected to the source of the GaN device.

[0006] Furthermore, the clamping network includes a PMOS transistor P1, the drain of which is grounded, and its gate is connected to the grounding resistor R1 and the source of an NMOS transistor N1, respectively. The source of the PMOS transistor N1 is connected to the grounding resistor R2, the source of an NMOS transistor N2, and the voltage follower network, respectively. The gate of an NMOS transistor N2, as well as the gate and drain of an NMOS transistor N1, are all connected to the power supply VDD. The drain of an NMOS transistor N2 is connected to the drain voltage Vs of the Si power transistor.

[0007] Furthermore, the voltage follower network includes an operational amplifier OP1, the non-inverting input of which is connected to the source of a PMOS transistor P1, and both its inverting input and output are connected to the replication network.

[0008] Furthermore, the replication network includes PMOS transistors P2 and P3. The sources of PMOS transistors P2 and P3 are both connected to the power supply VDD. The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P2, the gate of PMOS transistor P3, and the drain of NMOS transistor N4. The gate of NMOS transistor N4 is connected to the output of operational amplifier OP1, and its source is connected to the inverting input of operational amplifier OP1 and the drain of NMOS transistor N3. The source of NMOS transistor N3 is grounded, and its gate is connected to the power supply VDD. The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, and the comparator network. The source of NMOS transistor N5 is grounded.

[0009] Furthermore, the comparison network includes an NMOS transistor N6, whose source is grounded, its gate is connected to the gate of an NMOS transistor N5, and its drain is connected to the power supply VDD.

[0010] The beneficial effects of this invention are as follows: This invention does not directly limit the current of the depletion-type GaN device. Instead, it connects a Si power transistor to the source of the depletion-type GaN device and uses a comparison of the reference current and the replicated current to form negative feedback, thereby limiting the maximum load current of the Si power transistor and achieving overcurrent protection for the depletion-type GaN. Therefore, this invention avoids the normally open characteristic problem of traditional overcurrent protection for depletion-type GaN devices. While ensuring high-precision current limiting and fast response, it can greatly simplify the circuit structure and effectively reduce circuit costs. Attached Figure Description

[0011] Figure 1 The diagram shows an overcurrent protection circuit structure for a depletion-type GaN device. Detailed Implementation

[0012] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.

[0013] This invention provides an overcurrent protection circuit for depletion-mode GaN devices, such as... Figure 1 As shown, it includes a clamping network, a voltage follower network, a replication network, a comparator network, and a Si power transistor connected in sequence. The source of the Si power transistor is grounded, its gate is connected to the power supply VDD, and its drain is connected to the source of the GaN device.

[0014] like Figure 1As shown, the clamping network includes a PMOS transistor P1, whose drain is grounded. Its gate is connected to the grounding resistor R1 and the source of an NMOS transistor N1, respectively. Its source is connected to the grounding resistor R2, the source of an NMOS transistor N2, and the voltage follower network, respectively. The gate of an NMOS transistor N2, as well as the gate and drain of an NMOS transistor N1, are all connected to the power supply VDD. The drain of an NMOS transistor N2 is connected to the drain voltage Vs of the Si power transistor.

[0015] like Figure 1 As shown, the voltage follower network includes an operational amplifier OP1. The non-inverting input of the operational amplifier OP1 is connected to the source of the PMOS transistor P1, and its inverting input and output are both connected to the replication network.

[0016] like Figure 1 As shown, the replication network includes PMOS transistors P2 and P3. The sources of PMOS transistors P2 and P3 are both connected to the power supply VDD. The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P2, the gate of PMOS transistor P3, and the drain of NMOS transistor N4. The gate of NMOS transistor N4 is connected to the output of operational amplifier OP1, and its source is connected to the inverting input of operational amplifier OP1 and the drain of NMOS transistor N3. The source of NMOS transistor N3 is grounded, and its gate is connected to the power supply VDD. The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, and the comparator network. The source of NMOS transistor N5 is grounded.

[0017] like Figure 1 As shown, the comparison network includes NMOS transistor N6, whose source is grounded, its gate is connected to the gate of NMOS transistor N5, and its drain is connected to the power supply VDD.

[0018] The following is combined with Figure 1 The working principle and process of this invention are described in detail below:

[0019] like Figure 1 As shown, in the clamping network, I1 is the bias current supplied from the outside, which allows the NMOS transistor N2 to conduct. If the device current is too large, it will cause the drain voltage Vs of the Si power transistor to be extremely high. At this time, the PMOS transistor P1 will clamp Vs_COPY, i.e., the positive terminal voltage of the operational amplifier OP1, to I1*R1+VTH (VTH is the threshold voltage of the PMOS transistor P1), protecting the subsequent circuit from being burned out. When the current decreases, the voltage Vs will be gradually pulled down to VSS (i.e., the ground voltage), forcing the NMOS transistor N2 to enter the deep linear region. Therefore, at this time, Vs = Vs_COPY.

[0020] In the voltage follower network, during the overcurrent phenomenon, the voltage at the non-inverting input of operational amplifier OP1 is clamped to I1*R1+VTH. NMOS transistor N3 acts as a replica transistor. Operational amplifier OP1 makes the drain voltage of replica transistor N3 follow the source voltage of NMOS transistor N2. Because the current is large, current limiting is triggered, and the gate voltage of Si power transistor and replica transistor N3 is pulled down. Both Si power transistor and replica transistor N3 are in the saturation region. Therefore, although the drain voltages of replica transistor N3 and Si power transistor are different, the current replication is relatively accurate.

[0021] After the overcurrent phenomenon ends, the voltage Vs decreases, the NMOS transistor N2 is in the deep linear region, the voltage at the non-inverting input of the operational amplifier OP1 is approximately Vs, and both the Si power transistor and the replica transistor N3 are in the deep linear region. At this time, the on-resistance of the replica transistor N3 is very small, and the drain voltage has a significant impact on current replication. Therefore, the operational amplifier OP1 is used to implement a voltage follower so that the three-terminal voltages of the replica transistor N3 and the Si power transistor are the same, in order to ensure accurate current replication.

[0022] In both the replication and comparison networks, current mirroring is used. The replicating transistor N3 replicates the current of the Si power transistor at a certain ratio. PMOS transistor P2 receives the current replicated by N3 and then replicates it to PMOS transistor P3 at a certain ratio. The current flowing from the drain of NMOS transistor N5 into PMOS transistor P3 is then mirrored to NMOS transistor N6. Finally, the current of NMOS transistor N6, i.e., the pull-down current, can be compared with the reference current I2. When the current of the Si power transistor is too large, after three replications, the pull-down current also increases, pulling down the gate voltage of the Si power transistor, thereby reducing the current of the Si power transistor. This process forms negative feedback, stabilizing the gate voltage of the Si power transistor at an equilibrium value. Therefore, the current of the Si power transistor is limited within a threshold, avoiding overcurrent, thus achieving overcurrent protection for depletion-mode GaN.

[0023] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. An overcurrent protection circuit for depletion-mode GaN devices, characterized in that, It includes a clamping network, a voltage follower network, a replication network, a comparator network, and a Si power transistor connected in sequence. The source of the Si power transistor is grounded, its gate is connected to the power supply VDD, and its drain is connected to the source of the GaN device.

2. The overcurrent protection circuit for depletion-mode GaN devices according to claim 1, characterized in that, The clamping network includes a PMOS transistor P1, the drain of which is grounded, and its gate is connected to a grounding resistor R1 and the source of an NMOS transistor N1. The source of the PMOS transistor N1 is connected to a grounding resistor R2, the source of an NMOS transistor N2, and a voltage follower network. The gate of the NMOS transistor N2, as well as the gate and drain of the NMOS transistor N1, are all connected to the power supply VDD. The drain of the NMOS transistor N2 is connected to the drain voltage Vs of the Si power transistor.

3. The overcurrent protection circuit for depletion-type GaN devices according to claim 2, characterized in that, The voltage follower network includes an operational amplifier OP1, the non-inverting input of which is connected to the source of a PMOS transistor P1, and both its inverting input and output are connected to a replication network.

4. The overcurrent protection circuit for depletion-mode GaN devices according to claim 3, characterized in that, The replication network includes PMOS transistors P2 and P3. The sources of PMOS transistors P2 and P3 are both connected to the power supply VDD. The gate of PMOS transistor P2 is connected to the drain of PMOS transistor P2, the gate of PMOS transistor P3, and the drain of NMOS transistor N4. The gate of NMOS transistor N4 is connected to the output of operational amplifier OP1, and its source is connected to the inverting input of operational amplifier OP1 and the drain of NMOS transistor N3. The source of NMOS transistor N3 is grounded, and its gate is connected to the power supply VDD. The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, and the comparator network. The source of NMOS transistor N5 is grounded.

5. The overcurrent protection circuit for depletion-type GaN devices according to claim 4, characterized in that, The comparison network includes an NMOS transistor N6, the source of which is grounded, its gate is connected to the gate of an NMOS transistor N5, and its drain is connected to the power supply VDD.

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