High-frequency cavity frequency locking and phase sweeping system based on digital self-excitation
By using a digitally self-excited high-frequency cavity frequency locking and phase sweeping system, combined with a digital SEL loop and PLL loop, the problem of unstable RF frequency in conventional SEL mode is solved, achieving stable control and phase adjustment of the cavity field, which is suitable for high-frequency low-level operation of accelerator devices.
Patent Information
- Application Number
- CN202510931069.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-10-31
AI Technical Summary
In conventional SEL mode, the RF frequency is not fixed, and the phase of the high-frequency cavity radio frequency field cannot be controlled, resulting in cavity field instability. Therefore, it cannot be applied to the high-frequency low-level operation system of accelerator devices.
A high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation is adopted, including a digital SEL loop and a cavity frequency PLL loop. The algorithm is developed using a low-level control unit FPGA to realize the establishment of the radio frequency field and the locking of the cavity frequency. The phase adjustment is realized through the PLL loop.
It achieves RF frequency locking and controllable adjustment of cavity field amplitude and phase in SEL mode, which is suitable for high-frequency low-level operation of accelerator devices and overcomes the shortcomings of phase control in conventional SEL mode.
Smart Images
Figure CN120880432A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of accelerator technology, specifically relating to a high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation, which is applied to the high-frequency cavity radio frequency field establishment and phase sweeping of a high-frequency low-level control system. Background Technology
[0002] High-frequency low-level control is used to achieve amplitude and phase control of the cavity field and cavity frequency tuning control of the high-frequency cavity.
[0003] The low-level control operating modes are mainly divided into GDR (Generator Driven Resonator) mode and SEL (Self Exited Loop) mode. GDR mode is mainly used for high-power horizontal testing of high-frequency cavities and online formal operation of high-frequency devices in accelerators, while SEL mode is mainly used for vertical testing of high-frequency cavities.
[0004] In GDR mode, the frequency of the RF (Ratio Frequency) signal is fixed. If the frequency of the high-frequency cavity deviates from the frequency of the RF signal, the low-level tuning device will adjust the frequency of the cavity to stabilize it within an acceptable frequency range.
[0005] In conventional SEL mode, the frequency of the RF signal automatically tracks the frequency of the high-frequency cavity, eliminating the need for a frequency control loop. However, because the cavity frequency is not fixed, the phase of the cavity field is also variable and uncontrollable.
[0006] For superconducting cavities with a high quality factor (QL), due to their narrow bandwidth, the impact of external noise interference on the cavity frequency variation is relatively large, which can easily lead to cavity instability. In SEL mode, the radio frequency signal automatically tracks the cavity frequency variation, allowing the high-frequency cavity to operate stably even under significant external interference. Therefore, high-QL superconducting cavities are also suitable for SEL self-excited mode.
[0007] In accelerator operating systems, the frequency of the RF signal used to establish the high-frequency cavity field needs to be locked to the frequency of the reference line RF signal. At the same time, the amplitude and phase of the cavity field can be controlled and adjusted. This makes the conventional SEL mode unsuitable for the high-frequency, low-level operating system of accelerator devices. Summary of the Invention
[0008] To address the shortcomings of conventional SEL mode, where the RF frequency is not fixed and the phase of the RF field within the high-frequency cavity cannot be controlled, this invention aims to provide a high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation. This invention utilizes a low-level control unit (FPGA) for algorithm development and implementation, primarily comprising two loops: a digital self-excited SEL loop and a cavity frequency phase-locked loop (PLL). The reference line RF signal is input to the low-level control unit to generate a digital low-level clock signal. The cavity field RF retrieval signal serves as the input signal for the low-level control unit to acquire RF signals. The RF excitation signal output from the SEL loop is amplified by a power source and then sent to the high-frequency cavity via a high-power transmission line, thereby establishing the RF field within the high-frequency cavity. The piezo excitation signal output from the PLL loop is amplified by a piezo driver and applied to the high-frequency cavity to achieve frequency locking control. The vector rotation module within the PLL loop can adjust the cavity field phase, achieving phase sweeping.
[0009] The technical solution of this invention is as follows:
[0010] A high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation mainly consists of two parts: a digital SEL loop and a cavity frequency PLL loop.
[0011] Digital SEL loop:
[0012] The digital SEL loop consists of a low-level control unit, a power source, a transmission line, and a high-frequency cavity. The entire digital SEL link forms a self-closed loop, and the sum of the RF phases of the entire digital SEL link satisfies an integer multiple of 2π.
[0013] The low-level control unit mainly includes:
[0014] 1. Clock Distribution Module: The clock distribution module, which receives the reference line RF signal input to the low-level control unit, generates the ADC clock, DAC clock, FPGA operating clock, and IF (Intermediate Frequency) signal. The frequencies of the ADC clock, DAC clock, and FPGA operating clock are M-divisions of the RF frequency, and the frequency of the IF signal is N-divisions of the RF frequency. The division coefficients M and N are configured according to the Non-IQ algorithm.
[0015] 2. RF Up / Down Conversion Module: The reference line RF signal and the IF intermediate frequency signal are mixed to obtain the LO (Local Oscillator) signal, which is then sent to the up / down conversion channels. The down conversion channel downconverts the cavity field RF sampling signal into the cavity field IF intermediate frequency sampling signal; the up conversion channel upconverts the analog IF intermediate frequency excitation signal into a high-frequency RF excitation signal.
[0016] 3. High-frequency RF signal acquisition module: The cavity field RF retrieval signal from the high-frequency cavity is down-converted to obtain the cavity field IF retrieval signal. After analog-to-digital conversion by an ADC, it is sent to an FPGA (Field Programmable Gate Array) for Non-IQ sampling to obtain the I / Q domain signal pairs sel_i and sel_q. The two signals are then processed by the Cordic (Coordinate Rotation Digital Computer) IQ-to-phase algorithm to obtain the phase sel_pha and amplitude sel_amp. Only the phase value sel_pha is retained, and the amplitude is taken as the full-scale value and processed by the Cordic amplitude-to-phase IQ algorithm to obtain the normalized sel_cor_i and sel_cor_q.
[0017] 4. High-Frequency RF Excitation Signal Generation Module: The cavity field setting amplitude and cavity field setting phase are converted into sel_set_i and sel_set_q in the I / Q domain. The two pairs of I / Q signals, sel_set_i / q and sel_cor_i / q, are sent to the vector rotation module to realize the phase shift and amplitude setting of the sampled signal, resulting in the dds_i and dds_q signal pairs. The dds_i / q signal pairs are sent to the DDS (Direct Digital Synthesizer) module to output the digital IF intermediate frequency excitation signal rf_out. rf_out is converted from digital to analog by a DAC to obtain the analog IF intermediate frequency excitation signal, and then up-converted to obtain the high-frequency RF excitation signal.
[0018] The high-frequency RF excitation signal is amplified by a power source after passing through an RF switch, and then sent into the high-frequency cavity for high-frequency field establishment after passing through a high-power transmission line. The cavity field RF feedback signal obtained from the cavity field pickup port is input to the low-level control unit via a phase-stabilized cable, thus forming the entire SEL loop.
[0019] Furthermore, the SEL loop is a positive feedback loop and requires amplitude limiting. The amplitudes sel_amp and sel_pha are obtained through the cordicIQ amplitude-to-phase conversion module of the low-level control unit. The amplitude of sel_amp is discarded, and sel_pha and the full-scale amplitude (approximately 19890) are input to the cordic amplitude-to-phase conversion IQ module to obtain normalized sel_cor_i and sel_cor_q. Thus, the signal pair sel_cor_i / q only contains the phase information of the cavity field retrieval signal, discarding the amplitude information. The cavity field amplitude and phase setting parameters are converted into sel_set_i / q signal pairs. These two pairs of signals, sel_set_i / q and sel_cor_i / q, are input to the vector rotation module to obtain the output dds_i / q. The amplitude of the dds_i / q signal pair depends only on the amplitude of the sel_set_i / q setting signal and is independent of the actual amplitude of the RF retrieval signal, thereby achieving amplitude control of the self-excited loop and achieving amplitude limiting.
[0020] Furthermore, the sum of the RF phases of the entire SEL loop link needs to be an integer multiple of 2π. The vector rotation module of the low-level control unit can adjust the phase to ensure that the entire link meets the phase requirement. The high-frequency cavity has the narrowest bandwidth in the entire link. When the frequency of the high-frequency cavity changes, the original RF signal phase will no longer meet the 2π integer multiple requirement. Only RF signals with the same frequency as the high-frequency cavity will meet the phase requirement, thus ensuring that the self-excited loop RF field-building signal can automatically track the cavity frequency of the high-frequency cavity.
[0021] Cavity frequency PLL loop:
[0022] The cavity frequency PLL loop is a self-closing loop, consisting of a low-level control unit, a Piezo driver, and a high-frequency cavity. The low-level control unit performs phase detection and phase shifting functions, and outputs the detected phase. The detected phase is amplified by the Piezo driver and applied to the high-frequency cavity to adjust the cavity frequency. Simultaneously, the cavity field RF retrieval signal enters the low-level circuit for phase detection, thus forming the entire PLL phase-locked loop. A PLL loop typically consists of three parts: a phase detector, a loop filter, and a voltage-controlled oscillator. In this system, the low-level control unit performs phase detection and filtering functions, while the combination of the Piezo driver and the high-frequency cavity acts as the voltage-controlled oscillator in the PLL loop.
[0023] 1. Digital phase detection of cavity field RF re-acquisition signal: After low-level acquisition, the cavity field RF re-acquisition signal of the high-frequency cavity is used to obtain the I / Q domain signal pairs sel_i and sel_q. The PLL phase-locked loop sets the amplitude and phase parameters, which are converted into the IQ domain signal pairs pll_shift_i and pll_shift_q. The two pairs of I / Q signals, pll_shift_i / q and sel_i / q, are sent to the vector rotation module to realize the amplitude adjustment and phase shift of the re-acquisition signal, resulting in the cav_i and cav_q signal pairs. The cav_i / q signal pairs are processed by the cordic IQ amplitude and phase shifting algorithm to obtain the cavity phase signal cav_angle. The cavity phase is low-pass filtered by CIC (Cascaded Integrator Comb Filter) and then output as the piezo digital drive signal.
[0024] 2. Phase Detection Output and Cavity Tuning: The piezo digital drive signal is converted from digital to analog by an SDAC (Serial Digital-to-Analog Converter) to obtain a piezo analog drive signal. This piezo analog drive signal is output to a piezo driver for amplification to obtain a piezo tuning high-voltage signal. The piezo tuning high-voltage signal is applied to the ceramic on the cavity end of the high-frequency cavity to achieve frequency tuning of the high-frequency cavity.
[0025] 3. Acquisition of cavity field RF feedback signal: The cavity field RF feedback signal of the high-frequency cavity is connected to the low-level control unit via a phase-stabilized cable. After down-conversion, the cavity field IF feedback signal is obtained. After analog-to-digital conversion by ADC, it is sent to FPGA (Field Programmable Gate Array) for non-iq sampling to obtain I / Q domain signals sel_i and sel_q, thereby forming a PLL phase-locked loop closed loop.
[0026] Furthermore, the sel_i and sel_q of the I / Q domain obtained from the acquisition of the cavity field RF retrieval signal to the low-level control unit are shared by the self-excited loop and the phase-locked loop, while the vector rotation part uses different module units.
[0027] Furthermore, the self-excited loop and phase-locked loop algorithms are mainly developed based on the FPGA of the low-level digital signal processing board.
[0028] When the SEL loop and PLL loop operate simultaneously, frequency-locked and phase-locked operation of the cavity field in self-excited mode can be achieved. In SEL mode, after the PLL loop is closed, the cavity field sampling signal of the high-frequency cavity is locked to the reference line RF signal, that is, the frequency is locked to the frequency of the reference line RF signal, and the cav_angle phase is also locked to the phase of the reference line RF signal. Since the frequency and phase of the reference line RF signal are fixed as a reference signal, the frequency of the cavity field sampling signal is locked to the frequency of the reference line RF signal, and the phase detection phase cav_angle remains unchanged. Since there is a phase offset between the actual phase of the high-frequency cavity field and cav_angle, when this offset is changed, the actual phase of the high-frequency cavity field will change because cav_angle remains unchanged. The vector rotation module in the PLL loop corresponds to the adjustment of the phase offset. Therefore, when the set phase of the vector rotation module in the PLL is changed, the phase of the high-frequency cavity field can be adjusted. Changing the set phase of the vector rotation module by 360 degrees can achieve phase scanning of the high-frequency cavity field.
[0029] Compared with GDR mode and conventional SEL self-excitation control, the present invention has the following advantages:
[0030] 1) This method can achieve RF frequency locking in SEL mode, making it possible for low-level controlled self-excitation mode to operate in accelerator devices, rather than just in low-power vertical tests.
[0031] 2) This method overcomes the drawback of the inability to control the phase in the conventional SEL mode, and realizes that both the amplitude and phase of the cavity field can be controlled and adjusted.
[0032] 3) Compared to the GDR mode, the SEL mode has a simpler architecture and is easier to implement. Attached Figure Description
[0033] Figure 1 This is a block diagram of a high-frequency cavity frequency-locked phase-sweeping system based on digital self-excitation.
[0034] Figure 2 This is a block diagram illustrating the basic principle of a PLL (phase-locked loop).
[0035] Figure 3 This is a hardware algorithm block diagram of a high-frequency cavity frequency-locked phase-sweeping system based on digital self-excitation. Detailed Implementation
[0036] The present invention will now be described in further detail with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.
[0037] 1. Top-level design
[0038] The principle block diagram of the high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation is as follows: Figure 1 As shown, it mainly consists of two parts: a self-excited loop and a phase-locked loop.
[0039] The self-excited loop includes data acquisition from the low-level control unit, a first phase-shifting unit, a power source, a transmission line, and a high-frequency cavity. The low-level control unit acquires the RF feedback signal from the high-frequency cavity, converting it into a digital signal within the FPGA. The first phase-shifting unit adjusts the phase of the self-excited loop so that the sum of the RF phases of the entire loop is an integer multiple of 2π. The power source amplifies the low-level excitation signal, which is then sent to the high-frequency cavity via the transmission line for field establishment.
[0040] A PLL (phase-locked loop) typically consists of three parts: a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). Figure 2 As shown. The PLL loop of this system mainly includes data acquisition from the low-level control unit, a second phase-shifting unit, phase detection and filtering, a Piezo driver, and a high-frequency cavity. The low-level control unit performs phase detection and filtering, while the combination of the Piezo driver and the high-frequency cavity acts as a voltage-controlled oscillator. The data acquisition from the low-level control unit converts the cavity field RF feedback signal of the high-frequency cavity into a digital signal inside the FPGA. The second phase-shifting unit rotates and shifts the phase of the cavity field RF feedback signal vector before performing phase detection again. The phase detection output is filtered and then output to the Piezo driver. The Piezo driver amplifies the output signal and applies it to the ceramic of the high-frequency cavity to adjust the cavity frequency, thereby locking the cavity frequency. The second phase-shifting unit can change the phase offset between the phase detection phase and the cavity field phase of the PLL loop to achieve phase sweeping of the high-frequency cavity field.
[0041] 2. Hardware and Algorithm Design
[0042] The hardware and algorithm block diagram of the high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation is as follows: Figure 3 As shown.
[0043] The self-excited loop mainly consists of a low-level control unit, a power source, a transmission line, and a high-frequency cavity. The cavity field RF feedback signal of the high-frequency cavity enters the low-level control unit, first undergoes down-conversion, and then is converted into a cavity field IF intermediate frequency feedback digital signal by an ADC and sent to the FPGA unit. After a series of algorithm control, the FPGA unit outputs the IF intermediate frequency excitation analog signal through a DAC digital-to-analog conversion. After up-conversion, the RF excitation signal is output from the low-level control unit, amplified by the power source, and then sent to the high-frequency cavity for field establishment via the transmission line.
[0044] The control algorithm of the SEL loop FPGA unit is as follows: The cavity field IF intermediate frequency retrieval digital signal is processed by the Non-IQ sampling module to obtain the I / Q domain signal pairs sel_i and sel_q. The sel_i / q signals are sent to the first cordic IQ-to-phase conversion module to obtain the amplitude sel_amp and phase sel_pha of the retrieval signal. Only the phase value is retained, and the amplitude is set to the full scale value (approximately 19890). The first cordic amplitude-to-phase conversion module obtains the I / Q domain sel_cor_i and sel_cor_q signal pairs. The first amplitude-phase setting module of the self-excited loop generates the sel_set_i and sel_set_q signal pairs. The sel_set_i / q and sel_cor_i / q signals are sent to the first vector rotation module to realize amplitude setting and phase shifting. The output is then sent to the DDS. The DDS generates the IF intermediate frequency digital excitation signal, which is then output to the DAC for digital-to-analog conversion.
[0045] The PLL loop mainly consists of a low-level control unit, a Piezo driver, and a high-frequency cavity. The main algorithm of the PLL loop is also implemented by an FPGA unit.
[0046] The control algorithm of the PLL loop FPGA is as follows: The second amplitude and phase setting module of the phase-locked loop generates the pll_set_i and pll_set_q signal pairs. The pll_set_i / q signal pairs and the sel_i / q signal pairs obtained in the self-excited loop are sent to the second vector rotation module to realize the phase shift of the sel_i / q signal pairs. The phase-shifted signal is passed through the second cordic IQ amplitude and phase shifting module to obtain the cavity field phase signal cav_angle. The cav_angle signal is low-pass filtered by CIC (Cascaded Integrator Comb Filter) to remove high-frequency signals and obtain the piezo excitation digital signal.
[0047] The Piezo excitation digital signal is converted into a Piezo excitation analog signal by a DAC and then sent to a Piezo driver for amplification. The amplified high-voltage signal is applied to the ceramic body mounted on the high-frequency cavity end side to achieve frequency adjustment of the cavity. The cavity field RF retrieval signal is used as a feedback signal input to the low-level control unit to form the entire phase-locked loop.
[0048] 3. System integration and debugging
[0049] Building such Figure 3After establishing the hardware system shown, the self-excited loop is first debugged. Establishing the self-excited loop requires the RF phase of the entire link to be an integer multiple of 2π. This phase requirement can be achieved by adjusting the phase setting value of the first vector rotation module of the self-excited loop, using a phase sweep method. This ensures that the sum of the RF phases of the digital SEL loop is an integer multiple of 2π. Simultaneously, amplitude limiting is implemented through amplitude setting, ultimately enabling the self-excited loop to operate normally, allowing the frequency of the high-frequency cavity field-building RF signal to automatically track the cavity resonant frequency in real time.
[0050] Once the self-excited loop is operating normally, closing the phase-locked loop switch will enable real-time tuning of the cavity frequency, locking the cavity frequency to the reference line RF signal frequency. Adjusting the phase setting value of the second vector rotation module of the phase-locked loop allows for control of the high-frequency cavity field phase, completing the phase sweep of the cavity field.
[0051] The high-power level test of the 1.3GHz superconducting module developed by the Institute of High Energy Physics, Chinese Academy of Sciences, in Dalian, was completed using the method of this invention to achieve high Q value and high gradient experiments. Furthermore, the dark current test of the 1.3GHz superconducting module was achieved using the 360-degree phase sweep of the PLL loop of this invention.
[0052] The above description is only used to illustrate a specific embodiment of the present invention and is not intended to limit the invention. Those skilled in the art can make substitutions, modifications and simple changes to it without departing from the scope of the present technical solution, and these substitutions, modifications and simple changes cannot cause the essence of the corresponding technical solution to deviate from the scope of the present new embodiment.
Claims
1. A high-frequency cavity frequency locking and phase sweeping system based on digital self-excitation, characterized in that, Including digital SEL loop and cavity frequency PLL loop; The digital SEL loop is a self-closed loop consisting of a low-level control unit, a power source, and a high-frequency cavity, and the sum of the radio frequency phases of the digital SEL loop satisfies an integer multiple of 2π. The clock distribution module in the low-level control unit is used to generate ADC clock, DAC clock, FPGA operating clock and IF signal according to the input reference line RF signal; The mixing module in the low-level control unit is used to mix the input reference line RF signal and the IF signal to obtain a local oscillator signal, which is then sent to the RF up-conversion module and the RF down-conversion module in the low-level control unit, respectively. The RF up-conversion module is used to up-convert the analog IF intermediate frequency excitation signal into a high-frequency RF excitation signal and then send it to the power source via an RF switch. The RF down-conversion module is used to down-convert the cavity field RF sampling signal of the high-frequency cavity into a cavity field IF intermediate frequency sampling signal. The ADC analog-to-digital converter in the low-level control unit is used to convert the cavity field IF intermediate frequency retrieval signal into a digital signal and then send it to the FPGA. The FPGA data acquisition module in the low-level control unit is used to sample the digital signal using the Non-IQ algorithm to obtain I / Q domain signal pairs sel_i and sel_q. The two signals are then converted to phase and amplitude values sel_pha and sel_amp by the Cordic IQ amplitude-phase conversion algorithm. After taking the full-range value of amplitude sel_amp, the phase value sel_pha and the amplitude sel_amp are normalized to sel_cor_i and sel_cor_q by the cordic amplitude-phase conversion IQ algorithm and then sent to the first vector rotation module. The high-frequency RF excitation signal generation module in the low-level control unit is used to convert the cavity field setting amplitude and cavity field setting phase provided by the first amplitude and phase setting module into I / Q domain signal pairs sel_set_i and sel_set_q and send them to the first vector rotation module. The first vector rotation module performs phase shifting and amplitude setting according to the input sel_set_i, sel_set_q and sel_cor_i, sel_cor_q, and obtains signal pairs dds_i and dds_q, which are sent to the direct digital frequency synthesizer (DDS). The output digital IF intermediate frequency excitation signal rf_out is converted from digital to analog by a DAC to obtain an analog IF intermediate frequency excitation signal, which is then input to the RF upconversion module. The power source is used to amplify the high-frequency RF excitation signal input through the RF switch and send it into the high-frequency cavity for high-frequency field establishment. The cavity frequency PLL loop is a self-closed loop consisting of the low-level control unit, the Piezo driver, and the high-frequency cavity. The FPGA inputs the I / Q domain signal pairs sel_i and sel_q into the second vector rotation module, and converts the PLL phase-locked loop set amplitude and PLL phase set provided in the second amplitude-phase setting module into IQ domain signal pairs pll_shift_i and pll_shift_q, which are then sent to the second vector rotation module. The second vector rotation module performs phase shift and amplitude adjustment on the input signal pairs sel_i, sel_q and pll_shift_i, pll_shift_q to obtain signal pairs cav_i and cav_q. The cav_i / q signal pairs are then processed by the second cordic IQ amplitude-phase conversion module to obtain the cavity phase signal cav_angle. The cav_angle signal is then low-pass filtered by CIC and output as a piezo digital drive signal. The Piezo digital drive signal is converted into a Piezo analog drive signal and then amplified by a Piezo driver to obtain a Piezo tuning high voltage signal; the Piezo tuning high voltage signal is applied to the ceramic on the cavity end of the high-frequency cavity to achieve frequency tuning of the high-frequency cavity.
2. The system according to claim 1, characterized in that, The frequencies of the ADC clock, DAC clock, and FPGA operating clock are M-divisions of the reference line RF signal frequency, and the frequency of the IF signal is N-divisions of the reference line RF signal frequency. The division coefficients M and N are configured according to the Non-IQ algorithm.
3. The system according to claim 1, characterized in that, The Piezo digital drive signal is converted from digital to analog by a serial digital-to-analog converter (SDAC) to obtain the Piezo analog drive signal.
4. The system according to claim 1, 2, or 3, characterized in that, The cavity field RF retrieval signal is acquired through the cavity field pickup port of the high-frequency cavity and sent to the RF downconversion unit via a phase-stable cable.
5. The system according to claim 1, 2, or 3, characterized in that, The power source amplifies the high-frequency RF excitation signal input through the RF switch and then sends it through the transmission line into the high-frequency cavity for high-frequency field establishment.
6. The system according to claim 1, 2, or 3, characterized in that, By adjusting the phase setting value of the second vector rotation module, the cavity field phase of the high-frequency cavity is controlled, and the phase sweep of the cavity field phase is completed.
7. The system according to claim 1, 2, or 3, characterized in that, By adjusting the phase setting value of the first vector rotation module, the sum of the radio frequency phases of the digital SEL loop is made to satisfy an integer multiple of 2π through a phase sweep method.