A PLL layout structure for MCU chips

Abstract

This application provides a PLL layout structure for use in MCU chips. By providing a digital function layout area, an analog function layout area, and a signal output layout area, the digital function layout area includes a first function area for placing a frequency and phase detector; the analog function layout area includes a second function area for placing a charge pump, a third function area for placing a low-pass filter, a fourth function area for placing a current mirror, and a fifth function area for placing a voltage-controlled oscillator; the lower sides of the second and fourth function areas are close to the upper sides of the first function area, the left side of the fourth function area is close to the right side of the second function area, the lower side of the third function area is close to the upper sides of the second and fourth function areas, and the right side of the fifth function area is close to the left sides of the first and fourth function areas, thereby significantly improving the loop signal stability of the PLL and enabling multiple PLLs to be arranged in parallel within the MCU chip.

Description

Technical Field

[0001] This application relates to the field of CMOS analog integrated circuit layout design technology, and in particular to a PLL layout structure applied to MCU chips. Background Technology

[0002] Analog layout is a crucial step in the physical implementation of circuit design, and its quality directly determines circuit performance. In MCU chips, PLLs are used to generate stable clock signals, providing a timing basis for the digital modules within the MCU chip. Multiple PLLs are typically integrated to meet different frequency requirements. However, existing PLL layouts lack compatibility support for parallel multi-PLL structures, and unreasonable internal module arrangement leads to insufficient stability of reference current and voltage signals, affecting the loop stability of the PLL. Consequently, excessive clock jitter generated by the PLL occurs during post-layout simulation and chip testing, severely restricting the overall reliability of the chip. Summary of the Invention

[0003] The purpose of this application is to at least solve one of the technical problems existing in the prior art, and to provide a PLL layout structure for MCU chips. The frequency and phase detector, charge pump, low-pass filter, mirror current source and voltage-controlled oscillator are partitioned and precisely attached, realizing that multiple PLLs can share the reference current and voltage source in parallel within the MCU chip. This significantly improves the loop signal stability and anti-interference capability of the PLL, while reducing the layout area, reducing chip cost, effectively suppressing clock jitter, and ensuring the high-frequency timing accuracy and operational reliability of the MCU.

[0004] To achieve the above objectives, a first aspect of this application proposes a PLL layout structure for use in MCU chips, comprising:

[0005] The digital functional layout area includes the first functional area;

[0006] The analog function layout area is located above the digital function layout area. The analog function layout area includes the second, third, fourth and fifth function areas.

[0007] The signal output layout area is located below the digital function layout area.

[0008] Among them, the lower side of the second functional area and the lower side of the fourth functional area are close to the upper side of the first functional area, the left side of the fourth functional area is close to the right side of the second functional area, the lower side of the third functional area is close to the upper side of the second functional area, the upper side of the fourth functional area and the upper side of the fifth functional area, and the right side of the fifth functional area is close to the left side of the first functional area and the fourth functional area.

[0009] The first functional area is used to house the frequency and phase detector circuitry; the second functional area is used to house the charge pump circuitry; the third functional area is used to house the low-pass filter circuitry; the fourth functional area is used to house the mirror current source circuitry; and the fifth functional area is used to house the voltage-controlled oscillator circuitry.

[0010] Furthermore, in some embodiments, the digital functional layout area also includes a sixth functional area, the upper side of which is close to the lower side of the first functional area, and the left side of which is close to the right side of the fifth functional area. The sixth functional area is used to house the functional circuitry of the frequency divider.

[0011] Furthermore, in some embodiments, the signal output layout area includes a seventh functional area, the upper side of which is close to the lower side of the fifth functional area and the lower side of the sixth functional area, respectively. The seventh functional area is used to place the level conversion functional circuit.

[0012] Furthermore, in some embodiments, the first functional area is used to house the functional circuitry of the frequency and phase detector, including:

[0013] The first functional area is used to connect the functional circuit of the frequency and phase detector to the functional circuit of the charge pump and the functional circuit of the frequency divider, respectively, and to receive the reference clock signal and the frequency-divided clock signal input by the functional circuit of the frequency divider, and to perform frequency / phase differential comparison between the frequency-divided clock signal and the reference clock signal to obtain the differential analog signal and output the differential analog signal to the functional circuit of the charge pump.

[0014] Furthermore, in some embodiments, the fourth functional area is used to house the functional circuitry for the mirror current source, including:

[0015] The fourth functional area is used to connect the circuit of the mirror current source to the functional circuit of the voltage-controlled oscillator, generate a bias current signal, and output a bias current signal to the functional circuit of the charge pump.

[0016] Furthermore, in some embodiments, the second functional area is used to house the functional circuitry of the charge pump, including:

[0017] The second functional area is used to connect the functional circuit of the charge pump to the functional circuit of the low-pass filter, and to receive differential analog signals and bias current signals through the functional circuit of the charge pump, and to combine the differential analog signals and bias current signals into charge and discharge control signals, and output the charge and discharge control signals to the functional circuit of the low-pass filter.

[0018] Furthermore, in some embodiments, the third functional area is used to house the functional circuitry of a low-pass filter, including:

[0019] The third functional area is used to connect the functional circuit of the low-pass filter to the functional circuit of the voltage-controlled oscillator, and to receive the charge and discharge control signal through the functional circuit of the low-pass filter, and to filter and convert the charge and discharge control signal to obtain the control voltage signal, and output the control voltage signal to the functional circuit of the voltage-controlled oscillator.

[0020] Furthermore, in some embodiments, the fifth functional area is used to house the functional circuitry of the voltage-controlled oscillator, including:

[0021] The fifth functional area is used to connect the functional circuit of the voltage-controlled oscillator to the functional circuit of the frequency divider and the functional circuit of the level conversion, respectively. It receives the control voltage signal through the functional circuit of the voltage-controlled oscillator, and performs oscillation processing on the control voltage signal to obtain a digital clock signal. The digital clock signal is then output to the functional circuit of the frequency divider and the functional circuit of the level conversion.

[0022] Furthermore, in some embodiments, the sixth functional area is used to house the functional circuitry of the frequency divider, including:

[0023] The sixth functional area is used to receive digital clock signals through the frequency divider's functional circuit, and to perform frequency division processing on the digital clock signals to obtain frequency-divided clock signals, and output the frequency-divided clock signals to the frequency and phase detector's functional circuit.

[0024] Furthermore, in some embodiments, the seventh functional area is used to house level-shifting functional circuitry, including:

[0025] The seventh functional area is used to receive digital clock signals through level conversion circuitry and output the digital clock signals in a level-converted manner.

[0026] According to an embodiment of this application, a PLL layout structure applied to an MCU chip has at least the following advantages: By placing the analog function layout area on top of the digital function layout area and the signal output layout area on the bottom of the digital function layout area, the analog function layout and the digital function layout are placed separately, which helps to reduce mutual interference between the two functional layouts, ensure the stability of the PLL loop, and reduce clock jitter of the output clock. At the same time, dividing the five core functional circuits—frequency and phase detector, charge pump, low-pass filter, mirror current source, and voltage-controlled oscillator—into closely fitted and relatively independent layout areas can improve the compatibility of the multi-PLL parallel structure, realize application scenarios where multiple PLLs are placed in parallel, and greatly save chip area, reduce the overall complexity and production cost of the multi-PLL system, thereby effectively improving the timing accuracy, system stability, and mass production yield of the MCU chip. By placing the lower side of the second functional area close to the upper side of the first functional area, the trace length between the functional circuit of the frequency and phase detector and the functional circuit of the charge pump can be effectively shortened, reducing the parasitic resistance and capacitance caused by the trace. Furthermore, by placing the lower side of the third functional area close to the upper side of the fourth functional area, the functional circuit of the mirror current source can be directly connected to the functional circuit of the low-pass filter, thereby improving the accuracy of the bias current signal generated and output by the functional circuit of the mirror current source.

[0027] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0028] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] The present application will be further described below with reference to the accompanying drawings and embodiments;

[0030] Figure 1 This is a schematic diagram of an optional PLL layout structure for an MCU chip provided in an embodiment of this application;

[0031] Figure 2 This is an optional schematic diagram of signal transmission within the PLL layout structure provided in this application embodiment;

[0032] Figure 3 This is a schematic diagram of one of the multiple PLL layout structures provided in the embodiments of this application within an MCU chip.

[0033] Figure reference numerals: PLL layout structure 10, digital function layout area 100, first function area 110, sixth function area 120, analog function layout area 200, second function area 210, third function area 220, fourth function area 230, fifth function area 240, signal output layout area 300, seventh function area 310. Detailed Implementation

[0034] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0035] In the description of this application, the use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features. It should be understood that such use of data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0037] MCU is an abbreviation for Microcontroller Unit, also known as a single-chip microcomputer. It is a chip that integrates a microprocessor core, memory, and peripheral interfaces, and is widely used in various electronic products, such as mobile phones, remote controls, and automotive electronics. The main function of an MCU is to control the operation of embedded systems, enabling different combinations of control.

[0038] PLL stands for Phase-Locked Loop, an electronic control circuit that uses feedback control to synchronize the phase of the output signal with the phase of the input signal. Its basic working principle is to compare the phase difference between the input and output signals using a phase detector, and then use the error voltage after processing by a low-pass filter to control the frequency of the voltage-controlled oscillator, so that the frequency of the output signal stably tracks the frequency and phase of the input signal. It is widely used in clock synchronization, frequency synthesis, modulation and demodulation, and clock recovery.

[0039] Analog layout is a crucial step in the physical implementation of circuit design, and its quality directly determines circuit performance. In MCU chips, PLLs are used to generate stable clock signals, providing a timing basis for the digital modules within the MCU chip. Multiple PLLs are typically integrated to meet different frequency requirements. However, existing PLL layouts lack compatibility support for parallel multi-PLL structures, and unreasonable internal module arrangement leads to insufficient stability of reference current and voltage signals, affecting the loop stability of the PLL. Consequently, excessive clock jitter generated by the PLL occurs during post-layout simulation and chip testing, severely restricting the overall reliability of the chip.

[0040] Based on this, this application provides a PLL layout structure for MCU chips. By partitioning and precisely arranging the frequency and phase detector, charge pump, low-pass filter, mirror current source, and voltage-controlled oscillator, multiple PLLs can be paralleled and share the reference current and voltage source within the MCU chip. This significantly improves the loop signal stability and anti-interference capability of the PLL, while reducing the layout area, lowering chip cost, effectively suppressing clock jitter, and ensuring the high-frequency timing accuracy and operational reliability of the MCU.

[0041] Therefore, the embodiments of this application will be further described below with reference to the accompanying drawings.

[0042] Reference Figures 1 to 3 As shown, Figure 1 This is a schematic diagram of an optional PLL layout structure for an MCU chip provided in an embodiment of this application. Figure 2 This is an optional schematic diagram of signal transmission within the PLL layout structure provided in this application embodiment. Figure 3 This is an optional schematic diagram of multiple PLL layout structures provided in the embodiments of this application within an MCU chip. The PLL layout structure 10 includes a digital function layout area 100, an analog function layout area 200, and a signal output layout area 300. The analog function layout area 200 is located above the digital function layout area 100, and the signal output layout area 300 is located below the digital function layout area 100.

[0043] The digital functional layout area 100 includes a first functional area 110 and a sixth functional area 120, the analog functional layout area 200 includes a second functional area 210, a third functional area 220, a fourth functional area 230 and a fifth functional area 240, and the signal output layout area 300 includes a seventh functional area 310.

[0044] Specifically, the lower sides of the second functional area 210 and the fourth functional area 230 are close to the upper sides of the first functional area 110, the left side of the fourth functional area 230 is close to the right side of the second functional area 210, the lower side of the third functional area 220 is close to the upper sides of the second functional area 210, the fourth functional area 230, and the fifth functional area 240, and the right side of the fifth functional area 240 is close to the left sides of the first functional area 110 and the fourth functional area 230, respectively; the upper side of the sixth functional area 120 is close to the lower side of the first functional area 110, the left side of the sixth functional area 120 is close to the right side of the fifth functional area 240, and the upper side of the seventh functional area 310 is close to the lower sides of the fifth functional area 240 and the sixth functional area 120, respectively.

[0045] The first functional area 110 is used to place the functional circuit of the frequency and phase detector; the second functional area 210 is used to place the functional circuit of the charge pump; the third functional area 220 is used to place the functional circuit of the low-pass filter; the fourth functional area 230 is used to place the functional circuit of the mirror current source; the fifth functional area 240 is used to place the functional circuit of the voltage-controlled oscillator; the sixth functional area 120 is used to place the functional circuit of the frequency divider; and the seventh functional area 310 is used to place the functional circuit of the level conversion.

[0046] It should be noted that by placing the analog function layout area 200 above the digital function layout area 100 and the signal output layout area 300 below the digital function layout area 100, the analog and digital function layouts are separated. This helps reduce mutual interference between the two functional layouts, ensures the stability of the PLL loop, and reduces clock jitter of the output clock. At the same time, dividing the five core functional circuits—frequency and phase detector, charge pump, low-pass filter, mirror current source, and voltage-controlled oscillator—into closely fitted yet relatively independent layout areas can improve the compatibility of multi-PLL parallel structures, enabling applications where multiple PLLs are placed in parallel. This also greatly saves chip area, reduces the overall complexity and production cost of multi-PLL systems, and effectively improves the timing accuracy, system stability, and mass production yield of the MCU chip.

[0047] When multiple PLLs are placed side by side on the MCU chip, the digital function layout area 100 and analog function layout area 200 of all PLLs will not interfere with each other. At the same time, the signal output layout area 300 that interacts with the MCU chip is located below the PLL, thereby reducing the difficulty of winding digital PRs inside the chip.

[0048] By placing the lower side of the second functional area 210 close to the upper side of the first functional area 110, the trace length between the functional circuit of the frequency and phase detector and the functional circuit of the charge pump can be effectively shortened, thereby reducing the parasitic resistance and capacitance caused by the traces.

[0049] Specifically, the first functional area 110 is used to place the functional circuit of the frequency and phase detector. The first functional area 110 is used to connect the functional circuit of the frequency and phase detector to the functional circuit of the charge pump and the functional circuit of the frequency divider, respectively, and to receive the reference clock signal and the frequency-divided clock signal input by the functional circuit of the frequency divider. It also performs frequency / phase differential comparison between the frequency-divided clock signal and the reference clock signal to obtain a differential analog signal and outputs the differential analog signal to the functional circuit of the charge pump.

[0050] It should be noted that by placing the upper side of the sixth functional area 120 close to the lower side of the first functional area 110, the first functional area 110 receives the frequency-divided clock signal from the sixth functional area 120. The reference clock signal and the frequency-divided clock signal output by the sixth functional area 120 are compared by the first functional area 110 to output a pair of differential analog signals. The differential analog signal needs to pay attention to length matching and noise shielding, so it is necessary to minimize the interference to the differential analog signal. In conjunction with the placement design where the lower side of the second functional area 210 is close to the upper side of the first functional area 110, the trace length between the functional circuit of the frequency and phase detector and the functional circuit of the charge pump is shortened, thereby effectively shortening the trace length of the differential analog signal output by the first functional area 110 and reducing the parasitic effect caused by excessively long traces in the differential analog signal.

[0051] Furthermore, the functional circuit in the fourth functional area 230 used to place the mirror current source can specifically be: the fourth functional area 230 is used to connect the circuit of the mirror current source to the functional circuit of the voltage-controlled oscillator to generate a bias current signal and output the bias current signal to the functional circuit of the charge pump.

[0052] Meanwhile, by having the lower side of the third functional area 220 close to the upper side of the fourth functional area 230, the functional circuit of the mirror current source can be directly connected to the functional circuit of the low-pass filter to improve the accuracy of the mirror current source's generation and output of the bias current signal, thereby improving the performance of the third functional area 220.

[0053] Furthermore, the second functional area 210 is used to house the functional circuit of the charge pump. Specifically, the second functional area 210 is used to connect the functional circuit of the charge pump to the functional circuit of the low-pass filter, and to receive differential analog signals and bias current signals through the functional circuit of the charge pump, and to combine the differential analog signals and bias current signals into charge and discharge control signals, and output the charge and discharge control signals to the functional circuit of the low-pass filter.

[0054] Furthermore, the third functional area 220 is used to place the functional circuit of the low-pass filter. Specifically, the third functional area 220 is used to connect the functional circuit of the low-pass filter to the functional circuit of the voltage-controlled oscillator, and to receive the charging and discharging control signal through the functional circuit of the low-pass filter, and to filter and convert the charging and discharging control signal to obtain the control voltage signal, and output the control voltage signal to the functional circuit of the voltage-controlled oscillator.

[0055] It should be noted that by placing the lower side of the third functional area 220 close to the upper side of the second functional area 210 and the upper side of the fourth functional area 230 respectively, the critical path of the charge pump output to the filter input of the charge and discharge control signal is greatly shortened. This extremely short physical distance and direct adjacent layout effectively minimizes the parasitic resistance and capacitance generated by the interconnecting wires, significantly reduces the risk of signal transmission delay, voltage drop and external noise coupling, thereby ensuring that the charge and discharge control signal can be received by the filter with extremely high fidelity and speed, enabling the loop to respond quickly and accurately to phase errors.

[0056] Furthermore, the fifth functional area 240 is used to place the functional circuit of the voltage-controlled oscillator. Specifically, the fifth functional area 240 is used to connect the functional circuit of the voltage-controlled oscillator to the functional circuit of the frequency divider and the functional circuit of the level conversion, respectively. The functional circuit of the voltage-controlled oscillator receives the control voltage signal, performs oscillation processing on the control voltage signal to obtain a digital clock signal, and outputs the digital clock signal to the functional circuit of the frequency divider and the functional circuit of the level conversion.

[0057] It should be noted that, since the lower side of the third functional area 220 is close to the upper side of the fifth functional area 240, the charge and discharge control signal filtered by the third functional area 220 is converted into a control voltage signal of the fifth functional area 240. The control voltage signal will control the fifth functional area 240 to oscillate and generate a digital clock signal. The generated digital clock signal will be used by other functional modules in the chip to provide the clock frequency for operation in the seventh functional area 310, and will also serve as the clock input for the sixth functional area 120.

[0058] Furthermore, the sixth functional area 120 is used to place the functional circuit of the frequency divider. Specifically, the sixth functional area 120 is used to receive the digital clock signal through the functional circuit of the frequency divider, and to perform frequency division processing on the digital clock signal to obtain the frequency-divided clock signal, and output the frequency-divided clock signal to the frequency and phase detector.

[0059] Specifically, by having the upper side of the sixth functional area 120 close to the lower side of the first functional area 110, and the left side of the sixth functional area 120 close to the right side of the fifth functional area 240, it is beneficial to shorten the trace length between the sixth functional area 120 and the first functional area 110 and the fifth functional area 240 respectively, thereby reducing the interference of the frequency division clock signal on other signals. Furthermore, the functional circuit of the voltage-controlled oscillator in the sixth functional area 120 will divide the digital clock signal (high-frequency signal) output by the fifth functional area 240 and output a lower frequency divided clock signal, and then send the divided clock signal to the functional circuit of the frequency and phase detector corresponding to the first functional area 110.

[0060] Furthermore, the seventh functional area 310 is used to place the level conversion function circuit, specifically: the seventh functional area 310 is used to receive the digital clock signal through the level conversion function circuit and output the digital clock signal in a level conversion manner.

[0061] It should be noted that the seventh functional area 310 is placed at the bottom of the entire PLL layout structure 10. This is beneficial for the frequency division clock signal generated by the PLL to be sent to other functional modules of the chip through the seventh functional area 310, and also for the logic control signals in the chip to control the PLL.

[0062] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0063] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0064] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0066] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0067] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0068] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0069] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0071] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A PLL layout structure applied to an MCU chip, characterized in that, The application relates to a chip layout structure of a phase-locked loop (PLL) and a chip layout structure of a phase-locked loop (PLL). The chip layout structure comprises a digital function layout area, an analog function layout area, and a signal output layout area. The digital function layout area comprises a first function area. The analog function layout area is located on the upper side of the digital function layout area and comprises a second function area, a third function area, a fourth function area, and a fifth function area. The signal output layout area is located on the lower side of the digital function layout area. The lower side of the second function area and the lower side of the fourth function area are close to the upper side of the first function area. The left side of the fourth function area is close to the right side of the second function area. The lower side of the third function area is close to the upper side of the second function area, the upper side of the fourth function area, and the upper side of the fifth function area.

2. The PLL layout structure of claim 1, wherein, The right side of the fifth function area is close to the left side of the first function area and the left side of the fourth function area. The first function area is used for placing the function circuit of a phase detector.

3. The PLL layout structure of claim 2, wherein, The second function area is used for placing the function circuit of a charge pump. The third function area is used for placing the function circuit of a low-pass filter.

4. The PLL layout structure of claim 3, wherein, The fourth function area is used for placing the function circuit of a mirror current source. The fifth function area is used for placing the function circuit of a voltage-controlled oscillator.

5. The PLL layout structure of claim 4, wherein, The digital function layout area further comprises a sixth function area. The upper side of the sixth function area is close to the lower side of the first function area. The left side of the sixth function area is close to the right side of the fifth function area. The sixth function area is used for placing the function circuit of a frequency divider. The signal output layout area comprises a seventh function area. The upper side of the seventh function area is close to the lower side of the fifth function area and the lower side of the sixth function area. The seventh function area is used for placing the function circuit of a level shifter. The first function area is used for placing the function circuit of a phase detector. The first function area is used for connecting the function circuit of the phase detector with the function circuit of the charge pump and the function circuit of the frequency divider. The first function area receives a reference clock signal and a frequency-divided clock signal input by the function circuit of the frequency divider. The first function area compares the frequency and phase difference of the frequency-divided clock signal and the reference clock signal to obtain a differential analog signal. The first function area outputs the differential analog signal to the function circuit of the charge pump. The fourth function area is used for placing the function circuit of a mirror current source. The fourth function area connects the function circuit of the mirror current source with the function circuit of the voltage-controlled oscillator. The fourth function area generates a bias current signal and outputs the bias current signal to the function circuit of the charge pump. The second function area is used for placing the function circuit of a charge pump. The second function area connects the function circuit of the charge pump with the function circuit of the low-pass filter. The second function area receives the differential analog signal and the bias current signal through the function circuit of the charge pump. The second function area combines and converts the differential analog signal and the bias current signal into a charge control signal. The second function area outputs the charge control signal to the function circuit of the low-pass filter. The third function area is used for placing the function circuit of a low-pass filter. The third function area receives the charge control signal from the function circuit of the charge pump. The third function area generates a low-pass filtered signal and outputs the low-pass filtered signal to the function circuit of the voltage-controlled oscillator. The third function area is used for connecting the function circuit of the low-pass filter with the function circuit of the voltage-controlled oscillator. The third function area receives the low-pass filtered signal from the function circuit of the low-pass filter. The third function area generates a voltage-controlled oscillator signal and outputs the voltage-controlled oscillator signal to the function circuit of the voltage-controlled oscillator. The third function area is used for connecting the function circuit of the low-pass filter with the function circuit of the voltage-controlled oscillator. The third function area receives the low-pass filtered signal from the function circuit of the low-pass filter. The third function area generates a voltage-controlled oscillator signal and outputs the voltage-controlled oscillator signal to the function circuit of the voltage-controlled oscillator. The third functional area is used for connecting the functional circuit of the low-pass filter with the functional circuit of the voltage-controlled oscillator, receiving the charge-discharge control signal through the functional circuit of the low-pass filter, filtering and converting the charge-discharge control signal to obtain a control voltage signal, and outputting the control voltage signal to the functional circuit of the voltage-controlled oscillator.

6. The PLL layout structure of claim 5, wherein, The fifth functional area is used for placing the functional circuit of the voltage-controlled oscillator, including: The fifth functional area is used for connecting the functional circuit of the voltage-controlled oscillator with the functional circuit of the frequency divider and the functional circuit of the level conversion respectively, receiving the control voltage signal through the functional circuit of the voltage-controlled oscillator, oscillating the control voltage signal to obtain a digital clock signal, and outputting the digital clock signal to the functional circuit of the frequency divider and the functional circuit of the level conversion.

7. The PLL layout structure of claim 6, wherein, The sixth functional area is used for placing the functional circuit of the frequency divider, including: The sixth functional area is used for receiving the digital clock signal through the functional circuit of the frequency divider, dividing the digital clock signal to obtain a frequency-divided clock signal, and outputting the frequency-divided clock signal to the functional circuit of the frequency discriminator.

8. The PLL layout structure of claim 7, wherein, The seventh functional area is used for placing the functional circuit of the level conversion, including: The seventh functional area is used for receiving the digital clock signal through the functional circuit of the level conversion, and outputting the digital clock signal in a level conversion manner.

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