Low-power phase detector

Abstract

A phase detector is provided according to this disclosure. The phase detector of this disclosure comprises a first transistor leg and a second transistor leg. Each of the first and second transistor legs includes a pair of transistors connected to each other at a plurality of common nodes. The phase detector of this disclosure further comprises an input section connected to the first transistor leg. The input section is configured to receive a first input signal and a second input signal. The phase detector of this disclosure further comprises an output section connected to the second transistor leg. The output section is configured to provide an output signal. The output signal includes a component indicating the phase difference between the first input signal and the second input signal.

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims priority based on U.S. Patent Application No. 18 / 328,879, filed on June 5, 2023. The entire disclosure of the above application is incorporated herein by reference.

[0002] (Technical Field) This disclosure generally relates to phase detectors.

Background Art

[0003] Phase detectors are used to detect the phase difference between two or more signals (e.g., high - frequency signals). Phase detectors can be used in various applications that require a signal indicating the phase difference between signals. For example, a phase detector can be used to test the operation of a phase shifter in a phased array system or to indicate the locked state in a phase - locked loop circuit or other phase - sensitive circuits. Exemplary phase detectors have been implemented using, for example, Gilbert multiplier cells. Also, exemplary phase detectors have been implemented using, for example, XOR logic gates.

Summary of the Invention

Means for Solving the Problems

[0004] Aspects and advantages of the present invention are in part set forth in the following description, or will be apparent from the description, or can be learned by practice of the present invention.

[0005] One embodiment of the present disclosure relates to a phase detector. The phase detector of the present disclosure comprises a first transistor leg and a second transistor leg. Each of the first and second transistor legs includes a pair of transistors connected to each other at a plurality of common nodes. The phase detector of the present disclosure further comprises an input section connected to the first transistor leg. The input section is configured to receive a first input signal and a second input signal. The phase detector of the present disclosure further comprises an output section connected to the second transistor leg. The output section is configured to provide an output signal. The output signal includes a component indicating the phase difference between the first input signal and the second input signal.

[0006] The above and other features, aspects and advantages of the present invention will be better understood by referring to the following description and the appended claims. The accompanying drawings are incorporated herein and constitute part thereof, illustrating embodiments of the present invention and serving to illustrate the principles of the present invention together with this specification. [Brief explanation of the drawing]

[0007] A complete and feasible disclosure of the present invention for those skilled in the art is described herein with reference to the accompanying drawings.

[0008] [Figure 1] Figure 1 is a block diagram of a phase detector according to an exemplary embodiment of the present disclosure. [Figure 2] Figure 2 is a circuit diagram of a phase detector according to an exemplary embodiment of the present disclosure. [Figure 3] Figure 3 shows the output signal of the phase detector of the present disclosure as a function of phase difference according to an exemplary embodiment. [Figure 4] Figure 4 is a circuit diagram of a phase detector according to another exemplary embodiment of the present disclosure. [Figure 5] Figure 5 is a flowchart of the method of the Disclosure according to an exemplary embodiment of the Disclosure.

[0009] Reference numerals used repeatedly in this specification and in the drawings are intended to represent identical or similar features or elements of the present invention. [Modes for carrying out the invention]

[0010] Various embodiments of the present invention and one or more examples thereof will be described in detail below. Each example is presented for illustrative purposes and does not limit the present invention. In fact, it will be apparent to those skilled in the art that various modifications and variations of the present invention are possible without departing from the scope and spirit of the invention. For example, features exemplified or described as part of one embodiment can be used together with another embodiment to create yet another embodiment. Thus, the present invention is intended to encompass such modifications and variations insofar as they fall within the scope of the appended claims and their equivalents.

[0011] As used herein, the terms “first,” “second,” “upper,” and “bottom” are used solely to distinguish one component or action from another, and do not necessarily require or imply any actual relationship or order between such components or actions. As used herein, the terms “comprises, comprising” and their inflections are intended to cover non-exclusive inclusion. For example, a process, method, article, or apparatus that includes the listed components is not necessarily limited to those components alone, and may include other components not expressly described, or other components specific to those processes, methods, articles, or apparatus. Unless further restricted, a component “including” does not preclude the presence of additional identical components in the process, method, article, or apparatus that includes that component.

[0012] Terms such as “combined,” “fixed,” and “attached” include not only direct combination, fixation, or attachment, but also indirect combination, fixation, or attachment via one or more intermediate components, unless otherwise specified herein. Furthermore, any arrangement of components to achieve the same function is effectively “associated” in such a way that the function is achieved. Thus, any two components combined herein to achieve a particular function can be considered “associated” with each other, regardless of architecture or intermediate components, in such a way that the desired function is achieved. Similarly, any two such associated components can be considered “operably connected” or “operably coupled” with each other to achieve the disclosed function, and any two such associated components can also be considered “operably coupled” with each other to achieve the disclosed function. Some examples of operatically coupled components, but not limited to, include physically coupled components, physically interacting components, wirelessly interacting components, wirelessly interacting components, logically interacting components, and / or logically interacting components.

[0013] The approximate expressions used throughout this specification and the claims may be applied to modify any quantitative expression that can vary within an acceptable range without altering the underlying function associated with it. Thus, values ​​modified by terms such as “about” or “approximately” are not limited to specified exact values. In at least some examples, approximate expressions may correspond to the precision of an instrument for measuring a value, or the precision of a method or apparatus for constructing or manufacturing components and / or systems. For example, an approximate expression may refer to being within a 10 percent tolerance.

[0014] Furthermore, the technology of this application will be described in relation to exemplary embodiments. As used herein, the term “exemplary” means “serving as an example, illustration, or explanatory role.” Embodiments described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments. In addition, unless otherwise stated, all embodiments described herein are considered exemplary.

[0015] When used herein, the term "and / or" used when listing two or more items means any one of the listed items or any combination of two or more of the listed items. For example, if a composition or assembly is described as containing component A, component B, and / or component C, then the composition or assembly may contain component A only, component B only, component C only, a combination of component A and component B, a combination of component A and component C, a combination of component B and component C, or a combination of component A, component B, and component C.

[0016] This specification, using examples, discloses the scope of the present invention, including the best embodiment, and enables a person skilled in the art to implement the invention (including the manufacture and use of any device or system, and the implementation of any method incorporated therein). The patentable technical scope of the present invention is defined by the description in the claims of the patent, and also includes other embodiments that a person skilled in the art could conceive. Such other embodiments are included in the scope of the claims if they include components that are not different from the language of the claims, or components that are substantially equivalent to the language of the claims.

[0017] An exemplary aspect of the present disclosure relates to a phase detector. The phase detector of the present disclosure generates a signal (e.g., a current signal or a voltage signal) that is substantially proportional to the phase difference between two applied input signals, such as two applied radio frequency (RF) input signals.

[0018] Phase detectors have been used to detect the phase difference between two applied signals. Phase detectors include, for example, circuits based on a Gilbert multiplier cell and / or one or more XOR gates. In a phase detector including a Gilbert multiplier cell, a first high-frequency signal (RF signal) is applied to the lower differential pair, and a second high-frequency signal is applied to the upper differential pair. The voltage difference at the output is proportional to the product of the first and second high-frequency signals. Therefore, a phase dependence exists for input signals of the same frequency. Phase detectors based on XOR gates require a full-swing input signal (e.g., between a low logic state and a high logic state). Two input signals are provided to the XOR gate. The output of the XOR gate, when averaged over time, is proportional to the phase difference between the two input signals.

[0019] An exemplary embodiment of this disclosure relates to a phase detector comprising a transistor core. The transistor core includes, for example, four transistors, or other devices having nonlinear transconductance. The transistors may be, for example, field-effect transistors (FETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high-electron-mobility transistors (HEMTs), power transistor devices, or other suitable transistors or devices having nonlinear transconductance. When field-effect transistors (FETs) are used, the transistors can be operated in the saturation region. When bipolar junction transistors (BJTs) are used, the transistors can be operated in the forward-active region. By operating the transistors in these regions, the transistor core can be operated at high speed. Two input signals are provided to the input section of the transistor core. The transistor core provides an output signal that is substantially proportional to the phase difference between the two input signals provided to the input section.

[0020] In some embodiments, the transistor core includes four transistors. More specifically, the transistor core includes a first transistor leg and a second transistor leg. The first transistor leg includes a pair of transistors connected to each other at a common node. The second transistor leg includes a pair of transistors connected to each other at a common node.

[0021] More specifically, in some examples, the first transistor leg includes a first transistor and a second transistor. The first transistor and the second transistor are connected to each other at a first common source node and a first common drain node. A first input signal is provided to the gate of the first transistor. A second input RF signal is provided to the gate of the second transistor. The second transistor leg includes a third transistor and a fourth transistor. The third transistor and the fourth transistor are connected to each other at the first common source node and a second common drain node.

[0022] Certain aspects of the present disclosure are described with respect to the "gate", "source", and "drain" of a transistor. These terms are typically used in relation to a field effect transistor (FET) or similar transistors. However, for convenience, these terms are also used in the present disclosure to refer to embodiments including bipolar junction transistors (BJTs). More specifically, the gate may refer to the base of a bipolar junction transistor (BJT). The source may refer to the emitter of a bipolar junction transistor (BJT). The drain may refer to the collector of a bipolar junction transistor (BJT). Thus, the terms gate and base can be used interchangeably. Also, the terms collector and drain can be used interchangeably. Also, the terms source and emitter can be used interchangeably.

[0023] In some embodiments, a bias current source is connected to a first common source node. In some embodiments, a DC bias voltage source is connected to the gates of the third transistor and the fourth transistor. In some embodiments, the DC bias voltage source is connected to the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0024] In some embodiments, the phase detector optionally includes a differential circuit. The differential circuit can provide a differential signal. The differential circuit performs at least two useful functions. First, the differential circuit can remove responses due to common-mode variations such as temperature that are seen in the low-frequency components of the individual total currents associated with the first output signal of the first transistor leg and the second output signal of the second transistor leg. Second, by calculating the difference between the first output signal and the second output signal rather than using either of the two currents as an output, a signal twice as large can be obtained.

[0025] However, those skilled in the art will understand that, using the content disclosed herein, a phase detector can provide an output signal without using a differential circuit. Despite the advantages obtained by the differential circuit, one of the currents of the first transistor leg or the second transistor leg may be used as an output. When only one of the two currents is used as an output, it is usually necessary to remove unwanted components generated by the transistor quad and filter to amplify the components containing information regarding the phase difference.

[0026] The difference circuit includes, for example, a current mirror circuit and / or a filter circuit. The filter circuit may be a low-pass filter configured to provide a band-pass response to difference signal components from DC up to a certain corner frequency. The purpose of filtering in the difference circuit is to remove the frequency at which the input signal is transmitted and the high-frequency components generated by the nonlinear behavior of the transistors. These removed components do not transmit useful information about the phase relationship between the input signals. In some embodiments, it is beneficial to remove these components so as not to adversely affect the circuit connected to the output.

[0027] Aspects of this disclosure are described in relation to a difference circuit having a low-pass filter, the difference circuit may include filtering for selecting any frequency range over which the phase transmits information. As used herein, the term low-pass filter is intended to encompass any filter that is expected to provide a band-pass response at frequencies lower than the frequency of the input signal. The term low-frequency component refers to frequencies lower than the frequency of the input signal and includes DC. The difference signal may include a component that indicates the phase difference between a first input signal and a second input signal. More specifically, if the input signal at the gate of the first transistor is in phase with the input signal at the gate of the second transistor, the difference signal is the input frequency. Under this condition, the first and second transistors work together to form one half of the differential pair, and the third and fourth transistors work together to form the other half of the differential pair. In this case, no DC component appears in the difference signal.

[0028] In contrast, when the phase difference between the input signal at the gate of the first transistor and the input signal at the gate of the second transistor is 180 degrees, a DC component appears in the difference signal due to the nonlinear behavior of the transistor core. The DC component is maximum when the phase difference at the input is 180 degrees. At intermediate phase differences, the DC component is somewhere between these two extremes. Therefore, the output signal contains a component that indicates the phase difference between the two input signals.

[0029] The phase detector of this disclosure can operate faster than, for example, a phase detector based on a Gilbert cell and / or an XOR gate. The high speed of the phase detector of this disclosure is due to the fact that the four transistors in the transistor core are connected to each other at their sources (emitters in the case of a bipolar junction transistor (BJT)). Since the output signal of the transistor core is low frequency, the rest of the circuit (e.g., a difference circuit) does not need to respond at high frequencies (RF frequencies). The transistor core generates a high-frequency voltage signal relative to a current source. However, while current sources typically have high impedance, the common source of the transistor core exhibits low impedance. This reduces the effect of the load generated by the current source. Thus, the high-frequency signal is confined within the transistor core. Because the phase detector of this disclosure contains four devices within the transistor core, it can operate at low power and does not require additional devices to be driven at high frequencies.

[0030] Aspects of this disclosure offer numerous technical advantages and benefits. For example, the phase detector of this disclosure according to exemplary embodiments can achieve a higher bandwidth compared to, for example, a phase detector based on a Gilbert multiplier cell, due to the smaller number of elements in the current path. In addition, the phase detector of this disclosure according to exemplary embodiments can operate at lower supply voltages and lower power compared to a phase detector based on a Gilbert multiplier cell.

[0031] Furthermore, in the case of XOR gate-based phase detectors, an input signal that changes between low and high logic states with rise and / or fall times much smaller than the period of the input signal is required. This can lead to harmonic noise, which can be transmitted into the circuit via the power rail and other components. However, the phase detector of this disclosure can receive sinusoidal input signals or other input signals without being limited by logic level amplitude and rise / fall times. Since the phase detector of this disclosure can operate with sinusoidal inputs without requiring logic level-based input signals, it does not generate harmonic noise. The phase detector of this disclosure, in exemplary embodiments, can operate at higher frequencies and with fewer active elements and lower supply currents compared to XOR gate-based phase detectors.

[0032] Furthermore, the phase detectors of the present disclosure, according to exemplary embodiments, can be implemented in a smaller semiconductor die area compared to, for example, phase detectors based on Gilbert multiplier cells or XOR gates. As a result, the phase detectors of the present disclosure are more suitable for use in larger systems as lower-cost diagnostic tools. The phase detectors of the present disclosure can be used, for example, to test the operation of a phase tuner in a phased array system, or to indicate a locked state in a phase-locked loop system or other phase-sensitive circuit.

[0033] Figure 1 is a schematic block diagram of a phase detector 100 of the present disclosure according to an exemplary embodiment. The phase detector 100 of the present disclosure comprises a transistor core 102, which includes a first transistor leg 104 and a second transistor leg 106.

[0034] The first transistor leg 104 has a first transistor 108 and a second transistor 110. The first transistor 108 and the second transistor 110 can be field-effect transistors (FETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high electron-mobility transistors (HEMTs), power transistors, or other transistors. The first transistor 108 and the second transistor 110 are connected to each other by one or more common nodes, for example, a common source node and / or a common drain node.

[0035] The second transistor leg 106 has a third transistor 112 and a fourth transistor 114. The third transistor 112 and the fourth transistor 114 can be a field-effect transistor (FET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a high electron-mobility transistor (HEMT), a power transistor, or other transistors. The third transistor 112 and the fourth transistor 114 are connected to each other by one or more common nodes, for example, a common source node and / or a common drain node.

[0036] A current source 116 (bias current source) is connected to the first transistor leg 104 and the second transistor leg 106. The current source 116 supplies a bias current I to each of the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114. biasThe bias current is supplied so that each of the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 operates in the saturation region (for FETs) or the forward-active region (for BJTs), thereby preventing the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 from acting as hard switches and instead being completely off. In some embodiments, such as when a field-effect transistor (FET) operates in the subthreshold region, the bias current can be extremely small (e.g., close to or 0A). In this case, the frequency of the input signal is low. However, when a field-effect transistor (FET) operates in the subthreshold region, it will have exponential transconductance, making this mode of operation suitable for use in phase detectors.

[0037] The bias voltage source 118 supplies a bias voltage V to each of the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114. bias A bias voltage is supplied. For example, the same bias voltage is supplied to the gate or base of each of the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114. In some embodiments, the bias voltage can be 0V.

[0038] The phase detector 100 includes an input unit 120. The input unit 120 is configured to receive a first input signal 122 and a second input signal 124. The phase detector 100 is configured to detect the phase difference between the first input signal 122 and the second input signal 124. The frequencies of the first input signal 122 and the second input signal 124 may be the same. The frequencies of the first input signal 122 and the second input signal 124 may be, for example, in the range of about 1 MHz to about 50 GHz, for example, in the range of about 20 GHz to about 50 GHz. These examples of operating frequency ranges for the phase detector can be considered typical, but the phase detector can also operate at much lower and much higher frequencies.

[0039] The first input signal 122 and the second input signal 124 are supplied to the first transistor leg 104. For example, the first input signal 122 is supplied to the gate or base of the first transistor 108. The second input signal 124 is supplied to the gate or base of the second transistor 110.

[0040] In some embodiments, the phase detector 100 includes a difference circuit 130. The difference circuit 130 includes, for example, a current mirror circuit 132 and / or a filter circuit 134. In some embodiments, the current mirror circuit 132 provides the difference between a first output signal 126 associated with a first transistor leg 104 and a second output signal 128 associated with a second transistor leg 106. The filter circuit 134 is configured to provide a band-pass response to the low-frequency components of the difference signal 138 and to block the high-frequency components. The low-frequency components relate to frequencies lower than the frequency of the input signal. Other difference circuits may be used without departing from the scope of this disclosure.

[0041] The difference circuit 130 includes an output section 136. The output section 136 of the difference circuit 130 is the output section of the phase detector 100. The difference circuit 130 outputs a difference signal 138 from the output section 136. The difference signal 138 represents the difference between a first output signal 126 associated with the first transistor leg 104 and a second output signal 128 associated with the second transistor leg 106. The difference signal 138 includes a component (e.g., a low-frequency component) that represents the phase difference between the first input signal 122 and the second input signal 124.

[0042] More specifically, when the first input signal 122 and the second input signal 124 are in phase, the difference signal 138 becomes the frequency of the input signals. Under these conditions, the first transistor 108 and the second transistor 110 work together to form one half of the differential pair, and the third transistor 112 and the fourth transistor 114 work together to form the other half of the differential pair. In this case, no DC component appears in the difference signal 138.

[0043] In contrast, when the phase difference between the first input signal 122 and the second input signal 124 is 180 degrees, a DC component appears in the difference signal 138 due to the nonlinear behavior of the transistor core 102. The DC component is maximum when the phase difference between the first input signal 122 and the second input signal 124 is 180 degrees. At intermediate phase differences, the DC component falls between these two extremes. Therefore, the difference signal 138 includes a component that indicates the phase difference between the first input signal 122 and the second input signal 124.

[0044] Figure 2 is an exemplary circuit diagram of the phase detector 100 of the present disclosure according to an exemplary embodiment. As shown in the figure, the phase detector 100 comprises a first transistor 108, a second transistor 110, a third transistor 112, and a fourth transistor 114. Each of the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 is a field-effect transistor (FET).

[0045] The first transistor 108 includes a first terminal 108.1 (e.g., gate), a second terminal 108.2 (e.g., source), and a third terminal 108.3 (e.g., drain). The second transistor 110 includes a fourth terminal 110.1 (e.g., gate), a fifth terminal 110.2 (e.g., source), and a sixth terminal 110.3 (e.g., drain). The third transistor 112 includes a seventh terminal 112.1 (e.g., gate), an eighth terminal 112.2 (e.g., source), and a ninth terminal 112.3 (e.g., drain). The fourth transistor 114 includes a tenth terminal 114.1 (e.g., gate), an eleventh terminal 114.2 (e.g., source), and a twelfth terminal 114.3 (e.g., drain).

[0046] The second terminal 108.2 (e.g., source) of the first transistor 108 and the fifth terminal 110.2 (e.g., source) of the second transistor 110 are connected to each other at the first common node 142 (e.g., common source node). In addition, the eighth terminal 112.2 (e.g., source) of the third transistor 112 and the eleventh terminal 114.2 (e.g., source) of the fourth transistor 114 are connected to each other at the first common node 142.

[0047] The third terminal 108.3 (e.g., drain) of the first transistor 108 and the sixth terminal 110.3 (e.g., drain) of the second transistor 110 are connected to each other at a second common node 144 (e.g., common drain node). The ninth terminal 112.3 (e.g., drain) of the third transistor 112 and the twelfth terminal 114.3 (e.g., drain) of the fourth transistor 114 are connected to each other at a third common node 146 (e.g., common drain node).

[0048] The current source 116 supplies a bias current I to the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114. biasThe current source 116 is connected to the first common node 142 (e.g., the common source node). The bias voltage source 118 supplies a bias voltage V to the first terminal 108.1 (e.g., the gate) of the first transistor 108, the fourth terminal 110.1 (e.g., the gate) of the second transistor 110, the seventh terminal 112.1 (e.g., the gate) of the third transistor 112, and the tenth terminal 114.1 (e.g., the gate) of the fourth transistor 114. bias The first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 are kept in a saturation mode where the drain-source voltage exceeds the difference between the gate-source voltage and the threshold voltage. This eliminates the need for the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 to be fully switched, resulting in high-speed operation.

[0049] The first terminal 108.1 (e.g., gate) of the first transistor 108 receives the first input signal 122. The fourth terminal 110.1 (e.g., gate) of the second transistor 110 receives the second input signal 124. The first input signal 122 and the second input signal 124 may have substantially the same amplitude and / or frequency.

[0050] The sum of the currents from the first transistor 108 and the second transistor 110 is formed at the second common node 144 (e.g., a common drain node). The sum of the currents from the third transistor 112 and the fourth transistor 114 is formed at the third common node 146 (e.g., a common drain node). Transistors 148 and 150 form a current mirror circuit. The current mirror circuit generates a difference current between the sum of the currents from the first transistor 108 and the second transistor 110 and the sum of the currents from the third transistor 112 and the fourth transistor 114. The difference current is formed at the third common node 146 as a difference signal 138, which is the output signal of the phase detector. The difference signal may be formed by other circuit components without departing from the scope of this disclosure. For example, transistors 148 and 150 may be replaced with resistors connected to the input of a voltage differential amplifier.

[0051] The low-frequency components of the difference signal (for example, the DC component present when the phase difference between the first input signal 122 and the second input signal 124 is time-stable) represent the phase difference between the first input signal 122 and the second input signal 124. A filter circuit (for example, a low-pass filter circuit) can be used to extract the low-frequency components (e.g., the DC component) of the difference signal from the difference circuit.

[0052] Figure 3 shows a plot 152 of the low-frequency component of the difference signal as a function of the phase difference between the first input signal 122 and the second input signal 124, according to an exemplary embodiment of the present disclosure. Figure 3 plots the phase difference on the horizontal axis and the amplitude (e.g., voltage such as mV) on the vertical axis. As shown, there is a direct correlation between the magnitude of the low-frequency component of the difference signal and the phase difference between the first input signal 122 and the second input signal 124. More specifically, the response starts at a minimum value at approximately 0 degrees, reaches a maximum value at approximately 180 degrees, and then returns to a minimum value again at approximately 360 degrees. In other circuit configurations, the minimum and maximum outputs may occur at 0 degrees and 180 degrees, respectively.

[0053] Figure 4 is an exemplary circuit diagram of the phase detector 100 of the present disclosure according to another exemplary embodiment. However, in the example of Figure 4, the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 are bipolar junction transistors (BJTs). The first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 operate in a region where the collector potential does not fall below the base potential. This means that the first transistor 108, the second transistor 110, the third transistor 112, and the fourth transistor 114 do not need to be fully switched, and as a result, high-speed operation is possible.

[0054] Furthermore, in the embodiment shown in Figure 4, the difference circuit is not a current mirror circuit. Rather, the difference circuit includes a differential amplifier 152 configured to provide a difference signal showing the difference between the signal of the second common node 144 and the signal of the third common node 146.

[0055] Figure 5 is a flowchart of Method 200 of the Disclosure according to an exemplary embodiment. Method 200 of the Disclosure can be carried out using the phase detector of the Disclosure described with reference to Figures 1-4. Figure 5 shows exemplary method steps for illustrative and explanatory purposes. Those skilled in the art will understand that, using the contents disclosed herein, any method step described herein can be adapted, modified, additional or omitted steps not shown can be added, and / or reconfigured without departing from the scope of the Disclosure.

[0056] In step 202, the method of the present disclosure provides a first input signal to the transistor core of the phase detector. The first input signal can be a high-frequency signal (RF signal). In some embodiments, the first input signal may have a frequency in the range of about 20 GHz to about 50 GHz, for example, in the range of about 1 MHz to about 50 GHz. While these examples of operating frequency ranges for the phase detector can be considered typical, the phase detector can also operate at much lower and much higher frequencies. In some embodiments, the first input signal is provided to one of the exemplary transistor cores described with reference to Figures 1-4. For example, the first input signal is provided to the gate or base of a transistor in the transistor core.

[0057] The method of the present disclosure provides a second input signal to the transistor core of the phase detector in step 204. The second input signal can be a high-frequency signal (RF signal). In some examples, the second input signal may have a frequency in the range of about 20 GHz to about 50 GHz, for example, in the range of about 1 MHz to about 50 GHz. The second input signal may have substantially the same amplitude and / or frequency as the first input signal. In some embodiments, the second input signal is provided to one of the exemplary transistor cores described with reference to Figures 1-4. For example, the second input signal is provided to the gate or base of a transistor in the transistor core.

[0058] The method of the present disclosure, in step 206, determines a difference signal between a first output signal associated with a first transistor leg of a transistor core and a second output signal associated with a second transistor leg of the transistor core. The first and second transistor legs each include a pair of transistors connected to a common source node (or common emitter node) and a common drain node (common collector node). The difference signal can be determined, for example, using a difference circuit. The difference circuit can be any of the difference circuits described with reference to Figures 1-4, or any other suitable difference circuit.

[0059] The method of the present disclosure, in step 208, filters the difference signal to provide an output signal. The output signal may be the low-frequency components (e.g., DC components) of the difference signal. The difference signal may be filtered using a low-pass filter circuit configured to provide a band-pass response to the low-frequency components (e.g., DC components). The low-pass filter circuit may be configured to block high frequencies.

[0060] In step 210, the method of the present disclosure provides an output signal as the output of a phase detector. The output signal includes a component indicating the phase difference between a first input signal and a second input signal.

[0061] Aspects of this disclosure have been described with reference to a transistor core used in conjunction with a phase detector. The transistor core can be used in other applications without departing from the scope of this disclosure.

[0062] For example, in one application, a filter circuit can be used with a transistor core. The filter circuit is configured to provide a band-pass response to signal components at frequencies equal to or near the frequencies of the first and second input signals. The amplitude of the output signal component at the input signal frequency changes depending on the phase difference between the two input signals. When the phase difference is 0 degrees, this component is maximum, and when the phase difference is 180 degrees, this component approaches 0. Therefore, in this application example, the output of the filter circuit becomes an amplitude-modulated signal at the input signal frequency. In this respect, the transistor core and the filter circuit function as a conversion circuit from phase modulation to amplitude modulation.

[0063] While specific exemplary embodiments of the subject matter of this disclosure have been described in detail above, those skilled in the art will readily conceive of modifications, variations, and equivalents to these embodiments based on the understanding of the above description. Therefore, the scope of this disclosure is illustrative and not limiting, and this disclosure does not exclude modifications, variations, and / or additional inclusions to the subject matter that would be readily conceivable to those skilled in the art.

Claims

1. A phase detector, A first transistor leg and a second transistor leg, each of which includes a pair of transistors connected to each other by a plurality of common nodes, An input unit connected to the first transistor leg, configured to receive a first input signal and a second input signal, The device comprises an output section connected to the second transistor leg, configured to provide an output signal, A phase detector, wherein the output signal includes a component indicating the phase difference between the first input signal and the second input signal.

2. A phase detector according to claim 1, The first transistor leg includes a first transistor and a second transistor. A phase detector in which the first transistor and the second transistor are connected to each other at a first common source node and a first common drain node.

3. A phase detector according to claim 2, The first input signal is supplied to the gate of the first transistor. The second input signal is supplied to the gate of the second transistor, which is a phase detector.

4. A phase detector according to claim 2 or 3, The second transistor leg includes a third transistor and a fourth transistor. A phase detector in which the third transistor and the fourth transistor are connected to each other at the first common source node and the second common drain node.

5. A phase detector according to claim 4, A phase detector further comprising a bias current source connected to the first common source node.

6. A phase detector according to claim 4, A phase detector in which a DC bias voltage source is connected to the gate of the third transistor and the gate of the fourth transistor.

7. A phase detector according to claim 6, The DC bias voltage source is a phase detector connected to the gates of the first transistor and the second transistor.

8. A phase detector according to any one of claims 1 to 7, Further equipped with a differential circuit, The difference circuit provides a difference signal as the output signal. A phase detector in which the difference signal indicates the difference between a first output signal associated with the first transistor leg and a second output signal associated with the second transistor leg.

9. A phase detector according to claim 8, The difference circuit is a phase detector including a current mirror circuit.

10. A phase detector according to any one of claims 1 to 7, It also includes a filter circuit, The filter circuit is configured to provide a band-pass response to the low-frequency components of the difference signal. The low-frequency component indicates the phase difference between the first input signal and the second input signal, and is a phase detector.

11. A phase detector, A transistor core having an input section that receives a first input signal and a second input signal, The output unit, which is related to the transistor core, is configured to provide an output signal that includes a component indicating the phase difference between the first input signal and the second input signal, and comprises: The transistor core includes a first pair of transistors connected to each other at a first common node and a second common node, and a second pair of transistors connected to each other at a first common node and a third common node. The output unit is a phase detector provided at the third common node.

12. A phase detector according to claim 11, The first pair of transistors and the second pair of transistors include field-effect transistors (FETs) in a phase detector.

13. A phase detector according to claim 11 or 12, A phase detector in which the first pair of transistors and the second pair of transistors include bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), or high electron mobility transistors (HEMTs).

14. A phase detector according to any one of claims 11 to 13, The system further includes a difference circuit that provides a difference signal to the output unit provided at the third common node, A phase detector wherein the difference signal includes a component indicating the phase difference between the first input signal and the second input signal.

15. A phase detector according to claim 14, The difference circuit is a phase detector including a current mirror circuit.

16. A phase detector according to claim 14 or 15, The difference circuit includes a phase detector, which also includes a filter circuit.

17. A phase detector according to claim 16, The filter circuit provides a predetermined bandwidth pass-through response to the output signal, which includes a component indicating the phase difference between the first input signal and the second input signal, and removes components in the first input signal and the second input signal that are outside the predetermined bandwidth; this is a phase detector.

18. A phase detector, A first transistor including a first terminal, a second terminal, and a third terminal, A second transistor including a fourth terminal, a fifth terminal, and a sixth terminal, A third transistor including a seventh terminal, an eighth terminal, and a ninth terminal, A fourth transistor including a tenth terminal, an eleventh terminal, and a twelfth terminal, The first terminal receives the first input signal, The fourth terminal receives the second input signal, The second terminal, the fifth terminal, the eighth terminal, and the eleventh terminal are connected to each other at the first common node. The third terminal and the sixth terminal are connected to each other at the second common node. The ninth terminal and the twelfth terminal are connected to each other at a third common node. An output unit is provided at the third common node, A phase detector, wherein the output unit is configured to provide an output signal that includes a component indicating the phase difference between the first input signal and the second input signal.

19. A phase detector according to claim 18, A phase detector to which bias voltages are supplied to the first terminal, the fourth terminal, the seventh terminal, and the tenth terminal.

20. A phase detector according to claim 18 or 19, Further equipped with a differential circuit, The difference circuit is configured to provide the output signal to the output unit, and is a phase detector.

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