Time-to-Digital Conversion Device

Abstract

The present invention provides a time-to-digital conversion device with superior resolution in the time domain and a wider measurement range. [Solution] An embodiment of the time-to-digital converter includes a first oscillator configured to output a first clock signal in response to a first event, and a second oscillator configured to output a second clock signal in response to a second event. The embodiment of the time-to-digital converter further includes a phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is lagging behind the phase of the first clock signal. The count value indicates the time difference between the first event and the second event.

Description

Background Art

[0001] Time-to-digital conversion devices such as time-to-digital converters (TDCs) are configured to convert time information into digital values. In some applications, a time-to-digital conversion device can be combined with a voltage-to-timing converter (VTC) to detect waveforms on an integrated circuit (IC) die and to monitor the power integrity (PI) characteristics of the IC die. In some applications, a time-to-digital conversion device can be used to measure the phase noise of a phase-locked loop (PLL). In some applications, a time-to-digital conversion device can be used to measure the time of flight (ToF) of radio signals, acoustic signals, and / or optical signals.

[0002] In some applications that require waveform measurement with excellent accuracy and flexibility, a time-to-digital conversion device with a resolution of less than 100 femtoseconds (fs) and a wide dynamic range may be used. In some applications, due to the constraint on the implementation area of the time-to-digital conversion device, the resolution and / or dynamic range of the time-to-digital conversion device may be limited.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a time-to-digital conversion device, a method for generating a count value indicating a time difference between a first event and a second event, and an integrated circuit die.

Means for Solving the Problems

[0004] One embodiment of the present invention provides a time-to-digital converter. The time-to-digital converter includes a first oscillator, a second oscillator, a phase detector, and a clock counter. The first oscillator is configured to output a first clock signal having a first clock period in response to a first event. The second oscillator is configured to output a second clock signal having a second clock period in response to a second event. The first event occurs before the second event, and the first clock period is greater than the second clock period. The phase detector is configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal. The clock counter is configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is delayed compared to the phase of the first clock signal, the count value indicating the time difference between the first event and the second event.

[0005] One embodiment of the present invention provides a method for generating a count value indicating a time difference between a first event and a second event. This method includes: outputting a first clock signal having a first clock period in response to a first event using a first oscillator; outputting a second clock signal having a second clock period in response to a second event using a second oscillator, wherein the first event occurs before the second event and the first clock period is greater than the second clock period; generating a detection signal using a phase detector based on the phase relationship between the first clock signal and the second clock signal; and generating a count value using a clock counter based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal is delayed compared to the phase of the first clock signal.

[0006] One embodiment of the present invention provides an integrated circuit die. The integrated circuit die includes one or more digital circuit blocks and a time-to-digital converter. One or more digital circuit blocks are configured to output a first reference signal and a second reference signal. The time-to-digital converter is configured to output a count value indicating the time difference between a first event and a second event. The time-to-digital converter includes a first oscillator, a second oscillator, a phase detector, and a clock counter. The first oscillator is configured to output a first clock signal having a first clock period based on the first reference signal in response to a first event, and the second oscillator is configured to output a second clock signal having a second clock period based on the second reference signal in response to a second event, wherein the first event occurs before the second event and the first clock period is greater than the second clock period. The phase detector is configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal. The clock counter is configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is lagging behind the phase of the first clock signal. [Effects of the Invention]

[0007] Considering the above, in embodiments of the present invention, configurations based on one or more embodiments of the present invention still have excellent resolution in the time domain (e.g., resolution of less than 80 femtoseconds) and a measurement range of 0 to 245 picoseconds without increasing the number of delay stages, thereby improving landscape efficiency in integrated circuit dies, reducing circuit complexity, and lowering manufacturing costs. [Brief explanation of the drawing]

[0008] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Figure 1A] This is a block diagram of an application example based on a time-to-digital conversion device according to several embodiments. [Figure 1B] This is a block diagram of an application example based on a time-to-digital conversion device according to several embodiments. [Figure 2] This is a block diagram of an example of a time-to-digital conversion device according to several embodiments. [Figure 3] This is a process flow diagram of an example process flow performed by a time-to-digital conversion device according to several embodiments. [Figure 4A] This is a circuit diagram of an oscillator example according to several embodiments. [Figure 4B] This is a circuit diagram of a NAND gate in the delay circuit of Figure 4A, according to several embodiments. [Figure 5] This is a circuit diagram of an example of a phase detector according to several embodiments. [Figure 6A] This is a circuit diagram of an example of a clock gating circuit according to several embodiments. [Figure 6B] This is a circuit diagram of a modified version based on the clock gating circuit of Figure 6A according to several embodiments. [Figure 6C] This is a circuit diagram of a modified version based on the clock gating circuit of Figure 6A according to several embodiments. [Figure 7] This is a block diagram of an example counter according to several embodiments. [Figure 8A] This figure shows the signal waveforms and / or digital values ​​of an example time-to-digital conversion session using a time-to-digital conversion device, based on examples in Figures 2-6A and 7 of several embodiments. [Figure 8B] This figure shows the signal waveforms and / or digital values ​​of an example time-to-digital conversion session using a time-to-digital conversion device, based on examples in Figures 2-6A and 7 of several embodiments. [Figure 8C] This figure shows the signal waveforms and / or digital values ​​of an example time-to-digital conversion session using a time-to-digital conversion device, based on examples in Figures 2-6A and 7 of several embodiments. [Figure 8D] This figure shows the signal waveforms and / or digital values ​​of an example time-to-digital conversion session using a time-to-digital conversion device, based on examples in Figures 2-6A and 7 of several embodiments. [Figure 9A] This is a diagram illustrating an example of a delay circuit based on a phase interpolator according to several embodiments. [Figure 9B] This is a diagram illustrating an example of a delay circuit based on a phase interpolator according to several embodiments. [Figure 10A] This figure shows an example of a delay circuit based on an adjustable load resistor according to several embodiments. [Figure 10B] This figure shows an example of a delay circuit based on an adjustable load resistor according to several embodiments. [Figure 10C] This figure shows an example of a delay circuit based on an adjustable load resistor according to several embodiments. [Figure 11] This is a circuit diagram of an oscillator configured to accommodate different clock periods according to several embodiments. [Figure 12] This is a flowchart of a method for generating a count value indicating the time difference between a first event and a second event according to several embodiments. [Modes for carrying out the invention]

[0009] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. For the sake of brevity of the invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, and the first and second features do not need to be in direct contact. Furthermore, the invention may repeat reference numerals and / or words in various examples. This repetition is for the sake of brevity and clarity and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0010] Furthermore, as shown in the figures, in order to facilitate the description of the relationship between certain elements or features and other elements or features, spatially relative terms such as "lower", "below", "underside", "upper", "upper part", etc. may be used in this specification. The spatially relative terms are intended to encompass different directions of the device during use or operation in addition to the directions shown in the figures. The device may be arranged in other directions (90-degree rotation or other directions), and the spatially relative descriptions used in this specification may be interpreted accordingly. Furthermore, the term "made of" may mean either "comprising" or "consisting of". In the present invention, the phrase "any of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean one element from A, one element from B, and one element from C unless otherwise specified.

[0011] With the recent development of computer technology, the demand for computing power has been increasing. For example, artificial intelligence (AI) has become more powerful than ever with advanced large language models having a large number of parameters. Enormous computing power is required for the training of large language models and / or inference operations based on large language models, and the need for high-performance computing (HPC) devices is increasing. Processing circuits and components such as central processing units (CPUs), graphics processing units (GPUs), and tensor processing units (TPUs) in HPC devices are facing the problem of power integrity due to large currents, but this can be addressed by monitoring the power impedance of the processing circuits and components.

[0012] In some applications, monitoring of the power impedance includes monitoring of the on-chip waveform or signal delay relative to a reference signal. For example, FIG. 1A is a block diagram 100A of a first application example for determining clock skew within digital logic 110 in an integrated circuit die according to some embodiments. In FIG. 1A, two clock signals CLK1 (e.g., a reference signal) and CLK2 (e.g., a monitoring signal) output by the digital logic 110 are coupled to a time-to-digital conversion device 120 for comparison. In this example, the time-to-digital conversion device 120 is configured to generate an output signal TDC_OUT based on the clock signals CLK1 and CLK2, where the output signal TDC_OUT represents a value (e.g., multi-bit digital data) indicating the time difference between the clock signal CLK1 and the clock signal CLK2.

[0013] Also, FIG. 1B is a block diagram 100B of a second application example for detecting the voltage level of a waveform within an integrated circuit die according to some embodiments. In FIG. 1B, a voltage signal VSENSE is acquired by a voltage-to-time converter (denoted as “VTC”) 130. The voltage-to-time converter 130 generates a delay signal CLK_DELAY based on a reference clock signal CLK_REF and converts the voltage level of the voltage signal VSENSE into a time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY. In this example, the time-to-digital conversion device 140 is configured to generate an output signal TDC_OUT based on the reference clock signal CLK_REF and the delay signal CLK_DELAY, where the output signal TDC_OUT represents a value (e.g., multi-bit digital data) indicating the time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY.

[0014] In some applications, a time-to-digital conversion device based on a Vernier delay line configuration can achieve excellent resolution (e.g., less than 100 femtoseconds (fs)) at the expense of increased delay stages, area, complexity, and cost.

[0015] The present invention describes, in one or more embodiments, a time-to-digital converter based on the clock period difference between two oscillators. In some embodiments, the two oscillators are activated in response to two events, and the later activated clock signal follows the earlier activated clock signal by an increment of the clock period difference with each clock cycle. In some embodiments, the configuration based on one or more embodiments of the present invention still has excellent resolution in the time domain (e.g., resolution of less than 80 femtoseconds) and a measurement range of 0 to 245 picoseconds without increasing the number of delay stages, thereby improving landscape efficiency on integrated circuit dies, reducing circuit complexity, and lowering manufacturing costs.

[0016] Figure 2 is a block diagram of a time-to-digital converter 200 according to several embodiments. The time-to-digital converter 200 in Figure 2 is shown as a non-limiting example. In some embodiments, some components of the time-to-digital converter 200 are simplified or omitted in Figure 2.

[0017] In Figure 2, the time-to-digital converter 200 includes a first oscillator 210, a second oscillator 220, a phase detector 230, and a clock counter 240. The first oscillator 210 is configured to receive a first reference signal START1 and a first slowdown control signal SLOW1. The first oscillator 210 is configured to output a first clock signal CKA_M in response to a first event. In some embodiments, the first oscillator 210 is further configured to output a first buffer clock signal CKA_OUT, which is derived based on the first clock signal CKA_M having passed through the buffer stage of the first oscillator 210. In some embodiments, the first clock signal CKA_M and the first buffer clock signal CKA_OUT have a first clock period T1.

[0018] Furthermore, the second oscillator 220 is configured to receive a second reference signal START2 and a second slowdown control signal SLOW2. The second oscillator 220 is configured to output a second clock signal CKB_M in response to a second event. In some embodiments, the second clock signal CKB_M has a second clock period T2. In some embodiments, the first event occurs before the second event. In some embodiments, the first clock period T1 is greater than the second clock period T2. In some embodiments, the second clock period T2 is at least 100 times the period difference ΔT between the first clock period T1 and the second clock period T2. In some embodiments, the second clock period T2 is in the range of 2 nanoseconds (ns) to 6 ns. In some embodiments, the period difference ΔT is in the range of 60 femtoseconds (fs) to 100 fs.

[0019] In some embodiments, as a non-limiting example, a first event corresponds to a change or transition of a first reference signal START1 from a first logic state (e.g., logic LOW, or LOW in the present invention) to a second logic state (e.g., logic HIGH, or HIGH in the present invention). In some embodiments, a second event corresponds to a change or transition of a second reference signal START2 from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH). In some embodiments, the first oscillator 210 is configured to be deactivated based on the first reference signal START1 being in a first logic state and to be deactivated based on the first reference signal START1 being in a second logic state. In some embodiments, the second oscillator 220 is configured to be deactivated based on the second reference signal START2 being in a first logic state and to be activated based on the second reference signal START2 being in a second logic state.

[0020] In some embodiments, the first clock period T1 is adjustable based on a first slowdown control signal SLOW1, and the second clock period T2 is adjustable based on a second slowdown control signal SLOW2. In some embodiments, the first oscillator 210 and the second oscillator 220 are based on the same hardware configuration. In some embodiments, the first oscillator 210 is a first ring oscillator configured to set a first configurable delay of the first oscillator 210 by including one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two consecutive inverting stages of the first oscillator 210. In some embodiments, the second oscillator 220 is a second ring oscillator configured to set a second configurable delay of the second oscillator 220 by including one or more of a second load capacitance, a second load resistance, or a second phase interpolator between two consecutive inverting stages of the second oscillator 220. In some embodiments, the first clock period T1 is determinable based on a first configurable delay of the first oscillator 210, and the second clock period T2 is determinable based on a second configurable delay of the second oscillator 220.

[0021] During operation of the time-to-digital converter 200, the first clock period T1 and the second clock period T2 are set based on the first slowdown control signal SLOW1 and the second slowdown control signal SLOW2. For example, during operation, the first slowdown control signal SLOW1 is set to a second logical state (e.g., HIGH) indicating that the first clock period T1 corresponds to a slower clock setting of the first oscillator 210 (e.g., setting the first configurable delay to a larger value), and the second slowdown control signal SLOW2 is set to a first logical state (e.g., LOW) indicating that the second clock period T2 corresponds to a faster clock setting of the second oscillator 220 (e.g., setting the second configurable delay to a smaller value).

[0022] Furthermore, in some alternative embodiments, the first oscillator 210 and the second oscillator 220 are based on different hardware configurations corresponding to outputting clock signals having a first clock period T1 and a second clock period T2, respectively. In some embodiments, adjustable delays are not available based on the hardware configurations of the first oscillator 210 and the second oscillator 220, and therefore the first slowdown control signal SLOW1 and / or the second slowdown control signal SLOW2 are omitted.

[0023] The phase detector 230 is configured to generate a detection signal HITB based on the phase relationship between a first clock signal CKA_M and a second clock signal CKB_M. In some embodiments, as a non-limiting example, the detection signal HITB has a first logic state (e.g., LOW) indicating that the phase of the first clock signal CKA_M is delayed compared to the phase of the second clock signal CKB_M, and a second logic state (e.g., HIGH) indicating that the phase of the second clock signal CKB_M is delayed compared to the phase of the first clock signal CKA_M.

[0024] The clock counter 240 is configured to generate a count value TDC_OUT based on the first clock signal CKA_M in response to a detection signal HITB indicating that the phase of the second clock signal CKA_M is delayed compared to the phase of the first clock signal CKA_M. In some embodiments, the count value TDC_OUT represents the time difference between the first event and the second event. In some embodiments, the clock counter 240 is configured to receive and count the clock cycles of the first clock signal CKA_M. In some embodiments, the clock counter 240 is configured to receive and count the clock cycles of the first buffer clock signal CKA_OUT. In yet another embodiment, instead of the first clock signal CKA_M or the first buffer clock signal CKA_OUT, the clock counter 240 is configured to generate a count value TDC_OUT based on the second clock signal CKA_M in response to a detection signal HITB indicating that the phase of the second clock signal CKA_M is delayed compared to the phase of the first clock signal CKA_M.

[0025] In Figure 2, the clock counter 240 includes a clock gating circuit 250 and a counter 260. In some embodiments, the clock gating circuit 250 is configured to generate a count clock signal CKC based on a first clock signal CKA_M (or a first buffer clock signal CKA_OUT derived from the first clock signal CKA_M) and a detection signal HITB. In some embodiments, the clock gating circuit 250 is configured to generate a count clock signal CKC having the same frequency and period as the first clock signal CKA_M in response to the detection signal HITB being in a second logic state (e.g., HIGH) indicating that the phase of a second clock signal CKB_M is lagging behind the phase of the first clock signal CKA_M. In some embodiments, the clock gating circuit 250 is configured to set the count clock signal CKC to a logic state (e.g., a first logic state or LOW) in response to the detection signal HITB being in a first logic state (e.g., LOW). In this example, the clock gating circuit 250 includes a clock terminal (indicated by a triangle) configured to receive a first clock signal CKA_M or a first buffer clock signal CKA_OUT, an enable terminal (indicated as "EN") configured to receive a detection signal HITB, and an output terminal configured to output a count clock signal CKC.

[0026] In some embodiments, the counter 260 is an N-bit counter, and TDC_OUT is a count value which is an N-bit unsigned integer. In some embodiments, N is in the range of 6 to 12 or in the range of 8 to 10. In this example, the counter 260 includes a clock terminal (indicated by a triangle) configured to receive a count clock signal CKC, and an output terminal configured to output the count value TDC_OUT.

[0027] In some embodiments, the integrated circuit die includes one or more digital circuit blocks configured to output various reference signals (e.g., a first reference signal START1 and a second reference signal START2). In some embodiments, the integrated circuit die further includes a time-to-digital converter 200 configured to output a count value (e.g., a count value TDC_OUT) indicating the time difference between a first event based on the first reference signal and a second event based on the second reference signal.

[0028] Figure 3 is a process flow diagram of a process flow 300 performed by a time-to-digital converter according to several embodiments. In some embodiments, the process flow 300 is shown as a non-limiting example based on various operations performed by the time-to-digital converter 200 in Figure 2. In Figure 3, the process flow 300 includes stages 310 to 355.

[0029] In stage 310, various components of the time-to-digital converter are reset. For example, the phase detector 230, the clock gating circuit 250, and the counter 260 are reset to clear any data or logic state from the previous time-to-digital conversion session. In stage 310, the detection signal HITB is set to deactivate the clock gating circuit 250, and the count clock signal CKC is set to perform no action on the counter 260.

[0030] In stage 315, a first reference signal (e.g., first reference signal START1) changes from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH). This logic state transition indicates the occurrence of a first event. In stage 320, a first oscillator (e.g., first oscillator 210) outputs a first clock signal (e.g., first clock signal CKA_M) as an oscillation signal in response to the first event. In some embodiments, the first clock signal CKA_M has a first clock period T1.

[0031] In stage 325, based on the presence of the first clock signal CKA_M (as an oscillation signal) and the absence of the second clock signal CKB_M (as an oscillation signal), the phase detector 230 initiates the output of the detection signal HITB in a first logic state (e.g., LOW) indicating that the phase of the second clock signal CKB_M is lagging behind the phase of the first clock signal CKA_M, thereby activating the clock gating circuit 250, and subsequently the counter 260.

[0032] In stage 330, a second reference signal (e.g., second reference signal START2) changes from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH). This logic state transition indicates the occurrence of a second event. In some embodiments, the transition of the logic state of the second reference signal START2 from LOW to HIGH is delayed by a time difference Tsense compared to the transition of the logic state of the first reference signal START1 from LOW to HIGH. In stage 335, a second oscillator (e.g., second oscillator 220) outputs a second clock signal (e.g., second clock signal CKB_M) as an oscillation signal in response to the second event. In some embodiments, the second clock signal CKB_M has a second clock period T2 equal to (T1-ΔT). In stage 335, the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, and the clock gating circuit 250 and counter 260 remain active.

[0033] In stage 340, after Tsense / ΔT cycles, the phase of the second clock signal CKB_M catches up to and then leads the phase of the first clock signal CKA_M. In stage 345, in response to the update of the phase relationship between the first clock signal CKA_M and the second clock signal CKB_M, the phase detector 230 outputs a detection signal HITB of a second logic state (e.g., HIGH) indicating that the phase of the first clock signal CKA_M is lagging behind the phase of the second clock signal CKB_M.

[0034] In stage 350, the detection signal HITB is in a second logic state (e.g., HIGH), so the clock gating circuit 250 is deactivated. In stage 350, the clock gating circuit 250 sets the count clock signal CKC to a fixed logic state so that the counter 260 does not perform any operation. In stage 355, the counter 260 stops. The counter output (e.g., count value TDC_OUT) is read as the conversion result. In some embodiments, the count value TDC_OUT represents the ratio of the time difference Tsense to the period difference ΔT. In some embodiments, the time difference Tsense is determined based on TDC_OUT × ΔT. In some embodiments, ΔT also represents the time-domain resolution of the time-to-digital converter, and the count value range of the counter 260 corresponds to the measurable range of the time-to-digital converter.

[0035] Figure 4A is a circuit diagram of an oscillator 400, which is a ring oscillator according to several embodiments. In some embodiments, the hardware configuration of oscillator 400 is a non-limiting example that can be used to implement the first oscillator 210 and / or the second oscillator 220 in Figure 2.

[0036] The oscillator 400 includes a first NAND gate 412 as an input stage, a first inverter group 414, a second inverter group 415, a third inverter group 416, a second NAND gate 417, and an inverter 418. The oscillator 400 further includes a buffer circuit 420 after the third inverter group 416 and a delay circuit 430 between the second inverter group 415 and the third inverter group 416. In some embodiments, the buffer circuit 420 includes one or more inverters. In this example, the delay circuit 430 includes a drive stage 432 (including one or more inverters, for example, one inverter in this example) and a third NAND gate 434. In Figure 4A, the first NAND gate 412, the first inverter group 414, the second inverter group 415, the drive stage 432 of the delay circuit 430, the third inverter group 416, the second NAND gate 417, and the inverter 418 are electrically connected in succession as a loop of K inverting stages, where K is an odd positive integer. In some embodiments, the signal at the output terminal of the first inverter group 414 is output as a clock signal CK_M by the oscillator 400.

[0037] In some embodiments, the first NAND gate 412 includes a first input terminal configured to receive a feedback clock signal CK_F from the inverter 418, and a second input signal configured to receive a reference signal START. In some embodiments, in response to the reference signal START being in a first logic state (e.g., LOW), the first NAND gate 412 outputs a second logic state (e.g., HIGH), thereby effectively deactivating the oscillator 400. In some embodiments, in response to the reference signal START being in a second logic state (e.g., HIGH), the first NAND gate 412 outputs an inverted feedback clock signal CK_F to its output terminal.

[0038] In some embodiments, the second NAND gate 417 includes a first input terminal electrically connected to the output terminal of the third inverter 416, and a second input signal configured to receive an enable signal EN. In some embodiments, in response to the enable signal EN being in a first logic state (e.g., LOW), the second NAND gate 417 outputs a second logic state (e.g., HIGH), thereby effectively deactivating the oscillator 400. In some embodiments, in response to the enable signal EN being in a second logic state (e.g., HIGH), the second NAND gate 417 outputs an inverted signal of the signal from the output terminal of the third inverter 416 to its output terminal. In some embodiments, the second NAND gate 417 is replaced by an inverter, and the enable signal EN is omitted.

[0039] In some embodiments, the buffer circuit 420 is configured to output a buffer clock signal CK_OUT having the same frequency and period as the clock signal CK_M. In some embodiments, the buffer circuit 420 provides the buffer clock signal CK_OUT with a higher driving capability than the clock signal CK_M while minimizing interference to the loop of the K inverting stages of the oscillator 400.

[0040] In some embodiments, the delay circuit 430 is configured to introduce an adjustable delay into the loop of K inversion stages of the oscillator 400. In this example, the third NAND gate 434 is shown as a non-limiting example. In some embodiments, a NOR gate is used instead of the third NAND gate 434.

[0041] In this example, the third NAND gate 434 includes a first input terminal (denoted as the "LOAD" terminal) connected to the output terminal of the drive stage 432, a second input terminal configured to receive a slowdown control signal SLOW, and an output terminal that is not electrically connected to any other circuit. In some embodiments, in response to the slowdown control signal SLOW being in a first logic state (e.g., LOW), the first input terminal exhibits a first equivalent load capacitance. In some embodiments, in response to the slowdown control signal SLOW being in a second logic state (e.g., HIGH), the first input terminal exhibits a second equivalent load capacitance that is greater than the first equivalent load capacitance.

[0042] In one example where the first oscillator 210 is based on oscillator 400, the reference signal START and its corresponding terminal in Figure 4A correspond to the first reference signal START1 and its corresponding terminal in Figure 2, the clock signal CK_M and its corresponding terminal in Figure 4A correspond to the first clock signal CKA_M and its corresponding terminal in Figure 2, the buffer clock signal CK_OUT and its corresponding terminal in Figure 4A correspond to the first buffer clock signal CKA_OUT and its corresponding terminal in Figure 2, and the slowdown control signal SLOW and its corresponding terminal in Figure 4A correspond to the first slowdown control signal SLOW1 and its corresponding terminal in Figure 2.

[0043] Figure 4B is a schematic diagram of a non-limiting example of a NAND gate 434 in the delay circuit 430 of Figure 4A according to several embodiments. In Figure 4B, the NAND gate 434 includes a first input terminal 442, also labeled "LOAD" in Figure 4A. The NAND gate 434 also includes a second input terminal 444 configured to receive a slowdown control signal SLOW, and an output terminal 446 that is not electrically connected to any other circuitry outside of the NAND gate 434.

[0044] The NAND gate 434 includes a first p-type transistor 452, a second p-type transistor 454, a first n-type transistor 456, and a second n-type transistor 458. The first drain / source terminals of the first p-type transistor 452 and the first drain / source terminal of the second p-type transistor 454 are electrically connected to a first power node configured to transmit a first power supply voltage (e.g., VDD). The second drain / source terminals of the first p-type transistor 452, the second drain / source terminal of the second p-type transistor 454, and the first drain / source terminal of the first n-type transistor 456 are electrically connected to the output terminal 446 of the NAND gate 434. The second drain / source terminal of the first n-type transistor 456 is electrically connected to the first drain / source terminal of the second n-type transistor 458. The second drain / source terminal of the second n-type transistor 458 is electrically connected to a second power node configured to transmit a second power supply voltage (e.g., VSS or ground). The gate terminals of the first p-type transistor 452 and the first n-type transistor 456 are electrically connected to the first input terminal 442 of the NAND gate 434. The gate terminals of the second p-type transistor 454 and the second n-type transistor 458 are electrically connected to the second input terminal 444 of the NAND gate 434.

[0045] In this example, in response to the slowdown control signal SLOW being in a first logic state (e.g., LOW), the second p-type transistor 454 turns on and the second n-type transistor 458 turns off, and the load capacitance observable at the first input terminal 442 is based primarily on the parasitic capacitance (represented by a capacitor with capacitance Cp) between the first input terminal 442 and the output terminal 446. Also, in response to the slowdown control signal SLOW being in a second logic state (e.g., HIGH), the second p-type transistor 454 turns off and the second n-type transistor 458 turns on, and the load capacitance observable at the first input terminal 442 is based on the amplification of the parasitic capacitance (e.g., capacitance Cp) due to the Miller effect, which is essentially (1+M)×Cp, where M is the gain from the output terminal 446 to the first input terminal 442.

[0046] In this example, the load difference between when the slowdown control signal SLOW is in a first logic state and when it is in a second logic state is M × Cp. In some embodiments, an oscillator based on oscillator 400 having a load capacitance Cp and another oscillator based on oscillator 400 having a load capacitance (1 + M) × Cp have different clock periods, and the difference in clock periods can be determined based on the load difference M × Cp.

[0047] Figure 5 is a circuit diagram of the phase detector 500 according to several embodiments. In some embodiments, the phase detector 500 is a non-limiting example of the phase detector 230 in Figure 2.

[0048] In Figure 5, the phase detector 500 includes a D-type flip-flop 510, a first buffer stage including inverters 522 and 524 connected in series, a second buffer stage including inverters 532 and 534 connected in series, and an output stage including inverter 542. In some embodiments, inverters 522 and 524 are configured to buffer a first clock signal (e.g., first clock signal CKA_M) from a first oscillator (e.g., first oscillator 210), and inverters 532 and 534 are configured to buffer a second clock signal (e.g., second clock signal CKB_M) from a second oscillator (e.g., second oscillator 220).

[0049] In this example, the D-type flip-flop 510 includes a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the D-type flip-flop 510 is configured to receive a first signal from a first buffer stage and corresponding to a first clock signal CKA_M. In some embodiments, the CLK terminal of the D-type flip-flop 510 is configured to receive a second signal that is inverted based on a signal from a second buffer stage and corresponds to the inversion of a second clock signal CKB_M. In some embodiments, the Q terminal of the D-type flip-flop 510 is configured to output a third signal corresponding to a detection signal HITB. In this example, the inverter 542 receives the third signal from the Q terminal of the D-type flip-flop 510 and outputs the detection signal HITB. In some embodiments, the CD terminal of the D-type flip-flop 510 is configured to receive a reset signal RST. The reset signal RST does not affect the operation of the D-type flip-flop 510 in response to the reset signal RST being in a first logic state (e.g., LOW), and resets the output of the Q terminal of the D-type flip-flop 510 in response to the reset signal RST being in a second logic state (e.g., HIGH).

[0050] Figure 6A is a schematic diagram of an example clock gating circuit 600 according to several embodiments. In some embodiments, the clock gating circuit 600 is a non-limiting example of the clock gating circuit 250 in Figure 2.

[0051] In Figure 6A, the clock gating circuit 600 includes a first D-type flip-flop 610, a second D-type flip-flop 620, a first buffer stage including inverters 632 and 634 connected in series, a second buffer stage including inverter 642, and an output stage including a NAND gate 644. In this example, each of the first D-type flip-flop 610 and the second D-type flip-flop 620 includes a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the first D-type flip-flop 610 is configured to receive a power supply voltage (e.g., VDD) representing a second logic state (e.g., HIGH). In some embodiments, the CLK terminal of the first D-type flip-flop 610 is configured to receive a signal inverted based on a detection signal HITB. In some embodiments, the CD terminal of the first D-type flip-flop 610 is configured to receive a reset signal RST. The reset signal RST does not affect the operation of the first D-type flip-flop 610 in response to the reset signal RST being in a first logic state (e.g., LOW), and resets the output of the Q terminal of the first D-type flip-flop 610 in response to the reset signal RST being in a second logic state (e.g., HIGH). In some embodiments, inverters 632 and 634 are configured to buffer the output signal from the Q terminal of the first D-type flip-flop 610 and supply the buffered output signal (denoted "STOP") to the second D-type flip-flop 620.

[0052] In some embodiments, the D terminal of the second D-type flip-flop 620 is configured to receive a buffer output signal STOP from the inverter 634. In some embodiments, the CLK terminal of the second D-type flip-flop 620 is configured to receive a first buffer clock signal CKA_OUT from the first oscillator (e.g., the first oscillator 210). In some embodiments, the CD terminal of the second D-type flip-flop 620 is configured to receive a reset signal RST. The reset signal RST does not affect the operation of the second D-type flip-flop 620 in response to the reset signal RST being in a first logic state (e.g., LOW), and causes the second D-type flip-flop 620 to reset the output of its Q terminal in response to the reset signal RST being in a second logic state (e.g., HIGH). In some embodiments, the Q terminal of the second D-type flip-flop 620 is configured to output the signal STOP_R based on the signal STOP and the first buffer clock signal CKA_OUT.

[0053] In this example, inverter 642 receives the signal STOP_R and outputs the inverted signal STOP_B. In some embodiments, NAND gate 644 includes a first input terminal configured to receive a first buffer clock signal CKA_OUT and a second input terminal configured to receive the signal STOP_B. In some embodiments, in response to the signal STOP_B being in a first logic state (e.g., LOW), NAND gate 644 outputs a second logic state (e.g., HIGH) from its output terminal as a counter clock signal CKC (e.g., a non-oscillating signal). In some embodiments, in response to the signal STOP_B being in a second logic state (e.g., HIGH), NAND gate 644 outputs the inverted signal of the first buffer clock signal CKA_OUT from its output terminal as a counter clock signal CKC (e.g., an oscillating signal).

[0054] In other embodiments, instead of the first buffer clock signal CKA_OUT, the first clock signal CKA_M, the second clock signal CKB_M, or a second buffer clock signal based on the second clock signal CKB_M may be used.

[0055] Figure 6B is a schematic diagram of a modified version 650A based on the clock gating circuit 600 of Figure 6A according to several embodiments. In some embodiments, the combination of the second D-type flip-flop 620, inverter 642, and NAND gate 644 can be replaced in modified version 650A.

[0056] In Figure 6B, modified example 650A includes a D-type flip-flop 620A and an AND gate 646. In this example, the D-type flip-flop 620A includes a D terminal, a CLK terminal, and a Q terminal. In some embodiments, the D terminal of the D-type flip-flop 620A is configured to receive the signal STOP. In some embodiments, the clock terminal of the D-type flip-flop 620A is configured to receive a first buffer clock signal CKA_OUT from a first oscillator (e.g., first oscillator 210). In some embodiments, the Q terminal of the D-type flip-flop 620A is configured to output the signal STOP_R based on the signal STOP and the first buffer clock signal CKA_OUT.

[0057] In Figure 6B, the first input terminal of the AND gate 646 is configured to receive the signal STOP_R, and the second input terminal of the AND gate 646 is configured to receive the first buffer clock signal CKA_OUT. In this example, the output terminal of the AND gate 646 is configured to output the counter clock signal CKC.

[0058] Figure 6C is a schematic diagram of a modified version 650B based on the clock gating circuit 600 of Figure 6A according to several embodiments. In some embodiments, the combination of the second D-type flip-flop 620, inverter 642, and NAND gate 644 can be replaced in modified version 650A.

[0059] In Figure 6C, modified example 650B includes a D-type latch 620B and an AND gate 646. In this example, the D-type flip latch 620B includes a D terminal, an EN terminal, and a Q terminal. In some embodiments, the D terminal of the D-type latch 620B is configured to receive the signal STOP. In some embodiments, the EN terminal of the D-type latch 620B is configured to receive a first buffer clock signal CKA_OUT from a first oscillator (e.g., first oscillator 210). In some embodiments, the Q terminal of the D-type latch 620B is configured to output the signal STOP_R based on the signal STOP and the first buffer clock signal CKA_OUT.

[0060] In Figure 6C, the first input terminal of the AND gate 646 is configured to receive the signal STOP_R, and the second input terminal of the AND gate 646 is configured to receive the first buffer clock signal CKA_OUT. In this example, the output terminal of the AND gate 646 is configured to output the counter clock signal CKC.

[0061] Figure 7 is a block diagram of a counter example 700 according to several embodiments. In some embodiments, the counter 700 is a non-limiting example of the counter example 260 in Figure 2.

[0062] In Figure 7, the counter 700 includes an N-bit adder 710 and an N-bit clocked buffer 720. In some embodiments, the N-bit adder 710 corresponds to an N-bit carry-ripple adder and includes a first N-bit input port Ain, a second N-bit input port Bin, a carry input terminal Cin, and an N-bit output port S. In some embodiments, the N-bit clocked buffer 720 corresponds to a set of N D-type flip-flops and includes an N-bit input port D, an N-bit output port Q, a clock terminal (indicated by a triangle), and a CD terminal. In some embodiments, the CD terminal of the N-bit clocked buffer 720 is configured to reset the binary value of the N-bit output port Q based on a reset signal RST. In some embodiments, the N-bit clocked buffer 720 is configured to update the binary value of the N-bit output port Q with the binary value of the N-bit input port D in response to a counter clock signal CKC at the clock terminal.

[0063] In this example, the N-bit output port Q of the N-bit clock buffer 720 is configured to transmit the count value TDC_OUT, and the first N-bit input port Ain of the N-bit adder 710 is configured to receive the count value TDC_OUT from the N-bit output port Q of the N-bit clock buffer 720. In this example, the second N-bit input port Bin is configured to receive the binary value 0001b, and the carry input terminal Cin is connected to a power supply voltage (e.g., VSS or ground) representing the binary value 0b. In some embodiments, the N-bit output port S is configured to output a binary value based on the sum of the binary values ​​in the first N-bit input port Ain, the second N-bit input port Bin, and the carry input terminal Cin. The N-bit input port D of the N-bit clock buffer 720 receives the binary value from the N-bit output port S of the N-bit adder 710.

[0064] During operation, in response to the counter clock signal CKC transitioning from a first logical state (e.g., LOW) to a second logical state (e.g., HIGH), the N-bit clock buffer 720 updates the count value TDC_OUT at the N-bit output port Q based on the output value of the N-bit adder 710. In response to the updated count value TDC_OUT, the N-bit adder 710 updates the digital value at the N-bit output port S by adding the updated count value TDC_OUT (the value at the first N-bit input port Ain) to 1 (the value at the second N-bit input port Bin). The updated digital value at the N-bit output port S is used to update the count value TDC_OUT at the N-bit output port Q when the counter clock signal CKC next transitions from a first logical state (e.g., LOW) to a second logical state (e.g., HIGH).

[0065] Figures 8A to 8D show the signal waveforms and / or digital values ​​of example time-to-digital conversion sessions using a time-to-digital conversion device, based on examples from Figures 2 to 6A and 7, according to several embodiments.

[0066] Figure 8A includes charts 801-808. In charts 801-807, time is represented on the horizontal axis, and the voltage levels of various signals are represented on the vertical axis. In chart 808, time is represented on the horizontal axis, and digital values ​​are represented on the vertical axis.

[0067] Chart 801 includes waveform 812 corresponding to the waveform of the reset signal RST in Figures 5, 6A, and 7. Chart 802 includes waveform 822 corresponding to the waveform of the first reference signal START1 in Figure 2, and waveform 824 corresponding to the waveform of the second reference signal START2 in Figure 2. Chart 803 includes waveform 832 corresponding to the waveform of the first clock signal CKA_M in Figures 2 and 5. Chart 804 includes waveform 834 corresponding to the waveform of the second clock signal CKB_M in Figures 2 and 5. Chart 805 includes waveform 836 corresponding to the waveform of the count clock signal CKC in Figures 2, 6A, and 7. Chart 806 includes waveform 842 corresponding to the waveform of the detection signal HITB in Figures 2, 5, and 6A. Chart 807 includes waveform 844 corresponding to the waveform of the buffer output signal STOP in Figure 6A. Chart 808 includes waveform 850, which corresponds to the waveform of the count value TDC_OUT in Figures 2 and 7.

[0068] In Figure 8A, the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834), and the count clock signal CKC (waveform 836) oscillate between high-voltage levels (e.g., corresponding to a HIGH logic state) and low-voltage levels (e.g., corresponding to a LOW logic state) in response to the transition from low-voltage levels to high-voltage levels of the first reference signal START1 (waveform 822) and the second reference signal START2 (waveform 824). In Figure 8A, the count value TDC_OUT (waveform 850) increases while the phase of the second reference signal START2 lags behind the phase of the first reference signal START1. In Figure 8A, when the detection signal HITB (waveform 842) and the buffer output signal STOP (waveform 844) indicate that the phase of the first reference signal START1 is delayed compared to the phase of the second reference signal START2, the count value TDC_OUT (waveform 850) stops increasing, and the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834), and the count clock signal CKC (waveform 836) are maintained in a fixed logic state (for example, represented by the low voltage level).

[0069] Some of the charts 801-808 in Part A are further shown in Figure 8B, and some of the charts 801-808 in Part B are further shown in Figure 8C.

[0070] Figure 8B is an enlarged view of Part A of Figure 8A. Figure 8B includes charts 801A to 808A, which correspond to parts of charts 801 to 808 in Part A. In Figure 8B, the same waveforms as in Figure 8A are given the same symbols.

[0071] In Figure 8B, before time t0, the reset signal RST (waveform 812) is at a high voltage level (e.g., HIGH) for resetting various components of the time-to-digital converter (e.g., time-to-digital converter 200), which corresponds to stage 310 in Figure 3. At time t0, the reset signal RST (waveform 812) transitions from a high voltage level (e.g., HIGH) to a low voltage level (e.g., LOW), allowing the time-to-digital converter to operate in response to various other signals.

[0072] At time t1, the first reference signal START1 (waveform 822) transitions from a low voltage level (e.g., LOW) to a high voltage level (e.g., HIGH), which corresponds to stage 315 in Figure 3. In response to this transition, corresponding to stage 320 in Figure 3, the first oscillator (e.g., first oscillator 210) begins outputting the first clock signal CKA_M (waveform 832) as an oscillating signal that transitions between the low voltage level and the high voltage level after an inherent delay. Also, a clock counter (e.g., clock counter 240) is shown as the count clock signal CKC (waveform 836) and is activated by the first clock signal CKA_M, corresponding to stage 325 in Figure 3.

[0073] At time t2, the second reference signal START2 (waveform 824) transitions from a low voltage level (e.g., LOW) to a high voltage level (e.g., HIGH), which corresponds to stage 330 in Figure 3. The transition of the second reference signal START2 is delayed by a time difference Tsense compared to the transition of the first reference signal START1 (e.g., t2-t1=Tsense). In response to the transition of the second reference signal START2, corresponding to stage 335 in Figure 3, the second oscillator (e.g., second oscillator 220) begins outputting the second clock signal CKB_M (waveform 834) as an oscillating signal that transitions between a low voltage level and a high voltage level after an inherent delay.

[0074] In some embodiments, the first clock signal CKA_M has a first clock period T1, and the second clock signal CKB_M has a second clock period T2, the second clock period T2 being smaller than the first clock period T1 by a period difference ΔT. In Figure 8B, the phase of the second clock signal CKB_M begins to lag behind the phase of the first clock signal CKA_M. In Figure 8B, the phase difference between the second clock signal CKB_M and the first clock signal CKA_M decreases by a period difference ΔT for each clock cycle of the first clock signal CKA_M or the second clock signal CKB_M. In this example, the count clock signal CKC (waveform 836) and the first clock signal CKA_M have the same frequency. Therefore, the clock counter counts the clock cycles of the count clock signal CKC, which represents the number of clock cycles elapsed for the first clock signal CKA_M.

[0075] Figure 8C is an enlarged view of Part B of Figure 8A. Figure 8C includes charts 801B to 808B, which correspond to parts of charts 801 to 808 within Part B. In Figure 8C, the same waveforms as in Figure 8A are given the same symbols.

[0076] In Figure 8C, at time t3, after Tsense / ΔT cycles following the activation of the first oscillator, the phase of the second clock signal CKB_M (waveform 834) catches up to and begins to lead the phase of the first clock signal CKA_M (waveform 832), which corresponds to stage 340 in Figure 3. At time t4, the phase detector (e.g., phase detector 230) detects a change in the phase relationship between the first clock signal CKA_M and the second clock signal CKB_M and outputs a detection signal HITB (waveform 842) that transitions from a high voltage level (e.g., HIGH) to a low voltage level (e.g., LOW), which corresponds to stage 345 in Figure 3.

[0077] In response to the detection signal HITB (waveform 842) transitioning from a high voltage level to a low voltage level, corresponding to stage 350 in Figure 3, the buffer output signal STOP (waveform 844) transitions from a low voltage level to a high voltage level, thereby deactivating the clock gating circuit (e.g., clock gating circuit 250) and outputting the count clock signal CKC (waveform 836). Subsequently, the digital value of the count value TDC_OUT (waveform 850) is read as the conversion result, which corresponds to stage 355 in Figure 3.

[0078] Figure 8D shows the digital value of the count value TDC_OUT (waveform 850) for the time difference (e.g., Tsense) between a first reference signal START1 and a second reference signal START2, based on the example in Figure 8A, according to several embodiments. In Figure 8D, the time difference Tsense is represented on the horizontal axis, and the digital value is represented on the vertical axis.

[0079] In this non-restrictive example, the time difference Tsesne and the digital value are in a linear proportional relationship, as shown by curve 860. In this example, data point 862 represents the count value TDC_OUT with a digital value of 476 in response to a time difference Tsesne of 45.2531 picoseconds (ps). In this example, data point 864 represents the count value TDC_OUT with a digital value of 2876 in response to a time difference Tsesne of 235.4562 ps. Thus, in this non-restrictive example, the resolution for measuring the time difference Tsesne is 79.4 fs (per unit digital value).

[0080] Figure 9A is a schematic diagram of an example delay circuit 900 based on a phase interpolator according to several embodiments. In some embodiments, the delay circuit 900 can be used as an alternative embodiment to the delay circuit 430 in Figure 4A. In Figure 9A, the delay circuit 900 includes inverters 912 and 914, capacitors 922 and 924, and a phase interpolator 932. The input terminals of inverters 912 and 914 are suitable for electrical connection to the second group of inverters 415 in Figure 4A, and the output terminal of the phase interpolator 932 is suitable for electrical connection to the third group of inverters 416 in Figure 4A.

[0081] In Figure 9A, capacitor 922 has one end connected to a power node configured to transmit the power supply voltage (e.g., VSS or ground) and the other end electrically connected to the output terminal of inverter 912 and the input terminal of phase interpolator 932. Capacitor 924 also has one end connected to a power node configured to transmit the power supply voltage (e.g., VSS or ground) and the other end electrically connected to the output terminal of inverter 912 and another input terminal of phase interpolator 932. In some embodiments, capacitor 922 has a capacitance of C1. In some embodiments, capacitor 924 has a capacitance of C2 in response to the slowdown control signal SLOW being in a first logic state (e.g., LOW) and a capacitance of C2+ΔC in response to the slowdown control signal SLOW being in a second logic state (e.g., HIGH). In some embodiments, capacitances C1 and C2 are set to be the same value or to vary within 10%. In some embodiments, capacitor 922 is omitted and capacitance C1 is considered to be zero.

[0082] In Figure 9A, the signal from one input terminal of the phase interpolator 932 connected to the output terminal of inverter 912 is denoted as PI_IN0, and the signal from the other input terminal of the phase interpolator 932 connected to the output terminal of inverter 914 is denoted as PI_IN1. The signal from the output terminal of the phase interpolator 932 is denoted as PI_OUT. In some embodiments, the phase interpolator 932 is configured to determine a first time delay of the signal transition of signal PI_IN1 relative to the signal transition of signal PI_IN0, and to output a signal PI_OUT having the signal transition of signal PI_IN0 and a second time delay. In some embodiments, the second time delay is a fraction of the first time delay.

[0083] Figure 9B shows various signals of the delay circuit 900 of Figure 9A according to several embodiments. In Figure 9B, time is represented on the horizontal axis. In Figure 9B, the signal transition of signal PI_IN1 has a first delay TD1 relative to the signal transition of signal PI_IN0. In Figure 9B, the signal transition of signal PI_OUT has a second delay TD2 relative to the signal transition of signal PI_IN0.

[0084] Therefore, the delay circuit 900 can be configured to further reduce the period difference ΔT between the two oscillators without further reducing the difference in the corresponding load capacitance values ​​of the two oscillators. In some embodiments, the period difference ΔT based on the second delay TD2 is in the range of tens of fs, thereby resulting in a higher resolution for the resulting time-to-digital converter than that based on the first delay TD1.

[0085] Figure 10A is a schematic diagram of an example delay circuit 1000 based on an adjustable load resistor according to several embodiments. In some embodiments, the delay circuit 1000 can be used as another alternative embodiment of the delay circuit 430 in Figure 4A. In Figure 10A, the delay circuit 1000 includes an inverter 1012, a capacitor 1014, and an adjustable resistor 1016. The input terminal of the inverter 1012 is suitable for electrical connection to the second group of inverters 415 in Figure 4A, and the output node 1018 of the delay circuit 1000 is suitable for electrical connection to the third group of inverters 416 in Figure 4A.

[0086] In Figure 10A, the capacitor 1014 has one end connected to a power node configured to transmit a power supply voltage (e.g., VSS or ground) and the other end electrically connected to an output node 1018. The adjustable resistor 1016 has one end electrically connected to the output terminal of the inverter 1012 and the other end electrically connected to the output node 1018. In some embodiments, the time delay between the input terminal of the inverter 1012 and the output node 1018 can be determined based on the resistance value of the adjustable resistor 1016, where a larger resistance value of the adjustable resistor 1016 results in a larger delay between the second inverter group 415 and the third inverter group 416.

[0087] Figure 10B is a circuit diagram of a first adjustable resistor example 1016A that can be used as the adjustable resistor 1016 in Figure 10A, according to several embodiments. The first adjustable resistor 1016A includes a first terminal 1022 and a second terminal 1024, corresponding to the two terminals of the adjustable resistor 1016 in Figure 10A. The first adjustable resistor 1016A includes a p-type transistor 1026, an n-type transistor 1028, and a bias generator 1030. The first drain / source terminals of the p-type transistor 1026 and the first drain / source terminals of the n-type transistor 1028 are electrically connected to the first terminal 1022. The second drain / source terminal of the n-type transistor 1028 is electrically connected to the second terminal 1024.

[0088] In some embodiments, the bias generator 1030 is configured to generate a first bias voltage Vbiasp supplied to the gate terminal of a p-type transistor 1026 and a second bias voltage Vbiasn supplied to the gate terminal of an n-type transistor 1028. In some embodiments, the bias generator 1030 is configured to output appropriate voltage levels in the first bias voltage Vbiasp and the second bias voltage Vbiasn in response to a slowdown control signal SLOW in order to adjust the resistance between the first terminal 1022 and the second terminal 1024.

[0089] Figure 10C is a circuit diagram of an example 1016B of a second adjustable resistor that can be used as the adjustable resistor 1016 of Figure 10A, according to several embodiments. The second adjustable resistor 1016B includes a first terminal 1042 and a second terminal 1044 corresponding to the two terminals of the adjustable resistor 1016 of Figure 10A. The second adjustable resistor 1016B includes a first resistor 1046, a second resistor 1048, and a switch 1050. In this example, the second resistor 1048 is electrically connected between the first terminal 1042 and the second terminal 1044. The first resistor 1046 has one end electrically connected to the second terminal 1044 and the other end electrically connected to the switch 1050.

[0090] In Figure 10C, the switch 1050 is configured to electrically connect the first resistor 1046 to the first terminal 1042 or electrically disconnect the first resistor 1046 from the first terminal 1042 in response to the inverted signal of the slowdown control signal SLOW (indicated as " / SLOW"). Therefore, the resistance value between the first terminal 1042 and the second terminal 1044 is adjustable based on the slowdown control signal SLOW.

[0091] Figure 11 is a circuit diagram of an oscillator configured to accommodate different clock periods according to several embodiments. In Figure 11, the first oscillator 1100A corresponds to the first oscillator 210 in Figure 2, and the second oscillator 1100B corresponds to the second oscillator 220 in Figure 2.

[0092] In some embodiments, the first oscillator 1100A is a ring oscillator and includes a NAND gate 1102A, a first inverter group 1104A, a second inverter group 1106A, and a third inverter group 1110. The first input terminal of the NAND gate 1102A is electrically connected to the output terminal of the third inverter group 1110. The second input terminal of the NAND gate 1102A is configured to receive a reference signal (e.g., a first reference signal START1). In some embodiments, the signal at the output terminal of the first inverter group 1104A is used as an output clock signal (e.g., a first clock signal CKA_M).

[0093] In some embodiments, the second oscillator 1100B is a ring oscillator and includes a NAND gate 1102B, a first inverter group 1104B, and a second inverter group 1106B. The first input terminal of the NAND gate 1102B is electrically connected to the output terminal of the second inverter group 1106B. The second input terminal of the NAND gate 1102B is configured to receive another reference signal (e.g., a second reference signal START2). In some embodiments, the signal at the output terminal of the first inverter group 1104B is used as an output clock signal (e.g., a second clock signal CKB_M).

[0094] In some embodiments, the hardware configuration of the NAND gate 1102A, the first inverter group 1104A, and the second inverter group 1106A is the same as the hardware configuration of the NAND gate 1102B, the first inverter group 1104B, and the second inverter group 1106B. In some embodiments, the third inverter group 1110 includes M inversion stages. In some embodiments, the NAND gate 1102A, the first inverter group 1104A, the second inverter group 1106A, and the third inverter group 1110 are electrically connected in sequence as a loop of K+M inversion stages. In some embodiments, the NAND gate 1102B, the first inverter group 1104B, and the second inverter group 1106B are also electrically connected in sequence as a loop of K inversion stages. In some embodiments, K is an odd positive integer and M is an even positive integer.

[0095] In this example, the additional delay introduced by the third inverter group 1110 further extends the time period of the first clock signal CKA_M relative to the second clock signal CKB_M. In some embodiments, the first slowdown control signal SLOW1 and / or the second slowdown control signal SLOW2 shown in Figure 2 are omitted because adjustable delays are not available based on the hardware configuration of the first oscillator 1100A and the second oscillator 1100B.

[0096] Figure 12 is a flowchart of Method 1200 for generating a count value indicating the time difference between a first event and a second event according to several embodiments. In some embodiments, various operations of Method 1200 are performed by the time-to-digital converter 200 of Figure 2, considering various implementation examples in Figures 3-11. Similar to Figure 12, Method 1200 includes blocks 1210-1240.

[0097] In block 1210, in response to a first event, a first oscillator (e.g., the first oscillator 210 in Figure 2) outputs a first clock signal (e.g., the first clock signal CKA_M in Figure 2). In some embodiments, the first clock signal has a first clock period. In some embodiments, block 1210 corresponds to the operation of at least stages 315 and 320 in Figure 3.

[0098] In some embodiments, method 1200 further includes receiving a first reference signal (e.g., the first reference signal START1 in Figure 2) by a first oscillator, where the first event corresponds to a change in the first reference signal from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH). In some embodiments, method 1200 further includes deactivating the first oscillator based on the first reference signal being in a first logic state, and / or activating the first oscillator based on the first reference signal being in a second logic state.

[0099] In block 1220, in response to a second event, a second oscillator (e.g., the second oscillator 220 in Figure 2) outputs a second clock signal (e.g., the second clock signal CKB_M in Figure 2). In some embodiments, the second clock signal has a second clock period. In some embodiments, the first event occurs before the second event (e.g., by a time difference Tsense). In some embodiments, the first clock period is greater than the second clock period by a period difference ΔT. In some embodiments, block 1220 corresponds to the operation of stages 330 and 335 in Figure 3.

[0100] In some embodiments, method 1200 further includes receiving a second reference signal (e.g., the second reference signal START2 in Figure 2) by a second oscillator, where the second event corresponds to a change in the second reference signal from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH). In some embodiments, method 1200 further includes deactivating a second oscillator based on the second reference signal being in a first logic state, and / or activating a second oscillator based on the second reference signal being in a second logic state.

[0101] In block 1230, a phase detector (e.g., phase detector 230 in Figure 2) generates a detection signal (e.g., detection signal HITB in Figure 2) based on the phase relationship between the first clock signal and the second clock signal. In some embodiments, block 1230 corresponds to the operation of at least stages 340 and 345 in Figure 3.

[0102] In block 1240, in response to a detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, a clock counter (e.g., clock counter 240 in Figure 2) generates a count value (e.g., count value TDC_OUT in Figure 2) based on the first clock signal. In some embodiments, block 1240 corresponds to at least part of the operation of stages 325-345 in Figure 3.

[0103] In some embodiments, to generate a count value by a clock counter, method 1200 further includes generating a count clock signal (e.g., the count clock signal CKC in Figure 2) based on a first clock signal and a detection signal by a clock gating circuit of the clock counter (e.g., the clock gating circuit 250 in Figure 2). In some embodiments, method 1200 further includes generating a count value based on the count clock signal by a counter (e.g., the counter 260 in Figure 2). In some embodiments, the counter is an N-bit counter, where N is in the range of 6 to 12 or in the range of 8 to 10. In some embodiments, the count value is an N-bit unsigned integer.

[0104] In some embodiments, Method 1200 further includes setting a first oscillator, a second oscillator, or both, such that the second clock period is at least 100 times the period difference ΔT between the first clock period and the second clock period. In some embodiments, the first oscillator is a first ring oscillator, and the second oscillator is a second ring oscillator. In some embodiments, Method 1200 further includes setting a first configurable delay of the first oscillator based on configuring one or more of a first load capacitance, a first load resistance, or a first phase interpolator between successive inverting stages of the first oscillator, as shown in the examples of Figures 4A, 4B, and 9A to 10C. In some embodiments, method 1200 further includes setting a second configurable delay of a second oscillator based on configuring one or more of a second load capacitance, a second load resistance, or a second phase interpolator between successive inversion stages of a first oscillator, as shown in the examples of Figures 4A, 4B, and 9A to 10C.

[0105] In some embodiments, the time-to-digital converter includes a first oscillator configured to output a first clock signal in response to a first event, and a second oscillator configured to output a second clock signal in response to a second event. The first event occurs before the second event. The first clock signal has a first clock period, and the second clock signal has a second clock period, with the first clock period being greater than the second clock period. The time-to-digital converter further includes a phase detector configured to generate a detection signal based on the phase relationship between the first and second clock signals, and a clock counter configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is lagging behind the phase of the first clock signal. The count value indicates the time difference between the first and second events.

[0106] In some embodiments, a first event corresponds to a change in a first reference signal from a first logic state to a second logic state, and a second event corresponds to a change in a second reference signal from a first logic state to a second logic state. In some embodiments, a first oscillator is configured to be deactivated based on the first reference signal being in a first logic state and activated based on the first reference signal being in a second logic state, and a second oscillator is configured to be deactivated based on the second reference signal being in a first logic state and activated based on the second reference signal being in a second logic state. In some embodiments, the first oscillator is a first ring oscillator configured to set a first configurable delay of the first oscillator by including one or more of a first load capacitance, a first load resistor, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and the second oscillator is a second ring oscillator configured to set a second configurable delay of the second oscillator by including one or more of a second load capacitance, a second load resistor, or a second phase interpolator between two consecutive inverting stages of the second oscillator. In some embodiments, the first or second load capacitance is based on a NAND gate or a NOR gate. In some embodiments, the phase detector includes a D-type flip-flop, the D terminal of the D-type flip-flop is configured to receive a first signal corresponding to a first clock signal, the clock terminal of the D-type flip-flop is configured to receive a second signal corresponding to the inversion of a second clock signal, and the Q terminal of the D-type flip-flop is configured to output a third signal corresponding to a detection signal. In some embodiments, the clock counter includes a clock gating circuit configured to generate a count clock signal based on a first clock signal and a detection signal, and a counter configured to generate a count value based on the count clock signal. In some embodiments, the clock gating circuit has a NAND gate or AND gate based on a D-type flip-flop or a D-type latch. In some embodiments, the counter is an N-bit counter, where N is in the range of 6 to 12.In some embodiments, the second clock period is at least 100 times the period difference between the first clock period and the second clock period.

[0107] In some embodiments, a method for generating a count value indicating a time difference between a first event and a second event includes: outputting a first clock signal in response to a first event using a first oscillator; and outputting a second clock signal in response to a second event using a second oscillator. The first event occurs before the second event. The first clock signal has a first clock period, and the second clock signal has a second clock period, with the first clock period being greater than the second clock period. The method further includes: generating a detection signal using a phase detector based on the phase relationship between the first clock signal and the second clock signal; and generating a count value using a clock counter based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal.

[0108] In some embodiments, the method further includes receiving a first reference signal by a first oscillator, wherein the first event corresponds to a change in the first reference signal from a first logic state to a second logic state; and receiving a second reference signal by a second oscillator, wherein the second event corresponds to a change in the second reference signal from a first logic state to a second logic state. In some embodiments, the method further includes deactivating the first oscillator based on the first reference signal being in a first logic state; activating the first oscillator based on the first reference signal being in a second logic state; deactivating the second oscillator based on the second reference signal being in a first logic state; or activating the second oscillator based on the second reference signal being in a second logic state. In some embodiments, the method further includes setting a first configurable delay of a first oscillator based on configuring one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two consecutive inverting stages of a first oscillator; and setting a second configurable delay of a second oscillator based on configuring one or more of a second load capacitance, a second load resistance, or a second phase interpolator between two consecutive inverting stages of a first oscillator, where the first oscillator is a first ring oscillator and the second oscillator is a second ring oscillator. In some embodiments, generating a count value by a clock counter includes generating a count clock signal based on a first clock signal and a detection signal by a clock gating circuit of the clock counter; and generating a count value based on the count clock signal by the counter. In some embodiments, the count value is an N-bit unsigned integer, where N is in the range of 6 to 12. In some embodiments, the method further includes setting a first oscillator, a second oscillator, or both, such that the second clock period is at least 100 times the period difference between the first clock period and the second clock period.

[0109] In some embodiments, the integrated circuit die includes one or more digital circuit blocks configured to output a first reference signal and a second reference signal, and a time-to-digital converter configured to output a count value indicating the time difference between a first event and a second event. The time-to-digital converter includes a first oscillator configured to output a first clock signal based on the first reference signal in response to a first event, and a second oscillator configured to output a second clock signal based on the second reference signal in response to a second event. The first event occurs before the second event. The first clock signal has a first clock period, and the second clock signal has a second clock period, with the first clock period being greater than the second clock period. The time-to-digital converter further includes a phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is lagging behind the phase of the first clock signal.

[0110] In some embodiments, the first oscillator is a first ring oscillator configured to set a first configurable delay of the first oscillator, by including one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and the second oscillator is a second ring oscillator configured to set a second configurable delay of the second oscillator, by including one or more of a second load capacitance, a second load resistance, or a second phase interpolator between two consecutive inverting stages of the second oscillator. In some embodiments, the clock counter includes a clock gating circuit configured to generate a count clock signal based on a first clock signal and a detection signal, and a counter configured to generate a count value based on the count clock signal.

[0111] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art will understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0112] The time-to-digital conversion device, the method for generating a count value indicating the time difference between a first event and a second event, and the integrated circuit die in embodiments of the present invention can be applied to integrated circuits for high-performance computing (HPC) equipment. [Explanation of Symbols]

[0113] 100A, 100B: Block Diagram 110: Digital Logic 120, 140, 200: Time-to-Digital Converter 130, VTC: Voltage-Time Converter 210, 1100A: First oscillator 220, 1100B: Second oscillator 230, 500: Phase detector 240: Clock counter 250, 600: Clock gating circuit 260: Counter 300: Process flow time - executed by a digital conversion device 310~355: Stage 400: Oscillator 412: First NAND gate 414, 415, 416, 418, 522, 524, 532, 534, 542, 632, 634, 642, 912, 914, 1012, 1104A, 1104B, 1106A, 1106B, 1110: Inverter 417: Second NAND gate 420: Buffer circuit 430, 900, 1000: Delay circuits 432: Drive stage 434, 1102A, 1102B: NAND gates 442, LOAD: First input terminal 444: Second input terminal 446: Output terminal 452: First p-type transistor 454: Second p-type transistor 456: First n-type transistor 458: Second n-type transistor 462: Terminal for VDD connection 466: Terminal for VSS or ground connection 500: Phase detector 510: Type D flip-flop 610: First D-type flip-flop 620: Second D-type flip-flop 620A, 620B: Type D flip-flops 644: NAND gate 646: AND Gate 650A, 650B: Modified versions of the clock gating circuit 700: Counter 710: N-bit adder 720: N-bit clocked buffer 801~808, 801A~808A, 801B~808B: Chart 812, 822, 824, 832, 834, 836, 842, 844, 850: Waveform 860:Curve 862, 864: Data points 922, 924, 1014, Cp: Capacitor 932: Phase Interpolator 1016, 1016A, 1016B: Adjustable resistors 1018: Output node 1022, 1042: First terminal 1024, 1044: Second terminal 1026: P-type transistor 1028: N-type transistor 1030: Bias Generator 1046: The First Resistance 1048: The Second Resistance 1050: Switch 1200: Method 1210~1240: Block CLK1, CLK2, CK_M: Clock signals STOP_R: Output signal / signal TDC_OUT: Output signal / count value CLK_REF: Reference clock signal VSENSE: Voltage signal CLK_delay: Delay signal START1: First reference signal START2: Second reference signal SLOW1: First slowdown control signal SLOW2: Second slowdown control signal CKA_M: First clock signal CKB_M: Second clock signal HITB: Detection signal START: Reference signal EN: Enable signal CKC: Counter Clock Signal LOAD: Input terminal 1 SLOW: Slowdown control signal / SLOW: Inverted signal of the slowdown control signal CK_F: Feedback clock signal CK_OUT: Buffer clock signal VDD: First power supply voltage / power supply voltage RST: Reset signal D, CLK, Q, CD: Terminals CKA_OUT: First buffer clock signal STOP: Buffer output signal / signal STOP_B: Output signal Ain: First N-bit input port Bin: Second N-bit input port Cin: Carry input terminal S, Q: N-bit output port D: N-bit input port 0001b: Binary value Tsense: Time difference ΔT: period difference Part A, Part B: Part t0~t4: time PI_IN0, PI_IN1, PI_OUT: Signals TD1: First delay TD2: Second delay Vbiasp: First bias voltage Vbiasn: Second bias voltage

Claims

1. A first oscillator configured to output a first clock signal having a first clock period in response to a first event, A second oscillator configured to output a second clock signal having a second clock period in response to a second event, wherein the first event occurs before the second event, and the first clock period is greater than the second clock period. A phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal, A clock counter configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal is delayed compared to the phase of the first clock signal, wherein the count value indicates the time difference between the first event and the second event, A time-to-digital conversion device, including a time-to-digital converter.

2. The first event corresponds to the first reference signal changing from a first logic state to a second logic state, The second event corresponds to the second reference signal changing from the first logic state to the second logic state. The time-to-digital conversion device according to claim 1.

3. The first oscillator is configured to be deactivated when the first reference signal is in a first logic state and to be activated when the first reference signal is in a second logic state. The second oscillator is configured to be deactivated based on the second reference signal being in the first logic state, and to be activated based on the second reference signal being in the second logic state. The time-to-digital conversion device according to claim 2.

4. The first oscillator is a first ring oscillator configured to include one or more of a first load capacitance, a first load resistor, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and to set a first configurable delay of the first oscillator. The second oscillator is a second ring oscillator configured to include one or more of a second load capacitance, a second load resistor, or a second phase interpolator between two consecutive inverting stages of the second oscillator, thereby setting a second configurable delay of the second oscillator. The time-to-digital conversion device according to claim 1.

5. The first load capacity or the second load capacity is based on a NAND gate or a NOR gate. The time-to-digital conversion device according to claim 4.

6. The phase detector includes a D-type flip-flop, The D terminal of the D-type flip-flop is configured to receive a first signal corresponding to the first clock signal. The clock terminal of the D-type flip-flop is configured to receive a second signal corresponding to the inversion of the second clock signal. The Q terminal of the D-type flip-flop is configured to output a third signal corresponding to the detection signal. The time-to-digital conversion device according to claim 1.

7. The aforementioned clock counter is A clock gating circuit configured to generate a count clock signal based on the first clock signal and the detection signal, A counter configured to generate the count value based on the count clock signal, A time-to-digital conversion device according to claim 1, including the above.

8. The clock gating circuit is based on a D-type flip-flop or a D-type latch and has a NAND gate or an AND gate. The time-to-digital conversion device according to claim 7.

9. The aforementioned counter is an N-bit counter, N is in the range of 6 to 12. The time-to-digital conversion device according to claim 7.

10. The second clock period is at least 100 times the period difference between the first clock period and the second clock period. The time-to-digital conversion device according to claim 1.

11. A method for generating a count value indicating the time difference between a first event and a second event, The first oscillator outputs a first clock signal having a first clock period in response to the first event, The second oscillator outputs a second clock signal having a second clock period in response to the second event, wherein the first event occurs before the second event, and the first clock period is greater than the second clock period. The phase detector generates a detection signal based on the phase relationship between the first clock signal and the second clock signal, The clock counter generates the count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal is delayed compared to the phase of the first clock signal, Methods that include...

12. The first oscillator receives a first reference signal, the first event being a change in the first reference signal from a first logical state to a second logical state, and the receiving of the signal. The second oscillator receives a second reference signal, the second event being a change in the second reference signal from the first logical state to the second logical state, and the receiving is as follows: The method according to claim 11, further comprising:

13. Deactivating the first oscillator based on the fact that the first reference signal is in the first logic state, Activating the first oscillator based on the fact that the first reference signal is in the second logic state, Deactivating the second oscillator based on the fact that the second reference signal is in the first logic state, Or, Activating the second oscillator based on the fact that the second reference signal is in the second logic state, The method according to claim 12, further comprising:

14. The first configurable delay of the first oscillator is set based on configuring one or more of the following between two consecutive inverting stages of the first oscillator: a first load capacitance, a first load resistance, or a first phase interpolator. The second configurable delay of the second oscillator is set based on configuring one or more of the following between two consecutive inverting stages of the first oscillator: a second load capacitance, a second load resistance, or a second phase interpolator. It further includes, The first oscillator is a first ring oscillator, and the second oscillator is a second ring oscillator. The method according to claim 11.

15. The clock counter generates the count value, The clock gating circuit of the clock counter generates a count clock signal based on the first clock signal and the detection signal, The counter generates the count value based on the count clock signal, The method according to claim 11, including the method described in claim 11.

16. The aforementioned count value is an N-bit unsigned integer, N is in the range of 6 to 12. The method according to claim 15.

17. The first oscillator, the second oscillator, or both thereof are set such that the second clock period is at least 100 times the period difference between the first clock period and the second clock period. The method according to claim 11, further comprising:

18. One or more digital circuit blocks configured to output a first reference signal and a second reference signal, A time-to-digital converter configured to output a count value indicating the time difference between a first event and a second event, The time-to-digital conversion device includes, A first oscillator configured to output a first clock signal having a first clock period in response to a first event based on the first reference signal, A second oscillator configured to output a second clock signal having a second clock period in response to a second event based on the second reference signal, wherein the first event occurs before the second event, and the first clock period is greater than the second clock period; A phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal, A clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal is delayed compared to the phase of the first clock signal, An integrated circuit die, including

19. The first oscillator is a first ring oscillator configured to include one or more of a first load capacitance, a first load resistor, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and to set a first configurable delay of the first oscillator. The second oscillator is a second ring oscillator configured to include one or more of a second load capacitance, a second load resistor, or a second phase interpolator between two consecutive inverting stages of the second oscillator, thereby setting a second configurable delay of the second oscillator. The integrated circuit die according to claim 18.

20. The aforementioned clock counter is A clock gating circuit configured to generate a count clock signal based on the first clock signal and the detection signal, A counter configured to generate the count value based on the count clock signal, The integrated circuit die according to claim 18, including the following:

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