Phase-locked loop and electronic equipment
By introducing a sampling phase detection module and a clock feedforward cancellation module into the phase-locked loop (PLL), and injecting reference and feedback disturbance compensation signals with opposite phases, the problem of reference spurious signals in the PLL is solved. This achieves spurious signal suppression without increasing area or reducing bandwidth, thereby improving the performance of the communication system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-15
Smart Images
Figure CN122052784A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and more particularly to a phase-locked loop and an electronic device. Background Technology
[0002] Phase-locked loops (PLLs) have been widely used in many technical fields such as filtering, frequency synthesis, modulation and demodulation, and signal detection, and have become an indispensable basic component in analog and digital communication systems.
[0003] In a phase-locked loop (PLL), reference spurious signals primarily originate from the periodic disturbance of the control voltage signal by the reference clock signal. Specifically, during the sampling process of the phase detection module in the PLL, the control voltage signal is periodically interfered with, resulting in reference spurious signals. Reference spurious signals typically cause severe crosstalk in the transmit / receive link, especially in 5G / 6G high-frequency systems, directly impacting communication sensitivity and bit error rate. Summary of the Invention
[0004] This invention provides a phase-locked loop and an electronic device that suppresses reference spurious signals at the output node of the phase-locked loop.
[0005] According to a first aspect of the present invention, a phase-locked loop is provided, comprising: The sampling phase detection module has a first input terminal that receives a reference clock signal, a second input terminal that receives a feedback clock signal, and an output terminal that is coupled to an output node and outputs an output clock signal to the output node. A clock feedforward cancellation module is provided, wherein its two inputs receive a reference feedforward clock signal and a feedback feedforward clock signal, respectively, and its output is coupled to the output node. The clock feedforward cancellation module is used to: based on the reference feedforward clock signal and the feedback feedforward clock signal, output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node, respectively, to form a target output clock signal at the output node. The reference disturbance compensation signal is configured to be out of phase and have the same amplitude as the disturbance component coupled to the output node by the reference clock signal, and the feedback disturbance compensation signal is configured to be out of phase and have the same amplitude as the disturbance component coupled to the output node by the feedback clock signal.
[0006] Optionally, the sampling phase detection module includes: a slanted sampling submodule, a first switch, a first node, a first capacitor, a first transmission gate, and a second capacitor; The input terminal of the beveled sampling submodule receives the reference clock signal, and the output terminal of the beveled sampling submodule is coupled to the first terminal of the first switch. The control terminal of the first switch receives the feedback clock signal, and the second terminal of the first switch outputs a first sampling output signal to the first node. The first node is also coupled to the first terminal of the first capacitor and the first terminal of the first transmission gate, respectively. The second terminal of the first capacitor is grounded. The first control terminal and the second control terminal of the first transmission gate receive the first sampling clock signal and the second sampling clock signal, respectively. The first sampling clock signal and the second sampling clock signal are a pair of clock signals that do not overlap. The output node is coupled to the second terminal of the first transmission gate and the first terminal of the second capacitor, respectively. The second terminal of the second capacitor is grounded. When the feedback clock signal is high, the first switch is turned on, and when both the first sampling clock signal and the second sampling clock signal are low, the first transmission gate is turned off. The feedback clock signal is characterized by the following: after the feedback clock signal drops from high to low, the first sampling clock signal is instantaneously high, and the first transmission gate is instantaneously turned on.
[0007] Optionally, the clock feedforward cancellation module includes: The first feedforward submodule includes at least: a second transmission gate, the second transmission gate having the same size as the first transmission gate, a first terminal of the second transmission gate receiving a reference feedforward clock signal, a second terminal of the second transmission gate being coupled to the output node and outputting the reference disturbance compensation signal to the output node, wherein the reference feedforward clock signal and the reference clock signal are the same signal, and the first control terminal and the second control terminal of the second transmission gate receiving power supply voltage and ground voltage respectively; The second feedforward submodule includes at least: a third transmission gate, the size of which is 1 / 2 the size of the first transmission gate; a first terminal of the third transmission gate receives a feedback feedforward clock signal; a second terminal of the third transmission gate is coupled to the output node and outputs the feedback disturbance compensation signal to the output node; wherein the feedback feedforward clock signal and the feedback clock signal are the same signal; and a first control terminal and a second control terminal of the third transmission gate receive power supply voltage and ground voltage, respectively.
[0008] Optionally, the first feedforward submodule further includes: a first converter, the input of which receives the reference feedforward clock signal, and the output of which is coupled to the first end of the second transmission gate.
[0009] Optionally, the second feedforward submodule further includes: a second pulse changer, the input of which receives the feedback feedforward clock signal, and the output of which is coupled to the first end of the third transmission gate.
[0010] Optionally, the sampling phase detection module further includes: a first MOS transistor, the control terminal of the first MOS transistor receiving the reference clock signal, the first terminal of the first MOS transistor being coupled to the first node, and the second terminal of the first MOS transistor being grounded.
[0011] Optionally, it further includes: a second-level sampling clock generation submodule, wherein the input terminal of the second-level sampling clock generation submodule receives the feedback clock signal, the first output terminal and the second output terminal of the second-level sampling clock generation submodule are respectively coupled to the first control terminal and the second control terminal of the first transmission gate, the first output terminal of the second-level sampling clock generation submodule outputs the first sampling clock signal to the first control terminal of the first transmission gate, and the second output terminal of the second-level sampling clock generation submodule outputs the second sampling clock signal to the second control terminal of the first transmission gate.
[0012] Optionally, the second-stage sampling clock generation submodule includes: a first inverter, a third buffer, a NAND gate, and a second inverter; The input terminal of the first inverter and the first input terminal of the NAND gate both receive the feedback clock signal. The output terminal of the first inverter is coupled to the input terminal of the third buffer. The output terminal of the third buffer is coupled to the second input terminal of the NAND gate. The output terminal of the NAND gate is coupled to the input terminal of the second inverter and the first control terminal of the first transmission gate. The output terminal of the NAND gate outputs a first sampling clock signal to the first control terminal of the first transmission gate. The output terminal of the second inverter is coupled to the second control terminal of the first transmission gate. The output terminal of the second inverter outputs a second sampling clock signal to the second control terminal of the first transmission gate.
[0013] Optional, also includes: A first resistor, a first end of which is coupled to the output node, and a second end of which receives the control voltage signal; The third capacitor has its first terminal coupled to the second terminal of the first resistor, and its second terminal grounded.
[0014] According to a second aspect of the present invention, the present invention also provides an electronic device including a phase-locked loop as described above.
[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the phase-locked loop and electronic device of the present invention, a reference clock signal and a feedback clock signal are received respectively through the first input terminal and the second input terminal of the sampling phase detection module, and the output terminal of the sampling phase detection module is coupled to the output node; the two input terminals of the clock feedforward cancellation module receive the reference feedforward clock signal and the feedback feedforward clock signal respectively, and the output terminal of the clock feedforward cancellation module is coupled to the output node. The clock feedforward cancellation module is used to: output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node respectively, so as to form a target output clock signal at the output node. The reference disturbance compensation signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node by the reference clock signal, and the feedback feedforward clock signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node by the feedback clock signal. Therefore, by injecting a reference disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node with the reference clock signal, and injecting a feedback disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node with the feedback clock signal, the reference spurious caused by the sampling phase-locked loop during the sampling process is canceled out. Thus, the reference spurious of the phase-locked loop is suppressed without increasing the area of the phase-locked loop or affecting the bandwidth of the phase-locked loop. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the phase-locked loop structure according to an embodiment of the present invention. Figure 1 ; Figure 2 This is a schematic diagram of the sampling phase detection module according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the phase-locked loop structure according to an embodiment of the present invention. Figure 2 ; Figure 4 This is a schematic diagram of the phase-locked loop structure according to an embodiment of the present invention. Figure 3 ; Figure 5 This is a schematic diagram of the phase-locked loop structure according to an embodiment of the present invention. Figure 4 ; Figure 6 This is a schematic diagram of the structure of the second-level sampling clock generation submodule according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the phase-locked loop structure according to an embodiment of the present invention. Figure 5 ; Figure 8 This is a timing diagram of the relevant signals of a phase-locked loop according to an embodiment of the present invention. Detailed Implementation
[0018] As described in the background section, the present invention aims to solve the technical problem of suppressing reference spurious signals in phase-locked loops.
[0019] In existing technologies, low-bandwidth filters are typically used to filter out reference spurious signals generated during the sampling phase detection module's operation. However, this method increases the area of the phase-locked loop (PLL) and reduces its bandwidth.
[0020] In view of this, the present invention proposes a phase-locked loop (PLL). A reference clock signal is received at the first input of a sampling phase detection module, and a feedback clock signal is received at the second input of the sampling phase detection module. The output of the sampling phase detection module is coupled to an output node and outputs an output clock signal to the output node. A clock feedforward cancellation module receives a reference feedforward clock signal and a feedback feedforward clock signal at its two inputs, respectively. The output of the clock feedforward cancellation module is coupled to the output node. The clock feedforward cancellation module is used to: based on the reference feedforward clock signal and the feedback feedforward clock signal, output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node, respectively, to form a target output clock signal at the output node. The reference disturbance compensation signal is configured to have the same phase and the same amplitude as the disturbance component coupled to the output node by the reference clock signal, and the feedback disturbance compensation signal is configured to have the same phase and the same amplitude as the disturbance component coupled to the output node by the feedback clock signal. Therefore, by injecting a reference disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node with the reference clock signal, and injecting a feedback disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node with the feedback clock signal, the reference spurious caused by the sampling phase-locked loop during the sampling process is canceled out. Thus, the reference spurious at the output node of the phase-locked loop is suppressed without increasing the area of the phase-locked loop or affecting the bandwidth of the phase-locked loop.
[0021] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0023] Please refer to Figure 1 An embodiment of the present invention provides a phase-locked loop, which may include a sampling phase detection module 100 and a clock feedforward cancellation module 200.
[0024] The first input terminal of the sampling phase detection module 100 receives the reference clock signal CLKDTCREF, the second input terminal of the sampling phase detection module 100 receives the feedback clock signal CLKDTCFB, and the output terminal of the sampling phase detection module 100 is coupled to the output node VS2 and outputs the output clock signal to the output node VS2.
[0025] The clock feedforward cancellation module 200 receives a reference feedforward clock signal CLKDTCRFP and a feedback feedforward clock signal CLKDTCFFP at its two inputs, respectively. The output of the clock feedforward cancellation module 200 is coupled to the output node VS2. The clock feedforward cancellation module 200 is used to: output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node VS2 based on the reference feedforward clock signal CLKDTCRFP and the feedback feedforward clock signal CLKDTCFFP, respectively, to form a target output clock signal at the output node. The reference disturbance compensation signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node VS2 by the reference clock signal CLKDTCRFP. The feedback disturbance compensation signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node VS2 by the feedback clock signal CLKDTCFB.
[0026] As can be seen, this embodiment injects a reference disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node VS2 with the reference clock signal CLKDTCREF, and injects a feedback disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node VS2 with the feedback clock signal CLKDTCFB, thereby canceling the reference spurious caused by the sampling phase detection module 100 during the sampling process. Thus, without increasing the area of the phase-locked loop and without reducing the bandwidth of the phase-locked loop, the reference spurious at the output node VS2 of the phase-locked loop is suppressed.
[0027] For one specific implementation method, please refer to Figure 2 The sampling phase detection module 100 may include: a slanted sampling submodule 101, a first switch S1, a first node VS1, a first capacitor CS1, a first transmission gate 102, and a second capacitor CS2.
[0028] The input terminal of the beveled sampling submodule 101 receives the reference clock signal CLKDTCREF. The output terminal of the beveled sampling submodule 101 is coupled to the first terminal of the first switch S1. The control terminal of the first switch S1 receives the feedback clock signal CLKDTCFB. The second terminal of the first switch S1 outputs the first sampling output signal to the first node VS1. The first node VS1 is also coupled to the first terminal of the first capacitor CS1 and the first terminal of the first transmission gate 102. The second terminal of the first capacitor CS1 is grounded. The first control terminal and the second control terminal of the first transmission gate 102 receive the first sampling clock signal CLKS2B and the second sampling clock signal CLKS2, respectively. CLKS2B is the second sampling clock signal. CLKS2 is a pair of clock signals that are non-overlapping and mutually exclusive. The output node VS2 is coupled to the second terminal of the first transmission gate 102 and the first terminal of the second capacitor CS2, respectively. The second terminal of the second capacitor CS2 is grounded. When the feedback clock signal CLKDTCFB is high, the first switch S1 is turned on, and both the first sampling clock signal CLKS2B and the second sampling clock signal CLKS2 are low, and the first transmission gate 102 is turned off. The feedback clock signal CLKDTCFB is characterized by the following: after the feedback clock signal drops from high to low, the first sampling clock signal CLKS2B is momentarily high, and the first transmission gate 102 is momentarily turned on.
[0029] In this embodiment, please continue to refer to Figure 2 The sampling phase detection module 100 may further include: a first MOS transistor M1, the control terminal of the first MOS transistor M1 receiving a reference clock signal CLKDTCREF, the first terminal of the first MOS transistor M1 being coupled to the first node VS1, and the second terminal of the first MOS transistor M1 being grounded.
[0030] In this embodiment, the sloping sampling submodule 101 is triggered at a certain edge of the reference clock signal and starts to generate a linearly rising first sampling output signal at the first node VS1. At this time, the first sampling output signal is characterized as a linearly rising ramp voltage. This first sampling output signal will be sampled in the window when the feedback clock signal is high. After the sampling is completed, the ramp voltage of the first sampling output signal is reset to the logic low level through the first MOS transistor M1.
[0031] For one specific implementation method, please refer to Figure 3 The clock feedforward cancellation module 200 may include a first feedforward submodule 210 and a second feedforward submodule 220.
[0032] The first feedforward submodule 210 may include at least: a second transmission gate 211, the second transmission gate 211 having the same size as the first transmission gate 102, the first terminal of the second transmission gate 211 receiving a reference feedforward clock signal CLKDTCRFP, the second terminal of the second transmission gate 211 being coupled to the output node VS2 and outputting a reference disturbance compensation signal to the output node VS2, wherein the reference feedforward clock signal CLKDTCRFP and the reference clock signal CLKDTCREF are the same signal, and the first control terminal and the second control terminal of the second transmission gate 211 receiving the power supply voltage VDD and the ground voltage, respectively.
[0033] The second feedforward submodule 220 may include at least: a third transmission gate 221, the size of which is half the size of the first transmission gate 102. The first terminal of the third transmission gate 221 receives the feedback feedforward clock signal CLKDTCFFP, and the second terminal of the third transmission gate 221 is coupled to the output node VS2 and outputs a feedback disturbance compensation signal to the output node VS2. The feedback feedforward clock signal CLKDTCFFP and the feedback clock signal CLKDTCFB are the same signal. The first control terminal and the second control terminal of the third transmission gate 221 receive the power supply voltage VDD and the ground voltage, respectively.
[0034] In this embodiment, since the size of the first transmission gate 102 is the same as the size of the second transmission gate 211, the parasitic capacitance value of the second transmission gate 211 is the same as the parasitic capacitance value of the first transmission gate 102. Since the size of the first transmission gate 102 is twice the size of the third transmission gate 221, the parasitic capacitance value of the third transmission gate 221 is half the parasitic capacitance value of the first transmission gate 102.
[0035] In this embodiment, the first feedforward submodule 210 receives a reference feedforward clock signal CLKDTCRFP, which is the same as the reference clock signal CLKDTCREF, and couples the reference feedforward clock signal CLKDTCRFP to the output node through a second transmission gate 211 of the same size as the first transmission gate 102. Therefore, the first feedforward submodule 210 couples the reference clock signal CLKDTCREF to the output node VS2 at a first preset ratio. The first preset ratio can be 0.9•VDD•Cds / CS2 to 1.1•VDD•Cds / CS2, where Cds is the parasitic capacitance value of the first transmission gate 102. It should be understood that the parasitic capacitance value of the second transmission gate 211 is also equal to the parasitic capacitance value Cds of the first transmission gate 102, and CS2 is the capacitance value of the second capacitor CS2. Thus, the first feedforward submodule 210 can inject a reference disturbance compensation signal into the output node VS2 that has the opposite phase and the same amplitude as the disturbance component of the reference clock signal CLKDTCRFP coupled to the output node VS2. The second feedforward submodule 220 receives a feedback feedforward clock signal CLKDTCFFP, which is the same as the feedback clock signal CLKDTCFB, and couples the feedback feedforward clock signal CLKDTCFFP to the output node VS2 through a second transmission gate 211, which is half the size of the first transmission gate 102. Therefore, the second feedforward submodule 220 couples the feedback clock signal CLKDTCFB to the output node VS2 at a second preset ratio. This second preset ratio can be 0.9•0.5•VDD•Cds / CS2 to 1.1•0.5•VDD•Cds / CS2, where 0.5•Cds represents the parasitic capacitance value of the third transmission gate 221. Thus, the second feedforward submodule 220 can inject a feedback disturbance compensation signal into the output node VS2 that has the opposite phase and the same amplitude as the disturbance component of the feedback clock signal CLKDTCFB coupled to the output node VS2. Therefore, the clock feedforward cancellation module 200 can eliminate the reference spurious signals generated by the sampling phase detector module 100 during the sampling process.
[0036] As an alternative implementation method, please refer to Figure 4 The first feedforward submodule 210 may further include: a first converter buffer1, the input of which receives a reference feedforward clock signal CLKDTCFFP, and the output of which is coupled to the first end of the second transmission gate 211.
[0037] In this embodiment, a controllable delay is introduced by cascading the first pulse changer Buffer1 to optimize the injection effect of the reference disturbance compensation signal.
[0038] Please refer to Figure 5The second feedforward submodule 220 may further include: a second converter Buffer2, the input of which receives the feedback feedforward clock signal CLKDTCRFP, and the output of which is coupled to the first end of the third transmission gate 221.
[0039] In this embodiment, a controllable delay is introduced through the second pulse changer Buffer2 to optimize the injection effect of the feedback disturbance compensation signal.
[0040] For one specific implementation method, please refer to Figure 6 The phase-locked loop may further include: a second-stage sampling clock generation submodule 300, the input terminal of which receives a feedback clock signal CLKDTCFB, the first and second output terminals of which are respectively coupled to the first and second control terminals of the first transmission gate 102, the first output terminal of which outputs a first sampling clock signal CLKS2B to the first control terminal of the first transmission gate 102, and the second output terminal of which outputs a second sampling clock signal CLKS2 to the second control terminal of the first transmission gate 102.
[0041] For one specific implementation method, please refer to Figure 6 The second-level sampling clock generation submodule 300 may include: a first inverter INV1, a third buffer Buffer3, a NAND gate NOT, and a second inverter INV1; The input of the first inverter INV1 and the first input of the NAND gate NOT both receive the feedback clock signal CLKDTCFB. The output of the first inverter INV1 is coupled to the input of the third buffer Buffer3. The output of the third buffer Buffer3 is coupled to the second input of the NAND gate NOT. The output of the NAND gate NOT is coupled to the input of the second inverter INV2 and the first control terminal of the first transmission gate 102. The output of the NAND gate NOT outputs the first sampling clock signal CLKS2B to the first control terminal of the first transmission gate 102. The output of the second inverter INV2 is coupled to the second control terminal of the first transmission gate 102. The output of the second inverter INV2 outputs the second sampling clock signal CLKS2 to the second control terminal of the first transmission gate 102.
[0042] For one specific implementation method, please refer to Figure 7 The voltage-controlled oscillation module includes: a first resistor R1 and a third capacitor C1.
[0043] The first end of the first resistor R1 is coupled to the output node VS2, and the second end of the first resistor R1 receives the control voltage signal Vctrl-p. The first terminal of the third capacitor C1 is coupled to the second terminal of the first resistor R1, and the second terminal of the third capacitor CS3 is grounded.
[0044] Please refer to Figure 8 A timing diagram of the relevant signals of a phase-locked loop according to an embodiment of the present invention; Figure 8 In the diagram, CLKDTCREF represents the reference clock signal; CLKDTCFB represents the feedback clock signal; VS1 represents the first sampled output signal; Feed From VS1 can be understood as the output clock signal output to output node VS2 after passing through the sampling phase detector module; the red line Feed From CLKDTCRFP can be understood as the reference disturbance compensation signal injected into output node VS2; Feed After CLKDTCRFP can be understood as the signal at output node VS2 after injecting the reference disturbance compensation signal; Feed From CLKDTCFFP can be understood as the feedback disturbance compensation signal injected into output node VS2; Feed After CLKDTCRFP & CLKDTCFFP can be understood as the target output clock signal at output node VS2 after injecting the reference disturbance compensation signal and the feedback disturbance compensation signal.
[0045] It can be seen that, in Figure 8At time t1: The falling edge of the reference clock signal CLKDTCREF triggers the slant sampling submodule 101 to sample, causing the voltage of the first sampled output signal at the first node VS1 to begin to rise linearly. At time t2: The feedback clock signal CLKDTCFB is high, the first switch S1 is turned on, and the instantaneous voltage at the first node VS1 is sampled to the first capacitor CS1. At time t3: The feedback clock signal CLKDTCFB falls to low, and the first transmission gate 102 is briefly turned on to transmit the sampled value at the first node VS1 to the output node VS2. During the time period t1-t3, the parasitic capacitance of the first transmission gate 102, affected by the rapid rise and reset action of the first sampled output signal at the first node VS1, will couple to the output node VS2 through the second capacitor CS2, generating periodic voltage disturbances (i.e., "reference spurious signals"). In this embodiment, a reference disturbance compensation signal, which is out of phase and has the same amplitude as the disturbance component coupled to the reference clock signal CLKDTCREF at the output node VS2, is input to the output node VS2 through the clock feedforward cancellation module 200 to cancel a portion of the reference spurious signals at the output node VS2. Then, a feedback disturbance compensation signal, which is out of phase and has the same amplitude as the disturbance component coupled to the feedback clock signal CLKDTCFB at the output node VS2, is injected into the output node VS2 through the clock feedforward cancellation module 200, further cancelling a portion of the reference spurious signals at the output node VS2. After injecting the reference disturbance compensation signal and the feedback disturbance compensation signal into the output node VS2, the reference spurious signals of the output clock signal at the output node VS2 are suppressed.
[0046] Accordingly, the present invention also provides an electronic device including the phase-locked loop as described above.
[0047] In summary, the embodiments of the present invention receive a reference clock signal CLKDTCREF and a feedback clock signal CLKDTCFB respectively through the first input terminal and the second input terminal of the sampling phase detection module 100. The output terminal of the sampling phase detection module 100 is coupled to the output node VS2. The two input terminals of the clock feedforward cancellation module 200 receive a reference feedforward clock signal CLKDTCREP and a feedback feedforward clock signal CLKDTCFFP respectively. The output terminal of the clock feedforward cancellation module 200 is coupled to the output node VS2. The clock feedforward cancellation module 200 is used to: output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node VS2 respectively, so as to form a target output clock signal at the output node VS2. The reference disturbance compensation signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node VS2 by the reference clock signal CLKDTCREF. The feedback compensation clock signal is configured to be opposite in phase and have the same amplitude as the disturbance component coupled to the output node VS2 by the feedback clock signal CLKDTCFB. Therefore, by injecting a reference disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node VS2 with the reference clock signal CLKDTCREF, and injecting a feedback disturbance compensation signal that is opposite in phase and has the same amplitude as the disturbance component coupled to the output node VS2 with the feedback clock signal CLKDTCFB, the reference spurious caused by the sampling phase detection module 100 during the sampling process is canceled out. Thus, the reference spurious at the output node VS2 of the phase-locked loop is suppressed without increasing the area of the phase-locked loop or affecting the bandwidth of the phase-locked loop.
[0048] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A phase-locked loop, characterized in that, include: The sampling phase detection module has a first input terminal that receives a reference clock signal, a second input terminal that receives a feedback clock signal, and an output terminal that is coupled to an output node and outputs an output clock signal to the output node. A clock feedforward cancellation module is provided, wherein its two inputs receive a reference feedforward clock signal and a feedback feedforward clock signal, respectively, and its output is coupled to the output node. The clock feedforward cancellation module is used to: based on the reference feedforward clock signal and the feedback feedforward clock signal, output a reference disturbance compensation signal and a feedback disturbance compensation signal to the output node, respectively, to form a target output clock signal at the output node. The reference disturbance compensation signal is configured to be out of phase and have the same amplitude as the disturbance component coupled to the output node by the reference clock signal, and the feedback disturbance compensation signal is configured to be out of phase and have the same amplitude as the disturbance component coupled to the output node by the feedback clock signal.
2. The phase-locked loop as described in claim 1, characterized in that, The sampling phase detection module includes: a slanted sampling submodule, a first switch, a first node, a first capacitor, a first transmission gate, and a second capacitor; The input terminal of the beveled sampling submodule receives the reference clock signal, and the output terminal of the beveled sampling submodule is coupled to the first terminal of the first switch. The control terminal of the first switch receives the feedback clock signal, and the second terminal of the first switch outputs a first sampling output signal to the first node. The first node is also coupled to the first terminal of the first capacitor and the first terminal of the first transmission gate, respectively. The second terminal of the first capacitor is grounded. The first control terminal and the second control terminal of the first transmission gate receive the first sampling clock signal and the second sampling clock signal, respectively. The first sampling clock signal and the second sampling clock signal are a pair of clock signals that do not overlap. The output node is coupled to the second terminal of the first transmission gate and the first terminal of the second capacitor, respectively. The second terminal of the second capacitor is grounded. When the feedback clock signal is high, the first switch is turned on, and when both the first sampling clock signal and the second sampling clock signal are low, the first transmission gate is turned off. The feedback clock signal is characterized by the following: after the feedback clock signal drops from high to low, the first sampling clock signal is instantaneously high, and the first transmission gate is instantaneously turned on.
3. The phase-locked loop as described in claim 2, characterized in that, The clock feedforward cancellation module includes: The first feedforward submodule includes at least: a second transmission gate, the second transmission gate having the same size as the first transmission gate, a first terminal of the second transmission gate receiving a reference feedforward clock signal, a second terminal of the second transmission gate being coupled to the output node and outputting the reference disturbance compensation signal to the output node, wherein the reference feedforward clock signal and the reference clock signal are the same signal, and the first control terminal and the second control terminal of the second transmission gate receiving power supply voltage and ground voltage respectively; The second feedforward submodule includes at least: a third transmission gate, the size of which is 1 / 2 the size of the first transmission gate; a first terminal of the third transmission gate receives a feedback feedforward clock signal; a second terminal of the third transmission gate is coupled to the output node and outputs the feedback disturbance compensation signal to the output node; wherein the feedback feedforward clock signal and the feedback clock signal are the same signal; and a first control terminal and a second control terminal of the third transmission gate receive power supply voltage and ground voltage, respectively.
4. The phase-locked loop as described in claim 3, characterized in that, The first feedforward submodule further includes: a first converter, the input of which receives the reference feedforward clock signal, and the output of which is coupled to the first end of the second transmission gate.
5. The phase-locked loop as described in claim 3, characterized in that, The second feedforward submodule further includes: a second pulse changer, the input of which receives the feedback feedforward clock signal, and the output of which is coupled to the first end of the third transmission gate.
6. The phase-locked loop as described in claim 2, characterized in that, The sampling phase detection module further includes: a first MOS transistor, the control terminal of the first MOS transistor receiving the reference clock signal, the first terminal of the first MOS transistor being coupled to the first node, and the second terminal of the first MOS transistor being grounded.
7. The phase-locked loop as described in claim 2, characterized in that, Also includes: The second-level sampling clock generation submodule receives the feedback clock signal at its input terminal. The first and second output terminals of the second-level sampling clock generation submodule are respectively coupled to the first control terminal and the second control terminal of the first transmission gate. The first output terminal of the second-level sampling clock generation submodule outputs the first sampling clock signal to the first control terminal of the first transmission gate, and the second output terminal of the second-level sampling clock generation submodule outputs the second sampling clock signal to the second control terminal of the first transmission gate.
8. The phase-locked loop as described in claim 7, characterized in that, The second-stage sampling clock generation submodule includes: a first inverter, a third buffer, a NAND gate, and a second inverter; The input terminal of the first inverter and the first input terminal of the NAND gate both receive the feedback clock signal. The output terminal of the first inverter is coupled to the input terminal of the third buffer. The output terminal of the third buffer is coupled to the second input terminal of the NAND gate. The output terminal of the NAND gate is coupled to the input terminal of the second inverter and the first control terminal of the first transmission gate. The output terminal of the NAND gate outputs a first sampling clock signal to the first control terminal of the first transmission gate. The output terminal of the second inverter is coupled to the second control terminal of the first transmission gate. The output terminal of the second inverter outputs a second sampling clock signal to the second control terminal of the first transmission gate.
9. The phase-locked loop as described in claim 8, characterized in that, Also includes: A first resistor, a first end of which is coupled to the output node, and a second end of which receives the control voltage signal; The third capacitor has its first terminal coupled to the second terminal of the first resistor, and its second terminal grounded.
10. An electronic device, characterized in that, Including the phase-locked loop as described in any one of claims 1-9.