Signal processing method and device, clock data recovery circuit and electronic equipment

Abstract

The invention discloses a signal processing method and device, a clock data recovery circuit and electronic equipment. The signal processing method comprises the following steps: acquiring signal data; determining first phase information of the signal data based on the signal data and the signal transmission mode; when it is determined that the signal data is in the phase non-offset state, changing the phase information of the signal data into a phase offset state; when the signal data is in the phase deviation state, controlling the clock data recovery circuit to be in an open loop, and adjusting the signal data to move a first preset phase; controlling a closed loop of the clock data recovery circuit, continuously adjusting the signal data to move a second preset phase, and determining second phase information of the adjusted signal data; based on the first phase information and the second phase information, the signal data is adjusted to move by a third preset phase, and the third preset phase is opposite to the first preset phase and the second preset phase in moving direction. The clock data recovery circuit has the technical effect of improving the processing efficiency of the clock data recovery circuit.

Description

Technical Field

[0001] This application relates to the field of clock data recovery technology, and more particularly to a signal processing method, apparatus, clock data recovery circuit, and electronic device. Background Technology

[0002] In Passive Optical Network (PON) and high-speed serial link (SerDes) systems, the receiver needs to perform clock and data recovery (CDR) on burst multi-rate data signals from the network. However, with the continuous increase in data rates and the need for short burst packet switching in service scenarios, the lock-in time of the clock and data recovery circuit is limited by loop bandwidth, phase detector metastability, and digital decision delay, making it difficult to meet the rapid switching requirements of current technological developments. Therefore, the problem of excessively long lock-in time in the clock and data recovery process deserves attention. Summary of the Invention

[0003] In view of this, embodiments of this application provide a signal processing method, apparatus, clock data recovery circuit, and electronic device to improve the processing efficiency of the clock data recovery circuit. In a first aspect, a signal processing method is provided, applied to a clock data recovery circuit, comprising: acquiring signal data; determining first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information including: a phase offset state or a phase-free state, the phase offset state including: phase delay or phase advance; when the signal data is determined to be in a phase-free state, changing the phase information of the signal data to a phase offset state; when the signal data is in a phase offset state, controlling the clock data recovery circuit to open-loop, adjusting the signal data to move a first preset phase; controlling the clock data recovery circuit to close-loop, continuing to adjust the signal data to move a second preset phase, determining the second phase information of the adjusted signal data; and adjusting the signal data to move a third preset phase based on the first and second phase information, the third preset phase moving in the opposite direction to the first and second preset phases, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0004] Optionally, when the signal data is determined to be in burst mode, determining the first phase information of the signal data based on the signal data further includes: waiting for a first preset number of cycles, and when the signal data reaches the first preset number of cycles, determining the first phase information based on the signal data.

[0005] Optionally, determining the first phase information of the signal data based on the signal data further includes: determining the first phase information of the signal data within a second preset number of cycles of the signal data; and determining the signal data as having no phase offset state when each cycle within the second preset number of cycles does not satisfy the phase offset state.

[0006] Optionally, adjusting the signal data to move a first preset phase includes: adjusting the signal data to move a first preset phase based on a third preset period; adjusting the signal data to move a second preset phase includes: adjusting the signal data to move a second preset phase based on a fourth preset number of periods.

[0007] Optionally, based on the first phase information and the second phase information, the signal data is adjusted to move to a third preset phase, including: when the second phase information is opposite to the first phase information, the signal data is adjusted to move to a third preset phase.

[0008] Optionally, the phase value of the second preset phase is determined based on the loop delay and phase gain of the clock data recovery circuit.

[0009] Optionally, based on the signal data and the signal transmission mode, the first phase information of the signal data is determined, including: based on the preamble in the signal data, determining the transmission mode of the signal data, the transmission mode including: burst mode and continuous mode; when the signal data is determined to be in burst mode, the first phase information of the signal data is determined.

[0010] In a second aspect, a signal processing apparatus is provided, comprising: an acquisition unit for acquiring signal data; a first determination unit for determining first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information including a phase offset state or a phase-free state, the phase offset state including a phase delay or a phase advance; a first adjustment unit for adjusting the signal data to move a first preset phase when the first determination unit determines that the signal data is in a phase-free state, thereby changing the phase information of the signal data to a phase offset state; a second adjustment unit for adjusting the signal data to move a second preset phase when the first determination unit determines that the signal data is in a phase offset state; the second determination unit for determining second phase information of the adjusted signal data, wherein the acquisition timing of the second phase information is later than that of the first phase information; and a third adjustment unit for adjusting the signal data to move a third preset phase based on the first and second phase information, wherein the movement direction of the third preset phase is opposite to that of the first and second preset phases, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0011] Thirdly, a clock data recovery circuit is provided, comprising: a phase detection circuit, a state machine, and a digital filter; the phase detection circuit is used to acquire signal data and determine first phase information of the signal data based on the signal data and the signal transmission mode, the first phase information including: a phase offset state or a phase-free state, the phase offset state including: phase delay or phase advance; the state machine is used to change the phase information of the signal data to a phase offset state when the phase detection circuit determines that the signal data is in a phase-free state; it is also used to control a phase interpolator through the digital filter to adjust the signal data to move a first preset phase when the phase detection circuit determines that the signal data is in a phase offset state; it is also used to control the clock data recovery circuit to close the loop and continue to adjust the signal data to move a second preset phase through the phase interpolator through the digital filter, and determine the second phase information of the adjusted signal data; and it is used to adjust the signal data to move a third preset phase through the digital filter based on the first phase information and the second phase information, the third preset phase moving in the opposite direction to the first preset phase and the second preset phase, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0012] Fourthly, an electronic device is provided, comprising: the clock data recovery circuit provided in the third aspect above. Attached Figure Description

[0013] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below: Figure 1 A schematic diagram of the circuit structure of a clock data recovery circuit provided in some embodiments of this application is shown; Figure 2 A schematic flowchart of a signal processing method provided in some embodiments of this application is shown; Figure 3 This illustration shows a schematic diagram of the relationship between a period and a unit time interval provided in some embodiments of this application; Figure 4 A flowchart illustrating another signal processing method provided in some embodiments of this application is shown; Figure 5 A schematic diagram of the structure of a signal processing apparatus provided in some embodiments of this application is shown. Detailed Implementation

[0014] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0015] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0016] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0017] Clock data recovery circuits are a crucial component of high-speed serial link systems, commonly used for clock and data recovery in receivers. In passive optical communication networks, to accommodate multiple users, data transmission typically employs time-division multiplexing (TDM) and wavelength-division multiplexing (WDM). In both scenarios, the data received by the receiver is broken down into multiple short data packets, each containing a preamble, valid data, and a stop symbol. The rates and phases of these different data packets may vary; therefore, the clock data recovery circuit must re-lock the data phase upon each received data transmission. In modern passive optical networks and high-speed serial links, the receiver must precisely align the received serial signal with the local reference clock via a clock data recovery loop to achieve reliable sampling. Clock data recovery circuits employ a closed-loop feedback structure consisting of a phase detector, loop filter, and phase interpolator to gradually correct phase deviations. However, due to limitations in loop bandwidth caused by jitter suppression and stability requirements, they struggle to respond quickly to large phase errors. The phase detector is prone to entering a metastable state with uncertain decisions at critical zero-crossing points. Furthermore, the digital processing logic (such as FPGA or ASIC) exhibits a significant delay between the phase detection result's decision and the phase interpolator's drive. This means that when rapid switching of short data packets with multiple burst rates is required, the clock data recovery process often cannot complete phase locking within a very short preamble window, thus affecting the overall communication system's error rate performance and service continuity. On one hand, in the clock data recovery circuit, when the phase detector samples near the zero-crossing point of the signal data, the input signal and the sampling clock are extremely close to zero crossover. The phase detector cannot reliably distinguish between "advanced" and "delayed" states, resulting in an uncertain period where it outputs a jitter decision or no decision at all. At this point, the loop cannot continue closed-loop fine-tuning or enter normal locking, causing the locking process to be delayed or stalled. On the other hand, the loop bandwidth of the clock data recovery circuit determines its response speed to phase error changes. The narrower the bandwidth, the stronger the attenuation of high-frequency (rapidly changing) phase error signals by the loop filter, allowing only very slow offset components to pass. This means that each phase adjustment can only be performed in very small steps and requires multiple feedback → filtering → correction cycles to gradually compress the large initial phase deviation to zero. At each step, the phase interpolator can only be driven after the filter smooths the error signal. The entire process often takes tens to hundreds of clock cycles, naturally resulting in a long lock-in time. Therefore, when a burst packet causes a large phase deviation, the "slow response" and "multiple iterations" caused by the narrow-band loop filter lengthen the total time from the start of clock data recovery to final precise alignment. Therefore, this application provides a signal processing method, apparatus, clock data recovery circuit, and electronic device that improves the processing efficiency of the clock data recovery circuit by setting a state machine to take over the clock data recovery loop after the burst mode of signal transmission begins and adjusting the local clock phase shift.

[0018] The following description is in conjunction with the accompanying drawings: Figure 1 A schematic diagram of the circuit structure of a clock data recovery circuit provided in some embodiments of this application is shown. The clock data recovery circuit 100 includes: a phase detection circuit 110, a state machine 120, and a digital filter 130. The phase detection circuit 110 can determine the phase difference between the zero-crossing point of the signal data from the receiver front-end 20 and the current sampling clock, and output the phase state information of the signal data to the state machine 120. The state machine 120 can control the gain state of the digital filter 130 according to the decision result of the phase detection circuit 110 and the preset periodic logic, thereby adjusting the phase of the local clock and realizing the loop locking and releasing of the clock data recovery circuit. The digital filter 130 can generate a voltage to drive the phase interpolator 30 based on the phase adjustment command of the state machine 120, and the output voltage is directly used as the control input of the phase interpolator 30.

[0019] Figure 2 A schematic flowchart of a signal processing method provided in some embodiments of this application is shown. This signal processing method is applied to a clock data recovery circuit and includes: S210: Acquire signal data; S220: Based on the signal data and the signal transmission mode, determine the first phase information of the signal data. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. S230: When it is determined that the signal data is in a phase-off state, change the phase information of the signal data to a phase-off state; S240: When the signal data is in a phase-off state, the control clock data recovery circuit is opened to adjust the local clock to move the first preset phase. S250: Controls the closed-loop clock data recovery circuit to continue adjusting the local clock to move the second preset phase and determine the second phase information of the adjusted signal data; S260: Based on the first phase information and the second phase information, adjust the local clock to move a third preset phase. The third preset phase moves in the opposite direction to the first preset phase and the second preset phase. The phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0020] In the embodiments of the above signal processing method, serial signal data is first continuously acquired from the signal input port. When determining the first phase information of the signal data based on the signal data and signal transmission mode, the first valid sampling point of the signal data can be compared with the reference time of the local clock to determine whether the first phase information of the signal data belongs to a phase offset state or a phase-free state. The phase offset state can include phase delay (late) or phase advance (early), and the determination result is latched as the first phase information. If the first phase information is a phase-free state, the system can immediately rewrite the internal state mark of the signal data to "phase delay" or "phase advance" to ensure that the subsequent phase adjustment process proceeds in a predetermined direction. The internal state mark can be selected from either of the two phase offset states, thereby causing the signal data determined to be in a metastable state to leave the metastable state. Furthermore, the system can control the clock data recovery circuit to open the loop, temporarily suspend the feedback correction mechanism, thereby adjusting the local clock to move by a first preset phase. In the next several clock cycles, the local clock is cumulatively driven to shift by a first preset phase at a certain amplitude per cycle, so that the phase of the local clock moves by a large step at once, and the clock data recovery loop leaves the metastable state. After completing the large-step movement to escape the metastable state, the clock data recovery circuit can lock. During locking, the loop gain cannot be too large; otherwise, the phase difference between the final locked point and the ideal locked point will be too large, resulting in a significant distance between the locked point and the actual locked point. Therefore, the local clock is further adjusted by moving a second preset phase, which is smaller than the first preset phase. The second phase information of the signal data is determined again, and then the stored first phase information is compared with the second phase information. If the directions are opposite, the required fine-tuning amount (third preset phase) is calculated, and within one or several clock cycles, reverse fine-tuning is completed through closed-loop micro-drive, ultimately achieving precise alignment of the local clock. After this process, the clock data recovery circuit returns to its normal operating mode, completing rapid locking. The longest locking time of the clock data recovery circuit occurs when the sampling clock is near a zero-crossing point, while the shortest locking time occurs when the clock phase coincides with the center locking point (at which point it almost approaches or equals 0). To reduce the longest locking time, this application adjusts the loop gain of the clock data recovery circuit to the maximum gain that the clock data recovery circuit can tolerate, thereby shifting the local clock phase first by the first preset phase, allowing the local clock phase to move in a large step at once. The second phase information, determined during subsequent operation, is compared with the first phase information read during the first read. If a result showing the opposite phase from the first read occurs, it indicates that the local clock phase has flipped from one end of the center lock point to the other, and the clock data recovery circuit is approaching the optimal lock point.Because of the delay in the phase update of the local clock, the phase of the sampling clock of the current phase detection circuit is transmitted by the phase interpolator multiple cycles ago. Therefore, it is also necessary to backtrack the local clock phase to the phase corresponding to the local clock before the flip, that is, to adjust the local clock using a third preset phase. In this embodiment, by making a large open-loop shift of the first preset phase, adjusting the second preset phase in a closed loop, and fine-tuning the third preset phase based on the first and second phase information, the loop of the clock data recovery circuit can be quickly locked under bursts of signal data transmission. This allows for rapid escape from metastability and high-precision alignment with small steps in the final stage, effectively avoiding metastability and loop bandwidth limitations, improving adaptability to multi-rate burst data packets, significantly shortening the locking time, and enhancing system stability and reliability.

[0021] In some embodiments of this application, determining the first phase information of the signal data based on the signal data and the signal transmission mode further includes: waiting for a first preset number of cycles, and when the signal data reaches the first preset number of cycles, determining the first phase information based on the signal data.

[0022] In this embodiment, after determining that the signal data transmission has started in burst mode based on the signal data and signal transmission mode, the first phase information is not immediately determined. Instead, period counting is performed, for example, waiting for two clock cycles before starting phase detection. This allows the signal data to be fully established within the receiver, avoiding abnormal decision results. When the receiving window crosses a preset first number of cycles, the decision result at that moment is latched as the first phase information to avoid misjudging the phase state when the preamble has just entered the eye diagram and the signal has not yet stabilized. By delaying the decision, it is ensured that the input signal data has undergone sufficient filtering and timing stability before phase judgment is made, thereby improving the reliability of phase information and reducing the risk of misjudgment.

[0023] In some embodiments of this application, determining the first phase information of the signal data based on the signal data further includes: determining the first phase information of the signal data within a second preset number of cycles of the signal data; and determining the signal data as having no phase offset state when each cycle within the second preset number of cycles does not satisfy the phase offset state.

[0024] In this embodiment, after acquiring signal data, the phase information of the signal data can be continuously judged within a second preset number of cycles. As long as there is a determination that the signal is ahead or behind, the result can be latched as the first phase information. If the phase detector continuously determines that there is no delay or advance within the second preset period, it is determined that there is a metastable state, and the first phase information of the signal data is forcibly set to the phase offset state to prepare for phase adjustment.

[0025] In some embodiments of this application, adjusting the local clock to move a first preset phase includes: adjusting the local clock to move a first preset phase based on a third preset number of cycles; adjusting the local clock to move a second preset phase includes: adjusting the local clock to move a second preset phase based on a fourth preset number of cycles.

[0026] In this embodiment, to prevent the clock data recovery circuit from metastable conditions, a third preset number of cycles are continuously sent during the open-loop coarse adjustment phase. Each cycle sends a phase offset command to the phase interpolator, allowing the local clock to make large adjustments and shortening the lock-in time. Subsequently, during the closed-loop fine adjustment phase, a fourth preset number of cycles are continuously sent, with each cycle making a small adjustment step until the acquisition of the second phase information is completed. By limiting the number of adjustment cycles in each stage, the execution time of both coarse and fine adjustments is controllable, while avoiding closed-loop instability caused by excessive open-loop or excessive gain.

[0027] In some embodiments of this application, adjusting the local clock to move a third preset phase based on the first phase information and the second phase information includes: adjusting the local clock to move a third preset phase when the second phase information is opposite to the first phase information.

[0028] When the second phase information is opposite to the first phase information, it indicates that the local clock phase has flipped from one end of the center lock point to the other, and the clock data recovery circuit is close to the optimal lock point. Since there is a delay in the local clock phase update, the phase of the sampling clock in the current phase detection circuit is transmitted by the phase interpolator several cycles ago. Therefore, it is necessary to backtrack the local clock phase to the phase corresponding to the local clock before the flip, i.e., adjust the local clock using the third preset phase. Afterwards, the clock data recovery circuit returns to the normal operating mode and reports the end of the burst mode. By comparing the latched first and second phase information, if their directions are opposite, the local clock phase is adjusted in reverse according to the pre-calculated third preset phase amount to compensate for the "out-of-bounds" error caused by loop delay.

[0029] In some embodiments of this application, the phase value of the second preset phase is determined based on the loop delay and phase gain of the clock data recovery circuit.

[0030] Loop delay refers to the total delay in the closed-loop path from the output of a decision by the phase detection circuit to the processing of that decision signal by the state machine and digital filter, ultimately driving the phase interpolator to change the phase. This delay can include the decision delay of the phase detection circuit itself, the latching and state switching delay of the state machine, or the processing delay of the digital filter. Phase gain refers to the CDR's ability to change the phase decision result, i.e., how much phase shift the UI is caused by each acquired phase decision result. When it is determined that the first phase information is out of phase with the second phase information, the ideal compensation phase amount can be the product of the loop delay and the phase gain. Then, the state machine outputs a corresponding voltage to the phase interpolator through the digital filter, causing it to shift in the opposite direction for precise compensation. By precisely matching the third preset phase with the loop characteristics, convergence to the optimal locking point can be achieved faster during the callback phase.

[0031] In some embodiments of this application, determining the first phase information of the signal data based on the signal data and the signal transmission mode includes: determining the transmission mode of the signal data based on the preamble in the signal data, wherein the transmission mode includes burst mode and continuous mode; and determining the first phase information of the signal data when the signal data is determined to be burst mode.

[0032] Continue to refer to Figure 1 A phase detection circuit 110 is used to acquire signal data and determine the first phase information of the signal data based on the signal data and the signal transmission mode. The first phase information includes a phase offset state or a phase-free state. The phase offset state includes a phase delay or a phase advance. A state machine 120 is used to change the phase information of the signal data to a phase offset state when the phase detection circuit determines that the signal data is in a phase-free state. It is also used to control the phase interpolator through the digital filter 130 to adjust the local clock to move a first preset phase when the phase detection circuit determines that the signal data is in a phase offset state. It is also used to control the clock data recovery circuit to close the loop and continue to control the phase interpolator 30 through the digital filter 130 to adjust the local clock to move a second preset phase, and determine the second phase information of the adjusted signal data. It is also used to control the phase interpolator 30 through the digital filter 130 to adjust the local clock to move a third preset phase based on the first and second phase information. The third preset phase moves in the opposite direction to the first and second preset phases. The phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0033] The phase detection circuit 110 detects the start of a burst and waits for two clock cycles before starting phase detection. This two-cycle wait allows the signal to fully build up within the receiver, preventing abnormal decision results. Figure 3This diagram illustrates the relationship between a period and a unit interval (UI) as provided in some embodiments of this application. The unit interval (UI) represents the duration of one bit period or one symbol period and is used to measure the magnitude of phase offset or delay. For example, a deviation of 1 / 2UI means that the clock phase differs from the ideal sampling point by half a bit period. The phase detection circuit 110 begins detecting phase information and determines whether an advance or delay has occurred. After the phase detection circuit 110 detects an advance or delay, the state machine 120 latches the current result. If no advance or delay occurs for four consecutive periods, the state machine 120 forcibly writes a delay (or advance) to the phase detection circuit 110 and latches the result. Then, the state machine 120 disconnects the loop of the clock data recovery circuit and controls the phase interpolator 30 to adjust the phase by 1 / 16UI each period through the digital filter 130. After four periods, the state machine 120 releases the loop control over the clock recovery circuit (i.e.,...). Figure 3 (As shown at the point of departure from the merging point), the phase detection circuit 110 normally outputs phase information, only adjusting the gain of the digital filter 130 so that the phase interpolator 30 moves at 1 / 64UI phase per cycle. After re-timing for 4 cycles, the state machine 120 begins to read the phase information output by the phase detection circuit 110 and checks whether a phase opposite to the first detected phase appears. The 4-cycle wait is because the phase written to the phase interpolator 30 in the previous step requires 4 cycles to return to the phase detection circuit 110. When opposite phase information is detected (i.e.,...) Figure 3 (As shown in the backoff clock phase diagram), state machine 120 controls digital filter 130 to cause phase interpolator 30 to move in the reverse direction. The magnitude of the shifted phase corresponds to the product of the loop delay and phase gain of the clock data recovery circuit. Simultaneously, state machine 120 relinquishes control of the clock data recovery circuit, which then enters its normal operating mode and reports the end of the burst lockout process. The phase detection circuit 110, state machine 120, and digital filter 130 can be implemented using analog circuits, thereby increasing the clock rate and shortening the lockout time of the clock data recovery circuit. Figure 4 This paper illustrates a flowchart of another signal processing method provided in some embodiments of this application. This method can be implemented using the clock data recovery circuit 100 described above, and includes the following steps: S410: Acquire signal data and determine the start of burst mode; S420: Wait for 2 cycles and start detecting phase information; S430: Detect phase information for 4 consecutive cycles and determine in real time whether there is a delay or advance; if there is no delay or advance, execute step S431; if there is a delay or advance, execute step S432. S431: Force the phase information to be set to delay; S432: Controls the clock data recovery circuit gain to be adjusted to 1 / 16 UI per step for 4 cycles, and stores the phase information read for the first time; S440: Controls the clock data recovery circuit gain adjustment to 1 / 64UI per step for 8 cycles; S450: Detect whether phase information different from the first stored phase information has appeared; S460: Back off the phase corresponding to the gain loop of the clock data recovery circuit and adjust the gain to 1 / 512UI.

[0034] The specific details and beneficial effects of the above process steps can be found in the specific content of the above signal processing method embodiments, and will not be repeated here.

[0035] Figure 5 The diagram illustrates a structural schematic of a signal processing apparatus 500 provided in some embodiments of this application. The signal processing apparatus 500 includes: an acquisition unit 510 for acquiring signal data; a first determination unit 520 for determining first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information including a phase offset state or a phase-free state, the phase offset state including a phase delay or a phase advance; a first adjustment unit 530 for adjusting a local clock to move a first preset phase when the first determination unit 520 determines the signal data to be in a phase-free state, thereby changing the phase information of the signal data to a phase offset state; a second adjustment unit 540 for adjusting a local clock to move a second preset phase when the first determination unit 520 determines the signal data to be in a phase offset state; a second determination unit 550 for determining the second phase information of the adjusted signal data; and a third adjustment unit 560 for adjusting a local clock to move a third preset phase based on the first and second phase information, the third preset phase moving in the opposite direction to the first and second preset phases, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

[0036] The above division of units is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these units can be implemented by a processor calling software; for example, a signal processing device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to realize the functions of each unit. The processor can be, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory can be internal or external to the device. Alternatively, these units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, in some embodiments, the hardware circuit is an application-specific integrated circuit (ASIC), which implements the functions of some or all units by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby realizing the functions of some or all units. All units of the above devices can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs with the remaining parts implemented through hardware circuits.

[0037] Based on the same technical concept, this application also provides an electronic device, including: the clock data recovery circuit provided in the above embodiments.

[0038] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A signal processing method, characterized in that, Applications in clock data recovery circuits include: Acquire signal data; Based on the signal data and signal transmission mode, a first phase information of the signal data is determined. The first phase information includes: a phase offset state or a phase no offset state. The phase offset state includes: a phase delay or a phase advance. When it is determined that the signal data is in the phase-no-offset state, the phase information of the signal data is changed to the phase-offset state. When the signal data is in the phase offset state, control the clock data recovery circuit to open the loop and adjust the local clock to move the first preset phase; Control the closed-loop of the clock data recovery circuit, continue to adjust the local clock to move the second preset phase, and determine the second phase information of the adjusted signal data; Based on the first phase information and the second phase information, the local clock is adjusted to move a third preset phase. The third preset phase moves in the opposite direction to the first preset phase and the second preset phase. The phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

2. The signal processing method according to claim 1, characterized in that, The step of determining the first phase information of the signal data based on the signal data and the signal transmission mode further includes: Wait for a first preset number of cycles. When the signal data reaches the first preset number of cycles, determine the first phase information based on the signal data.

3. The signal processing method according to claim 2, characterized in that, The step of determining the first phase information of the signal data based on the signal data further includes: determining the first phase information of the signal data within a second preset number of cycles of the signal data; If the phase offset state is not satisfied in each of the second preset number of cycles, the signal data is determined to be in a phase-offset state.

4. The signal processing method according to claim 3, characterized in that, The adjustment of the local clock to move a first preset phase includes: The local clock is adjusted to move the first preset phase based on a third preset number of cycles; The adjustment of the local clock to move a second preset phase includes: The local clock is adjusted to move the second preset phase based on the fourth preset number of cycles.

5. The signal processing method according to claim 4, characterized in that, The step of adjusting the local clock to move a third preset phase based on the first phase information and the second phase information includes: When the second phase information is opposite to the first phase information, the local clock is adjusted to move the third preset phase.

6. The signal processing method according to any one of claims 1 to 5, characterized in that, The phase value of the second preset phase is determined based on the loop delay and phase gain of the clock data recovery circuit.

7. The signal processing method according to any one of claims 1 to 5, characterized in that, Determining the first phase information of the signal data based on the signal data and the signal transmission mode includes: Based on the preamble in the signal data, the transmission mode of the signal data is determined, and the transmission mode includes: burst mode and continuous mode; When the signal data is determined to be in the burst mode, the first phase information of the signal data is determined.

8. A signal processing apparatus, characterized in that, include: Acquisition unit, used to acquire signal data; The first determining unit is configured to determine first phase information of the signal data based on the signal data and the signal transmission mode. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. The first adjustment unit is used to adjust the local clock to move a first preset phase when the first determining unit determines that the signal data is in the phase-no-offset state, so that the phase information of the signal data is changed to the phase-offset state. The second adjustment unit is used to adjust the local clock to move a second preset phase when the first determining unit determines that the signal data is in the phase offset state. The second determining unit is used to determine the second phase information of the adjusted signal data; The third adjustment unit is used to adjust the local clock to move a third preset phase based on the first phase information and the second phase information. The third preset phase moves in the opposite direction to the first preset phase and the second preset phase. The phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

9. A clock data recovery circuit, characterized in that, include: Phase detection circuit, state machine, and digital filter; The phase detection circuit is used to acquire signal data and determine first phase information of the signal data based on the signal data and the signal transmission mode. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. The state machine is configured to: change the phase information of the signal data to the phase-offset state when the phase detection circuit determines that the signal data is in the phase-offset state; control the phase interpolator through the digital filter to adjust the local clock by a first preset phase when the phase detection circuit determines that the signal data is in the phase-offset state; and control the clock data recovery circuit to close the loop and continue to control the phase interpolator through the digital filter to adjust the local clock by a second preset phase, thereby determining the second phase information of the adjusted signal data. And for adjusting the local clock to move a third preset phase by controlling the phase interpolator through the digital filter based on the first phase information and the second phase information, wherein the third preset phase moves in the opposite direction to the first preset phase and the second preset phase, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

10. An electronic device, characterized in that, include: The clock data recovery circuit according to claim 9.

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