Implementation method and device of multi-rate Ethernet interface
By splitting data frames into multiple sub-data frames and transmitting them with different configuration parameters, the problems of long development cycles and high costs in existing multi-rate Ethernet interface designs are solved, achieving more efficient system adaptation and compatibility.
Patent Information
- Application Number
- CN202511019307.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-10-31
AI Technical Summary
Existing multi-rate Ethernet interface design methods require separate development and debugging for each different rate, resulting in long development cycles, high costs, and low system flexibility and scalability.
By splitting data frames into multiple sub-data frames and transmitting them with different configuration parameters, the unified logic engineering and driver can be adapted to various configuration parameters, enabling flexible adjustment of data transmission.
It reduces design, development, and maintenance costs, improves the scalability of transmission methods and the flexibility of the system, shortens the development cycle, and enhances system compatibility.
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Figure CN120880893A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data transmission, and in particular to a method and apparatus for implementing a multi-rate Ethernet interface. Background Technology
[0002] In today's rapidly developing field of network communication, multi-rate Ethernet technology is being used more and more widely. With the continuous growth of network data traffic, the requirements for network interface speeds are becoming increasingly diverse, necessitating the implementation of multi-rate interface conversion within the same network system to meet the needs of different devices and application scenarios.
[0003] Conventional multi-rate Ethernet interface design methods involve specific development for each different rate using different Advanced Extensible Interface Stream (AXIS) interface bit widths, requiring separate logic engineering and driver design. This development approach is not only extremely labor-intensive, but also necessitates extensive modifications and debugging of logic and drivers when switching or upgrading between different rate interfaces, increasing development time and cost, and reducing system flexibility and scalability. Summary of the Invention
[0004] This application provides a method and apparatus for implementing a multi-rate Ethernet interface, which solves the technical problems of high implementation cost and low scalability in the prior art when multiple transmission configuration parameters need to be deployed simultaneously.
[0005] To achieve the above objectives, this application adopts the following technical solution:
[0006] In a first aspect, a method for implementing a multi-rate Ethernet interface is provided, comprising: receiving a data frame transmitted with a first configuration parameter; splitting the data frame into multiple sub-data frames and transmitting the sub-data frames with a second configuration parameter; wherein the second configuration parameter corresponds to the transmission interface.
[0007] Based on the above technical solution, in the implementation method of the multi-rate Ethernet interface provided in this application, the configuration parameters of data transmission can be adjusted so that a set of logic engineering and driver programs deployed on the bus can be applied to a variety of configuration parameters. This avoids the need to develop and deploy separately for various configuration parameters, effectively reducing the cost of design, development, installation and maintenance, and increasing the scalability of the transmission method.
[0008] In conjunction with the first aspect above, in one possible implementation, the first configuration parameter includes a first bit width, and the second configuration parameter includes a second bit width; the method of splitting a data frame into multiple sub-data frames and transmitting the sub-data frames with the second configuration parameter specifically includes: splitting a data frame into multiple sub-data frames and transmitting the sub-data frames with the second bit width; the second bit width is smaller than the first bit width.
[0009] In conjunction with the first aspect above, in one possible implementation, the method further includes: identifying the end frame among multiple sub-data frames; combining the end frame and the multiple sub-data frames transmitted before the end frame into a merged frame, and outputting the merged frame with a third bit width.
[0010] In conjunction with the first aspect mentioned above, in one possible implementation, the method of splitting a data frame into multiple sub-data frames and transmitting the sub-data frames with a second bit width specifically includes: when the first bit width is not equal to an integer multiple of the second bit width, splitting the data frame into multiple sub-data frames with a second bit width and an end frame with a width less than the second bit width; padding the end frame with zeros to achieve the second bit width.
[0011] In conjunction with the first aspect mentioned above, in one possible implementation, the method of combining the end frame and the multiple sub-data frames transmitted before the end frame into a merged frame and outputting the merged frame with a third bit width specifically includes: when the sum of the bit widths of the end frame and the multiple sub-data frames transmitted before the end frame is less than the third bit width, padding the merged frame with zeros to achieve the third bit width.
[0012] In conjunction with the first aspect mentioned above, in one possible implementation, the third bit width is 512 bits.
[0013] In conjunction with the first aspect mentioned above, in one possible implementation, the first bit width is the transmission bit width corresponding to the maximum transmission rate under the transmission protocol.
[0014] In conjunction with the first aspect mentioned above, in one possible implementation, the first configuration parameter further includes a first data transmission format, and the second configuration parameter further includes a second data transmission format.
[0015] In conjunction with the first aspect mentioned above, in one possible implementation, the transmission interface is the AXIS interface.
[0016] In a second aspect, an apparatus for implementing a multi-rate Ethernet interface is provided, comprising: a communication unit and a processing unit; the communication unit is configured to receive data frames transmitted with first configuration parameters; the processing unit is configured to split the data frames into multiple sub-data frames and transmit the sub-data frames with second configuration parameters; the second configuration parameters correspond to the transmission interface.
[0017] Thirdly, this application provides an apparatus for implementing a multi-rate Ethernet interface, comprising: a processor and a storage medium; the storage medium includes instructions, and the processor is configured to execute the instructions to implement the methods described in the first aspect and any possible implementation thereof. This apparatus for implementing the multi-rate Ethernet interface can be an electronic device or a chip within an electronic device.
[0018] Fourthly, this application provides a system for implementing a multi-rate Ethernet interface, comprising: a transmitting module and a receiving module; the transmitting module is used to receive data frames transmitted with first configuration parameters; the receiving module is used to split the data frames into multiple sub-data frames and transmit the sub-data frames with second configuration parameters; the second configuration parameters correspond to the transmission interface.
[0019] Fifthly, this application provides a computer-readable storage medium storing instructions that, when executed on an apparatus for implementing a multi-rate Ethernet interface, cause the apparatus to perform the method described in the first aspect and any possible implementation thereof.
[0020] In a sixth aspect, this application provides a computer program product containing instructions that, when run on a multi-rate Ethernet interface implementation apparatus, causes the multi-rate Ethernet interface implementation apparatus to perform the methods described in the first aspect and any possible implementation thereof.
[0021] This application provides a method and apparatus for implementing a multi-rate Ethernet interface, which can adjust the configuration parameters of data transmission so that a single set of logic engineering and driver programs deployed on the bus can be applied to various configuration parameters. This avoids the need to develop and deploy separately for various configuration parameters, effectively reducing the cost of design, development, installation and maintenance, and increasing the scalability of the transmission method.
[0022] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description
[0023] Figure 1 A system architecture diagram of a data transmission system provided in this application embodiment;
[0024] Figure 2 A timing diagram of a transmitting-side interface adaptation module provided in an embodiment of this application;
[0025] Figure 3 A timing diagram of a receiving-side interface adaptation module provided in an embodiment of this application;
[0026] Figure 4 A flowchart illustrating a method for implementing a multi-rate Ethernet interface according to an embodiment of this application;
[0027] Figure 5 A flowchart illustrating another method for implementing a multi-rate Ethernet interface provided in this application embodiment;
[0028] Figure 6 An example diagram illustrating the relationship between the rate of position change and the number of position feedbacks provided in this application embodiment;
[0029] Figure 7 A flowchart illustrating another method for implementing a multi-rate Ethernet interface provided in this application embodiment;
[0030] Figure 8 A flowchart illustrating another method for implementing a multi-rate Ethernet interface provided in this application embodiment;
[0031] Figure 9 A flowchart illustrating a method for implementing a 40G / 50G transmission interface according to an embodiment of this application;
[0032] Figure 10 A simulation timing diagram of a 40G / 50G transmission interface provided for embodiments of this application;
[0033] Figure 11 A flowchart illustrating a method for implementing a 40G / 50G receiving interface according to an embodiment of this application;
[0034] Figure 12 A simulation timing diagram of a 40G / 50G receiver interface provided for embodiments of this application;
[0035] Figure 13 A flowchart illustrating a method for implementing a 25G transmission interface according to an embodiment of this application;
[0036] Figure 14 A simulation timing diagram of a 25G transmission interface provided for embodiments of this application;
[0037] Figure 15 A flowchart illustrating a method for implementing a 25G receiving interface according to an embodiment of this application;
[0038] Figure 16 A simulation timing diagram of a 25G receiving interface provided for embodiments of this application;
[0039] Figure 17 A flowchart illustrating a method for implementing a 10G transmission interface according to an embodiment of this application;
[0040] Figure 18 A simulation timing diagram of a 10G transmission interface provided for an embodiment of this application;
[0041] Figure 19 A flowchart illustrating a method for implementing a 10G receiving interface according to an embodiment of this application;
[0042] Figure 20 A simulation timing diagram of a 10G receiver interface provided for an embodiment of this application;
[0043] Figure 21 A schematic diagram of a multi-rate Ethernet interface implementation device provided in an embodiment of this application;
[0044] Figure 22 A schematic diagram of the hardware structure of a multi-rate Ethernet interface implementation device provided in an embodiment of this application; Detailed Implementation
[0045] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.
[0046] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0047] The multi-rate Ethernet interface implementation method provided in this application embodiment can be applied to the data transmission system 100, such as... Figure 1 As shown, the data transmission system 100 includes: an interface bus 101, a transmitting-side interface adapter module 102, a receiving-side interface adapter module 103, and multiple sets of transmitting and receiving interfaces. Figure 1 (The following is an example using two sets of transmitting interfaces 104 and 105, and transmitting interface 106 and receiving interface 107).
[0048] Each set of transmitting and receiving interfaces transmits data through interface bus 101.
[0049] Optionally, the interface bus 101 is a standard AXIS interface bus for a field-programmable gate array (FPGA) media access control (MAC) network interconnection protocol (IP).
[0050] The implementation method of the multi-rate Ethernet interface provided in this application embodiment requires configuring a set of transmission configuration parameters on the interface bus 101.
[0051] For example, taking Xilinx's 100 gigabyte (G) multi-rate media access control (MRMAC) multi-rate Ethernet (MRMAC) as an example, it supports five rates: 100G, 50G, 40G, 25G, and 10G. However, the AXIS bus width supported by each rate is different. The AXIS width for 100G is 384 bits, for 50G and 40G it is 256 bits, for 25G it is 128 bits, and for 10G it is 32 bits. In a multi-rate Ethernet system, interfaces of different rates need to perform efficient data transmission and adaptation with the MAC layer.
[0052] After the logic engineering and driver debugging tests of the 100G interface are completed and found to be normal, the implementation of other rates only requires the transmitting side interface adaptation module 102 and the receiving side interface adaptation module 103 to adjust the transmission configuration parameters of the transmitted data frames.
[0053] For example, the timing diagram of the sending-side interface adaptation module is as follows: Figure 2 As shown, the timing diagram of the receiving-side interface adapter module is as follows: Figure 3 As shown.
[0054] The definitions of the transmit and receive interface signals in the transmitted data frames are shown in Table 1.
[0055] Table 1. Definitions of Transmit and Receive Interface Signals
[0056]
[0057] To address the technical problems of high cost and low scalability in existing technologies when multiple transmission configuration parameters need to be deployed simultaneously, this application provides a method for implementing a multi-rate Ethernet interface. The method includes: receiving a data frame transmitted with a first configuration parameter; splitting the data frame into multiple sub-data frames and transmitting the sub-data frames with a second configuration parameter; the second configuration parameter corresponding to the transmission interface. Based on this, the configuration parameters for data transmission can be adjusted so that a single set of logic engineering and driver programs deployed on the bus can be applied to multiple configuration parameters. This avoids the need for separate development and deployment for each configuration parameter, effectively reducing design, development, installation, and maintenance costs, and increasing the scalability of the transmission method.
[0058] like Figure 4 As shown in the embodiments of this application, the method for implementing a multi-rate Ethernet interface includes:
[0059] S401, Receive a data frame transmitted with the first configuration parameters.
[0060] In some implementations, configuration parameters may include transmission bit width, transmission rate, data transmission format, etc.
[0061] S402, Split the data frame into multiple sub-data frames and transmit the sub-data frames with the second configuration parameters.
[0062] The second configuration parameter corresponds to the transmission interface.
[0063] Based on the above technical solution, the implementation method of the multi-rate Ethernet interface provided in this application can adjust the configuration parameters of data transmission so that a set of logic engineering and driver programs deployed on the bus can be applied to a variety of configuration parameters. This avoids the need to develop and deploy separately for various configuration parameters, effectively reduces the cost of design, development, installation and maintenance, and increases the scalability of the transmission method.
[0064] In one possible implementation, combining Figure 4 ,like Figure 5 As shown, when the first configuration parameter includes the first bit width and the second configuration parameter includes the second bit width, the above S402 can be specifically implemented through the following S501, which will be explained in detail below:
[0065] S501. The data frame is split into multiple sub-data frames and the sub-data frames are transmitted with a second bit width.
[0066] The width of the second dimension is smaller than that of the first dimension.
[0067] In some implementations, the first bit width is the transmission bit width corresponding to the maximum transmission rate under the transmission protocol. This makes it applicable to all low-rate transmissions under the transmission protocol.
[0068] For example, the logic processing within the interface adaptation module converts data at different rates into the required data format and rate. The 40G / 50G transmission interface needs to convert 384 bits to 256 bits; the 25G transmission interface needs to convert 384 bits to 128 bits; and the 10G transmission interface needs to convert 384 bits to 32 bits.
[0069] In some implementations, the order of multiple sub-data frames can be identified, or only the last ending frame can be identified.
[0070] Based on the above technical solution, the following effects can be achieved:
[0071] 1. Improved development efficiency: There is no need to develop separate interface logic and drivers for each different speed, which reduces a lot of development work and shortens the development cycle.
[0072] 2. Reduce development costs: Avoid the human and material costs caused by repeated development and improve resource utilization.
[0073] 3. Enhance system flexibility and scalability: It can quickly adapt to various low-speed interfaces without modifying drivers and logic functions, making it convenient for system upgrades and expansions to meet the needs of different application scenarios.
[0074] 4. Improve system compatibility: Through a unified interface adapter module, interfaces with different speeds can be better compatible with the MAC layer, thereby improving the overall performance of the system.
[0075] In one possible implementation of the embodiments of this application, combined with Figure 5 ,like Figure 6 As shown, after S501 above, the method further includes S601 to S602, which are described in detail below:
[0076] S601, Identifies the end frame among multiple sub-data frames.
[0077] In some implementations, the "tx_tlast" field is used to indicate whether it is the end frame; "tx_tlast = 0" for non-end frames and "tx_tlast = 1" for end frames.
[0078] S602. Combine the ending frame and the multiple sub-data frames transmitted before the ending frame into a merged frame, and output the merged frame with a third bit width.
[0079] In some implementations, the third bit width is 512 bits.
[0080] It should be noted that in high-speed communication systems, the receiving interface is designed to uniformly convert data to 512 bits, primarily based on the following key reasons:
[0081] 1. Improve bus efficiency and throughput:
[0082] (1) Bandwidth matching: The sending end (e.g., 40G / 50G / 25G / 10G) has different rates, but the receiving end (e.g., CPU, switching chip or storage controller) usually needs to handle higher aggregate bandwidth.
[0083] For example, multiple low-speed channels (10G×4) may converge to a high-speed core (40G), and the 512-bit width can hold more data at once, reducing the number of processing steps.
[0084] (2) Reduce clock cycle consumption: If the core processing bit width of the receiver is 512 bits, it only takes 1 clock cycle to receive 512 bits each time, while it takes 2 cycles to receive 256 bits, which significantly improves efficiency.
[0085] 2. Align data blocks with protocol requirements:
[0086] (1) Protocol frame alignment: Many high-speed protocols (such as the MAC layer of Ethernet, PCIe TLP packets) require data blocks to be aligned to a fixed size (such as 512 bits, which is a common cache line size).
[0087] For example, the maximum payload of a PCIe TLP packet is 512 bytes, and 512 bits (64 bytes) is its natural alignment unit.
[0088] (2) Simplify verification and error correction: Larger data blocks (such as 512 bits) can be centrally checked for CRC or corrected for FEC, reducing the overhead of fragmented verification.
[0089] 3. Cache and storage optimization:
[0090] (1) Cache line matching: Modern processor cache lines are typically 64B (512 bits). Directly aligning received data can avoid extra splicing operations and improve DMA efficiency.
[0091] For example, DMA writes 512 bits of data directly into memory, which can be cached by the CPU without splitting the data.
[0092] (2) Reduce memory accesses: Writing 512 bits reduces memory accesses by 50% compared to writing 256 bits, thus reducing latency.
[0093] 4. Unified processing for multi-rate interfaces:
[0094] (1) Multi-channel convergence: Transmitting interfaces with different rates (such as 40G / 25G / 10G) may eventually converge to the same processing unit at the receiving end. The 512-bit width can be flexibly accommodated as follows: 2×256 bits (from 40G / 50G), 4×128 bits (from 25G), and 16×32 bits (from 10G).
[0095] (2) Unified data path: The receiving end does not need to design different processing logic for interfaces with different rates, simplifying hardware design.
[0096] 5. Advantages of hardware implementation:
[0097] (1) Clock domain isolation: The receiver may operate in an independent clock domain (such as the core frequency being higher than the interface frequency). A 512-bit wide data bus can reduce the frequency of cross-clock domain synchronization.
[0098] For example, 256 bits of data from a 40G interface need to be concatenated twice in the clock domain at the receiving end to become 512 bits, while receiving 512 bits directly can reduce the number of synchronization operations.
[0099] (2) Pipeline optimization: Large bit width data is more suitable for pipeline processing (such as encryption and compression modules) to improve parallelism.
[0100] For example, the logic processing within the interface adapter module converts data at different rates into the required data format and rate. The 40G / 50G receiving interface needs to convert 256 bits to 512 bits; the 25G receiving interface needs to convert 128 bits to 512 bits; and the 10G receiving interface needs to convert 32 bits to 512 bits.
[0101] Based on the above technical solutions, it is possible to optimize throughput, reduce the number of processing operations, match the core high-frequency clock, meet the fixed data block requirements of high-speed protocols, directly align CPU cache lines (64B) to improve memory access efficiency, unify bit width to reduce the complexity of multi-rate interfaces and support flexible convergence, and reduce bus switching frequency and dynamic power consumption by increasing bit width.
[0102] In one possible implementation of the embodiments of this application, combined with Figure 6 ,like Figure 7 As shown, the above S501 can be specifically implemented through the following S701 to S702, which are explained in detail below:
[0103] S701. When the width of the first bit is not equal to an integer multiple of the width of the second bit, the data frame is split into multiple sub-data frames of the second bit width and an end frame that is smaller than the width of the second bit.
[0104] S702, Pad the end frame with zeros to achieve the second bit width.
[0105] It should be noted that zero-padding is a common operation in digital signal processing and data transmission, especially in bit width conversion, alignment, or protocol adaptation.
[0106] Based on the above technical solution, zero-padding can directly fill the target bit width, avoiding complex splicing logic, simplifying hardware design, and ensuring compatibility with standard protocols. Furthermore, zero padding ensures that undefined bits are 0, does not increase the actual information content, avoids logic errors caused by random values, and reduces dynamic power consumption during signal switching.
[0107] In one possible implementation of the embodiments of this application, combined with Figure 7 ,like Figure 8 As shown, the above S602 can be specifically implemented through the following S801, which will be explained in detail below:
[0108] S801. When the sum of the bit widths of the ending frame and the multiple sub-data frames transmitted before the ending frame is less than the third bit width, the merged frame is padded with zeros to reach the third bit width.
[0109] Based on the above technical solution, zero-padding can directly fill the target bit width, avoiding complex splicing logic, simplifying hardware design, and ensuring compatibility with standard protocols. Furthermore, zero padding ensures that undefined bits are 0, does not increase the actual information content, avoids logic errors caused by random values, and reduces dynamic power consumption during signal switching.
[0110] In one exemplary description, taking a transmission rate of 40G / 50G as an example, such as Figure 9 As shown, when the transmitting interface receives a valid data frame, it splits it into two frames for transmission. The first frame transmits the lower 256 bits of data, with the tx_tlast1 signal set to 0. The second frame transmits the higher 128 bits of data (padded with zeros to 256 bits), with the tx_tlast1 signal being the tx_tlast signal of this frame. The simulation timing diagram is as follows. Figure 10 .
[0111] like Figure 11 As shown, when the receiving interface receives a valid data frame, if rx_tlast1 = 1, indicating it is the last frame, it is padded with zeros to 512 bits and sent directly, while simultaneously sending rx_tlast = 1; if rx_tlast1 = 0, it means this frame is not the last frame, and it waits for the next frame to arrive before merging and sending it, while simultaneously sending the rx_tlast1 signal of the following frame as the rx_tlast signal of the merged frame, and then returns to the initial state to wait for the next frame input. The simulation timing diagram is as follows. Figure 12 .
[0112] In yet another exemplary description, taking a transmission rate of 25G as an example, such as Figure 13 As shown, when the transmitting interface receives a valid data frame, it splits it into three frames for transmission. The first frame transmits the lower 128 bits of data, with the tx_tlast1 signal set to 0. The second frame transmits the middle 128 bits of data, with the tx_tlast1 signal set to 0. The third frame transmits the higher 128 bits, with tx_tlast1 being the tx_tlast signal for this frame. The simulation timing diagram is as follows. Figure 14 .
[0113] like Figure 15 As shown, when the receiving interface receives the first valid frame of data, if rx_tlast1 = 1, indicating it is the last frame, it pads the high-order bits with zeros to 512 bits and sends it directly, while simultaneously sending tx_tlast = 1; if rx_tlast1 = 0, it means this frame is not the last frame, and it waits for the next frame to arrive. Upon receiving the second frame, if rx_tlast1 = 1, indicating it is the last frame, it pads the high-order bits of the previous two frames with zeros to 512 bits and sends it directly, while simultaneously sending tx_tlast = 1; if rx_tlast1 = 0, it means this frame is not the last frame, and it waits for the next frame to arrive. If the frame is not the last frame, wait for the next frame. Upon receiving the third frame, if rx_tlast1 = 1, indicating it is the last frame, pad the high bits of the first three frames with zeros to 512 bits and send them directly, while simultaneously sending tx_tlast = 1. If rx_tlast1 = 0, it means this frame is not the last frame, and wait for the next frame. Upon receiving the fourth frame, merge the four frames and send them directly, while using the rx_tlast1 signal of the last frame as the rx_tlast signal of the merged frame. Then return to the initial state and wait for the next frame input. The simulation timing diagram is as follows. Figure 16 .
[0114] In yet another exemplary description, taking a transmission rate of 10G as an example, such as Figure 17As shown, when the sending interface receives a valid data frame, it splits it into twelve frames for transmission. The first frame transmits [31:0] bits of data, with the tx_tlast1 signal set to 0; the second frame transmits [63:32] bits of data, with the tx_tlast1 signal set to 0; the third frame transmits [95:64] bits of data, with the tx_tlast1 signal set to 0; the fourth frame transmits [127:96] bits of data, with the tx_tlast1 signal set to 0; the fifth frame transmits [159:128] bits of data, with the tx_tlast1 signal set to 0; and the sixth frame transmits [191:160] bits of data, with the tx_tlast1 signal set to 0. The signal is 0; the seventh frame sends [223:192] bits of data, and the tx_tlast1 signal is 0; the eighth frame sends [255:224] bits of data, and the tx_tlast1 signal is 0; the ninth frame sends [287:256] bits of data, and the tx_tlast1 signal is 0; the tenth frame sends [319:288] bits of data, and the tx_tlast1 signal is 0; the eleventh frame sends [351:320] bits of data, and the tx_tlast1 signal is 0; the twelfth frame sends [383:352] bits of data, and tx_last1 is the tx_last signal of this frame. The simulation timing diagram is as follows. Figure 18 .
[0115] like Figure 19 As shown, when the receiving interface receives the first valid frame of data, if rx_tlast1 = 1, indicating it is the last frame, it pads the high-order bits with zeros to 512 bits and sends it directly, while simultaneously sending tx_tlast = 1; if rx_tlast1 = 0, it means this frame is not the last frame, and it waits for the next frame to arrive. Upon receiving the second frame, if rx_tlast1 = 1, indicating it is the last frame, it pads the high-order bits of the previous two frames with zeros to 512 bits and sends it directly, while simultaneously sending tx_tlast = 1; if rx_tlast1 = 0, it means this frame is not the last frame. Upon receiving the first frame, the system waits for the next frame. Upon receiving the third frame, if rx_tlast1 = 1, indicating it's the last frame, the high-order bits of the first three frames are padded with zeros to 512 bits and sent directly, along with tx_tlast = 1. If rx_tlast1 = 0, it means this is not the last frame, and the system waits for the next frame. This process continues until the sixteenth frame is received. The sixteen frames are then merged and sent, with the rx_tlast1 signal of the last frame used as the rx_tlast signal for the merged frame. The system then returns to its initial state, waiting for the next frame input. The simulation timing diagram is shown below. Figure 20 .
[0116] Based on the above example, throughout the process, the sending and receiving interface adaptation module is responsible for handling data conversion and format adaptation between different rates, so that the logic functions of the driver and MAC layer can be adapted to a variety of low-rate interfaces without modification.
[0117] The foregoing mainly describes the solutions of the embodiments of this application from the perspective of device implementation. It is understood that each device, such as a multi-rate Ethernet interface implementation apparatus, includes at least one of the hardware structures and software modules corresponding to each function in order to achieve the above-mentioned functions. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0118] This application embodiment can divide the multi-rate Ethernet interface implementation device into functional units according to the above method example. For example, each function can be divided into separate functional units, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.
[0119] When using integrated units, Figure 21 A possible structural schematic diagram of the multi-rate Ethernet interface implementation device (referred to as interface implementation device 2100) involved in the above embodiments is shown. The interface implementation device 2100 includes a processing unit 2101 and a communication unit 2102, and may also include a storage unit 2103. Figure 21 The structural diagram shown can be used to illustrate the structure of the implementation device for the multi-rate Ethernet interface involved in the above embodiments.
[0120] when Figure 21 The schematic diagram shown illustrates the structure of the multi-rate Ethernet interface implementation device involved in the above embodiments. The processing unit 2101 is used to control and manage the operation of the multi-rate Ethernet interface implementation device, the communication unit 2102 is used for the multi-rate Ethernet interface implementation device to communicate with other devices, and the storage unit 2103 is used to store the program code and data of the multi-rate Ethernet interface implementation device.
[0121] For example, communication unit 2102 and processing unit 2101;
[0122] Communication unit 2102 is used to receive data frames transmitted with first configuration parameters;
[0123] The processing unit 2101 is used to split a data frame into multiple sub-data frames and transmit the sub-data frames with a second configuration parameter; the second configuration parameter corresponds to the transmission interface.
[0124] In one possible implementation, the first configuration parameter includes a first bit width, and the second configuration parameter includes a second bit width; the processing unit 2101 is specifically used to split the data frame into multiple sub-data frames and transmit the sub-data frames with the second bit width; the second bit width is smaller than the first bit width.
[0125] In one possible implementation, the processing unit 2101 is further configured to identify the end frame among multiple sub-data frames; combine the end frame and the multiple sub-data frames transmitted before the end frame into a merged frame, and output the merged frame with a third bit width.
[0126] In one possible implementation, the processing unit 2101 is specifically used to split the data frame into multiple sub-data frames of the second bit width and an end frame smaller than the second bit width when the first bit width is not equal to an integer multiple of the second bit width; and to pad the end frame with zeros to achieve the second bit width.
[0127] In one possible implementation, the processing unit 2101 is specifically used to pad the merged frame with zeros to achieve the third bit width when the sum of the bit widths of the end frame and the multiple sub-data frames transmitted before the end frame is less than the third bit width.
[0128] The processing unit 2101 can be a processor or a controller, and the communication unit 2102 can be a communication interface, transceiver, transceiver circuit, transceiver device, etc. The term "communication interface" is a general term and may include one or more interfaces. The storage unit 2103 can be a memory. When the interface implementation device 2100 is a chip, the processing unit 2101 can be a processor or a controller, and the communication unit 2102 can be an input interface and / or an output interface, pins, or circuits, etc. The storage unit 2103 can be a storage unit within the chip (e.g., a register, cache, etc.) or a storage unit located outside the chip (e.g., read-only memory (ROM), random access memory (RAM, etc.)).
[0129] The communication unit can also be called a transceiver unit. The antenna and control circuit with transceiver functions in the interface implementation device 2100 can be considered as the communication unit 2102 of the interface implementation device 2100, and the processor with processing functions can be considered as the processing unit 2101 of the interface implementation device 2100. Optionally, the device in the communication unit 2102 used to implement the receiving function can be considered as a communication unit. The communication unit is used to execute the receiving steps in the embodiments of this application, and the communication unit can be a receiver, a receiver circuit, etc. The device in the communication unit 2102 used to implement the transmitting function can be considered as a transmitting unit. The transmitting unit is used to execute the transmitting steps in the embodiments of this application, and the transmitting unit can be a transmitter, a transmitter, a transmitting circuit, etc.
[0130] Figure 21 If the integrated units in the process are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. Storage media for storing computer software products include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0131] Figure 21 The units in the process can also be called modules; for example, a processing unit can be called a processing module.
[0132] This application embodiment also provides a hardware structure diagram of a multi-rate Ethernet interface implementation device (denoted as interface implementation device 2200), see [link to hardware structure diagram]. Figure 22 The interface implementation device 2200 includes a processor 2201, and optionally, a memory 2202 connected to the processor 2201.
[0133] In the first possible implementation, see Figure 22The interface implementation device 2200 further includes a transceiver 2203. The processor 2201, memory 2202, and transceiver 2203 are connected via a bus. The transceiver 2203 is used to communicate with other devices or communication networks. Optionally, the transceiver 2203 may include a transmitter and a receiver. The device in the transceiver 2203 used to implement the receiving function can be considered as a receiver, which is used to perform the receiving steps in the embodiments of this application. The device in the transceiver 2203 used to implement the transmitting function can be considered as a transmitter, which is used to perform the transmitting steps in the embodiments of this application.
[0134] Based on the first possible implementation method Figure 22 The structural diagram shown can be used to illustrate the structure of the implementation device for the multi-rate Ethernet interface involved in the above embodiments.
[0135] in, Figure 22 The diagram can also illustrate the system chip in the device implementing the multi-rate Ethernet interface. In this case, the actions performed by the aforementioned device implementing the multi-rate Ethernet interface can be implemented by the system chip. The specific actions performed can be found above and will not be repeated here.
[0136] In implementation, each step of the method provided in this embodiment can be completed by integrated logic circuits in the processor or by instructions in software form. The steps of the method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.
[0137] The processor in this application may include, but is not limited to, at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., which are various computing devices that run software. Each computing device may include one or more cores for executing software instructions to perform calculations or processing. The processor may be a separate semiconductor chip or integrated with other circuits into a single semiconductor chip. For example, it may be integrated with other circuits (such as encoding / decoding circuits, hardware acceleration circuits, or various bus and interface circuits) to form a SoC (System-on-a-Chip), or it may be integrated as a built-in processor within an ASIC. The ASIC with the integrated processor may be packaged separately or together with other circuits. In addition to the cores for executing software instructions to perform calculations or processing, the processor may further include necessary hardware accelerators, such as field-programmable gate arrays (FPGAs), PLDs (programmable logic devices), or logic circuits that implement dedicated logic operations.
[0138] The memory in the embodiments of this application may include at least one of the following types: read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; or electrically erasable programmable read-only memory (EEPROM). In some scenarios, the memory may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.
[0139] This application also provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to perform any of the methods described above.
[0140] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the methods described above.
[0141] This application also provides a chip including a processor and an interface circuit. The interface circuit is coupled to the processor. The processor is used to run computer programs or instructions to implement the above-described method. The interface circuit is used to communicate with other modules outside the chip.
[0142] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).
[0143] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, the disclosure, and the appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.
[0144] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.
Claims
1. A method for implementing a multi-rate Ethernet interface, characterized in that, include: Receive data frames transmitted with the first configuration parameters; The data frame is split into multiple sub-data frames, and the sub-data frames are transmitted using the second configuration parameters; The second configuration parameter corresponds to the transmission interface.
2. The method according to claim 1, characterized in that, The first configuration parameter includes a first bit width, and the second configuration parameter includes a second bit width; the step of splitting the data frame into multiple sub-data frames and transmitting the sub-data frames according to the second configuration parameter includes: The data frame is split into multiple sub-data frames, and the sub-data frames are transmitted with the second bit width; the second bit width is smaller than the first bit width.
3. The method according to claim 2, characterized in that, Also includes: Identify the end frame among the plurality of sub-data frames; The ending frame and the multiple sub-data frames transmitted before the ending frame are combined into a merged frame, and the merged frame is output with a third bit width.
4. The method according to claim 3, characterized in that, The step of splitting the data frame into multiple sub-data frames and transmitting the sub-data frames with a second bit width includes: When the first bit width is not equal to an integer multiple of the second bit width, the data frame is split into multiple sub-data frames of the second bit width and an end frame smaller than the second bit width; The ending frame is padded with zeros to achieve the second bit width.
5. The method according to claim 4, characterized in that, The step of combining the ending frame and the multiple sub-data frames transmitted before the ending frame into a merged frame, and outputting the merged frame with a third bit width, includes: When the sum of the bit widths of the ending frame and the multiple sub-data frames transmitted before the ending frame is less than the third bit width, the merged frame is padded with zeros to reach the third bit width.
6. The method according to claim 5, characterized in that, The third bit width is 512 bits.
7. The method according to claim 6, characterized in that, The first bit width is the transmission bit width corresponding to the maximum transmission rate under the transmission protocol.
8. The method according to claim 1, characterized in that, The first configuration parameter further includes a first data transmission format, and the second configuration parameter further includes a second data transmission format.
9. The method according to any one of claims 1 to 8, characterized in that, The transmission interface is an AXIS interface.
10. An apparatus for implementing a multi-rate Ethernet interface, characterized in that, The device includes: a communication unit and a processing unit; The communication unit is used to receive data frames transmitted with the first configuration parameters; The processing unit is used to split the data frame into multiple sub-data frames and transmit the sub-data frames with a second configuration parameter; the second configuration parameter corresponds to the transmission interface.