Varactor structure
By employing a specific combination design of substrate, conductive layer, dielectric layer and doped region in the variable capacitor structure, the quality factor and capacitance per unit area of the variable capacitor are improved, solving the problem of insufficient quality factor and capacitance per unit area in the prior art and meeting the needs of high-performance circuit design.
Patent Information
- Application Number
- CN202410469264.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-10-31
AI Technical Summary
Existing variable capacitors have low quality factors and low unit capacitance, making it difficult to meet the requirements of high-performance circuit design.
A specific structural design is adopted, including a substrate, a first conductive layer, a second conductive layer, a first dielectric layer, a second dielectric layer, a first doped region, and a second doped region. By connecting the conductive layers and combining the materials of the dielectric layers, a ring-shaped wire and a conductive plug are formed to improve the electrical connection efficiency of the capacitor.
This achieves a high quality factor and high unit capacitance in the variable capacitor structure, thus improving the performance of circuit design.
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Figure CN120882010A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a varactor structure. Background Technology
[0002] A variable capacitor is a device whose capacitance value can be adjusted by voltage. Variable capacitors can be integrated into various circuit designs. However, continuously improving the quality factor (Q factor) and capacitance per unit capacity of variable capacitors remains a continuous goal. Summary of the Invention
[0003] This invention provides a variable capacitor structure that can have a high quality factor and a high unit capacitance.
[0004] This invention proposes a variable capacitor structure, including a substrate, a first conductive layer, a second conductive layer, a first dielectric layer, a second dielectric layer, a first doped region, and a second doped region. The first conductive layer is located on the substrate. The second conductive layer is located on the first conductive layer. The first dielectric layer is located between the substrate and the first conductive layer. The second dielectric layer is located between the first conductive layer and the second conductive layer. The first doped region and the second doped region are located in the substrate on both sides of the first conductive layer. The second conductive layer is electrically connected to the first doped region and the second doped region.
[0005] According to one embodiment of the present invention, the variable capacitor structure described above may further include a first conductive wire. The first conductive wire is electrically connected to the second conductive layer, the first doped region, and the second doped region.
[0006] According to one embodiment of the present invention, in the above-described variable container structure, the top view pattern of the first conductor may include a ring shape.
[0007] According to an embodiment of the present invention, the variable capacitor structure may further include a first conductive plug, a second conductive plug, and a third conductive plug. The first conductive plug is located between the first conductive wire and the second conductive layer. The first conductive plug is electrically connected to the first conductive wire and the second conductive layer. The second conductive plug is located between the first conductive wire and the first doped region. The second conductive plug is electrically connected to the first conductive wire and the first doped region. The third conductive plug is located between the first conductive wire and the second doped region. The third conductive plug is electrically connected to the first conductive wire and the second doped region.
[0008] According to one embodiment of the present invention, the above-described variable capacitor structure may further include a second conductor. The second conductor is electrically connected to the first conductive layer.
[0009] According to one embodiment of the present invention, the above-described variable capacitor structure may further include a fourth conductive plug. The fourth conductive plug is located between the second conductor and the first conductive layer. The fourth conductive plug is electrically connected to the second conductor and the first conductive layer.
[0010] According to an embodiment of the present invention, in the above-described variable container structure, the first conductive layer and the second conductive layer may extend in a first direction.
[0011] According to an embodiment of the present invention, in the above-described variable container structure, the length of the first conductive layer in the first direction may be greater than the length of the second conductive layer in the first direction.
[0012] According to one embodiment of the present invention, in the above-described variable capacitor structure, the first doped region and the second doped region may be arranged in a second direction. The first direction may intersect with the second direction.
[0013] According to one embodiment of the present invention, in the above-described variable capacitor structure, the material of the first conductive layer is, for example, doped polycrystalline silicon or metal.
[0014] According to one embodiment of the present invention, in the above-described variable capacitor structure, the material of the second conductive layer is, for example, a metal, a metal compound, or a combination thereof.
[0015] According to an embodiment of the present invention, in the above-described variable capacitor structure, the material of the first dielectric layer is, for example, silicon oxide, a high dielectric constant material, or a combination thereof.
[0016] According to an embodiment of the present invention, in the above-described variable capacitor structure, the material of the second dielectric layer is, for example, a low dielectric constant material or a high dielectric constant material.
[0017] According to one embodiment of the present invention, the variable container structure described above may further include a spacer. The spacer is located on the sidewall of the first conductive layer.
[0018] According to one embodiment of the present invention, the variable capacitor structure described above may further include a well region. The well region is located in the substrate. The first doped region and the second doped region may be located in the well region.
[0019] According to an embodiment of the present invention, in the above-described variable capacitor structure, the first doped region, the second doped region, and the well region may have the same conductivity type.
[0020] According to one embodiment of the present invention, the variable capacitor structure described above may further include an isolation structure. The isolation structure is located in the substrate. The isolation structure can define an active region in the substrate.
[0021] According to an embodiment of the present invention, in the above-described variable capacitor structure, the first doped region and the second doped region may be located in the active region.
[0022] According to one embodiment of the present invention, in the above-described variable container structure, the isolation structure is, for example, a shallow trench isolation structure.
[0023] According to one embodiment of the present invention, the variable capacitor structure may further include a third dielectric layer and a fourth dielectric layer. The third dielectric layer is located between the second dielectric layer and the substrate. The fourth dielectric layer is located on the second dielectric layer.
[0024] Based on the above, in the variable capacitor structure proposed in this invention, the second conductive layer is located on the first conductive layer, the second dielectric layer is located between the first and second conductive layers, and the second conductive layer is electrically connected to the first doped region and the second doped region. Therefore, the variable capacitor structure proposed in this invention can have a high quality factor and a high capacitance per unit area.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figures 1A to 1D This is a cross-sectional view of the manufacturing process of the variable container structure according to some embodiments of the present invention;
[0027] Figure 2 for Figure 1D A top view of the variable container structure;
[0028] Figure 3 for Figure 1D A simplified circuit diagram of a variable capacitor structure.
[0029] Explanation of icon numbers:
[0030] 10: Variable Container Structure
[0031] 100: Substrate
[0032] 102: Isolation Structure
[0033] 104, 120, 122, 128: Dielectric layers
[0034] 106,124a: Conductive layer
[0035] 108, 110: Doped regions
[0036] 112: Spacer
[0037] 114: Tunnel
[0038] 116, 118: Metal silicide layers
[0039] 124: Conductive material layer
[0040] 126: Hard mask material layer
[0041] 126a: Hard mask layer
[0042] 130, 132, 134, 136: Conductive plugs
[0043] 138, 140: Conductors
[0044] AA: Active region
[0045] C1, C3: Capacitors
[0046] C2: Variable capacitor
[0047] D1, D2: Direction
[0048] L1, L2: Length
[0049] R1, R2: Resistors Detailed Implementation
[0050] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.
[0051] Figures 1A to 1D This is a cross-sectional view of the manufacturing process of a variable container structure according to some embodiments of the present invention. Figure 2 for Figure 1D A top view of the variable container structure. Figures 1A to 1D For along Figure 2 The cross-sectional views of section lines I-I' and II-II' in the diagram. Figure 2 in, omit Figure 1D Some components in the text are explained clearly. Figure 2 The setting relationship between components. Figure 3 for Figure 1D A simplified circuit diagram of a variable capacitor structure.
[0052] Please refer to Figure 1A A substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, an isolation structure 102 may be formed in the substrate 100. In some embodiments, the isolation structure 102 is, for example, a shallow trench isolation structure. In some embodiments, the material of the isolation structure 102 is, for example, silicon oxide.
[0053] Next, a dielectric layer 104 is formed on the substrate 100. The dielectric layer 104 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 104 is, for example, silicon oxide, a high dielectric constant material, or a combination thereof.
[0054] Then, a conductive layer 106 may be formed on the dielectric layer 104. The conductive layer 106 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the conductive layer 106 is, for example, doped polysilicon or a metal. In some embodiments, the conductive layer 106 may be used as a gate. In some embodiments, the conductive layer 106 may be a polysilicon gate or a metal gate.
[0055] Next, doped regions 108 and 110 are formed in the substrates 100 on both sides of the conductive layer 106. In some embodiments, doped regions 108 and 110 can be used as source / drain regions. In some embodiments, doped regions 108 and 110 may have N-type conductivity, but the present invention is not limited thereto. In other embodiments, doped regions 108 and 110 may have P-type conductivity.
[0056] In some embodiments, spacers 112 may be formed on the sidewalls of the conductive layer 106. The spacers 112 may be a single-layer or multi-layer structure. In some embodiments, the material of the spacers 112 may be, for example, silicon oxide, silicon nitride, or a combination thereof.
[0057] In some embodiments, a well region 114 may be formed in the substrate 100. In some embodiments, the doped regions 108 and 110 and the well region 114 may have the same conductivity type. In some embodiments, the well region 114 may have an N-type conductivity type, but the invention is not limited thereto. In other embodiments, the well region 114 may have a P-type conductivity type.
[0058] In some embodiments, metal silicide layers 116 and 118 may be formed on doped region 108 and doped region 110, respectively. In some embodiments, the materials of metal silicide layer 116 and metal silicide layer 118 are, for example, nickel silicide or cobalt silicide.
[0059] In some embodiments, a dielectric layer 120 may be formed on the isolation structure 102, the spacer 112, the metal silicide layer 116, and the metal silicide layer 118. The dielectric layer 120 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 120 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the dielectric layer 120 is formed by, for example, chemical vapor deposition.
[0060] Please refer to Figure 1BA dielectric layer 122 is formed on the conductive layer 106. The dielectric layer 122 may also be formed on the dielectric layer 120. In some embodiments, the material of the dielectric layer 122 is, for example, a low-dielectric-constant material or a high-dielectric-constant material. In some embodiments, the low-dielectric-constant material is, for example, silicon oxide. In some embodiments, the high-dielectric-constant material is, for example, a metal oxide, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or aluminum oxide (Al2O3). In some embodiments, the dielectric layer 122 is formed by, for example, chemical vapor deposition.
[0061] Next, a conductive material layer 124 may be formed on the dielectric layer 122. In some embodiments, the material of the conductive material layer 124 is, for example, a metal (e.g., titanium or copper), a metal compound (e.g., titanium nitride), or a combination thereof. In some embodiments, the conductive material layer 124 is formed by, for example, chemical vapor deposition or physical vapor deposition.
[0062] Then, a hard mask material layer 126 may be formed on the conductive material layer 124. In some embodiments, the material of the hard mask material layer 126 is, for example, silicon nitride. In some embodiments, the hard mask material layer 126 is formed by, for example, chemical vapor deposition.
[0063] Please refer to Figure 1C The hard mask material layer 126 and the conductive material layer 124 can be patterned to form a hard mask layer 126a and a conductive layer 124a. In some embodiments, the material of the hard mask layer 126a is, for example, silicon nitride. In some embodiments, the material of the conductive layer 124a is, for example, a metal (e.g., titanium or copper), a metal compound (e.g., titanium nitride), or a combination thereof. In some embodiments, the hard mask material layer 126 and the conductive material layer 124 can be patterned using photolithography and etching processes.
[0064] Please refer to Figure 1D The hard mask layer 126a can be removed. In some embodiments, the method for removing the hard mask layer 126a is, for example, dry etching.
[0065] Next, a dielectric layer 128 may be formed on the dielectric layer 122 and the conductive layer 124a. In some embodiments, the material of the dielectric layer 128 is, for example, silicon oxide. In some embodiments, the method for forming the dielectric layer 128 is, for example, chemical vapor deposition.
[0066] Then, conductive plugs 130, 132, 134, and 136 can be formed. Conductive plug 130 is located in dielectric layer 128. Conductive plug 130 is electrically connected to conductive layer 124a. Conductive plug 132 is located in dielectric layers 128, 122, and 120. Conductive plug 132 is electrically connected to doped region 108. Conductive plug 134 is located in dielectric layers 128, 122, and 120. Conductive plug 134 is electrically connected to doped region 110. Conductive plug 136 is located in dielectric layers 128 and 122. Conductive plug 136 is electrically connected to conductive layer 106. In some embodiments, the materials of conductive plugs 130, 132, 134, and 136 are, for example, tungsten, titanium, titanium nitride, or combinations thereof.
[0067] Next, wires 138 and 140 can be formed. Wire 138 is located on dielectric layer 128, conductive plug 130, conductive plug 132, and conductive plug 134. Wire 138 is electrically connected to conductive plugs 130, 132, and 134. Wire 140 is located on dielectric layer 128 and conductive plug 136. Wire 140 is electrically connected to conductive plug 136. The material of wires 138 and 140 is, for example, copper (Cu).
[0068] The following is through Figure 1D , Figure 2 and Figure 3 The variable container structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the variable container structure 10 is described using the above method as an example, the present invention is not limited thereto.
[0069] Please refer to Figure 1D and Figure 2 The variable capacitor structure 10 includes a substrate 100, a conductive layer 106, a conductive layer 124a, a dielectric layer 104, a dielectric layer 122, a doped region 108, and a doped region 110. The conductive layer 106 is located on the substrate 100. The conductive layer 124a is located on the conductive layer 106. In some embodiments, such as... Figure 2 As shown, conductive layer 106 and conductive layer 124a may extend in direction D1. In some embodiments, the length L1 of conductive layer 106 in direction D1 may be greater than the length L2 of conductive layer 124a in direction D1. Dielectric layer 104 is located between substrate 100 and conductive layer 106. Dielectric layer 122 is located between conductive layer 106 and conductive layer 124a. Doped regions 108 and 110 are located in the substrate 100 on both sides of conductive layer 106. In some embodiments, as Figure 2As shown, doped regions 108 and 110 can be arranged in direction D2. Direction D1 can intersect direction D2. In some embodiments, direction D1 can be perpendicular to direction D2. Conductive layer 124a is electrically connected to doped regions 108 and 110.
[0070] In some embodiments, the variable capacitor structure 10 may further include an isolation structure 102. The isolation structure 102 is located in the substrate 100. The isolation structure 102 may define an active region AA in the substrate 100. Doped regions 108 and 110 may be located in the active region AA. In some embodiments, the variable capacitor structure 10 may further include a well region 114. The well region 114 is located in the substrate 100. Doped regions 108 and 110 may be located in the well region 114.
[0071] In some embodiments, the variable capacitor structure 10 may further include a spacer 112. The spacer 112 is located on the sidewall of the conductive layer 106. In some embodiments, the variable capacitor structure 10 may further include a metal silicide layer 116 and a metal silicide layer 118. The metal silicide layer 116 is located on the doped region 108. The metal silicide layer 118 is located on the doped region 110.
[0072] In some embodiments, the variable capacitor structure 10 may further include a dielectric layer 120 and a dielectric layer 128. The dielectric layer 120 is located between the dielectric layer 122 and the substrate 100. The dielectric layer 120 may also be located on the isolation structure 102, the spacer 112, the metal silicide layer 116, and the metal silicide layer 118. The dielectric layer 128 is located on the dielectric layer 122. The dielectric layer 128 may also be located on the conductive layer 124a.
[0073] In some embodiments, the variable capacitor structure 10 may further include a wire 138. The wire 138 is electrically connected to the conductive layer 124a, the doped region 108, and the doped region 110. In some embodiments, such as Figure 2 As shown, the top view pattern of conductor 138 may include a loop.
[0074] In some embodiments, the variable capacitor structure 10 may further include conductive plugs 130, 132, and 134. Conductive plug 130 is located between the conductor 138 and the conductive layer 124a. Conductive plug 130 is electrically connected to the conductor 138 and the conductive layer 124a, thereby allowing the conductor 138 to be electrically connected to the conductive layer 124a. Conductive plug 132 is located between the conductor 138 and the doped region 108. Conductive plug 132 is electrically connected to the conductor 138 and the doped region 108, thereby allowing the conductor 138 to be electrically connected to the doped region 108. In some embodiments, conductive plug 132 may be electrically connected to the doped region 108 via a metal silicide layer 116. Conductive plug 134 is located between the conductor 138 and the doped region 110. Conductive plug 134 is electrically connected to the conductor 138 and the doped region 110, thereby allowing the conductor 138 to be electrically connected to the doped region 110. In some embodiments, the conductive plug 134 can be electrically connected to the doped region 110 via the metal silicide layer 118.
[0075] In some embodiments, the conductive layer 124a can be electrically connected to the metal silicide layer 116 via conductive plug 130, wire 138, and conductive plug 132. In some embodiments, the conductive layer 124a can be electrically connected to the metal silicide layer 118 via conductive plug 130, wire 138, and conductive plug 134.
[0076] In some embodiments, the variable capacitor structure 10 may further include a conductor 140. The conductor 140 is electrically connected to the conductive layer 106. In some embodiments, the variable capacitor structure 10 may further include a conductive plug 136. The conductive plug 136 is located between the conductor 140 and the conductive layer 106. The conductive plug 136 is electrically connected to the conductor 140 and the conductive layer 106, thereby allowing the conductor 140 to be electrically connected to the conductive layer 106.
[0077] Furthermore, the details of each component in the variable container structure 10 (such as materials, arrangement methods, and formation methods) have been described in detail in the above embodiments and will not be described again here.
[0078] Please refer to Figure 1D and Figure 3Capacitor C1 can be a capacitor formed by conductive layer 106, dielectric layer 104, and substrate 100. Variable capacitor C2 can be a variable capacitor formed by the depletion region of the well region 114 directly below the conductive layer 106 (gate). Capacitor C3 can be a capacitor formed by conductive layer 124a, dielectric layer 122, and conductive layer 106. Furthermore, since the variable capacitor structure 10 can include an additional capacitor C3, the variable capacitor structure 10 can have a higher capacitance per unit area. Resistor R1 can be a series resistance between the depletion region capacitance and the wire 138. Resistor R2 can be the resistance of conductive layer 124a. Furthermore, since resistor R1 (resistance of substrate 100) and resistor R2 (resistance of conductive layer 124a) are connected in parallel, the overall resistance can be reduced, thereby improving the quality factor.
[0079] As can be seen from the above embodiments, in the variable capacitor structure 10, the conductive layer 124a is located on the conductive layer 106, the dielectric layer 122 is located between the conductive layer 106 and the conductive layer 124a, and the conductive layer 124a is electrically connected to the doped region 108 and the doped region 110. Therefore, the variable capacitor structure 10 can have a high quality factor and a high unit capacitance.
[0080] In summary, the variable capacitor structure of the above embodiments includes a substrate, a first conductive layer, a second conductive layer, a first dielectric layer, a second dielectric layer, a first doped region, and a second doped region. The first conductive layer is located on the substrate. The second conductive layer is located on the first conductive layer. The first dielectric layer is located between the substrate and the first conductive layer. The second dielectric layer is located between the first conductive layer and the second conductive layer. The first doped region and the second doped region are located in the substrate on both sides of the first conductive layer. The second conductive layer is electrically connected to the first doped region and the second doped region. Therefore, the variable capacitor structure of the above embodiments can have a high quality factor and a high capacitance per unit area.
[0081] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A variable container structure, comprising: Substrate; A first conductive layer is located on the substrate; The second conductive layer is located on the first conductive layer; A first dielectric layer is located between the substrate and the first conductive layer; A second dielectric layer is located between the first conductive layer and the second conductive layer; and The first doped region and the second doped region are located in the substrate on both sides of the first conductive layer, wherein The second conductive layer is electrically connected to the first doped region and the second doped region.
2. The variable container structure according to claim 1 further includes: The first conductive wire is electrically connected to the second conductive layer, the first doped region, and the second doped region.
3. The variable container structure according to claim 2, wherein the top view pattern of the first conductor includes a ring shape.
4. The variable container structure according to claim 2 further includes: The first conductive plug is located between the first wire and the second conductive layer, and is electrically connected to the first wire and the second conductive layer; The second conductive plug is located between the first wire and the first doped region, and is electrically connected to the first wire and the first doped region. as well as The third conductive plug is located between the first wire and the second doped region, and is electrically connected to the first wire and the second doped region.
5. The variable container structure according to claim 4, further comprising: The second wire is electrically connected to the first conductive layer.
6. The variable container structure according to claim 5 further includes: The fourth conductive plug is located between the second conductor and the first conductive layer, and is electrically connected to the second conductor and the first conductive layer.
7. The variable container structure according to claim 1, wherein the first conductive layer and the second conductive layer extend in a first direction.
8. The variable container structure according to claim 7, wherein the length of the first conductive layer in the first direction is greater than the length of the second conductive layer in the first direction.
9. The variable container structure according to claim 7, wherein the first doped region and the second doped region are arranged in a second direction, and the first direction intersects the second direction.
10. The variable capacitor structure according to claim 1, wherein the material of the first conductive layer includes doped polycrystalline silicon or metal.
11. The variable container structure according to claim 1, wherein the material of the second conductive layer includes a metal, a metal compound, or a combination thereof.
12. The variable capacitor structure according to claim 1, wherein the material of the first dielectric layer comprises silicon oxide, a high dielectric constant material, or a combination thereof.
13. The variable capacitor structure according to claim 1, wherein the material of the second dielectric layer comprises a low dielectric constant material or a high dielectric constant material.
14. The variable container structure according to claim 1, further comprising: The spacer is located on the sidewall of the first conductive layer.
15. The variable container structure according to claim 1, further comprising: A well region is located in the substrate, wherein the first doped region and the second doped region are located in the well region.
16. The variable capacitor structure according to claim 15, wherein the first doped region, the second doped region, and the well region have the same conductivity type.
17. The variable container structure according to claim 1, further comprising: An isolation structure is located in the substrate, and an active region is defined in the substrate.
18. The variable capacitor structure according to claim 17, wherein the first doped region and the second doped region are located in the active region.
19. The variable container structure according to claim 17, wherein the isolation structure includes a shallow trench isolation structure.
20. The variable container structure according to claim 1, further comprising: The third dielectric layer is located between the second dielectric layer and the substrate; as well as The fourth dielectric layer is located on the second dielectric layer.