Interdigital capacitor and analog-to-digital conversion circuit

Abstract

The invention discloses an interdigital capacitor and an analog-to-digital conversion circuit, and the interdigital capacitor comprises at least one first metal layer, and each first metal layer is provided with a first electrode, at least one piece of first interdigital metal connected with the first electrode, a second electrode, and a plurality of pieces of second interdigital metal connected with the second electrode. And at least one third interdigital metal connected with the second electrode. Wherein the at least one piece of first interdigital metal and the plurality of pieces of second interdigital metal are alternately arranged to form a capacitor, and the at least one piece of third interdigital metal is dummy interdigital metal.

Description

[0001] This application is a divisional application. The original application has the application number 201980097924.9 and the original application date is June 29, 2019. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of circuit technology, and in particular to an interdigital capacitor and an analog-to-digital converter circuit. Background Technology

[0003] With the rapid development of digital electronics technology, various digital devices, especially digital computers, are widely used in all sectors of the national economy, such as industrial control and communications. Digital devices can only process digital signals; therefore, analog signals (such as temperature and pressure) need to be converted into digital signals by an analog-to-digital converter before digital devices can process them.

[0004] ADCs based on binary weighted capacitor networks (such as pipelined ADCs and charge redistribution successive approximation register (SAR) ADCs) are widely used in digital devices due to their low cost and ease of integration. Among them, the accuracy of the capacitors has a significant impact on the performance of capacitor array-based ADCs.

[0005] For example, the margin gain unit (multiplying digital-to-analog converter, MDAC) is a key circuit in a pipelined ADC, and improving the performance of the MDAC is one of the keys to improving the overall performance of the pipelined ADC. Figure 1 As shown, the MDAC employs a capacitor charge transfer closed-loop structure and a sampling capacitor array, C i For sampling capacitor, C f For closed-loop feedback capacitor, D i = ±1, determined by the output of the sub-ADC in the pipelined ADC, Ф1 and Ф2 are switches controlled by the sample-and-hold control clock, V ref Let be the reference voltage of the sub-DAC. Assuming the gain of operational amplifier A is infinite, the transfer function of the MDAC can be obtained according to the principle of charge conservation:

[0006]

[0007] in C s W is the total sampling capacitance. iThis represents the weight of each unit sampling capacitance. As shown in the above equation, sampling capacitance mismatch will cause a linear gain (C0) in the transfer function. s / C f Errors in the pipelined ADC and the analog-to-digital converter (DAC) cause the final output quantization result to be nonlinear.

[0008] As the accuracy requirements for ADCs based on binary weighted capacitor networks increase, only metal-oxide-metal (MOM) capacitors among existing capacitor types can be manufactured with small capacitance values ​​at a low cost. Therefore, to improve the accuracy of ADCs based on binary weighted capacitor networks, there is an urgent need to propose a high-precision MOM capacitor. Summary of the Invention

[0009] This application provides an interdigital capacitor and an analog-to-digital converter circuit to reduce the mismatch rate of the interdigital capacitor and improve its accuracy.

[0010] In a first aspect, this application provides an interdigital capacitor, comprising: at least one first metal layer, each first metal layer having a first electrode, at least one first interdigital metal connected to the first electrode, a second electrode, a plurality of second interdigital metals connected to the second electrode, and at least one third interdigital metal connected to the second electrode. The at least one first interdigital metal and the plurality of second interdigital metals are alternately disposed to form a capacitor, and the at least one third interdigital metal is a dummy interdigital metal, meaning that the at least one third interdigital metal, at least one first interdigital metal, and any one of the plurality of second interdigital metals will not form a capacitor.

[0011] Through the above scheme, since the first metal layer of the interdigital capacitor contains one or more dummy interdigital metals (third interdigital metals), the capacitance value of the interdigital capacitor can be flexibly changed by adjusting parameters such as the number of first, second, and third interdigital metals, as well as the lengths of the first and second interdigital metals, given a fixed interdigital capacitor layout area. Furthermore, the presence of one or more dummy interdigital metals in the first metal layer allows interdigital capacitors of different capacitance values ​​to have the same layout size, which is beneficial for the layout of the circuit where the interdigital capacitor is located, the rational utilization of area, and reducing process deviations between interdigital capacitors of different capacitance values.

[0012] In one possible implementation, the first metal electrodes in two adjacent first metal layers are interconnected through a first conductive channel, and the second metal electrodes in two adjacent first metal layers are interconnected through a second conductive channel. The first and second conductive channels can be vias filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers.

[0013] In one possible implementation, at least one third interdigital metal is located on the same side of the plurality of second interdigital metals; or, when the interdigital capacitor includes a plurality of third interdigital metals, the plurality of third interdigital metals are located on both sides of the plurality of second interdigital metals.

[0014] In one possible implementation, when the first metal layer includes a plurality of first interdigitated metals, the lengths of the plurality of first interdigitated metals are different.

[0015] In one possible implementation, the lengths of the multiple second interdigital metals are different.

[0016] In one possible implementation, for any first metal layer in the interdigital capacitor, the number of first interdigital metals, the number of second interdigital metals, the effective length of the first interdigital metals, and the distance between adjacent first and second interdigital metals are set according to the capacitance value of the first metal layer. Specifically, the effective length of the first interdigital metal is the length of the portion of the first interdigital metal that can form a sidewall capacitor with an adjacent second interdigital metal; the capacitance value of the first metal layer is positively correlated with the number of first and second interdigital metals and the effective length of the first interdigital metals; and the capacitance value of the first metal layer is negatively correlated with the distance between adjacent first and second interdigital metals.

[0017] In one possible implementation, the distance between two adjacent interdigitated metals in the first metal layer is greater than or equal to a first threshold, and the width of each interdigitated metal in the first metal layer is greater than or equal to a second threshold. When the distance between two adjacent interdigitated metals in the first metal layer is greater than or equal to the first threshold and the width of each interdigitated metal in the first metal layer is greater than or equal to the second threshold, the interdigitated capacitor can be placed both horizontally and vertically.

[0018] In one possible implementation, the distance between two adjacent interdigitated metals in the first metal layer can be greater than or equal to 0.08 μm, and the width of each interdigitated metal in the first metal layer can be greater than or equal to 0.08 μm.

[0019] In one possible implementation, the interdigital capacitor further includes a second metal layer disposed on at least one first metal layer, the second metal layer being used to shield the at least one first metal layer from external environmental interference.

[0020] In one possible implementation, the second metal layer includes a third electrode and a plurality of fourth interdigitated metals respectively connected to the third electrode. The third electrode is electrically connected to a first electrode in a first metal layer adjacent to the second metal layer via a third conductive channel, or the third electrode is electrically connected to a second electrode in a second metal layer adjacent to the second metal layer via a third conductive channel. The third conductive channel can be a via filled with metal (such as tungsten) in a dielectric layer between the second metal layer and the first metal layer adjacent to the second metal layer.

[0021] Furthermore, the second metal layer may also include a fifth electrode, wherein when the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel; when the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel.

[0022] In one possible implementation, the interdigital capacitor may further include a third metal layer disposed beneath at least one first metal layer, the third metal layer being used to shield the at least one first metal layer from external environmental interference.

[0023] In one possible implementation, the third metal layer includes a fourth electrode and a plurality of fifth interdigitated metals respectively connected to the fourth electrode. The fourth electrode is electrically coupled to a first electrode in a first metal layer adjacent to the third metal layer via a fourth conductive channel, or the fourth electrode is electrically connected to a second electrode in a first metal layer adjacent to the third metal layer via a fourth conductive channel. The fourth conductive channel can be a via filled with metal (such as tungsten) in a dielectric layer between the third metal layer and the first metal layer adjacent to the second metal.

[0024] Furthermore, the third metal layer may also include a sixth electrode, wherein when the fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel; when the fourth electrode is electrically coupled to the second electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel.

[0025] In one possible implementation, to meet the metal density requirements of the processing technology in the interdigital capacitor, the interdigital capacitor further includes at least one fourth metal layer. This fourth metal layer is used for density filling, i.e., to increase the metal density of the layer containing the fourth metal layer in the interdigital capacitor. Specifically, at least one fourth metal layer is disposed on top of the interdigital capacitor, meaning all fourth metal layers are disposed on the top of the interdigital capacitor; or, at least one fourth metal layer is disposed on the bottom of the interdigital capacitor, meaning all fourth metal layers are disposed on the bottom of the interdigital capacitor; or, a portion of at least one fourth metal layer is disposed on top of the interdigital capacitor, and another portion of at least one fourth metal layer is disposed on the bottom of the interdigital capacitor.

[0026] In one possible implementation, each fourth metal layer comprises one or more strips of filler metal.

[0027] In one possible implementation, in order to minimize the influence of the filler metal on the interdigital capacitor, the length direction of the filler metal is perpendicular to the length direction of the first interdigital metal and the length direction of the second interdigital metal, respectively.

[0028] In one possible implementation, the interdigital capacitor further includes a substrate in which an intrinsic layer (such as an NT_N layer) is disposed, and at least one first metal layer is disposed on the upper surface of the intrinsic layer to avoid interference from noise in the substrate on the interdigital capacitor.

[0029] In one possible implementation, the interdigital capacitor is a metal-oxide-metal (MOM) capacitor, which includes a plurality of first metal layers stacked in parallel with each other.

[0030] Secondly, this application also provides another type of interdigital capacitor, which includes: at least one first metal layer, each first metal layer having a first electrode, at least one first interdigital metal connected to the first electrode, and a second electrode, and a plurality of second interdigital metals connected to the second electrode. The at least one first interdigital metal and at least one second interdigital metal are alternately arranged to form a capacitor, and the number of second interdigital metals is greater than the number of first interdigital metals.

[0031] In one possible implementation, the first metal electrodes in two adjacent first metal layers are interconnected through a first conductive channel, and the second metal electrodes in two adjacent first metal layers are interconnected through a second conductive channel. The first and second conductive channels can be vias filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers.

[0032] In one possible implementation, when the first metal layer includes a plurality of first interdigitated metals, the lengths of the plurality of first interdigitated metals are different.

[0033] In one possible implementation, the lengths of the multiple second interdigital metals are different.

[0034] In one possible implementation, for any first metal layer in the interdigital capacitor, the number of first interdigital metals, the number of second interdigital metals, the effective length of the first interdigital metals, and the distance between adjacent first and second interdigital metals are set according to the capacitance value of the first metal layer. Specifically, the effective length of the first interdigital metal is the length of the portion of the first interdigital metal that can form a sidewall capacitor with an adjacent second interdigital metal; the capacitance value of the first metal layer is positively correlated with the number of first and second interdigital metals and the effective length of the first interdigital metals; and the capacitance value of the first metal layer is negatively correlated with the distance between adjacent first and second interdigital metals.

[0035] In one possible implementation, the distance between two adjacent first interdigitated metals and second interdigitated metals in the first metal layer is greater than or equal to a first threshold, and the width of the first interdigitated metal and the width of the second interdigitated metal in the first metal layer are greater than or equal to a second threshold. When the distance between two adjacent first interdigitated metals and second interdigitated metals in the first metal layer is greater than or equal to the first threshold, and the width of each interdigitated metal in the first metal layer is greater than or equal to the second threshold, the interdigitated capacitor can be placed both horizontally and vertically.

[0036] In one possible implementation, the distance between two adjacent interdigitated metals in the first metal layer can be greater than or equal to 0.08 μm, and the width of each interdigitated metal in the first metal layer can be greater than or equal to 0.08 μm.

[0037] In one possible implementation, the interdigital capacitor further includes a second metal layer disposed on at least one first metal layer, the second metal layer being used to shield the at least one first metal layer from external environmental interference.

[0038] In one possible implementation, the second metal layer includes a third electrode and a plurality of fourth interdigitated metals respectively connected to the third electrode. The third electrode is electrically connected to a first electrode in a first metal layer adjacent to the second metal layer via a third conductive channel, or the third electrode is electrically connected to a second electrode in a second metal layer adjacent to the second metal layer via a third conductive channel. The third conductive channel can be a via filled with metal (such as tungsten) in a dielectric layer between the second metal layer and the first metal layer adjacent to the second metal layer.

[0039] Furthermore, the second metal layer may also include a fifth electrode, wherein when the third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel; when the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through the third conductive channel, the fifth electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through the fifth conductive channel.

[0040] In one possible implementation, the interdigital capacitor may further include a third metal layer disposed beneath at least one first metal layer, the third metal layer being used to shield the at least one first metal layer from external environmental interference.

[0041] In one possible implementation, the third metal layer includes a fourth electrode and a plurality of fifth interdigitated metals respectively connected to the fourth electrode. The fourth electrode is electrically coupled to a first electrode in a first metal layer adjacent to the third metal layer via a fourth conductive channel, or the fourth electrode is electrically connected to a second electrode in a first metal layer adjacent to the third metal layer via a fourth conductive channel. The fourth conductive channel can be a via filled with metal (such as tungsten) in a dielectric layer between the third metal layer and the first metal layer adjacent to the second metal.

[0042] Furthermore, the third metal layer may also include a sixth electrode, wherein when the fourth electrode is electrically coupled to the first electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel; when the fourth electrode is electrically coupled to the second electrode in the first metal layer adjacent to the third metal layer through the fourth conductive channel, the sixth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through the sixth conductive channel.

[0043] In one possible implementation, to meet the metal density requirements of the processing technology in the interdigital capacitor, the interdigital capacitor further includes at least one fourth metal layer. This fourth metal layer is used for density filling, i.e., to increase the metal density of the layer containing the fourth metal layer in the interdigital capacitor. Specifically, at least one fourth metal layer is disposed on top of the interdigital capacitor, meaning all fourth metal layers are disposed on the top of the interdigital capacitor; or, at least one fourth metal layer is disposed on the bottom of the interdigital capacitor, meaning all fourth metal layers are disposed on the bottom of the interdigital capacitor; or, a portion of at least one fourth metal layer is disposed on top of the interdigital capacitor, and another portion of at least one fourth metal layer is disposed on the bottom of the interdigital capacitor.

[0044] In one possible implementation, each fourth metal layer comprises one or more strips of filler metal.

[0045] In one possible implementation, in order to minimize the influence of the filler metal on the interdigital capacitor, the length direction of the filler metal is perpendicular to the length direction of the first interdigital metal and the length direction of the second interdigital metal, respectively.

[0046] In one possible implementation, the interdigital capacitor further includes a substrate in which an intrinsic layer (such as an NT_N layer) is disposed, and at least one first metal layer is disposed on the upper surface of the intrinsic layer to avoid interference from noise in the substrate on the interdigital capacitor.

[0047] In one possible implementation, the interdigital capacitor is a metal-oxide-metal (MOM) capacitor, which includes a plurality of first metal layers stacked in parallel with each other.

[0048] Thirdly, this application also provides a multiplication digital-to-analog converter circuit, which includes: a switched capacitor array, a feedback capacitor, and an operational amplifier. The switched capacitor array includes k switches and k interdigital capacitors provided in any of the possible embodiments of the first or second aspect described above, each corresponding to one of the k switches, where k is a positive integer. For any one of the k switches, the switch is used to selectively output the voltage to be processed or a reference voltage to the first terminal of the interdigital capacitor corresponding to that switch. The second terminal of the interdigital capacitor corresponding to that switch is coupled to the first input terminal of the operational amplifier and the first terminal of the feedback capacitor, respectively. The second terminal of the operational amplifier is grounded, and the second terminal of the feedback capacitor is coupled to the output terminal of the operational amplifier.

[0049] In one possible implementation, the capacitance values ​​of the k interdigital capacitors are C, 2C, 2C, and 2C, respectively. 2 C,…,2 k-1 C is a constant. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of an MDAC in the prior art;

[0051] Figure 2 This is a schematic diagram of the structure of a MOM capacitor in the prior art;

[0052] Figure 3 A schematic diagram illustrating the relationship between the capacitance value of the interdigital capacitor and the number of interdigital metals in the interdigital capacitor provided in the embodiments of this application;

[0053] Figure 4a This is one of the structural schematic diagrams of an interdigital capacitor provided in an embodiment of this application;

[0054] Figure 4b This is one of the structural schematic diagrams of a first metal layer provided in an embodiment of this application;

[0055] Figure 4c This is a second schematic diagram of the structure of a first metal layer provided in an embodiment of this application;

[0056] Figure 4d This is the third schematic diagram of the structure of a first metal layer provided in the embodiments of this application;

[0057] Figure 4e Fourth schematic diagram of a first metal layer provided in the embodiments of this application;

[0058] Figure 5a A schematic diagram of a horizontally placed interdigital capacitor provided in an embodiment of this application;

[0059] Figure 5b A schematic diagram of a vertically placed interdigital capacitor provided in an embodiment of this application;

[0060] Figure 6 Fifth schematic diagram of the structure of the first metal layer in an interdigital capacitor provided in this application embodiment;

[0061] Figure 7a This is a second schematic diagram of the structure of an interdigital capacitor provided in an embodiment of this application;

[0062] Figure 7b This is the third schematic diagram of an interdigital capacitor provided in the embodiments of this application;

[0063] Figure 7c This is the fourth schematic diagram of an interdigital capacitor provided in the embodiments of this application;

[0064] Figure 8 This is the fifth schematic diagram of an interdigital capacitor provided in the embodiments of this application;

[0065] Figure 9 This is the sixth schematic diagram of an interdigital capacitor provided in the embodiments of this application;

[0066] Figure 10 This is a schematic diagram of a multiplication digital-to-analog converter circuit provided in an embodiment of this application. Detailed Implementation

[0067] MOM capacitors, employing a combination of finger structures and layering, can fabricate capacitors with larger capacitance values ​​within a relatively small area. However, with advancements in manufacturing processes and the increasing parasitic capacitance of traces, the realization of high-precision MOM capacitors has become increasingly challenging. Currently, the capacitance value of MOM capacitors varies with the number of interdigitated metal fingers and the ratio W / L of the interdigitated metal finger width to length, resulting in an inability to achieve a proportional change. This leads to a high capacitance mismatch rate, thus limiting the performance improvement of ADCs based on binary weighted capacitor networks.

[0068] In existing MOM capacitor layouts, the number of interdigitated metal electrodes is 4*N (N is an integer, * indicates multiplication) according to manufacturing process requirements. The capacitance value of the MOM capacitor is mainly formed by the sidewall capacitance of two adjacent interdigitated metal electrodes. For example, Figure 2 The MOM capacitor shown is placed vertically. Assuming the capacitance of a unit capacitance formed by two adjacent interdigitated metal fingers in the MOM capacitor is C0, and assuming the width and length of the interdigitated metal fingers remain constant, the capacitance of the MOM capacitor is 11*C0 when it includes 12 interdigitated metal fingers, and 23*C0 when it includes 24 interdigitated metal fingers. That is, the capacitance of the MOM capacitor is always (M-1)*C0, where M is the number of interdigitated metal fingers in the MOM capacitor. Therefore, when the number of interdigitated metal fingers in the MOM capacitor changes proportionally, the capacitance of the MOM capacitor does not change proportionally. Figure 3 As shown, the actual capacitance value refers to the capacitance value of an existing MOM capacitor, while the ideal capacitance value refers to the capacitance value of a MOM capacitor whose capacitance varies proportionally to the number of interdigitated metal elements. Figure 3 It can be seen that when the number of interdigitated metals in the MOM capacitor changes proportionally, the actual capacitance value is larger than the ideal capacitance value, which will cause the ADC based on the binary weighted capacitor network to produce a linear error.

[0069] In addition, the smallest MOM capacitor provided by the existing 16-nanometer (nm) process library has a capacitance of 2.33 femtofarads (fF), while for ADC circuit designs with high precision requirements, the minimum capacitance value can be as small as 0.25 fF. Therefore, multiple capacitors need to be connected in series, resulting in a large layout area overhead.

[0070] Based on this, this application provides an interdigital capacitor and a multiplicative digital-to-analog converter circuit to improve the above-mentioned defects of existing MOM capacitors.

[0071] This application provides an interdigital capacitor, specifically a MOM capacitor. For example... Figure 4aAs shown, the interdigitated capacitor includes at least one first metal layer 410. Each first metal layer 410 has a first electrode 411, at least one first interdigitated metal 412 connected to the first electrode 411, a second electrode 413, a plurality of (two or more) second interdigitated metals 414 connected to the second electrode 413, and at least one third interdigitated metal 415 connected to the second electrode 413. The at least one first interdigitated metal 412 and the plurality of second interdigitated metals 414 are alternately arranged to form a capacitor. The at least one third interdigitated metal 415 is a dummy interdigitated metal. Those skilled in the art should understand that in integrated circuit design, in addition to designing circuits that can implement the logic or function of the circuit to ensure the correctness of LVS (Layout Versus Schematics) verification, some patterns unrelated to LVS, i.e., dummy circuits, are added according to design requirements. Therefore, it can be understood that the at least one third interdigitated metal 415, as a dummy circuit, will not form a capacitor with any of the at least one first interdigitated metal 412 or the at least one second interdigitated metal 414.

[0072] In this interdigitated capacitor, the first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 are finger-shaped metals connected to the corresponding electrodes. The first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 in the first metal layer 410 are typically multiple parallel conductive electrodes obtained by photolithography and etching of the metal on the first metal layer 410. They are usually arranged in a comb-like (i.e., comb structure) configuration, with the first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 forming the comb teeth. Therefore, the interdigital metals (first interdigital metal 412, second interdigital metal 414, and third interdigital metal 415) in the interdigitated capacitor can also be called electrode interdigitals. At least one first interdigital metal 412 is alternately arranged with multiple second interdigital metals 414, meaning that the first interdigital metal 412 and the second interdigital metal 414 are arranged in a repetitive and alternating manner, for example... Figure 4a As shown, the first metal layer 410 includes two first interdigitated metals 412 and three second interdigitated metals. These five interdigitated metals appear in the horizontal direction in a pattern of first interdigitated metal 412 followed by second interdigitated metal 414.

[0073] When the interdigital capacitor comprises multiple (two or more) first metal layers 410, these multiple first metal layers 410 can be stacked parallel to each other. When the interdigital capacitor is a MOM capacitor, the MOM capacitor typically comprises multiple first metal layers 410 stacked parallel to each other. Further, the first metal electrodes 411 in two adjacent first metal layers 410 are interconnected through a first conductive channel, and the second metal electrodes 413 in two adjacent first metal layers 410 are interconnected through a second conductive channel. The first conductive channel and the second conductive channel can be vias filled with metal (such as tungsten) in the dielectric layer between two adjacent first metal layers 410.

[0074] A dielectric material may be disposed between adjacent first interdigitated metals 412 and second interdigitated metals 414 in the same first metal layer 410. Figure 4a (Not shown in the image, usually an oxide), and adjacent first metal layers 410 can also be separated by a dielectric layer. Figure 4a (Not shown in the image).

[0075] Because the first metal layer 410 of the interdigital capacitor contains one or more dummy interdigital metals—a third interdigital metal 415—the capacitance value of the interdigital capacitor can be flexibly changed by adjusting parameters such as the number of first interdigital metals 412, the number of second interdigital metals 414 and the third interdigital metals 415, and the lengths of the first interdigital metals 412 and the second interdigital metals 414, given a fixed interdigital capacitor layout area. Furthermore, because the first metal layer 410 contains one or more dummy interdigital metals, interdigital capacitors with different capacitance values ​​can have the same layout size. This is beneficial for the layout of the circuit where the interdigital capacitor is located, the rational utilization of area, and reducing process deviations between interdigital capacitors with different capacitance values, thereby improving the matching performance of the interdigital capacitor.

[0076] Furthermore, when the first metal layer 410 includes a plurality of first interdigitated metals 412, the lengths of the plurality of first interdigitated metals 412 are different, and the lengths of the plurality of second interdigitated metals 414 can be the same or different, that is, the lengths of the plurality of first interdigitated metals 412 are different, and the lengths of the plurality of second interdigitated metals 414 are the same, such as... Figure 4b As shown, or, the lengths of the multiple first interdigital metals 412 are different, and the lengths of the multiple second interdigital metals 414 are also different, such as... Figure 4c As shown; or, the lengths of the multiple second interdigitated metals 414 are different, such as Figure 4d As shown. At this time, the capacitance formed by every two adjacent first interdigital metals 412 and second interdigital metals 414 in the first metal layer 410 can be different, so that the capacitance value of the first metal layer 410 can be changed more flexibly according to actual needs.

[0077] It should be noted that different lengths of multiple first interdigital metals 412 refer to some or all of the multiple first interdigital metals 412 having different lengths, and different lengths of multiple second interdigital metals 414 refer to some or all of the multiple second interdigital metals 414 having different lengths.

[0078] Furthermore, such as Figure 4e As shown, at least one third interdigitated metal 415 may be located on the same side of the plurality of second interdigitated metals 414; or, when the interdigitated capacitor includes a plurality of third interdigitated metals 415, the plurality of third interdigitated metals 415 are located on both sides of the plurality of second interdigitated metals 414, as shown. Figure 4a As shown. Furthermore, when the length of the second interdigitated metal 414 is greater than the length of the first interdigitated metal 412 adjacent to it, the third interdigitated metal 415 can also be located at the position opposite to the first interdigitated metal 412 adjacent to it, and the sum of the lengths of the third interdigitated metal 415 and the first interdigitated metal 412 is less than the length of the second interdigitated metal 414. That is, when the first metal layer 410 includes multiple third interdigitated metals 415, some or all of the lengths of the multiple third interdigitated metals 415 can be different.

[0079] In specific implementation, the number of first interdigital metals 412, the number of second interdigital metals 414, the effective length of the first interdigital metals 412 (the effective length of the second interdigital metals 414 forming the sidewall capacitor is the same as the effective length of the first interdigital metals 412 forming the sidewall capacitor), and the distance between adjacent first interdigital metals 412 and second interdigital metals 414 are set according to the capacitance value of the first metal layer 410. Specifically, the effective length of the first interdigital metal 412 is the length of the portion of the first interdigital metal 412 that can form a sidewall capacitor with the adjacent second interdigital metals 414; the capacitance value of the first metal layer 410 is positively correlated with the number of first interdigital metals 412, the number of second interdigital metals 414, and the effective length of the first interdigital metals 412; and the capacitance value of the first metal layer 410 is negatively correlated with the distance between adjacent first interdigital metals 412 and second interdigital metals 414.

[0080] Specifically, for any one of the first metal layers 410 in the interdigital capacitor, the capacitance value of the first metal layer 410 is the sum of the capacitance values ​​of the multiple sidewall capacitors formed by at least one first interdigital metal 412 and multiple second interdigital metals 414 in the first metal layer 410. The sidewall capacitor is the capacitance formed between an adjacent first interdigital metal 412 and a second interdigital metal 414. The interdigital capacitor is obtained by connecting the capacitors of the first metal layer 410 included in the interdigital capacitor in parallel. Therefore, in order to realize the interdigital capacitor with a set capacitance value, the number of sidewall capacitors formed by at least one first interdigital metal 412 and multiple second interdigital metals 414 and the capacitance value of each sidewall capacitor are set according to the capacitance value of the first metal layer 410. The number of sidewall capacitors formed by at least one first interdigital metal 412 and multiple second interdigital metals 414 is related to the number of first interdigital metals 412 and the number of second interdigital metals 414. N1 first interdigital metals 412 and N2 second interdigital metals 414 can form (N1+N2)-1 sidewall capacitors. At this time, the capacitance of the first metal layer 410 is... Among them, C i Let be the capacitance value of the i-th sidewall capacitor among (N1+N2)-1 sidewall capacitors.

[0081] Since the lengths of each first interdigitated metal 412 included in the first metal layer 410 can be the same or different, the lengths of each second interdigitated metal 412 included in the first metal layer 410 can be the same or different, the lengths of the first interdigitated metal 412 and the second interdigitated metal 414 included in the first metal layer 410 can be the same or different, and the distances between any two adjacent first interdigitated metal 412 and second interdigitated metal 412 in the first metal layer 410 can be the same or different, etc., the capacitance values ​​of the N-1 sidewall capacitors may be the same or different. In most cases, the length of each first interdigital metal 412 included in the first metal layer 410 is the same as the length of the second interdigital metal 414, the distance between adjacent first interdigital metal 412 and second interdigital metal 412 is also the same, the capacitance values ​​of (N1+N2)-1 sidewall capacitors are also equal, and the sum of the capacitance values ​​of N-1 sidewall capacitors is ((N1+N2)-1)*C, where C is the capacitance value of any one of the (N1+N2)-1 sidewall capacitors.

[0082] Furthermore, the effective length of the first interdigital metal 412 forming the sidewall capacitor, and the distance between the first interdigital metal 412 forming the sidewall capacitor and the second interdigital metal 414 are set according to the capacitance value of the sidewall capacitor. The effective length of the first interdigital metal is the length of the portion of the first interdigital metal that can form a sidewall capacitor with the adjacent second interdigital metal. The capacitance value of the sidewall capacitor is positively correlated with the length of the shortest interdigitated metal in the first interdigitated metal 412 and the second interdigitated metal 414 that form the sidewall capacitor. That is, when other parameters of the first interdigitated metal 412 and the second interdigitated metal 413 that form the sidewall capacitor (the width of the first interdigitated metal 412 and the width of the second interdigitated metal 414, and the distance between the first interdigitated metal 412 and the second interdigitated metal 414) remain unchanged, the longer the shortest interdigitated metal in the first interdigitated metal 412 and the second interdigitated metal 414 that forms the sidewall capacitor, the larger the capacitance value of the sidewall capacitor; the shorter the shortest interdigitated metal in the first interdigitated metal 412 and the second interdigitated metal 414, the smaller the capacitance value of the sidewall capacitor. The capacitance value of the sidewall capacitor is negatively correlated with the distance between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor. When other parameters of the first interdigital metal 412 and the second interdigital metal 413 forming the sidewall capacitor remain unchanged (width of the first interdigital metal 412 and width of the second interdigital metal 414, length of the first interdigital metal 412 and length of the second interdigital metal 414), the greater the distance between the first interdigital metal 412 forming the sidewall capacitor and the second interdigital metal 414 adjacent to the first interdigital metal 412, the smaller the capacitance value of the sidewall capacitor. The smaller the distance between the first interdigital metal 412 forming the sidewall capacitor and the second interdigital metal 414 adjacent to the first interdigital metal 412, the larger the capacitance value of the sidewall capacitor.

[0083] In the scenario where the width of the first interdigital metal 412 is equal to the width of the second interdigital metal 414, the capacitance C0 of the sidewall capacitor satisfies the following conditions with respect to the effective length L of the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor, the width W of the first interdigital metal 412 (or the second interdigital metal 414), and the distance S between the first interdigital metal 412 and the second interdigital metal 414 forming the sidewall capacitor:

[0084]

[0085] ε is the dielectric constant of the dielectric between the first interdigital metal 412 and the second interdigital metal 414 that form the sidewall capacitor, and L is the length of the portion of the first interdigital metal 412 and the second interdigital metal 414 that can form the capacitor.

[0086] In practical applications, due to limitations in manufacturing processes, the smallest MOM capacitor provided by existing 16nm process libraries has a capacitance of 2.33fF. However, for ADC circuit designs with high precision requirements, the minimum capacitance value needs to be as small as 0.25fF. Therefore, multiple capacitors need to be connected in series, resulting in a large layout area overhead. The interdigital capacitor provided in this application embodiment can achieve a smaller capacitance value by adjusting the length of the first interdigital metal 412, the length of the second interdigital metal, the number of first interdigital metal 412, and the number of second interdigital metal 414. For example, the interdigital capacitor provided in this application embodiment can reach 1.202fF or even smaller. Compared to the smallest capacitor of 2.33178fF provided by existing process libraries, the capacitance value of the interdigital capacitor provided in this application embodiment is reduced by 50%. Specifically, the distance between two adjacent first interdigital metal 412 and second interdigital metal 414 can be greater than or equal to 0.08μm.

[0087] Furthermore, during the manufacturing process of interdigital capacitors, the requirements for the distance between adjacent interdigital metal fingers and the width of the interdigital metal fingers also differ depending on the placement orientation (horizontal or vertical). Therefore, to ensure that interdigital capacitors can be placed horizontally (e.g., ...), the manufacturing process requires different techniques. Figure 5a It can also be placed vertically (e.g.) Figure 5b As shown in the diagram, the interdigital capacitor can be arbitrarily flipped. The distance between any two adjacent interdigital metals in the first metal layer 410 (including the distance between adjacent first interdigital metals 412 and second interdigital metals 414, adjacent second interdigital metals 414 and third interdigital metals 415, and the distance between adjacent third interdigital metals) is greater than or equal to a first threshold. The width of each interdigital metal in the first metal layer 410 (including the width of the first interdigital metal 412, the width of the second interdigital metal 414, and the distance between the third interdigital metals 415) is greater than or equal to a second threshold to satisfy the minimum width and spacing design rule check (DRC) for horizontal and vertical placement, allowing the interdigital capacitor to be placed both horizontally and vertically. For a 16nm process library, the first threshold can be 0.08μm, and the second threshold can also be 0.08μm.

[0088] For example, such as Figure 6 The first metal layers 410 shown in (a)-(d) have the same area, and the width of the first interdigitated metal 412, the width of the second interdigitated metal 414, and the distance between two adjacent first interdigitated metal 412 and second interdigitated metal 414 in the first metal layers 410 shown in (a)-(d) are the same. Figure 6The first metal layer 410 shown in (a) includes one first interdigitated metal 412, two second interdigitated metals 414 and seven third interdigitated metals 415. The length of the portion of the first interdigitated metal 412 and the second interdigitated metal 414 that can form a capacitor, that is, the effective length of the first interdigitated metal 412 and the second interdigitated metal 414, is L. At this time, the capacitance of the first metal layer 410 is C1. Figure 6 The first metal layer 410 shown in (b) includes one first interdigitated metal 412, two second interdigitated metals 414 and six third interdigitated metals 415. The length of the portion of the first interdigitated metal 412 and the second interdigitated metal 414 that can form a capacitor, that is, the effective length of the first interdigitated metal 412 and the second interdigitated metal 414, is 2L. At this time, the theoretical value of the capacitance of the first metal layer 410 is 2C1. Figure 6 The first metal layer 410 shown in (c) includes two first interdigitated metals 412, three second interdigitated metals 414, and four third interdigitated metals 415. The length of the first interdigitated metals 412 and the second interdigitated metals 414 that can form the capacitor portion, i.e., the effective length of the first interdigitated metals 412 and the second interdigitated metals 414, is 2L. At this time, the theoretical capacitance of the first metal layer 410 is 4C1, and different capacitance values ​​can be obtained by analogy. Since the third interdigitated metals 415 in the first metal layer 410 are dummy metals, they do not contribute to the capacitance value of the first metal layer 410. Therefore, when the first metal layer 410 needs to be configured to a larger capacitance value, the first metal layer 410 may not have any third interdigitated metals, such as... Figure 6 The first metal layer 410 shown in (d) includes four first interdigitated metals 412 and five second interdigitated metals 414. The length of the first interdigitated metals 412 and the second interdigitated metals 414 that can form a capacitor portion, i.e., the effective length of the first interdigitated metals 412 and the second interdigitated metals 414, is 2L. At this time, the theoretical value of the capacitance of the first metal layer 410 is 8C1.

[0089] In the scenario where the first metal layer 410 does not include the third interdigitated metal 415, the number of first interdigitated metals 412 and the number of second interdigitated metals 414 in the first metal layer 410 are not equal. The difference between the number of first interdigitated metals 412 and the number of second interdigitated metals 414 in the first metal layer 410 is 1, so that the capacitance value of the first metal layer 410 can change proportionally. For example, as... Figure 6 As shown in (d).

[0090] When the width of the first interdigital metal 412 and the width of the second interdigital metal 414 are both 0.08 micrometers (μm), and L is 3.16 μm, for Figure 6Simulation of the layout of the first metal layer 410 shown in (a)-(d) yields the results shown in Table 1. Table 1 shows that by adjusting parameters such as the number of first interdigital metals 412, the number of second interdigital metals 412, and the effective lengths of the first interdigital metals 412 and second interdigital metals 414 in the first metal layer 410, the capacitance value of the interdigital capacitor can be proportionally changed. Since the capacitance value in the capacitor network of an ADC based on a capacitor network typically changes according to a geometric progression with a common ratio of 2, when the interdigital capacitor provided in this application is used in the capacitor network of an ADC based on a capacitor network, the interdigital capacitor provided in this embodiment can achieve high-precision interdigital capacitance by adjusting the parameters of the first interdigital metals 412 and second interdigital metals 414 in the first metal layer, and the capacitance value of the interdigital capacitor can change proportionally. Therefore, it can effectively improve the conversion accuracy and linearity of the output result of the ADC based on the capacitor network.

[0091] Table 1 Simulation results of capacitor values

[0092]

[0093] In addition, in specific implementations, in order to shield the influence of the external environment on the interdigital capacitor, the interdigital capacitor provided in this application embodiment also includes a second metal layer 420 disposed on at least one first metal layer 410. The second metal layer 420 is used to shield the interference of the external environment on at least one first metal layer 410.

[0094] Specifically, such as Figure 7a As shown, the second metal layer 420 includes a third electrode 421 and a plurality of fourth interdigitated metals 422 respectively connected to the third electrode 421. The third electrode 421 is electrically connected to a first electrode 411 in the adjacent first metal layer 410 via a third conductive channel, or the third electrode 421 is electrically connected to a second electrode 413 in the adjacent second metal layer 410 via a third conductive channel. The third conductive channel can be a via filled with metal (such as tungsten) in the dielectric layer between the second metal layer 420 and the adjacent first metal layer 410.

[0095] Furthermore, the second metal layer 420 may also include a fifth electrode 423, wherein when the third electrode 421 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the second metal layer 420 through the third conductive channel, the fifth electrode 423 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the second metal layer 420 through the fifth conductive channel; when the third electrode 421 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the second metal layer 420 through the third conductive channel, the fifth electrode 423 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the second metal layer 420 through the fifth conductive channel.

[0096] In addition, to ensure that the parasitic capacitance generated by the fourth interdigital metal 422 in the second metal layer 420 on the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer 420 is the same and to avoid capacitance mismatch, the distance between the fourth interdigital metal 422 corresponding to the first interdigital metal 412 and the fourth interdigital metal 422 corresponding to the second interdigital metal 414 is the same as the distance between the first interdigital metal 412 and the second interdigital metal 414. The size parameters (length, width, etc.) of the fourth interdigital metal 422 corresponding to the first interdigital metal 412 in the second metal layer 420 are the same as the parameters (length, width, etc.) of the fourth interdigital metal 422 corresponding to the second interdigital metal 414 in the second metal layer 420.

[0097] In order to shield the interdigital capacitor from the influence of the external environment, the interdigital capacitor provided in this application embodiment may further include a third metal layer 430 disposed below at least one first metal layer 410. The third metal layer 430 is used to shield the interference of the external environment on at least one first metal layer 410.

[0098] Specifically, such as Figure 7b As shown, the third metal layer 430 includes a fourth electrode 431 and a plurality of fifth interdigitated metals 432 respectively connected to the fourth electrode 431. The fourth electrode 431 is electrically coupled to a first electrode 411 in the adjacent first metal layer 410 via a fourth conductive channel, or the fourth electrode 431 is electrically connected to a second electrode 413 in the adjacent first metal layer 410 via a fourth conductive channel. The fourth conductive channel can be a via filled with metal (such as tungsten) in the dielectric layer between the third metal layer 430 and the adjacent first metal layer 410.

[0099] The third metal layer 430 may further include a sixth electrode 433, wherein when the fourth electrode 431 is electrically coupled to the first electrode 411 in the first metal layer 410 adjacent to the third metal layer 430 through the fourth conductive channel, the sixth electrode 433 is electrically connected to the second electrode 413 in the first metal layer 410 adjacent to the third metal layer 430 through the sixth conductive channel; when the fourth electrode 431 is electrically coupled to the second electrode 413 in the first metal layer 410 adjacent to the third metal layer 430 through the fourth conductive channel, the sixth electrode 433 is electrically connected to the first electrode 411 in the first metal layer 410 adjacent to the third metal layer 430 through the sixth conductive channel.

[0100] In addition, to ensure that the parasitic capacitance generated by the fifth interdigital metal 432 in the third metal layer 430 on the first interdigital metal 412 and the second interdigital metal 414 in the first metal layer 420 is the same and to avoid capacitance mismatch, the distance between the fifth interdigital metal 432 corresponding to the first interdigital metal 412 and the fifth interdigital metal 432 corresponding to the second interdigital metal 414 is the same as the distance between the first interdigital metal 412 and the second interdigital metal 414. The parameters (length, width, etc.) of the fifth interdigital metal 432 corresponding to the first interdigital metal 412 in the third metal layer 430 are the same as the parameters (length, width, etc.) of the fifth interdigital metal 432 corresponding to the second interdigital metal 414 in the third metal layer 430.

[0101] In other words, the interdigital capacitor provided in this application embodiment may include any one of the second metal layer 420 and the third metal layer 430, such as Figure 7a or Figure 7b As shown, or simultaneously including a second metal layer 420 and a third metal layer 430, such as Figure 7c As shown.

[0102] Furthermore, in order to meet the requirements of the processing technology regarding the metal density in interdigital capacitors, such as... Figure 8 As shown, the interdigital capacitor provided in this embodiment further includes at least one fourth metal layer 440, which is used for density filling, i.e., to increase the metal density of the layer containing the fourth metal layer 440 in the interdigital capacitor. Specifically, at least one fourth metal layer 440 is disposed on the top of the interdigital capacitor, meaning all fourth metal layers 440 are disposed on the top of the interdigital capacitor; or, at least one fourth metal layer 440 is disposed on the bottom of the interdigital capacitor, meaning all fourth metal layers 440 are disposed on the bottom of the interdigital capacitor; or, a portion of at least one fourth metal layer 440 is disposed on the top of the interdigital capacitor, and another portion of at least one fourth metal layer 440 is disposed on the bottom of the interdigital capacitor.

[0103] In a scenario where the interdigitated capacitor does not include the second metal layer 420 and the third metal layer 430, the top of the interdigitated capacitor points above at least one first metal layer 410 (i.e., above the topmost first metal layer 410 among at least one first metal layer 410), and the bottom of the interdigitated capacitor points below at least one first metal layer 410 (i.e., below the bottommost first metal layer 410 among at least one first metal layer 410). In a scenario where the interdigitated capacitor includes the second metal layer 420 but does not include the third metal layer 430, the top of the interdigitated capacitor points above the second metal layer 420, and the bottom of the interdigitated capacitor points below at least one first metal layer 410 (i.e., below the bottommost first metal layer 410 among at least one first metal layer 410). In a scenario where the interdigitated capacitor includes the third metal layer 430 but does not include the second metal layer 420, the top of the interdigitated capacitor points above at least one first metal layer 410 (i.e., above the topmost first metal layer 410 among at least one first metal layer 410), and the bottom of the interdigitated capacitor points below the third metal layer 430. In a scenario where the interdigital capacitor includes a second metal layer 420 and a third metal layer 430, the top of the interdigital capacitor points above the second metal layer 420, and the bottom of the interdigital capacitor points below the third metal layer 430.

[0104] In a specific implementation, each fourth metal layer 440 may include one or more strip-shaped metals. To minimize the impact of the strip-shaped metals on the interdigital capacitance, the length direction of the strip-shaped metals is perpendicular to the length direction of the first interdigital metal 412. Typically, the first interdigital metal 412, the second interdigital metal 414, and the third interdigital metal 415 in the first metal layer 410 are arranged in parallel. Therefore, the perpendicularity of the length direction of the strip-shaped metals to the length direction of the first interdigital metal 412 also means that the length direction of the strip-shaped metals is perpendicular to the length directions of both the second interdigital metal 414 and the third interdigital metal 415.

[0105] Furthermore, such as Figure 9 As shown, the interdigital capacitor provided in this embodiment further includes a substrate 450, in which an intrinsic layer (such as an NT_N layer) 451 is disposed. At least one first metal layer 410 is disposed on the upper surface of the intrinsic layer 451 to avoid interference from noise in the substrate 450 on the interdigital capacitor. The substrate 450 is typically a semiconductor material, such as single-crystal, crystalline, or amorphous silicon or silicon-germanium (SiGe). It can also be a mixed semiconductor material, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. The intrinsic layer 451 refers to the undoped region.

[0106] Through the above solution, the interdigital capacitor provided in this application embodiment includes a first interdigital metal 412 and a second interdigital metal 413 capable of forming a capacitor, as well as a dummy interdigital metal (i.e., a third interdigital metal). By adjusting the parameters of the first interdigital metal 412 and the second interdigital metal 414, such as the length of the first interdigital metal 412 and the length of the second interdigital metal, the number of the first interdigital metal 412 and the number of the second interdigital metal 414, the capacitance value of the interdigital capacitor can be finely adjusted. Compared with the prior art, it can provide an interdigital capacitor with higher precision and flexible capacitance value.

[0107] Based on the above embodiments, this application also provides a multiplication digital-to-analog converter circuit, which can be applied to pipelined analog-to-digital converters. For example... Figure 10 As shown, the multiplication digital-to-analog converter circuit includes: a switched capacitor array 1010, a feedback capacitor Cf, and an operational amplifier 1020. The switched capacitor array 1010 includes k switches (S1, S2, ..., Sk) and k interdigital capacitors (C1, C2, ..., Ck) of any type provided in the above embodiments, each corresponding to one of the k switches, where k is a positive integer. For any one of the k switches, the first terminal of the switch is used to selectively output the voltage to be processed or the reference voltage to the first terminal of the interdigital capacitor corresponding to the switch. The second terminal of the interdigital capacitor corresponding to the switch is coupled to the first input terminal of the operational amplifier 1020 and the first terminal of the feedback capacitor Cf, respectively. The second terminal of the operational amplifier 1020 is grounded, and the second terminal of the feedback capacitor Cf is coupled to the output terminal of the operational amplifier 1030.

[0108] The switches in the switched capacitor array 1010 can be controllable switches such as metal oxide field-effect transistors (MOS) or transistors.

[0109] In a specific implementation, for any one of the k switches, the switch includes a first signal input terminal, a second signal input terminal, and a signal output terminal. The first signal input terminal is used to input the voltage to be processed, the second signal input terminal is used to input a reference voltage, and the signal output terminal is used to selectively output the voltage to be processed or the reference voltage to the first terminal of the interdigital capacitor corresponding to the switch.

[0110] This switch selectively outputs either the voltage to be processed or a reference voltage to the first terminal of the interdigitated capacitor corresponding to the switch, typically controlled by a sample-and-hold signal. The switch may also include a control terminal for inputting the sample-and-hold signal. Specifically, during the sampling phase, under the control of the sample-and-hold signal, the switch opens the path between the first signal input terminal and the signal output terminal, closes the path between the second signal input terminal and the signal output terminal, and outputs the voltage to be processed to the first terminal of the interdigitated capacitor corresponding to the switch. During the holding phase, the path between the first signal input terminal and the signal output terminal is closed, and the path between the second signal input terminal and the signal output terminal is opened, and the reference voltage is output to the first terminal of the interdigitated capacitor corresponding to the switch. This switch can be two single-pole single-throw switches or one single-pole multi-throw switch (such as a single-pole double-throw switch).

[0111] Furthermore, the capacitance values ​​of the k interdigital capacitors are C, 2C, 2 2 C,…,2 k-1 C, C are constants. The capacitance values ​​are C, 2C, and 2, respectively. 2 C,…,2 k-1 The k interdigitated capacitors of C can be achieved by adjusting one or more of the following parameters: the length of the first interdigitated metal 412, the length of the second interdigitated metal, the number of the first interdigitated metal 412, the number of the second interdigitated metal 414, and the distance between the first interdigitated metal 412 and the second interdigitated metal 414.

[0112] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An interdigital capacitor, characterized in that, include: A first metal layer, wherein the first metal layer is provided with: First electrode; At least one first interdigitated metal electrically connected to the first electrode; Second electrode; A plurality of second interdigital metals and at least one third interdigital metal electrically connected to the second electrode; Wherein, the at least one first interdigital metal is alternately disposed with the plurality of second interdigital metals, and the at least one third interdigital metal is a dummy interdigital metal.

2. The interdigital capacitor as described in claim 1, characterized in that, The at least one third interdigital metal is located on the same side of the plurality of second interdigital metals; Alternatively, when the first metal layer includes a plurality of third interdigital metals, the plurality of third interdigital metals are located on both sides of the plurality of second interdigital metals.

3. The interdigital capacitor as described in claim 1 or 2, characterized in that, When the first metal layer includes a plurality of first interdigitated metals, the lengths of the plurality of first interdigitated metals are different.

4. The interdigital capacitor as described in any one of claims 1-3, characterized in that, The lengths of the multiple second interdigital metals are different.

5. The interdigital capacitor as described in any one of claims 1-4, characterized in that, The number of the first interdigital metals, the number of the second interdigital metals, the effective length of the first interdigital metals, and the distance between adjacent first interdigital metals and second interdigital metals are set according to the capacitance value of the first metal layer. Wherein, the effective length of the first interdigital metal is the length of the portion of the first interdigital metal that can form a sidewall capacitor with the adjacent second interdigital metal; the capacitance of the first metal layer is positively correlated with the number of the first interdigital metals, the number of the second interdigital metals, and the effective length of the first interdigital metals; the capacitance of the first metal layer is negatively correlated with the distance between adjacent first and second interdigital metals.

6. The interdigital capacitor as described in any one of claims 1-5, characterized in that, The first metal layers are multiple and stacked, and the first electrodes in two adjacent first metal layers are connected through a first conductive channel, and the second electrodes in two adjacent first metal layers are connected through a second conductive channel.

7. The interdigital capacitor as described in any one of claims 1-6, characterized in that, Also includes: A second metal layer is disposed on top of the first metal layer; the second metal layer is used to shield the first metal layer from interference from the external environment.

8. The interdigital capacitor as described in claim 7, characterized in that, The second metal layer includes a third electrode and a plurality of fourth interdigital metals respectively connected to the third electrode; The third electrode is electrically connected to the first electrode in the first metal layer adjacent to the second metal layer through a third conductive channel, or the third electrode is electrically connected to the second electrode in the first metal layer adjacent to the second metal layer through a third conductive channel.

9. The interdigital capacitor as described in any one of claims 1-8, characterized in that, Also includes: A third metal layer is disposed below the first metal layer; the third metal layer is used to shield the first metal layer from interference from the external environment.

10. The interdigital capacitor as described in claim 9, characterized in that, The third metal layer includes a fourth electrode and a plurality of fifth interdigital metals respectively connected to the fourth electrode; The fourth electrode is electrically connected to the first electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel, or the fourth electrode is electrically connected to the second electrode in the first metal layer adjacent to the third metal layer through a fourth conductive channel.

11. The interdigital capacitor as described in any one of claims 1-10, characterized in that, Also includes: At least one fourth metal layer, the fourth metal layer being used for metal density filling; The at least one fourth metal layer is disposed on top of the interdigital capacitor; Alternatively, at least one fourth metal layer may be disposed at the bottom of the interdigitated capacitor; or, a portion of the at least one fourth metal layer may be disposed at the top of the multilayer first metal layer, and another portion of the at least one fourth metal layer may be disposed at the bottom of the multilayer first metal layer.

12. The interdigital capacitor as described in claim 11, characterized in that, Each fourth metal layer comprises one or more strip metals.

13. The interdigital capacitor as described in claim 12, characterized in that, The length direction of the strip metal is perpendicular to the length direction of the first interdigitated metal.

14. The interdigital capacitor as described in any one of claims 1-13, characterized in that, Also includes: A substrate having an intrinsic layer therein, wherein the first metal layer is disposed on the upper surface of the intrinsic layer.

15. The interdigital capacitor as described in any one of claims 1-14, characterized in that, The distance between two adjacent interdigitated metals in the first metal layer is greater than or equal to a first threshold, and the width of each interdigitated metal in the first metal layer is greater than or equal to a second threshold.

16. The interdigital capacitor as described in any one of claims 1-15, characterized in that, The interdigital capacitor is a metal-oxide-metal (MOM) capacitor, and the MOM capacitor includes multiple first metal layers stacked in parallel.

17. A multiplication digital-to-analog converter circuit, characterized in that, include: Switched capacitor array, feedback capacitor, and operational amplifier; The switched capacitor array includes k switches and k interdigital capacitors as described in any one of claims 1-16, each corresponding to one of the k switches, where k is a positive integer. For any one of the k switches, the switch is used to selectively output the voltage to be processed or the reference voltage to the first terminal of the interdigital capacitor corresponding to the switch, and the second terminal of the interdigital capacitor corresponding to the switch is coupled to the first input terminal of the operational amplifier and the first terminal of the feedback capacitor, respectively. The second terminal of the operational amplifier is grounded, and the second terminal of the feedback capacitor is coupled to the output terminal of the operational amplifier.

18. The circuit as described in claim 17, characterized in that, The capacitance values ​​of the k interdigital capacitors are C, 2C, 2 2 C,…,2 k-1 C is a constant.

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