Formation method of semiconductor structure
By etching away the composite layer on both sides of the pseudo-gate structure and growing an epitaxial layer along the first sacrificial layer lattice, the problem of small channel volume in the BDI structure is solved, and the performance and operating current of the GAA structure are improved.
Patent Information
- Application Number
- CN202410497619.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-23
- Publication Date
- 2025-10-31
AI Technical Summary
The performance of existing GAAs containing BDI structures still needs improvement, especially the problem of limited operating current caused by the small volume of the channel region in the fin.
By etching away the composite layer on both sides of the pseudo-gate structure, the surface of the first sacrificial layer is exposed, forming an epitaxial layer. The epitaxial layer is then grown along the lattice of the first sacrificial layer from bottom to top. An isolation trench is then formed between the composite layer and the substrate, and a bottom isolation layer is filled in the isolation trench to prevent the formation of holes.
This improves the formation quality of the epitaxial layer, enhances the performance of the semiconductor structure, and increases the volume of the channel region, thereby increasing the operating current of the GAA structure MOSFET.
Smart Images
Figure CN120882022A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] With the further development of semiconductor technology, traditional fin field-effect transistors (FETs) face limitations in increasing their operating current. Specifically, because only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the channel region within the fin is relatively small, which limits the increase in the operating current of the FET. Therefore, a gate all-around (GAA) MOSFET structure has been proposed, which increases the volume of the channel region and further increases the operating current of the GAA structure MOSFET.
[0003] In the GAA structure, the BDI (Bottom Dielectric Isolation) structure can effectively block leakage current at the three terminals of the fin, source, and drain, and has broad application prospects.
[0004] However, the performance of GAAs containing the BDI structure still needs to be improved. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of GAA containing a BDI structure.
[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of discretely arranged fins on the substrate, each fin including a first sacrificial layer and a plurality of overlapping composite layers located on the surface of the first sacrificial layer, the composite layers including a second sacrificial layer and a channel layer located on the surface of the second sacrificial layer; forming a plurality of discrete dummy gate structures across the fins on the substrate, the dummy gate structures covering a portion of the sidewalls and top surface of the fins; etching away the composite layers on both sides of the dummy gate structures to expose the surface of the first sacrificial layer; forming an epitaxial layer on the surface of the first sacrificial layer; removing the first sacrificial layer to form an isolation trench between the composite layer and the substrate; and forming a bottom isolation layer within the isolation trench.
[0007] Optionally, the method for forming the epitaxial layer includes: forming a first epitaxial layer using a first epitaxial growth process; forming a second epitaxial layer using a second epitaxial growth process, wherein the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer, and the concentration of germanium atoms in the reaction gas used in the first epitaxial growth process is less than the concentration of germanium atoms in the reaction gas used in the second epitaxial growth process.
[0008] Optionally, the process parameters of the first epitaxial growth process include a germanium atom concentration of less than 30% and a reaction temperature of greater than 500°C.
[0009] Optionally, the process parameters of the second epitaxial growth process include a germanium atom concentration greater than 30% and a reaction temperature greater than 500°C.
[0010] Optionally, the material of the epitaxial layer is silicon-germanium.
[0011] Optionally, before removing the first sacrificial layer, the method further includes forming a capping layer on the surface of the epitaxial layer, the capping layer being made of the same material as the first sacrificial layer.
[0012] Optionally, the material of the bottom insulating layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.
[0013] Optionally, before etching away the composite layers on both sides of the dummy gate structure to expose the surface of the first sacrificial layer, the method further includes: forming a protective layer on the substrate, the protective layer being formed on the surfaces of the fins on both sides of the dummy gate structure and the sidewall surfaces of the dummy gate structure.
[0014] Optionally, after etching away the composite layers on both sides of the pseudo-gate structure to expose the surface of the first sacrificial layer, and before forming an epitaxial layer on the surface of the first sacrificial layer, the method further includes forming a spacer layer on the sidewall surface of the etched composite layer.
[0015] Optionally, the material of the spacer layer includes one or more of boron nitride, silicon nitride, and silicon oxide.
[0016] Optionally, the material of the first sacrificial layer is silicon-germanium, and the mass percentage of germanium atoms in the first sacrificial layer ranges from 40% to 60%.
[0017] Optionally, the material of the second sacrificial layer is silicon-germanium, and the mass percentage of germanium atoms in the second sacrificial layer ranges from 20% to 35%.
[0018] Optionally, it may also include an isolation structure formed on the substrate, wherein the top surface of the isolation structure is lower than or flush with the bottom surface of the bottom isolation layer.
[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0020] In the formation method of the technical solution of the present invention, the composite layers on both sides of the pseudo-gate structure are etched away to expose the surface of the first sacrificial layer. An epitaxial layer is formed on the surface of the first sacrificial layer. After the epitaxial layer is formed, the first sacrificial layer is removed. An isolation trench is formed between the composite layer and the substrate. A bottom isolation layer is formed in the isolation trench. The epitaxial layer can grow along the lattice of the first sacrificial layer. The epitaxial layer grows from the surface of the first sacrificial layer from bottom to top, which can avoid the existence of holes between the contact surface of the first sacrificial layer and the epitaxial layer, improve the formation quality of the epitaxial layer, and has a wide range of applications.
[0021] Furthermore, in the process of forming the epitaxial layer, the first epitaxial layer is first formed using a first epitaxial growth process, and then the second epitaxial layer is formed using a second epitaxial growth process. The concentration of germanium atoms in the first epitaxial growth process is lower than that in the second epitaxial growth process. By using a low concentration of germanium atoms as a transition layer and then using a high concentration of germanium atoms to form the epitaxial layer, the difficulty of germanium atom filling is reduced, the concentration of germanium atoms in the center is guaranteed, stress loss is eliminated, and the quality of the final epitaxial layer is improved, which helps to improve the performance of the semiconductor structure. Attached Figure Description
[0022] Figures 1 to 4 This is a schematic diagram of the steps in a method for forming a semiconductor structure in one embodiment.
[0023] Figures 5 to 25 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0024] As mentioned in the background section, the performance of existing GAAs containing BDI structures still needs improvement. Please refer to [link / reference needed]. Figures 1 to 4 Please provide an explanation.
[0025] Please refer to Figure 1 A substrate 100 is provided, on which a plurality of discretely arranged fins 101 are formed. Each fin 101 includes a first sacrificial layer 101a and a plurality of overlapping composite layers located on the surface of the first sacrificial layer 101a. The composite layers include a second sacrificial layer 101b and a channel layer 101c located on the surface of the second sacrificial layer 101b. A plurality of discrete pseudo-gate structures 102 are formed on the substrate 100, spanning the fins. The pseudo-gate structures 102 cover a portion of the sidewalls and top surface of the fins 101.
[0026] Please refer to Figure 2 Remove the first sacrificial layer 101a and form an isolation trench 103 between the surfaces of the composite layer and the substrate.
[0027] Please refer to Figure 3 A bottom isolation layer 104 is formed within the isolation groove 103.
[0028] Please refer to Figure 4 The fins 101 on both sides of the pseudo-gate structure 102 are etched to expose the bottom isolation layer 101, and a groove is formed in the fins 101; an epitaxial layer 105 is formed inside and outside the groove.
[0029] The inventors discovered that after the bottom isolation layer is formed, the epitaxial layer is formed on the surface of the bottom isolation layer. The epitaxial layer can only grow along the sidewall of the groove. As a result, after the epitaxial layer is formed, a hole will be formed between the epitaxial layer and the bottom isolation layer. Furthermore, since the epitaxial layer grows along the sidewall of the groove, as the sidewall epitaxial layers merge, it becomes more difficult for the epitaxial layer to fill the groove, and gaps will appear in the center of the epitaxial layer, affecting the formation quality of the epitaxial layer.
[0030] Based on this, the present invention provides a method for forming a semiconductor structure in which the composite layers on both sides of the dummy gate structure are etched away to expose the surface of the first sacrificial layer, an epitaxial layer is formed on the surface of the first sacrificial layer, the first sacrificial layer is removed after the epitaxial layer is formed, an isolation trench is formed between the composite layer and the substrate, a bottom isolation layer is formed in the isolation trench, and the epitaxial layer can grow along the lattice of the first sacrificial layer. The epitaxial layer grows from the surface of the first sacrificial layer from bottom to top, which can avoid the existence of holes between the contact surface of the first sacrificial layer and the epitaxial layer, improve the formation quality of the epitaxial layer, and has a wide range of applications.
[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] Figures 5 to 25 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.
[0033] First, please refer to Figure 5 and Figure 7 A substrate 200 is provided, on which a plurality of discretely arranged fins 201 are formed. Each fin 201 includes a first sacrificial layer 202 and a plurality of overlapping composite layers 203 located on the surface of the first sacrificial layer 202. The composite layer 203 includes a second sacrificial layer 203a and a channel layer 203b located on the surface of the second sacrificial layer 203a. A plurality of discrete pseudo-gate structures 204 are formed on the substrate 200 across the fins 201. The pseudo-gate structures 204 cover part of the sidewalls and top surface of the fins 201.
[0034] Figure 6 for Figure 5 Cross-sectional view of AA; Figure 7 for Figure 5 Cross-sectional view at BB.
[0035] In this embodiment, the fin 201 further includes a bottom structure 201a located between the first sacrificial layer 201 and the substrate 200.
[0036] In this embodiment, the number of fins 201 is three; the number of layers of the second sacrificial layer 203a is three; and the number of layers of the channel layer 203b is three.
[0037] In this embodiment, the method for forming the fin 201 includes: forming a fin material film (not shown) on the substrate 200, the fin material film including a plurality of sacrificial material films overlapping along the normal direction of the surface of the substrate 200, and a channel material film located between two adjacent sacrificial material films; forming a patterned layer (not shown) on the fin material film; etching the fin material film using the patterned layer as a mask until the top surface of the substrate 200 is exposed to form the fin 201, the structure of the fin 201 including a first sacrificial layer 202 and a plurality of overlapping composite layers 203 located on the surface of the first sacrificial layer 201, the composite layer 203 including a second sacrificial layer 203a and a channel layer 203b located on the surface of the second sacrificial layer 203a.
[0038] In this embodiment, the dummy gate structure 204 includes a gate oxide layer formed on the surface of the fin 201, a dummy gate layer 204a formed on the surface of the gate oxide layer, and a cap layer 204b formed on top of the dummy gate layer.
[0039] In this embodiment, the cap layer 204b is a stacked structure.
[0040] In other embodiments, the cap layer 204b may also be a single-layer structure.
[0041] In this embodiment, the cap layer 204b serves to protect the shape of the dummy gate layer 204a and prevent it from being damaged in subsequent processes.
[0042] In this embodiment, the material of the pseudo-gate layer 204a is polycrystalline silicon.
[0043] In this embodiment, the channel layer 203b is made of silicon.
[0044] In this embodiment, the material of the first sacrificial layer 202 is silicon germanium, and the mass percentage of germanium atoms in the first sacrificial layer 202 ranges from 40% to 60%. Specifically, the mass percentage of germanium atoms in the first sacrificial layer 202 is 50%.
[0045] In this embodiment, the material of the second sacrificial layer 203a is silicon germanium, and the mass percentage of germanium atoms in the second sacrificial layer 203a ranges from 20% to 35%. Specifically, the mass percentage of germanium atoms in the second sacrificial layer 203a is 30%.
[0046] In this embodiment, an isolation structure 211 is also formed on the substrate 200, the top surface of the isolation structure 211 being lower than or flush with the bottom surface of the first sacrificial layer 202.
[0047] Please refer to Figures 8 to 10 A protective layer 205 is formed on the substrate 200. The protective layer 205 is formed on the surface of the fins 201 on both sides of the pseudo-gate structure 204 and on the sidewall surface of the pseudo-gate structure 204.
[0048] Figure 9 for Figure 8 Cross-sectional view of AA; Figure 10 for Figure 8 Cross-sectional view at BB.
[0049] In this embodiment, the protective layer 205 is made of silicon nitride.
[0050] In other embodiments, the material of the protective layer 205 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.
[0051] In this embodiment, the protective layer 205 is formed on the sidewall of the dummy gate layer 204a to prevent damage to the dummy gate layer 204a during the subsequent etching process to remove the composite layer 203 on both sides of the dummy gate structure 204.
[0052] In this embodiment, the process for forming the protective layer 205 is chemical vapor deposition.
[0053] In other embodiments, the process for forming the protective layer 205 may also be physical vapor deposition, atomic layer deposition, etc.
[0054] Please refer to Figures 11 to 13 The composite layer 203 on both sides of the pseudo gate structure 204 is etched away until the surface of the first sacrificial layer 202 is exposed.
[0055] Figure 12 for Figure 11 Cross-sectional view of AA; Figure 13 for Figure 11 Cross-sectional view at BB.
[0056] In this embodiment, the composite layer 203 on both sides of the pseudo gate structure 204 is etched away, and a groove 212 is formed in the fin 201. The bottom of the groove 212 exposes the surface of the first sacrificial layer 202.
[0057] In this embodiment, a dry etching process is used to remove the composite layer 203 on both sides of the pseudo-gate structure 204. Specifically, an anisotropic dry etching process is used to etch and remove the composite layer. The parameters of the dry etching process include: the etching gas used includes HBr and Ar, wherein the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar is 10 sccm to 1000 sccm.
[0058] In other embodiments, a wet etching process can also be used to remove the composite layer 203 on both sides of the pseudo gate structure 204.
[0059] Please refer to Figures 14 to 16 A spacer layer 206 is formed on the sidewall surface of the etched composite layer 203.
[0060] Figure 15 for Figure 14 Cross-sectional view of AA; Figure 16 for Figure 14 Cross-sectional view at BB.
[0061] In this embodiment, the spacer layer 206 is made of silicon boride.
[0062] In other embodiments, the material of the spacer layer 206 includes one or more of boron nitride, silicon nitride, and silicon oxide.
[0063] In this embodiment, the spacer layer 206 serves to electrically isolate the subsequently formed epitaxial layer from the fin 201.
[0064] Please refer to Figures 17 to 19 An epitaxial layer 207 is formed on the surface of the first sacrificial layer 202.
[0065] Figure 18 for Figure 17 Cross-sectional view of AA; Figure 19 for Figure 17 Cross-sectional view at BB.
[0066] In this embodiment, the method for forming the epitaxial layer 207 includes: forming a first epitaxial layer (not shown in the figure) using a first epitaxial growth process; forming a second epitaxial layer (not shown in the figure) using a second epitaxial growth process, wherein the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer 207, and the concentration of germanium atoms in the reaction gas used in the first epitaxial growth process is less than the concentration of germanium atoms in the reaction gas used in the second epitaxial growth process.
[0067] In this embodiment, a first epitaxial layer is first formed using a first epitaxial growth process, and then a second epitaxial layer is formed using a second epitaxial growth process. The concentration of germanium atoms in the first epitaxial growth process is lower than that in the second epitaxial growth process. By using a low concentration of germanium atoms as a transition layer and then using a high concentration of germanium atoms to form the epitaxial layer 207, the difficulty of germanium atom filling is reduced, the concentration of germanium atoms in the center is guaranteed, stress loss is eliminated, the risk of gaps appearing in the center of the epitaxial layer 207 is eliminated, the quality of the final epitaxial layer 207 is improved, and the performance of the semiconductor structure is enhanced.
[0068] In this embodiment, the process parameters of the first epitaxial growth process include a germanium atom concentration of less than 30% and a reaction temperature of greater than 500°C.
[0069] In this embodiment, the process parameters of the second epitaxial growth process include a germanium atom concentration greater than 30% and a reaction temperature greater than 500°C.
[0070] In this embodiment, the material of the epitaxial layer 207 is silicon germanium.
[0071] In other embodiments, the epitaxial layer 207 may also be made of silicon.
[0072] In this embodiment, the epitaxial layer 207 can grow along the lattice of the first sacrificial layer 202. The epitaxial layer 207 grows from the surface of the first sacrificial layer 202 upwards, which can avoid the existence of voids between the contact surface of the first sacrificial layer 202 and the epitaxial layer 207, improve the formation quality of the epitaxial layer 207, and has a wide range of applications.
[0073] In this embodiment, after the epitaxial layer 207 is formed, in-situ doping is also performed.
[0074] Please continue to refer to this. Figures 17 to 19 A capping layer 208 is formed on the surface of the epitaxial layer 207.
[0075] In this embodiment, the covering layer 208 is made of the same material as the first sacrificial layer 202.
[0076] In this embodiment, the material of the capping layer 208 is silicon germanium, and the mass percentage of germanium atoms in the capping layer 208 ranges from 40% to 60%, specifically, the mass percentage of germanium atoms in the capping layer 208 is 50%.
[0077] In this embodiment, the capping layer serves two purposes: firstly, it protects the epitaxial layer 207 during the removal of the first sacrificial layer 202; secondly, since the capping layer 208 is made of the same material as the first sacrificial layer 202, it can be removed simultaneously with the removal of the first sacrificial layer 202. This reduces the process steps of removing the capping layer 208 separately, shortens the production cycle, improves production efficiency, and reduces damage to the epitaxial layer 207, thus ensuring the quality of the formed epitaxial layer 207.
[0078] Please refer to Figures 20 to 22 Remove the first sacrificial layer 202 and form an isolation trench 209 between the composite layer 203 and the substrate 200.
[0079] Figure 21 for Figure 20 Cross-sectional view of AA; Figure 22 for Figure 20 Cross-sectional view at BB.
[0080] In this embodiment, the process for removing the first sacrificial layer 202 is a wet etching process.
[0081] In this embodiment, since the cover layer 208 and the first sacrificial layer 202 are made of the same material, the cover layer 208 is also removed during the removal of the first sacrificial layer 202.
[0082] In this embodiment, a wet etching process is used to remove the first sacrificial layer 202. The etching rate of the wet etching process on the first sacrificial layer 202 is greater than the etching rate on the second sacrificial layer 203a.
[0083] In this embodiment, a wet etching process is used to remove the first sacrificial layer 202. The wet etching process uses a mixture of fluoride ions and hydrogen peroxide as the etching liquid.
[0084] In this embodiment, HF completely etches the gate oxide layer on the surface. E-2504 is mainly a mixture of F- and H2O2. The higher the F- concentration, the faster the etching rate of the first sacrificial layer 202, and the higher the selectivity for the channel layer 203b, with an etching selectivity greater than 50. The E-2504 process time can be appropriately extended to remove the first sacrificial layer 202 in all areas, reduce the residue of the first sacrificial layer 202, and improve the removal efficiency.
[0085] Please refer to Figures 23 to 25 A bottom isolation layer 210 is formed within the isolation groove 209.
[0086] Figure 24 for Figure 23 Cross-sectional view of AA; Figure 25 for Figure 23 Cross-sectional view at BB.
[0087] In this embodiment, the bottom isolation layer 210 is made of silicon nitride.
[0088] In other embodiments, the material of the bottom isolation layer 210 may be one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.
[0089] In this embodiment, the process for forming the bottom isolation layer 210 is chemical vapor deposition.
[0090] In other embodiments, the process for forming the bottom isolation layer 210 may also be physical vapor deposition, atomic layer deposition, etc.
[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of discretely arranged fins are formed on the substrate. Each fin includes a first sacrificial layer and a plurality of overlapping composite layers located on the surface of the first sacrificial layer. The composite layers include a second sacrificial layer and a channel layer located on the surface of the second sacrificial layer. Multiple discrete pseudo-gate structures are formed on the substrate, spanning the fin, and the pseudo-gate structures cover part of the sidewalls and top surface of the fin; The composite layers on both sides of the dummy gate structure are etched away until the surface of the first sacrificial layer is exposed; An epitaxial layer is formed on the surface of the first sacrificial layer; Remove the first sacrificial layer and form an isolation trench between the composite layer and the substrate; A bottom isolation layer is formed within the isolation groove.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the epitaxial layer includes: forming a first epitaxial layer using a first epitaxial growth process; forming a second epitaxial layer using a second epitaxial growth process, wherein the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer, and the concentration of germanium atoms in the reaction gas used in the first epitaxial growth process is less than the concentration of germanium atoms in the reaction gas used in the second epitaxial growth process.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters of the first epitaxial growth process include: the concentration of germanium atoms is less than 30%, and the reaction temperature is greater than 500℃.
4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the second epitaxial growth process include a germanium atom concentration greater than 30% and a reaction temperature greater than 500℃.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the epitaxial layer is silicon-germanium.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before removing the first sacrificial layer, the method further includes forming a capping layer on the surface of the epitaxial layer, the capping layer being made of the same material as the first sacrificial layer.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the bottom insulating layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material, or ultra-low-K dielectric material.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before etching away the composite layers on both sides of the dummy gate structure to expose the surface of the first sacrificial layer, the method further includes: forming a protective layer on the substrate, the protective layer being formed on the surfaces of the fins on both sides of the dummy gate structure and the sidewall surfaces of the dummy gate structure.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After etching away the composite layers on both sides of the pseudo-gate structure to expose the surface of the first sacrificial layer, and before forming an epitaxial layer on the surface of the first sacrificial layer, the method further includes forming a spacer layer on the sidewall surface of the etched composite layer.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The spacer layer is made of one or more of boron nitride, silicon nitride, and silicon oxide.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first sacrificial layer is made of silicon-germanium, and the mass percentage of germanium atoms in the first sacrificial layer ranges from 40% to 60%.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second sacrificial layer is silicon-germanium, and the mass percentage of germanium atoms in the second sacrificial layer ranges from 20% to 35%.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, It also includes an isolation structure formed on the substrate, wherein the top surface of the isolation structure is lower than or flush with the bottom surface of the bottom isolation layer.