Shield gate trench MOSFET device and preparation method of shield gate trench MOSFET device

Abstract

The invention provides a shield gate trench MOSFET device and a preparation method of the shield gate trench MOSFET device, and the method is characterized in that an epitaxial layer is located on a substrate, and the epitaxial layer is internally provided with a first trench; the first gate oxide layer is located on the inner wall surface of the first groove and the surface of the epitaxial layer; the shield gate is located in the first groove and comprises a first region and a second region located on the first region; the second gate oxide layer is located on the shielding gate in the first groove; the control gate is located on the second gate oxide layer in the first groove. According to the invention, the width of the shield grid in the second region is greater than that of the shield grid in the first region, so that the electric field of the epitaxial layer in the middle region is increased, the distribution of the electric fields of the epitaxial layers at the two sides of the first groove along the direction of the first groove is more uniform, the voltage resistance of the source and drain of the shield grid groove MOSFET device is improved, and the reliability of the device is improved. Therefore, the device can use the epitaxial layer with higher doping concentration under the condition of ensuring that the voltage-resistant performance of the device meets the requirements of the device, so that the on resistance of the shield gate trench MOSFET device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shielded gate trench MOSFET device and a method for fabricating the shielded gate trench MOSFET device. Background Technology

[0002] Shielded gate trench MOSFETs are a new type of power semiconductor device with features such as low on-resistance, fast switching speed, and small drive current. They are widely used in motor drives, power management, synchronous rectification, and other fields.

[0003] To reduce device losses and improve device efficiency, it is necessary to reduce the on-resistance of shielded gate MOSFET devices. One method to reduce the on-resistance of shielded gate MOSFET devices is to increase the doping concentration of the epitaxial layer in the shielded gate MOSFET device. However, the doping concentration of the epitaxial layer in the shielded gate MOSFET device will lead to a decrease in the device's breakdown voltage performance. Therefore, to ensure the reliability of the breakdown voltage performance of the shielded gate MOSFET device, the doping concentration of the epitaxial layer of the shielded gate MOSFET device is limited.

[0004] For traditional shielded gate trench MOSFET devices, please refer to... Figure 1 The trench in the device includes a shielding gate 10 and a control gate 20 located above the shielding gate 10. Due to the strong auxiliary depletion effect between the trenches, the electric field distribution along the trench direction Y1 is low in the middle and high on both sides. That is, the electric field is lower in the middle region along the trench direction Y1, and the charge coupling effect of the shielding gate 20 is limited, resulting in low voltage withstand performance of traditional shielding gate trench MOSFET devices.

[0005] Therefore, how to reduce the on-resistance of shielded gate trench MOSFET devices while ensuring that the withstand voltage performance meets the device requirements has become an urgent problem to be solved in the existing technology. Summary of the Invention

[0006] This invention provides a shielded gate trench MOSFET device and a method for fabricating the shielded gate trench MOSFET device, which improves the uniformity of the electric field distribution in the epitaxial layer of the shielded gate trench MOSFET device, and ensures that the withstand voltage performance of the device meets the device requirements while reducing the on-resistance of the device.

[0007] According to a first aspect of the present invention, the present invention provides a shielded gate trench MOSFET device, the device comprising: Substrate; An epitaxial layer is located on the substrate, the epitaxial layer has a first trench, and the bottom of the first trench is separated from the substrate by the epitaxial layer; The first gate oxide layer is located on the inner wall surface of the first trench and the surface of the epitaxial layer; A shielding grid is located within the first trench, and a first grid oxide layer is formed between the shielding grid and the inner wall of the first trench. The shielding grid includes a first region and a second region located on the first region, wherein the width of the shielding grid in the second region is greater than the width of the shielding grid in the first region. The second gate oxide layer is located within the first trench and on the shielding gate; The control gate is located within the first trench and on the second gate oxide layer.

[0008] Optionally, the epitaxial layer includes: a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked sequentially from bottom to top, wherein the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the ion doping concentration of the second epitaxial layer is greater than that of the third epitaxial layer; the boundary between the first region and the second region is flush with the top surface of the first epitaxial layer, and the top surface of the first region is flush with the top surface of the second epitaxial layer.

[0009] Optionally, it further includes: a third gate oxide layer, the third gate oxide layer being located between the first gate oxide layer and the shielding gate of the first region, and the shielding gate of the second region being located on the top surface of the third gate oxide layer.

[0010] Optionally, it further includes: a first isolation layer, the first isolation layer being located between the first gate oxide layer and the third gate oxide layer, between the first gate oxide layer and the shielding gate of the second region, and between the first gate oxide layer and the second gate oxide layer, the first isolation layer also being located under the control gate.

[0011] Optionally, the material of the first isolation layer is silicon nitride, and the materials of the first gate oxide layer, the second gate oxide layer and the third gate oxide layer are all silicon dioxide.

[0012] Optional, also includes: The well region is located on top of the epitaxial layer on both sides of the first trench; The source region is located at the top of the well region; An interlayer dielectric layer is located on the surface of the epitaxial layer and the surface of the control gate; A contact hole penetrates the source region and the interlayer dielectric layer, with the bottom of the contact hole located within the well region; A metal layer is located on the surface of the interlayer dielectric layer and fills the contact hole.

[0013] According to a second aspect of the present invention, the technical solution of the present invention provides a method for fabricating a shielded gate trench MOSFET device, the method comprising: A substrate is provided, wherein an epitaxial layer is present on the substrate; A first trench is formed in the epitaxial layer, and the bottom of the first trench is separated from the substrate by the epitaxial layer; A first gate oxide layer is formed on the surface of the epitaxial layer and on the inner wall of the first trench; After the first gate oxide layer is formed, a shielding gate is formed in the first trench. The shielding gate includes a first region and a second region located on the first region. The width of the shielding gate in the second region is greater than the width of the shielding gate in the first region. A second gate oxide layer is formed within the first trench and on the shielding gate; A control gate is formed within the first trench and on the second gate oxide layer.

[0014] Optionally, the method for forming a shielding grid within the first trench includes: An initial third gate oxide layer is formed on the surface of the first gate oxide layer, and the initial third gate oxide layer has a second trench extending into the first trench; An initial shielding grid is formed within the second trench, wherein the top surface of the initial shielding grid is lower than the top surface of the epitaxial layer; The third gate oxide layer is etched until a portion of the sidewall of the initial shielding gate is exposed, forming the third gate oxide layer; Material for the shielding gate is deposited on the top surface of the third gate oxide layer, the exposed initial shielding gate surface, and the first gate oxide layer; The material of the shielding gate is etched back until the shielding gate is formed.

[0015] Optionally, the method further includes: Before forming the initial third gate oxide layer, an initial first isolation layer is formed on the surface of the first gate oxide layer; After the second gate oxide layer is formed, and before the control gate is formed, the initial first isolation layer exposed above both sides of the second gate oxide layer is removed to form the first isolation layer.

[0016] Optionally, after removing the initial first isolation layer exposed above both sides of the second gate oxide layer and before forming the control gate, the method further includes: repairing the second gate oxide layer by a thermal oxidation process.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the shielded gate trench MOSFET device and its fabrication method provided by the technical solution of the present invention, since the first trench is located on the epitaxial layer on the substrate, the shielding gate on the first gate oxide layer in the first trench includes a first region and a second region located on the first region, and the shielding gate is located below the second gate oxide layer under the control gate in the first trench. Therefore, the shielding gate of the second region is located in the middle region along the direction of the first trench. Since the width of the shielding gate of the second region is greater than the width of the shielding gate of the first region, the charge coupling effect of the epitaxial layer in the middle region on both sides of the first trench is better. As a result, the electric field of the epitaxial layer in the middle region on both sides of the first trench is pulled up, making the electric field distribution of the epitaxial layer on both sides of the first trench more uniform, thereby improving the source and drain breakdown voltage performance of the shielded gate trench MOSFET device. Thus, the present invention enables the device to use an epitaxial layer with a higher doping concentration while ensuring that the source and drain breakdown voltage performance of the device meets the device requirements, thereby reducing the on-resistance of the shielded gate trench MOSFET device.

[0018] Furthermore, since an initial first isolation layer is formed on the surface of the first gate oxide layer before the initial third gate oxide layer is formed, the first isolation layer can act as a barrier, so when the second gate oxide layer is formed subsequently, the furnace tube oxidation process can be used, the process is simpler, and the cell size of the first trench will not be enlarged. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a cross-sectional structural diagram of a shielded gate trench MOSFET device in the prior art.

[0021] Figures 2-14 This is a cross-sectional structural diagram of each step in the fabrication method of the shielded gate trench MOSFET device according to an embodiment of the present invention.

[0022] 10-Shielding fence; 20-Control gate; Y1 - Trench direction; 100-substrate; 200 - Epitaxial layer; 240 - First trench; Y2 - Direction of the first trench; 210 - First epitaxial layer; 220 - Second epitaxial layer; 230 - Third epitaxial layer; 300 - First gate oxide layer; 410 - Initial First Isolation Layer; 510 - Initial third gate oxide layer; 520 - Third gate oxide layer; 600 - Second trench; 710 - Initial shielding grid; 420 - First isolation layer; 700 - Material of the shielding grid; 720 - Shielding fence; L2 - Width of the shielding grid in the second zone; L1 - Width of the shielding grid in Zone 1; II - Second Zone; I-First District; 800 - Second gate oxide layer; 900-Control gate; 1000-well region; 1100-Source Region; 1200 - Interlayer dielectric layer; 1300 - Metal layer. Detailed Implementation

[0023] As described in the background section, it is difficult in the prior art to reduce the on-resistance of shielded gate trench MOSFET devices while ensuring that the source and drain voltage withstand performance of the device meets the device requirements.

[0024] To address the aforementioned technical problems, the present invention provides a shielded gate trench MOSFET device, comprising: a substrate; an epitaxial layer located on the substrate, wherein the epitaxial layer has a first trench, and the bottom of the first trench is separated from the substrate by the epitaxial layer; a first gate oxide layer located on the inner wall surface of the first trench and the surface of the epitaxial layer; a shielding gate located in the first trench, wherein the shielding gate and the inner wall surface of the first trench have the first gate oxide layer, the shielding gate comprising a first region and a second region located on the first region, wherein the width of the shielding gate in the second region is greater than the width of the shielding gate in the first region; a second gate oxide layer located in the first trench and on the shielding gate; and a control gate located in the first trench and on the second gate oxide layer. By setting the width of the shielding gate in the second region to be greater than that in the first region, and the shielding gate in the second region being located in the middle region along the direction of the first trench, the charge coupling effect of the epitaxial layer located in the middle region on both sides of the first trench is better, which makes the electric field of the epitaxial layer located in the middle region on both sides of the first trench higher. The electric field distribution of the epitaxial layer on both sides of the first trench along the direction of the first trench is uniform, which improves the breakdown voltage performance of the shielding gate trench MOSFET device. Thus, under the condition that the breakdown voltage performance of the device meets the device requirements, the present invention enables the device to use an epitaxial layer with a higher doping concentration to reduce the on-resistance of the shielding gate trench MOSFET device.

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0028] Figures 2-14 This is a cross-sectional structural diagram of each step in the fabrication method of the shielded gate trench MOSFET device according to an embodiment of the present invention.

[0029] Please refer to Figure 2 A substrate 100 is provided, on which an epitaxial layer 200 is provided.

[0030] As an example, the material of substrate 100 may include semiconductor materials such as silicon, gallium arsenide, germanium, germanium silicon, or silicon-on-insulator.

[0031] In a preferred embodiment, the epitaxial layer 200 includes a first epitaxial layer 210, a second epitaxial layer 220, and a third epitaxial layer 230 stacked sequentially from bottom to top. The ion doping concentration of the second epitaxial layer 220 is greater than that of the first epitaxial layer 210, and the ion doping concentration of the second epitaxial layer 220 is greater than that of the third epitaxial layer 230.

[0032] Since the second epitaxial layer 220 is the epitaxial layer 200 with the highest ion doping concentration, the shielding gate 720 of the subsequently formed second region (such as...) Figure 9 The top surface of the shielding grid (as shown) is flush with the top surface of the second epitaxial layer 220, and the shielding grid subsequently formed (as shown) Figure 9 As shown) Zone I (as shown) Figure 9 (as shown) and the second zone II (as shown) Figure 9 The boundary between the second region (as shown) and the top surface of the first epitaxial layer 210 is flush, i.e., the second region II (as shown) Figure 9 The shielding grid 720 (as shown) Figure 9 As shown) and the second epitaxial layer 220 are both located along the first trench 240 (as shown) Figure 3 The middle region in the direction shown can therefore further enhance the shielding of the second region (as shown). Figure 9 The charge coupling effect between the first trench 240 (as shown) and the second epitaxial layer 220 further increases the electric field of the epitaxial layer 200 on both sides of the first trench 240 located in the middle region, making the electric field distribution along the first trench direction Y2 more uniform, and further improving the withstand voltage performance of the shielded gate trench MOSFET device.

[0033] Please refer to Figure 3 A first trench 240 is formed in the epitaxial layer 200, and the bottom of the first trench 240 is separated from the substrate 100 by the epitaxial layer 200.

[0034] Specifically, the bottom of the first trench 240 is located within the first epitaxial layer 210.

[0035] Please refer to Figure 4 A first gate oxide layer 300 is formed on the surface of the epitaxial layer 200 and the inner wall of the first trench 240.

[0036] Specifically, the material of the first gate oxide layer 300 can be silicon dioxide. The process for forming the first gate oxide layer 300 can be thermal oxidation growth of silicon dioxide.

[0037] As an example, the thickness of the first gate oxide layer 300 can range from 300 angstroms to 800 angstroms. Setting the thickness of the first gate oxide layer 300 to 300 angstroms can make the device performance more stable, and an appropriate thickness can be selected according to the device threshold voltage requirements.

[0038] Next, a shielding grid 720 is formed within the first trench 240. The shielding grid 720 includes a first region I and a second region II located on the first region I. The width L2 of the shielding grid 720 in the second region II is greater than the width L1 of the shielding grid 720 in the first region I. For the steps of forming the shielding grid 720, please refer to [link to documentation]. Figures 5-9 .

[0039] Please refer to Figure 5 An initial first isolation layer 410 is formed on the surface of the first gate oxide layer 300.

[0040] Specifically, the material of the initial first isolation layer is different from the material of the first gate oxide layer 300. The material of the initial first isolation layer 410 can be silicon nitride.

[0041] Specifically, the thickness of the initial first isolation layer 410 can range from 500 angstroms to 2000 angstroms. Setting the thickness of the initial first isolation layer 410 within this range ensures good breakdown voltage performance of the device and also effectively isolates the first gate oxide layer 300 and the subsequently formed third gate oxide layer 520 (e.g., Figure 8 (As shown).

[0042] Since the initial material of the first isolation layer 410 is different from that of the first gate oxide layer 300 (the initial material of the first isolation layer 410 is silicon nitride, and the material of the first gate oxide layer 300 is silicon oxide), the first isolation layer 420 can act as a barrier, thereby allowing the second gate oxide layer 800 to be formed subsequently using a thermal oxidation process (e.g., ...). Figure 11 When (as shown), the cell size of the first trench 240 will not be enlarged. Further, the second gate oxide layer 800 (as shown) Figure 11 The thickness (as shown) can also be grown to the required thickness according to the needs of the device.

[0043] As an example, the thickness of the second gate oxide layer 800 can range from 1500 angstroms to 3000 angstroms. This thickness range allows the second gate oxide layer 800 to effectively isolate the shielding gate 720 from the subsequently formed control gate 900 (e.g., Figure 12 (As shown).

[0044] Then, please refer to Figure 6An initial third gate oxide layer 510 is formed on the surface of the initial first isolation layer 410, and the initial third gate oxide layer 510 has a second trench 600 extending into the first trench 240.

[0045] Specifically, the material of the initial third gate oxide layer 510 is different from the material of the initial first isolation layer 410.

[0046] Specifically, the material of the initial third gate oxide layer 510 is silicon dioxide.

[0047] Please refer to Figure 7 An initial shielding grid 710 is formed in the second trench 600, and the top surface of the initial shielding grid 710 is lower than the top surface of the epitaxial layer 200.

[0048] For example, the material of the initial shielding gate 710 can be a conductive material such as polycrystalline silicon or metallic tungsten silicon.

[0049] Please refer to Figure 8 The initial third gate oxide layer 510 is etched until a portion of the sidewall of the initial shielding gate 710 is exposed, forming the third gate oxide layer.

[0050] exist Figure 8 In one example, during the etching of the third gate oxide layer, all of the initial third gate oxide layer 510 on the surface of the epitaxial layer 200 and the initial third gate oxide layer 510 above the initial shielding gate 710 in the second trench 600 can be removed, leaving only the portion of the initial third gate oxide layer 510 below the top surface of the initial shielding gate 710. However, this invention is not limited to this. As another embodiment, a portion of the initial third gate oxide layer 510 on the surface of the epitaxial layer 200 and the initial third gate oxide layer 510 above the initial shielding gate 710 can be removed, leaving only the portion of the initial third gate oxide layer 510 above the top surface of the initial shielding gate 710.

[0051] The etching process for the initial third gate oxide layer 510 is an isotropic wet etching. The etchant used for wet etching can be hydrofluoric acid, but this invention is not limited to this. The etchant used for wet etching only needs to satisfy the requirement that the selectivity of the etching solution for silicon dioxide is greater than that for silicon nitride.

[0052] Please refer to Figure 9 Material 700 of the shielding gate is deposited on the top surface of the third gate oxide layer 520, the surface of the exposed initial shielding gate 710, and the first gate oxide layer 300.

[0053] Specifically, the material of the shielding grid 720 is the same as that of the initial shielding grid 710.

[0054] Please refer to Figure 10 The material 700 of the shielding gate is etched back until the shielding gate 720 is formed.

[0055] Since the first trench 240 is located on the epitaxial layer 200 on the substrate 100, the shielding gate 720 on the first gate oxide layer 300 within the first trench 240 includes a first region I and a second region II located on the first region I. The shielding gate 720 is located below the second gate oxide layer 800 below the control gate 900 within the first trench 240. Therefore, the shielding gate 720 of the second region II is located in the middle region along the first trench direction Y2. Furthermore, because the width L2 of the shielding gate 720 in the second region is greater than the width L1 of the shielding gate 720 in the first region I, the shielding gate 720 located in the second region II is... The charge coupling effect of the epitaxial layer 200 in the middle region on both sides of the first trench 240 is better, thereby increasing the electric field of the epitaxial layer 200 in the middle region on both sides of the first trench 240. This makes the electric field distribution of the epitaxial layer 200 on both sides of the first trench 240 more uniform, improving the source and drain breakdown voltage performance of the shielded gate trench MOSFET device. Thus, under the condition that the breakdown voltage performance of the device meets the device requirements, the present invention enables the device to use an epitaxial layer with a higher doping concentration to reduce the on-resistance of the shielded gate trench MOSFET device.

[0056] Please refer to Figure 11 A second gate oxide layer 800 is formed within the first trench 240 and on the shielding gate 720.

[0057] The material of the second gate oxide layer 800 is silicon dioxide, and the process for forming the second gate oxide layer 800 is thermal oxidation growth of silicon dioxide.

[0058] Because the initial material of the first isolation layer 410 is different from that of the first gate oxide layer 300 (the initial material of the first isolation layer 410 is silicon nitride, while the material of the first gate oxide layer 300 is silicon oxide), the first isolation layer 420 can act as a barrier, thus preventing the cell size of the first trench 240 from being enlarged when the second gate oxide layer 800 is formed using a thermal oxidation process. Furthermore, the thickness of the second gate oxide layer 800 can be grown to the required thickness according to the device's needs.

[0059] Next, please refer to Figure 12 Remove the initial first isolation layer 410 exposed above both sides of the second gate oxide layer 800 (e.g. Figure 11 As shown), this forms the first isolation layer 420.

[0060] The etching process for the initial first isolation layer 410 is an isotropic wet etching process. The etchant used for wet etching can be phosphoric acid, but this invention is not limited to this. The etchant used for wet etching only needs to satisfy the requirement that the selectivity of the etchant for silicon nitride is greater than that for silicon dioxide.

[0061] In a preferred embodiment, after removing the initial first isolation layer 410 exposed above both sides of the second gate oxide layer 800, the second gate oxide layer 800 is repaired by a thermal oxidation process.

[0062] Repairing the second gate oxide layer 800 by using a thermal oxidation process can eliminate the damage to the second gate oxide layer 800 caused when part of the first isolation layer 420 is removed.

[0063] Next, please refer to Figure 13 A control gate 900 is formed within the first trench 240 and on the second gate oxide layer 800.

[0064] Please refer to Figure 14 A well region 1000 is formed on top of the epitaxial layers 200 on both sides of the first trench 240. A source region 1100 is formed on top of the well region 1000. An interlayer dielectric layer 1200 is formed on the surface of the epitaxial layer 200 and the surface of the control gate 900. A contact hole is formed penetrating the source region 1100 and the interlayer dielectric layer 1200, with the bottom of the contact hole located within the well region 1000. A metal layer 1300 is located on the surface of the interlayer dielectric layer 1200 and fills the contact hole. The source region 1100 is located on top of the well region 1000. The interlayer dielectric layer 1200 is located on the surface of the epitaxial layer 200 and the surface of the control gate 900. A contact hole penetrates the source region 1100 and the interlayer dielectric layer, with the bottom of the contact hole located within the well region 1000. A metal layer 1300 is formed within the contact hole and on the surface of the interlayer dielectric layer 1200.

[0065] Accordingly, embodiments of the present invention also provide a shielded gate trench MOSFET device formed using the above-described preparation method. Please refer to [link to relevant documentation]. Figure 14 The shielded gate trench MOSFET device includes: a substrate 100, an epitaxial layer 200, a first gate oxide layer 300, a shielding gate 720, a second gate oxide layer 800, and a control gate 900.

[0066] The epitaxial layer 200 is located on the substrate 100. The epitaxial layer 200 has a first trench 240, and the bottom of the first trench 240 is separated from the substrate 100 by the epitaxial layer 200.

[0067] The first gate oxide layer 300 is located on the inner wall surface of the first trench 240 and the surface of the epitaxial layer 200.

[0068] The shielding grid 720 is located within the first trench 240, and a first grid oxide layer 300 is provided between the shielding grid 720 and the inner wall surface of the first trench 240. The shielding grid 720 includes a first region I and a second region II located on the first region I. The width L2 of the shielding grid 720 in the second region II is greater than the width L1 of the shielding grid 720 in the first region I.

[0069] The second gate oxide layer 800 is located within the first trench 240 and on the shielding gate 720.

[0070] The control gate 900 is located within the first trench 240 and on the second gate oxide layer 800.

[0071] Since the first trench 240 is located on the epitaxial layer 200 on the substrate 100, the shielding gate 720 on the first gate oxide layer 300 within the first trench 240 includes a first region and a second region II located on the first region I. The shielding gate 720 is located below the second gate oxide layer 800 below the control gate 900 within the first trench 240. Therefore, the shielding gate 720 of the second region II is located in the middle region along the first trench direction Y2. Furthermore, because the width L2 of the shielding gate 720 of the second region II is greater than the width L1 of the shielding gate 720 of the first region I, it is located in the middle region of the first trench direction Y2. The charge coupling effect of the epitaxial layer 200 in the middle region on both sides of the first trench 240 is better, thereby increasing the electric field of the epitaxial layer 200 in the middle region on both sides of the first trench 240. This makes the electric field distribution of the epitaxial layer 200 on both sides of the first trench 240 more uniform, improving the source and drain breakdown voltage performance of the shielded gate trench MOSFET device. Thus, under the condition that the breakdown voltage performance of the device meets the device requirements, the present invention enables the device to use an epitaxial layer with a higher doping concentration to reduce the on-resistance of the shielded gate trench MOSFET device.

[0072] As a preferred embodiment, please continue to refer to Figure 14 The epitaxial layer 200 includes a first epitaxial layer 210, a second epitaxial layer 220, and a third epitaxial layer 230 stacked sequentially from bottom to top. The ion doping concentration of the second epitaxial layer 220 is greater than that of the first epitaxial layer 210, and the ion doping concentration of the second epitaxial layer 220 is greater than that of the third epitaxial layer 230. The boundary between the first region I and the second region II is flush with the top surface of the first epitaxial layer 210, and the top surface of the first region I is flush with the top surface of the second epitaxial layer 220.

[0073] Since the second epitaxial layer 220 is the epitaxial layer 200 with the highest ion doping concentration, the top surface of the shielding gate 720 of the subsequently formed second region is flush with the top surface of the second epitaxial layer 220, and the junction of the first region I and the second region II is flush with the top surface of the first epitaxial layer 210. That is, the shielding gate 720 of the second region and the second epitaxial layer 220 are both located in the middle region along the first trench direction Y2. Therefore, this embodiment can further improve the charge coupling effect between the shielding gate 720 of the second region II and the second epitaxial layer 220, thereby further increasing the electric field of the epitaxial layers 200 on both sides of the first trench 240 located in the middle region, making the electric field distribution along the first trench direction Y2 more uniform, and improving the source and drain breakdown voltage performance of the shielded gate trench MOSFET device. Thus, under the condition that the breakdown voltage performance of the device meets the device requirements, the present invention enables the device to use an epitaxial layer with a higher doping concentration to reduce the on-resistance of the shielded gate trench MOSFET device.

[0074] For details, please continue to refer to [the website / information]. Figure 14 The shielded gate trench MOSFET device further includes a third gate oxide layer 520, which is located between the first gate oxide layer 300 and the shielding gate 720 of the first region I, and the shielding gate 720 of the second region II is also located on the top surface of the third gate oxide layer 520.

[0075] As a preferred embodiment, please continue to refer to Figure 14 The shielded gate trench MOSFET device further includes: a first isolation layer 420, which is located between the first gate oxide layer 300 and the third gate oxide layer 520, between the first gate oxide layer 300 and the shielded gate 720 of the second region, and between the first gate oxide layer 300 and the second gate oxide layer 800. The first isolation layer 420 is also located under the control gate 900.

[0076] Specifically, the material of the first isolation layer 420 is different from the material of the first gate oxide layer 300, and the material of the first isolation layer 420 is different from the material of the third gate oxide layer 800.

[0077] Specifically, the first isolation layer 420 is made of silicon nitride, and the first gate oxide layer 300, the second gate oxide layer 800, and the third gate oxide layer 520 are all made of silicon dioxide.

[0078] For details, please continue to refer to [the website / information]. Figure 14The shielded gate trench MOSFET device further includes: a well region 1000 located on top of the epitaxial layer 200 on both sides of the first trench 240; a source region 1100 located on top of the well region 1000; an interlayer dielectric layer 1200 located on the surface of the epitaxial layer 200 and the surface of the control gate 900; a contact hole penetrating the source region 1100 and the interlayer dielectric layer, with the bottom of the contact hole located within the well region 1000; and a metal layer 1300 located on the surface of the interlayer dielectric layer 1200 and filling the contact hole.

[0079] The materials, forming process, working principle, specific implementation method and beneficial effects of the shielded gate trench MOSFET device in this embodiment can be found in the preparation method of resistive switching memory in the embodiment of the present invention, and will not be repeated here.

[0080] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A shielded gate trench MOSFET device, characterized in that, The device includes: Substrate; An epitaxial layer is located on the substrate, the epitaxial layer has a first trench, and the bottom of the first trench is separated from the substrate by the epitaxial layer; The first gate oxide layer is located on the inner wall surface of the first trench and the surface of the epitaxial layer; A shielding grid is located within the first trench, and a first grid oxide layer is formed between the shielding grid and the inner wall of the first trench. The shielding grid includes a first region and a second region located on the first region, wherein the width of the shielding grid in the second region is greater than the width of the shielding grid in the first region. The second gate oxide layer is located within the first trench and on the shielding gate; The control gate is located within the first trench and on the second gate oxide layer.

2. The shielded gate trench MOSFET device as described in claim 1, characterized in that, The epitaxial layer includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked sequentially from bottom to top. The ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the ion doping concentration of the second epitaxial layer is greater than that of the third epitaxial layer. The boundary between the first region and the second region is flush with the top surface of the first epitaxial layer, and the top surface of the first region is flush with the top surface of the second epitaxial layer.

3. The shielded gate trench MOSFET device as described in claim 2, characterized in that, Also includes: A third gate oxide layer is located between the first gate oxide layer and the shielding gate of the first region, and the shielding gate of the second region is also located on the top surface of the third gate oxide layer.

4. The shielded gate trench MOSFET device as described in claim 3, characterized in that, Also includes: A first isolation layer is located between the first gate oxide layer and the third gate oxide layer, between the first gate oxide layer and the shielding gate of the second region, and between the first gate oxide layer and the second gate oxide layer. The first isolation layer is also located under the control gate.

5. The shielded gate trench MOSFET device as described in claim 4, characterized in that, The first isolation layer is made of silicon nitride, and the first gate oxide layer, the second gate oxide layer, and the third gate oxide layer are all made of silicon dioxide.

6. The shielded gate trench MOSFET device as described in claim 1, characterized in that, Also includes: The well region is located on top of the epitaxial layer on both sides of the first trench; The source region is located at the top of the well region; An interlayer dielectric layer is located on the surface of the epitaxial layer and the surface of the control gate; A contact hole penetrates the source region and the interlayer dielectric layer, with the bottom of the contact hole located within the well region; A metal layer is located on the surface of the interlayer dielectric layer and fills the contact hole.

7. A method for fabricating a shielded gate trench MOSFET device, characterized in that, The method includes: A substrate is provided, wherein an epitaxial layer is present on the substrate; A first trench is formed in the epitaxial layer, and the bottom of the first trench is separated from the substrate by the epitaxial layer; A first gate oxide layer is formed on the surface of the epitaxial layer and on the inner wall of the first trench; After the first gate oxide layer is formed, a shielding gate is formed in the first trench. The shielding gate includes a first region and a second region located on the first region. The width of the shielding gate in the second region is greater than the width of the shielding gate in the first region. A second gate oxide layer is formed within the first trench and on the shielding gate; A control gate is formed within the first trench and on the second gate oxide layer.

8. The preparation method according to claim 7, characterized in that, The method for forming a shielding grid within the first trench includes: An initial third gate oxide layer is formed on the surface of the first gate oxide layer, and the initial third gate oxide layer has a second trench extending into the first trench; An initial shielding grid is formed within the second trench, wherein the top surface of the initial shielding grid is lower than the top surface of the epitaxial layer; The third gate oxide layer is etched until a portion of the sidewall of the initial shielding gate is exposed, forming the third gate oxide layer; Material for the shielding gate is deposited on the top surface of the third gate oxide layer, the exposed initial shielding gate surface, and the first gate oxide layer; The material of the shielding gate is etched back until the shielding gate is formed.

9. The preparation method according to claim 8, characterized in that, The method further includes: Before forming the initial third gate oxide layer, an initial first isolation layer is formed on the surface of the first gate oxide layer; After the second gate oxide layer is formed, and before the control gate is formed, the initial first isolation layer exposed above both sides of the second gate oxide layer is removed to form the first isolation layer.

10. The preparation method according to claim 9, characterized in that, After removing the initial first isolation layer exposed above both sides of the second gate oxide layer, and before forming the control gate, the process further includes: repairing the second gate oxide layer by a thermal oxidation process.

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