Trench mos structure and method of forming the same, mask pattern structure

Abstract

The application provides a trench type MOS structure and a forming method and a mask plate pattern structure thereof, a heavy doping layer with the same resistivity as that of the surface layer of the active area gate is arranged on the surface layer of the terminal area gate, so that the resistivity of the active area gate and the resistivity of the terminal area gate are the same.The unexpected technical effect of the application is that the surface layer of the terminal area gate is provided with the heavy doping layer, the resistivity of the terminal area gate is reduced to the same as that of the active area gate, the resistivity of the gate in all areas of the trench type MOS device is consistent, the problem of uneven distribution of the gate resistance at the connection between the active area and the terminal area is effectively solved, the uneven voltage distribution caused by the difference between the gate resistances of the active area and the terminal area is effectively avoided, the protection of the gate oxide layer is strengthened, and the influence of the electrostatic breakdown on the trench type MOS device is reduced.Meanwhile, the gate resistance of the trench type MOS device is reduced, and the risk of local hot spot burning caused by the high gate resistance and the high power density is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a trench MOS structure, a forming method thereof and a mask plate pattern structure. BACKGROUND

[0002] A trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is etched in an epitaxial layer on a silicon wafer, a gate oxide layer is then grown on the surface, polysilicon is deposited in the trench to form a gate, and ions are implanted on the silicon wafer to form a source, and the backside of the silicon wafer is the drain. The surface of the silicon wafer is divided into an active region and a termination region, and the gate polysilicon is led out from the active region and is connected to each other in the termination region.

[0003] The source polysilicon in the active region is directly connected to the terminal polysilicon in the termination region. The active region is heavily doped by ion implantation to form a heavily doped layer, and the heavily doped layer in the active region forms a conductive channel of the trench device. The gate polysilicon in the active region is doped at the same time, so the resistivity of the gate polysilicon in the active region is lowered. The terminal polysilicon in the termination region is not doped, so the resistivity of the terminal polysilicon in the termination region is high, and the two sections of gate polysilicon have a resistivity difference, which in turn leads to a high gate resistance of the device. The uneven gate resistance leads to uneven voltage distribution, and the voltage and current at the junction of the high resistance and the low resistance change abruptly, which easily leads to voltage breakdown when the voltage is too high or fluctuates, and the ESD (Electrostatic Discharge) resistance is poor. SUMMARY

[0004] The present application aims to provide a trench MOS structure, a forming method thereof and a mask plate pattern structure to solve at least one of the problems of local hot spot burning or voltage breakdown caused by the resistivity difference between the two ends of the gate due to the doping of the gate in the active region and the undoping of the gate in the termination region in the heavy doping process.

[0005] To solve the above technical problems, the present application provides a trench MOS structure, comprising:

[0006] a substrate, the substrate comprising an active region and a termination region;

[0007] an epitaxial layer, the epitaxial layer being located on the substrate;

[0008] a trench gate, the trench gate being located in the epitaxial layer and comprising an active region gate and a termination region gate.

[0009] a heavily doped layer located at a surface layer of the epitaxial layer of the active region, a surface layer of the active region gate, and a surface layer of the termination region gate, so that the resistivity of the active region gate and the termination region gate are the same.

[0010] Optionally, the heavily doped layer includes an active heavily doped layer and a termination heavily doped layer, the active heavily doped layer is located at a surface layer of the epitaxial layer of the active region and a surface layer of the active region gate, and the termination heavily doped layer is located at a surface layer of the termination region gate, the termination heavily doped layer completely covers the termination region gate, so that the resistivity of the active region gate and the termination region gate are the same.

[0011] Optionally, the termination region gate includes a first part of the termination region gate and a second part of the termination region gate connected to each other, the first part of the termination region gate is used for electrically connecting the active region gate, and the second part of the termination region gate is used for leading out the trench gate to the conductive layer.

[0012] Optionally, the region of the termination heavily doped layer includes a first part of the termination heavily doped layer and a second part of the termination heavily doped layer, the length of the first part of the termination heavily doped layer is greater than or equal to the length of the first part of the termination region gate, the width of the first part of the termination heavily doped layer is greater than or equal to the width of the first part of the termination region gate, the length of the second part of the termination heavily doped layer is greater than or equal to the length of the second part of the termination region gate, the width of the second part of the termination heavily doped layer is greater than or equal to the width of the second part of the termination region gate, and the first part of the termination heavily doped layer is longer or wider than the first part of the termination region gate and the second part of the termination heavily doped layer is longer or wider than the second part of the termination region gate meet a preset threshold value.

[0013] Optionally, an implant layer is further formed in the trench gate, the implant layer is located below the heavily doped layer, and the doping types of the heavily doped layer and the implant layer are opposite.

[0014] Based on the same inventive concept, the present application also provides a forming method of a trench MOS structure, comprising:

[0015] providing a substrate, the substrate includes an active region and a termination region, an epitaxial layer is formed on the substrate, a trench gate is formed in the epitaxial layer, and the trench gate includes an active region gate and a termination region gate;

[0016] An ion implantation process is performed to form a heavily doped layer in a surface layer of the epitaxial layer of the active region, a surface layer of the active region gate, and a surface layer of the termination region gate, so that the active region gate and the termination region gate have the same resistivity.

[0017] Optionally, the method for forming the trench gate in the epitaxial layer comprises:

[0018] An etching process is performed to form a trench in the epitaxial layer;

[0019] A gate oxide layer is formed to cover the bottom wall and the sidewall of the trench;

[0020] A polysilicon layer is formed to fill the trench and cover the epitaxial layer;

[0021] The polysilicon layer outside the trench is removed and the top surface of the polysilicon layer in the trench is leveled with the top surface of the epitaxial layer, and the polysilicon layer in the trench constitutes a trench gate.

[0022] Optionally, after the trench gate is formed, an ion implantation process is performed to form a well region in the epitaxial layer and an implantation layer in the trench gate.

[0023] Optionally, the well region and the implantation layer are of a first doping type, and the heavily doped layer is of a second doping type.

[0024] Based on the same inventive concept, the present application also provides a mask plate pattern structure for forming the trench MOS structure of any one of the above-mentioned embodiments, which comprises:

[0025] an active region pattern and a termination region pattern;

[0026] an epitaxial layer pattern on the active region pattern and the termination region pattern;

[0027] a trench gate pattern in the epitaxial layer pattern, and the trench gate pattern comprises an active region gate pattern and a termination region gate pattern;

[0028] a heavily doped layer pattern on the epitaxial layer pattern of the active region pattern, the active region gate pattern, and the termination region gate pattern.

[0029] In the trench type MOS structure provided by the application, the same heavy doping layer as the surface layer of the active region gate is arranged on the surface layer of the terminal region gate, so that the resistivity of the active region gate and the terminal region gate is the same. The unexpected technical effect of the application is that the surface layer of the terminal region gate is increased with the heavy doping layer, the resistivity of the terminal region gate is reduced to the same as the resistivity of the active region gate, the resistivity of the gate in all regions of the trench type MOS device is consistent, the problem of uneven distribution of the gate resistance at the connection between the active region and the terminal region is effectively solved, the uneven voltage distribution caused by the difference between the gate resistances of the active region and the terminal region is effectively avoided, the protection of the gate oxide layer is strengthened, and the influence of the electrostatic breakdown on the trench type MOS device is reduced. At the same time, the resistivity of the terminal region gate is reduced, thereby reducing the resistivity of the whole gate of the trench type MOS device, further reducing the gate resistance of the trench type MOS device, and further reducing the risk of local hot spot burning caused by the high resistance of the gate. BRIEF DESCRIPTION OF DRAWINGS

[0030] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application.

[0031] Figure 1 is a top view of the trench type MOS structure of the embodiment of the present application.

[0032] Figure 2 is an enlarged view of the middle A region of the trench type MOS structure after forming the trench type gate of the embodiment of the present application. Figure 1

[0033] Figure 3 is an enlarged view of the middle A region of the trench type MOS structure after forming the heavy doping layer of the embodiment of the present application. Figure 1

[0034] Figure 4 is a flow chart of the forming method of the trench type MOS structure of the embodiment of the present application.

[0035] Figure 5 is a schematic view of the trench type MOS structure after forming the trench type gate of the embodiment of the present application along the middle BB' section. Figure 2

[0036] Figure 6 is a schematic view of the trench type MOS structure after forming the well region and the implantation layer of the embodiment of the present application along the middle BB' section. Figure 2

[0037] Figure 7 is a schematic view of the trench type MOS structure after forming the heavy doping layer of the embodiment of the present application along the middle BB' section. Figure 2 ​​​​​

[0038] Figure 8 is a schematic view of a trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 2 is a schematic view of a cross section along CC' in Fig. 1.

[0039] In the drawings: 10 - substrate; 10a - active region; 10b - termination region; 10c - conductive region; 11 - epitaxial layer; 12 - gate oxide layer; 12a - trench; 13 - trench gate; 13a - active region gate; 13b - termination region gate; 13b-1 - first part of the termination region gate; 13b-2 - second part of the termination region gate; 14a - well region; 14b - implanted layer; 15 - heavily doped layer; 15a - active heavily doped layer; 15b - termination heavily doped layer; 15b-1 - first part of the termination heavily doped layer; 15b-2 - second part of the termination heavily doped layer. DETAILED DESCRIPTION

[0040] In order to make the objects, advantages and features of the present application clearer, the following will further describe the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that all the drawings are very simplified and not drawn according to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis shown in each drawing is different, and sometimes different scales are used.

[0041] As used in the present application, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of "and / or", the term "several" is generally used in the sense of "at least one", the term "at least two" is generally used in the sense of "two or more", and in addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present application, an element disposed in another element generally only indicates a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial positional relationship between the two elements, i.e. one element can be in any orientation inside, outside, above, below or one side of another element, unless the content is otherwise explicitly indicated. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] Figure 1 is a schematic view of a trench MOS structure according to an embodiment of the present application.Figure 7 is a cross-sectional view of a trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 2 is a cross-sectional view of a trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 1 and Figure 7 A trench MOS structure according to an embodiment of the present application includes:

[0043] a substrate 10 including an active region 10a and a termination region 10b;

[0044] an epitaxial layer 11 on the substrate 10;

[0045] a trench gate 13 in a trench 12a of the epitaxial layer 11, the trench gate 13 including an active region gate 13a and a termination region gate 13b;

[0046] a heavily doped layer 15 on a surface layer of the epitaxial layer 11 of the active region and on surface layers of the active region gate 13a and the termination region gate 13b, so that the resistivity of the active region gate 13a and the termination region gate 13b is the same.

[0047] Figure 2 is a cross-sectional view of a trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 1 is an enlarged view of a region A of the cross-sectional view of the trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 3 is a cross-sectional view of a trench MOS structure after forming a heavily doped layer according to an embodiment of the present application. Figure 1Enlarged view of region A. The heavily doped layer 15 includes an active heavily doped layer 15a located at the surface of the epitaxial layer 11 of the active region and at the surface of the active region gate 13a, and a termination heavily doped layer 15b located at the surface of the termination region gate 13b. The termination heavily doped layer 15b completely covers the termination region gate 13b, i.e. the area of the termination heavily doped layer 15b is greater than or equal to the area of the termination region gate 13b, to ensure that the resistivity of the active region gate 13a and the termination region gate 13b are the same. Specifically, the termination region gate 13b includes a first portion of the termination region gate 13b-1 and a second portion of the termination region gate 13b-2 connected to each other, the first portion of the termination region gate 13b-1 is rectangular in shape, and the second portion of the termination region gate 13b-2 is also rectangular in shape, but the length and width of the first portion of the termination region gate 13b-1 and the second portion of the termination region gate 13b-2 are different. The length L1 of the first portion of the termination region gate 13b-1 is greater than the length L2 of the second portion of the termination region gate 13b-2, but the width W1 of the first portion of the termination region gate 13b-1 is less than the width W2 of the second portion of the termination region gate 13b-2. The first portion of the termination region gate 13b-1 is used to electrically connect the active region gate 13a, and the second portion of the termination region gate 13b-2 is used to lead the active region gate 13a out to a conductive layer. That is, a subsequent process forms a metal plug on the second portion of the termination region gate 13b-2, the metal plug is used to electrically connect the second portion of the termination region gate 13b-2 and an upper conductive layer, and the upper conductive layer is electrically connected to the conductive region 10c.

[0048] Please refer to Figure 2 and Figure 3 , the termination heavily doped layer 15b includes a first portion of the termination heavily doped layer 15b-1 and a second portion of the termination heavily doped layer 15b-2. The first portion of the termination heavily doped layer 15b-1 is rectangular in shape, and the second portion of the termination heavily doped layer 15b-2 is also rectangular in shape, but the length and width of the first portion of the termination heavily doped layer 15b-1 and the second portion of the termination heavily doped layer 15b-2 are different. The length L3 of the first portion of the termination heavily doped layer 15b-1 is greater than the length L4 of the second portion of the termination heavily doped layer 15b-2, but the width W3 of the first portion of the termination heavily doped layer 15b-1 is less than the width W4 of the second portion of the termination heavily doped layer 15b-2.

[0049] Please refer to Figure 2 and Figure 3, the terminal heavily doped layer 15b completely covers the terminal region gate 13b. Specifically, the length L3 of the first part 15b-1 of the terminal heavily doped layer is greater than or equal to the length L1 of the first part 13b-1 of the terminal region gate, the width W3 of the first part 15b-1 of the terminal heavily doped layer is greater than or equal to the width W1 of the first part 13b-1 of the terminal region gate, the length L4 of the second part 15b-2 of the terminal heavily doped layer is greater than or equal to the length L2 of the second part 13b-2 of the terminal region gate, the width W4 of the second part 15b-2 of the terminal heavily doped layer is greater than or equal to the width W2 of the second part 13b-2 of the terminal region gate, and the first part 15b-1 of the terminal heavily doped layer is longer or wider than the first part 13b-1 of the terminal region gate and the second part 15b-2 of the terminal heavily doped layer is longer or wider than the second part 13b-2 of the terminal region gate satisfy a preset threshold value. If the area of the terminal heavily doped layer 15b is too large, it will cause the problem of leakage of the active region. Therefore, the preset threshold value is the process error range. That is, under the condition of ensuring that the terminal heavily doped layer 15b completely covers the terminal region gate 13b, the area of the terminal heavily doped layer 15b is as small as possible to avoid causing leakage of the active region.

[0050] The trench gate 13 also has an implant layer 14b formed therein, the implant layer 14b is located below the heavily doped layer 15 and the doping type of the heavily doped layer 15 and the implant layer 14b is opposite. The implant layer 14b and the well region 14a of the active region are formed at the same time, the well region 14a is formed in the epitaxial layer 11 of the active region, and the implant layer 14b is formed in the active region gate 13a. The doping type of the well region 14a and the implant layer 14b is, for example, the first doping type, and the doping type of the heavily doped layer 15 is the second doping type. In this embodiment, the first doping type is, for example, P type, and the second doping type is, for example, N type. The doping type of the heavily doped layer 15 is opposite to that of the well region 14a, so when the gate bias is greater than the threshold voltage, a reverse type layer will be formed around the gate oxide layer, and at this time the reverse type layer around the gate oxide layer and the heavily doped layer 15 constitute the conductive channel of the trench MOS device.

[0051] Figure 4 is a flow chart of a method for forming a trench MOS structure according to an embodiment of the present application. As shown in Figure 4 , the embodiment further provides a method for forming a trench MOS structure, comprising:

[0052] Step S10, providing a substrate, the substrate comprising an active region and a terminal region, an epitaxial layer is formed on the substrate, a trench gate is formed in the epitaxial layer, and the trench gate comprises an active region gate and a terminal region gate;

[0053] Step S20, performing ion implantation process to form a heavily doped layer in the surface layer of the epitaxial layer of the active region, the surface layer of the active region gate and the surface layer of the terminal region gate, so that the resistivity of the active region gate and the terminal region gate are the same.

[0054] Figure 5 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 2 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 6 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 2 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 7 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 2 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 8 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figure 2 is the trench type MOS structure along BB' section after forming the trench type gate of the embodiment of the present application. Figures 5 to 8 The specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0055] As shown in Figure 5 , a substrate 10 is provided, which can be a single crystal silicon or polycrystalline silicon substrate, or can be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or can be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art can select the type of semiconductor substrate according to the requirements of the semiconductor device, and the type of semiconductor substrate should not limit the protection scope of the present application.

[0056] Please continue to refer to Figure 1 and Figure 5 , the substrate 10 includes an active region 10a and a terminal region 10b, the active region 10a is used to form a semiconductor device, for example, a MOS device, and the terminal region 10b is used to lead out the semiconductor device on the active region 10a to a conductive layer, for example, the terminal region 10b leads the active region gate 13a to the upper conductive region 10c. An epitaxial layer 11 is formed on the substrate 10, and a trench type gate 13 is formed in the epitaxial layer 11, which includes an active region gate 13a and a terminal region gate 13b.

[0057] As shown in Figure 2 and Figure 5As shown, the method for forming a trench gate 13 within the epitaxial layer 11 includes: performing an etching process to form a trench 12a within the epitaxial layer 11, the trench 12a extending from the top surface of the epitaxial layer 11 into the epitaxial layer 11. The trench 12a includes an active region trench and a termination region trench, the active region trench being well-shaped and the termination region trench being a line. A gate oxide layer 12 is formed, the gate oxide layer 12 covering the bottom wall and sidewalls of the trench 12a; a polysilicon layer is formed, the polysilicon layer filling the trench 12a and covering the epitaxial layer 11; the polysilicon layer outside the trench 12a is removed and the top surface of the polysilicon layer within the trench 12a is flush with the top surface of the epitaxial layer 11, the polysilicon layer within the trench 12a constituting the trench gate 13. In this embodiment, the etching process for forming the trench 12a can be a dry etching process or a wet etching process. The process for forming the gate oxide layer 12 can be either thermal oxidation or chemical vapor deposition. The process for forming the polysilicon layer can be chemical vapor deposition. The process for removing the polysilicon layer outside the trench 12a and making the top surface of the polysilicon layer inside the trench 12a flush with the top surface of the epitaxial layer 11 can be chemical mechanical polishing.

[0058] like Figure 6 As shown, after forming the trench gate 13, an ion implantation process is performed to form a well region 14a within the epitaxial layer 11 and simultaneously implant a layer 14b within the trench gate 13. The well region 14a and the implanted layer 14b are doped with a first doping type. The first doping type is, for example, P-type.

[0059] like Figure 7 and Figure 8As shown, an ion implantation process is performed to form a heavily doped layer 15 on the surface of the epitaxial layer 11 of the active region, the surface of the active region gate 13a, and the surface of the terminal region gate 13b, so that the resistivity of the active region gate 13a and the resistivity of the terminal region gate 13b are the same. The heavily doped layer 15 is of a second doping type, for example, N-type. The heavily doped layer 15 includes an active heavily doped layer 15a and a terminal heavily doped layer 15b. The active heavily doped layer 15a constitutes a conductive channel of the trench MOS device. The terminal heavily doped layer 15b completely covers the terminal region gate 13b to ensure that the resistivity of the active region gate 13a and the resistivity of the terminal region gate 13b are the same. The terminal heavily doped layer 15b is added in the terminal region gate 13b, and the resistivity of the terminal region gate 13b is reduced to be the same as the resistivity of the active region gate 13a, ensuring that the resistivity of the gate of all regions of the trench MOS device is consistent, effectively solving the problem of uneven distribution of the gate resistance at the junction of the active region and the terminal region, and effectively avoiding uneven voltage distribution caused by the difference in gate resistance between the active region and the terminal region, strengthening the protection of the gate oxide layer, and reducing the impact of electrostatic breakdown on the device. At the same time, the resistivity of the terminal region gate 13b is reduced, thereby reducing the resistivity of the entire gate of the trench MOS device, further reducing the gate resistance of the trench MOS device, and thereby reducing the risk of local hot spot burning caused by the high resistance of the gate of the trench MOS.

[0060] The embodiment also provides a mask plate pattern structure for forming the trench MOS structure of any one of the above-mentioned embodiments, and the mask plate pattern structure comprises:

[0061] an active region pattern and a terminal region pattern;

[0062] an epitaxial layer pattern on the active region pattern and the terminal region pattern;

[0063] a trench gate pattern in the epitaxial layer pattern, and the trench gate pattern comprises an active region gate pattern and a terminal region gate pattern;

[0064] a heavily doped layer pattern on the epitaxial layer pattern of the active region pattern, the active region gate pattern, and the terminal region gate pattern.

[0065] Specifically, the terminal region pattern is located at the edge of the mask plate pattern structure, and the shape of the terminal region pattern is comb-shaped.

[0066] In the ion implantation process of forming the heavily doped layer, the active region in the mask plate pattern structure corresponding to the active region of the device is fully opened, and only the region corresponding to the terminal region gate in the mask plate pattern structure in the terminal region of the device is opened, so as to perform the ion implantation process on the entire active region and the terminal region gate region of the trench type MOS device to form the heavily doped layer, and then obtain the trench type MOS device with the same resistivity of the active region gate and the terminal region gate.

[0067] As can be seen from the above, in the trench type MOS structure provided by the embodiment of the present application, the heavily doped layer with the same resistivity as the surface layer of the active region gate is arranged on the surface layer of the terminal region gate, so that the resistivity of the active region gate and the resistivity of the terminal region gate are the same. The unexpected technical effect of the present application is that the surface layer of the terminal region gate is increased with the heavily doped layer, the resistivity of the terminal region gate is reduced to the same as the resistivity of the active region gate, which ensures that the resistivity of the gate in all regions of the trench type MOS device is consistent, effectively solves the problem of uneven distribution of the gate resistance value at the connection between the active region and the terminal region, effectively avoids uneven voltage distribution caused by the difference in gate resistance value between the active region and the terminal region, strengthens the protection of the gate oxide layer, and reduces the impact of electrostatic breakdown on the trench type MOS device. At the same time, the resistivity of the terminal region gate is reduced, thereby reducing the resistivity of the entire gate of the trench type MOS device, further reducing the gate resistance of the trench type MOS device, and thereby reducing the risk of local hot spot burning caused by high gate resistance leading to high power density.

[0068] In addition, it should be recognized that although the present application has been disclosed with the preferred embodiments as above, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible changes and modifications or equivalent embodiments of the above disclosed technical content can be made to the technical solution of the present application without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application without departing from the content of the technical solution of the present application, all still belong to the scope of protection of the technical solution of the present application.

Claims

1. A trench-type MOS structure, characterized in that, include: A substrate, the substrate comprising an active region and a termination region; Epitaxial layer, the epitaxial layer being located on the substrate; A trench gate, wherein the trench gate is located within the epitaxial layer and the trench gate includes an active region gate and a terminal region gate, the terminal region gate including a first portion of the terminal region gate and a second portion of the terminal region gate connected to each other, the first portion of the terminal region gate being used to electrically connect to the active region gate; A heavily doped layer, comprising an active heavily doped layer and a terminal heavily doped layer electrically connected, wherein the active heavily doped layer is located on the surface of the epitaxial layer of the active region and on the surface of the gate of the active region, and the terminal heavily doped layer is located on the surface of the gate of the terminal region, wherein the terminal heavily doped layer completely covers the gate of the terminal region such that the resistivity of the gate of the active region and the resistivity of the gate of the terminal region are the same.

2. The trench-type MOS structure according to claim 1, characterized in that, The second portion of the terminal region gate is used to lead the trench gate to the conductive layer.

3. The trench-type MOS structure according to claim 2, characterized in that, The region of the terminal heavily doped layer includes a first portion and a second portion of the terminal heavily doped layer. The length of the first portion of the terminal heavily doped layer is greater than or equal to the length of the first portion of the terminal gate region, and the width of the first portion of the terminal heavily doped layer is greater than or equal to the width of the first portion of the terminal gate region. The length of the second portion of the terminal heavily doped layer is greater than or equal to the length of the second portion of the terminal gate region, and the width of the second portion of the terminal heavily doped layer is greater than or equal to the width of the second portion of the terminal gate region. Furthermore, the portion of the first portion of the terminal heavily doped layer that is longer or wider than the first portion of the terminal gate region and the portion of the second portion of the terminal heavily doped layer that is longer or wider than the second portion of the terminal gate region satisfy a preset threshold.

4. The trench-type MOS structure according to claim 1, characterized in that, An implantation layer is also formed in the trench gate, the implantation layer being located below the heavily doped layer and the doping types of the heavily doped layer and the implantation layer being opposite.

5. A method for forming a trench-type MOS structure, characterized in that, include: A substrate is provided, the substrate including an active region and a termination region, an epitaxial layer is formed on the substrate, a trench gate is formed in the epitaxial layer, the trench gate including an active region gate and a termination region gate, the termination region gate including a first portion of the termination region gate and a second portion of the termination region gate connected to each other, the first portion of the termination region gate being used to electrically connect to the active region gate; An ion implantation process is performed to form heavily doped layers on the surface of the epitaxial layer of the active region, the surface of the gate of the active region, and the surface of the gate of the terminal region. The heavily doped layers include an active heavily doped layer and a terminal heavily doped layer, and the active heavily doped layer and the terminal heavily doped layer are electrically connected. The active heavily doped layer is located on the surface of the epitaxial layer of the active region and the surface of the gate of the active region, and the terminal heavily doped layer is located on the surface of the gate of the terminal region. The terminal heavily doped layer completely covers the gate of the terminal region so that the resistivity of the gate of the active region and the resistivity of the gate of the terminal region are the same.

6. The method for forming a trench-type MOS structure according to claim 5, characterized in that, The method for forming the trench gate within the epitaxial layer includes: An etching process is performed to form trenches within the epitaxial layer; A gate oxide layer is formed, which covers the bottom and sidewalls of the trench; A polysilicon layer is formed, which fills the trench and covers the epitaxial layer; The polysilicon layer outside the trench is removed and the top surface of the polysilicon layer inside the trench is flush with the top surface of the epitaxial layer, wherein the polysilicon layer inside the trench constitutes a trench gate.

7. The method for forming a trench-type MOS structure according to claim 6, characterized in that, After the trench gate is formed, an ion implantation process is performed to form a well region in the epitaxial layer and an implantation layer in the trench gate.

8. The method for forming a trench-type MOS structure according to claim 7, characterized in that, The well region and the implanted layer are doped with the first doping type, and the heavily doped layer is doped with the second doping type.

9. A photomask pattern structure for forming a trench-type MOS structure as described in any one of claims 1-4, characterized in that, The mask pattern structure includes: Active region graphics and terminal region graphics; An epitaxial layer pattern, wherein the epitaxial layer pattern is located on the active region pattern and the terminal region pattern; A trench gate pattern, wherein the trench gate pattern is located within the epitaxial layer pattern and the trench gate pattern includes an active region gate pattern and a terminal region gate pattern; A heavily doped layer pattern, wherein the heavily doped layer pattern is located on the epitaxial layer pattern of the active region pattern, on the active region gate pattern, and on the terminal region gate pattern.

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