A silicon carbide mos device with backside super junction structure and a preparation process thereof

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a silicon carbide MOS device with a back side super junction structure and a preparation process thereof, which comprises a plurality of parallel MOS cells, a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P+ layer, an N well layer and a P well layer, an N type column is formed in the middle region of a single MOS cell and between the N substrate layer and the N diffusion layer through ion implantation, and the N type column is internally provided with a plurality of super junction P columns which do not contact each other. The application sets the plurality of super junction P columns which do not contact each other in the N type column and sets P type columns on both sides of the N type column, effectively optimizes the electric field distribution, significantly improves the breakdown voltage of the device, meanwhile, the low on-resistance is maintained, and the reliability and stability of the device in high-voltage application are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a silicon carbide MOS device with a backside super junction structure and a preparation process thereof. BACKGROUND

[0002] Silicon carbide MOS devices are highly concerned in the field of power semiconductors due to their excellent voltage resistance and high temperature performance. However, the traditional structure is prone to electric field concentration and increased on-state resistance under high voltage. The prior art such as CN115799309A introduces a backside super junction layer on the drain side to optimize the electric field distribution to a certain extent, but still has limitations such as insufficient charge balance, high process complexity, and insufficient continuity of longitudinal current path, which restricts the further improvement of device performance and the reliability of high-frequency and high-voltage applications.

[0003] The existing patent discloses a SiC MOSFET structure with a backside super junction layer (publication number CN115799309A), which adds a super junction layer composed of P columns and N columns above the N+ substrate on the drain side based on the conventional trench type SiC MOSFET structure. The backside super junction structure in the existing patent refers to a special structure layer located on the drain side of the MOS device, which is composed of alternating P-type columns and N-type columns, used to optimize the electric field distribution of the device. However, the backside super junction structure in the existing patent has problems such as insufficient charge balance, high process complexity, insufficient continuity of longitudinal current path, and limited optimization of electric field distribution. SUMMARY

[0004] The present application provides a silicon carbide MOS device with a backside super junction structure and a preparation process thereof to solve the existing technical problems, solving the problem of insufficient continuity of longitudinal current path of the existing MOS device.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a silicon carbide MOS device with a backside super junction structure, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain, a semiconductor epitaxial layer, a source and a gate, the semiconductor epitaxial layer comprising an N substrate layer, an N diffusion layer, a P+ layer, an N well layer and a P well layer, the middle region of each MOS cell and between the N substrate layer and the N diffusion layer is formed with an N-type column by ion implantation, and the N-type column is provided with a plurality of super junction P columns that do not contact each other.

[0006] Each MOS cell and on both sides of the N-type column is formed with a P-type column by ion implantation.

[0007] Furthermore, the top end of the P-type column directly contacts the N diffusion layer, and the bottom end of the P-type column directly contacts the N substrate layer.

[0008] Further, the super junction P column further comprises a contact P column, which is in direct contact with the N substrate layer.

[0009] Further, the N type column further comprises a through N type column, the top end of which penetrates the N diffusion layer and is in contact with the P well layer.

[0010] Further, the inside of the N diffusion layer in a single MOS cell is formed with an N+ intermediate layer by ion implantation.

[0011] Further, the cross-sectional profile of the N+ intermediate layer is in the shape of a "U", and the two end portions of the N+ intermediate layer are in contact with the P well layer on both sides of the vector, respectively.

[0012] Further, the N substrate layer further comprises a through substrate layer, which is integrated with the N type column.

[0013] A preparation process of a silicon carbide MOS device with a backside super junction structure, specifically comprising:

[0014] S1, growing an N diffusion layer on the front surface of an N substrate layer;

[0015] S2, forming a P type column and an N type column in the N diffusion layer by a photoetching and ion implantation process, wherein the N type column is further implanted to form a plurality of super junction P columns that are not in contact with each other;

[0016] S3, performing a high-temperature annealing treatment to activate the implanted ions and repair the lattice damage;

[0017] S4, growing a gate oxide layer on the structure surface and depositing polysilicon to form a gate;

[0018] S5, forming a P well layer, an N well layer and a P+ layer by a photoetching and ion implantation process;

[0019] S6, forming a source and drain metallization layer and completing device interconnection;

[0020] S7, performing backside grinding and metallization treatment to form a drain contact.

[0021] Further, in step S2, when the P type column and the N type column are formed by ion implantation, multiple implantation and multiple photoetching processes are adopted to ensure that the longitudinal depth and lateral distribution of the columnar structure are uniform.

[0022] The present application provides a silicon carbide MOS device with a backside super junction structure and a preparation process thereof, compared with the prior art, the effects obtained by the present method are:

[0023] 1. The present application effectively optimizes the electric field distribution by setting multiple super-junction P columns that do not contact each other in the N-type column and setting P-type columns on both sides, significantly improves the breakdown voltage of the device, while maintaining a low on-resistance, enhances the reliability and stability of the device in high-voltage applications.

[0024] 2. The present application improves the charge balance ability of the device by further setting a contact P column in direct contact with the N substrate layer in the super-junction P column, enhances the voltage stability, and makes it exhibit better electric field modulation effect and overall reliability in high-voltage working environment.

[0025] 3. The present application enhances the continuity of the longitudinal current path by introducing a through N-type column structure and contacting its top end with the P well layer, effectively reduces the on-resistance of the device, improves the current carrying capacity, while maintaining good blocking characteristics, suitable for high power application scenarios.

[0026] 4. The present application forms a U-shaped cross-section N+ intermediate layer inside the N diffusion layer and contacts the P well layer on both sides, significantly enhances the current spreading ability between the source region and the drift region, improves the switching characteristics and on-uniformity of the device, and helps to improve the overall conversion efficiency and running stability.

[0027] 5. The present application further optimizes the longitudinal electrical connection and current distribution by designing the through substrate layer and N-type column as an integral structure, and combining the setting of N+ intermediate layer, improves the structural integrity and electrical performance of the device, so that it can still maintain excellent reliability and efficiency under harsh working conditions such as high temperature and high frequency. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of example one in the present application;

[0029] Figure 2 is a schematic diagram of example two in the present application;

[0030] Figure 3 is a schematic diagram of example three in the present application;

[0031] Figure 4 is a schematic diagram of example four in the present application;

[0032] Figure 5 is a schematic diagram of example five in the present application.

[0033] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N diffusion layer; 6, P+ layer; 7, N well layer; 8, P well layer; 9, P-type column; 10, N-type column; 11, super-junction P column; 12, N+ intermediate layer; 101, through N-type column; 401, through substrate layer; 1101, contact P column. DETAILED DESCRIPTION

[0034] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 1 As shown, a fabrication process for a silicon carbide MOS device with a back-side superjunction structure specifically includes:

[0036] Step 1: Epitaxially grow an N-diffusion layer 5 on the front side of the N substrate layer 4; Epitaxially growing an N-diffusion layer 5 on the front side of the N substrate layer 4 provides a high-quality material basis for subsequent ion implantation and the formation of superjunction structures.

[0037] Step 2: P-type pillars 9 and N-type pillars 10 are formed in the N-diffusion layer 5 using photolithography and ion implantation. Multiple non-contact superjunction P-pillars 11 are further implanted into the N-type pillars 10. In this step, multiple implantation and photolithography processes are used to ensure uniform vertical depth and lateral distribution of the pillar structures during the formation of the P-type pillars 9 and N-type pillars 10. The formation of the P-type pillars 9, N-type pillars 10, and superjunction P-pillars 11 through photolithography and ion implantation achieves precise doping distribution and structural control.

[0038] Step 3: Perform high-temperature annealing to activate the implanted ions and repair lattice damage; and grow a gate oxide layer on the surface of the structure and deposit polysilicon to form gate 3; the high-temperature annealing effectively activates the implanted ions and repairs lattice damage, improving the electrical properties and structural integrity of the material.

[0039] Step 4: Form P-well layer 8, N-well layer 7 and P+ layer 6 through photolithography and ion implantation. Forming P-well layer 8, N-well layer 7 and P+ layer 6 through photolithography and ion implantation enables fine control of the device's functional regions and optimizes the device's threshold voltage and conduction characteristics.

[0040] Step 5: Form source 2 and drain 1 metallization layers and complete device interconnection; then perform backside grinding and metallization to form drain contacts. Forming metallization layers and completing device interconnection, combined with backside grinding and metallization, achieves low-resistance ohmic contacts and good heat dissipation performance, improving the overall reliability and power handling capability of the device.

[0041] Example 1

[0042] like Figure 1As shown, according to one aspect of the present invention, a silicon carbide MOS device with a back-side superjunction structure is provided, comprising a plurality of parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-diffusion layer 5, a P+ layer 6, an N-well layer 7, and a P-well layer 8. An N-type pillar 10 is formed by ion implantation in the middle region of the individual MOS cell between the N-substrate layer 4 and the N-diffusion layer 5. A plurality of non-contact superjunction P-pillars 11 are disposed within the N-type pillar 10. P-type pillars 9 are formed by ion implantation on both sides of the N-type pillar 10 in the individual MOS cell. The top end of the P-type pillar 9 is in direct contact with the N-diffusion layer 5, and the bottom end of the P-type pillar 9 is in direct contact with the N-substrate layer 4.

[0043] A back-side superjunction structure is constructed by placing an N-type pillar 10 between the N-substrate layer 4 and the N-diffusion layer 5 in the middle region of each MOS cell, embedding multiple non-contacting superjunction P-pillars 11 inside the pillar, and forming P-type pillars 9 on both sides of the N-type pillars 10. This structure optimizes the electric field distribution through the alternating arrangement of P / N pillars, significantly improving the breakdown voltage of the device while maintaining a low on-resistance, thus enhancing the overall performance and reliability of the device.

[0044] Example 2

[0045] like Figure 2 As shown, the superjunction P-pillar 11 also includes a contact P-pillar 1101, which is in direct contact with the N-substrate layer 4. The introduction of the contact P-pillar 1101 into the superjunction P-pillar 11, which directly connects it to the N-substrate layer 4, further improves the charge balance effect and enhances the breakdown voltage stability of the device, especially exhibiting better electric field modulation capability and reliability in high-voltage applications.

[0046] Example 3

[0047] like Figure 3 As shown, the N-type pillar 10 also includes a through-type pillar 101, the top end of which penetrates the N-diffusion layer 5 and contacts the P-well layer 8. By providing a through-type pillar 101 in the N-type pillar 10, with its top end penetrating the N-diffusion layer 5 and contacting the P-well layer 8, the continuity of the longitudinal current path is enhanced, effectively reducing the on-resistance of the device, improving the current carrying capacity, and maintaining good blocking characteristics.

[0048] Example 4

[0049] like Figure 4As shown, an N+ intermediate layer 12 is formed inside the N-diffusion layer 5 in a single MOS cell through ion implantation. The cross-sectional profile of the N+ intermediate layer 12 is U-shaped, and its two ends are in contact with the P-well layers 8 on both sides of the vector. The formation of a U-shaped N+ intermediate layer 12 inside the N-diffusion layer 5 through ion implantation, with its two ends in contact with the P-well layers 8 on both sides, enhances the current spread capability between the source region and the drift region, improves the switching performance and conduction uniformity of the device, and helps to improve the overall efficiency and stability.

[0050] Example 5

[0051] like Figure 5 As shown, an N+ intermediate layer 12 is formed inside the N-diffusion layer 5 in a single MOS cell through ion implantation. The N-substrate layer 4 also includes a through-substrate layer 401, which is integrated with the N-type pillar 10. By designing the through-substrate layer 401 and the N-type pillar 10 as an integrated structure and forming the N+ intermediate layer 12 in the N-diffusion layer 5, the vertical electrical connection and current distribution are further optimized, improving the structural integrity and electrical performance of the device, especially exhibiting better reliability and efficiency in high-temperature and high-frequency applications.

[0052] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A silicon carbide MOS device with a back-side superjunction structure, comprising a plurality of MOS cells arranged in parallel, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: An N-type pillar (10) is formed in the middle region of a single MOS cell between the N substrate layer (4) and the N diffusion layer (5) by ion implantation. The contents of the N-type pillar (10) contain a plurality of non-contact superjunction P pillars (11). In a single MOS cell, P-type pillars (9) are formed on both sides of the N-type pillar (10) through ion implantation; An N+ intermediate layer (12) is formed inside the N diffusion layer (5) of a single MOS cell by ion implantation. The cross-sectional profile of the N+ intermediate layer (12) is U-shaped, and the two ends of the N+ intermediate layer (12) are in contact with the P-well layers (8) on both sides of the vector.

2. A silicon carbide MOS device with a back-side superjunction structure, comprising a plurality of MOS cells arranged in parallel, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (6), an N-well layer (7), and a P-well layer (8), characterized in that: An N-type pillar (10) is formed in the middle region of a single MOS cell between the N substrate layer (4) and the N diffusion layer (5) by ion implantation. The contents of the N-type pillar (10) contain a plurality of non-contact superjunction P pillars (11). In a single MOS cell, P-type pillars (9) are formed on both sides of the N-type pillar (10) through ion implantation; An N+ intermediate layer (12) is formed inside the N diffusion layer (5) of a single MOS cell by ion implantation. The N-substrate layer (4) further includes a through-substrate layer (401), wherein the through-substrate layer (401) and the N-type pillar (10) are integrated.

Images