Device structure for improving switching speed and robustness of SiC MOS device and manufacturing method

Abstract

According to the device structure for improving the switching speed and robustness of the SiC MOS device and the manufacturing method, an arc-shaped gate oxide layer which is locally thickened is selectively additionally arranged above a JFET area of a device cell, the total input capacitance is reduced by reducing the gate-drain capacitance, the switching speed is improved, and power consumption is reduced; meanwhile, the thickened JFET region gate oxide layer improves the gate oxide reliability and the single particle resistance, and the channel region gate oxide layer is kept thin so as to maintain low Ron. The key preparation method comprises two gate oxidation and polycrystalline silicon deposition processes: local oxidation is carried out in a JFET region, an arc-shaped polycrystalline silicon gate is formed, a main gate structure is formed through second overall oxidation, and doping distribution is regulated and controlled in combination with self-aligned injection, hard mask step-by-step treatment and a high-temperature activation process. According to the invention, low Ron, high switching speed and high robustness are taken into account, the method is suitable for SiC and Si-based MOS devices, and the performance and reliability of the devices are significantly improved.

Description

Technical Field

[0001] This invention relates to a device structure and fabrication method, specifically disclosing a device structure and fabrication method for improving the switching speed and robustness of SiC MOS devices. Background Technology

[0002] 4H-SiC power MOSFETs possess excellent characteristics such as short switching time, simple gate drive circuitry, high power density, and high conversion efficiency, giving them significant advantages in electric vehicles, motors, photovoltaics, and other fields, and attracting widespread attention in power electronics systems. For SiC MOSFETs, switching speed has a significant impact on power consumption and operating frequency, and the input capacitance Ciss is a major factor affecting its switching speed. Higher input capacitance increases switching losses, limiting high-frequency applications. Meanwhile, the on-resistance Ron is also a key parameter, representing the total transfer resistance between the drain and source when the device is in the on-state. This often requires optimizing device structural parameters to adjust Ron to keep it within a small range, thereby improving device performance. In this process, the gate oxide layer thickness t is minimized during device design and manufacturing. ox This reduces the channel resistance R of the device. CH However, since the input capacitance is composed of the gate-source capacitance Cgs and the gate-drain capacitance Cgd connected in parallel, its expression is Equation 1. It can be seen that reducing the gate oxide layer thickness t ox This increases the device's input capacitance, deteriorates its switching characteristics, reduces switching speed, increases switching power consumption, and lowers the device's operating frequency. Furthermore, since the reliability of the gate oxide layer increases exponentially with increasing oxide thickness, reducing the gate oxide layer thickness t... ox It will affect the robustness of the device and reduce its reliability.

[0003]

[0004] It can be seen that there is still room for improvement in the reliability of SiC MOSFETs. They often encounter reliability problems during long-term operation or under some extreme conditions. How to balance their low on-resistance, excellent switching characteristics and robustness has become the top priority in the development of SiC MOSFETs. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a device structure that improves the switching speed and robustness of SiC MOS devices, the technical solution of which is as follows:

[0006] A device structure for improving the switching speed and robustness of SiC MOS devices, characterized in that:

[0007] A locally thickened arc-shaped gate oxide layer (15) is provided above the JFET region (7) of the SiC MOSFET cell, and its thickness is greater than that of the gate oxide layer (8) above the channel region (4). The arc-shaped gate oxide layer (15) and the corresponding arc-shaped polysilicon gate (9) together constitute the gate control structure of the JFET region. By selectively increasing the thickness of the gate oxide layer in the JFET region, the input capacitance (Ciss) is reduced, while maintaining a low on-resistance (Ron).

[0008] This invention also discloses a fabrication method for improving the switching speed and robustness of SiC MOS devices, characterized by the following steps:

[0009] a. An epitaxial layer (2) of SiC is grown on a SiC substrate (1);

[0010] b. Perform selective ion implantation sequentially in the Pwell, Nplus, Pplus, and JFET regions;

[0011] c. Perform the first local oxidation above the JFET region (7) to form an arc-shaped gate oxide layer (15), and deposit and etch polysilicon (24) to form the arc-shaped gate structure of the JFET region;

[0012] d. Perform a second overall oxidation and deposition to form the gate oxide layer (8) and polysilicon gate (9) of the main gate;

[0013] e. Deposit an ILD dielectric layer (10), etch source contact holes and form an ohmic contact layer (11); f. Deposit a front metal electrode (13) and a back drain electrode (12).

[0014] 4. The preparation method according to claim 3, characterized in that:

[0015] In step c, the local thickening of the arc-shaped gate oxide layer (15) and the polysilicon gate (24) in the JFET region is achieved through two photolithography etching processes.

[0016] Preferably, step b further includes: after completing the JFET region implantation, depositing a carbon film (step 108), activating the doped impurities by high-temperature annealing, and removing the carbon film.

[0017] Preferably, step a further step includes: depositing an oxide layer and defining an active region by photolithography etching (step 110).

[0018] Preferably, step e further includes photolithographic etching of the ILD layer after depositing the ILD dielectric layer (10) to open the contact holes of the gate control bus region (step 114).

[0019] Preferably, the Nplus region (5) in step b is implanted through a self-aligned process, which specifically includes: depositing a hard mask layer (16, 19), photolithography to form an implantation window, etching to generate a sidewall (21), and using the sidewall and mask layer to achieve self-alignment between the Nplus region (5) and the channel region (4).

[0020] Preferably, step f includes a thinning process on the back side of the wafer (step 118) before depositing the back drain electrode (12).

[0021] Preferably, step d is followed by: removing surface damage to the wafer by high-temperature oxidation and etching the sacrificial oxide layer to optimize surface quality.

[0022] Beneficial effects

[0023] 1. The process steps are relatively simple. Compared with the traditional process, only a part of the arc-shaped gate oxide layer is grown on top of the JFET before the gate oxide layer is grown.

[0024] 2. By reducing the gate oxide layer thickness, the input capacitance can be reduced while lowering Ron, ensuring excellent switching speed and reducing switching power consumption.

[0025] 3. It can increase the robustness of the device, increase the reliability of the gate oxide, and make it less prone to gate oxide breakdown.

[0026] 4. The improvements and ideas in this device structure are applicable not only to SiC MOSFETs, but also to other structures such as Si MOSFETs, demonstrating strong technical applicability.

[0027] 5. No new process improvements or research and development are required, which reduces the difficulty of production and processing and makes it highly feasible.

[0028] 6. Increasing the thickness of the gate oxide layer above the JFET region can improve the device's resistance to single-event events. Attached Figure Description

[0029] Figure 1 Cross-sectional views of a conventional SiC MOSFET device and the SiC MOSFET device of the present invention are shown below; wherein, (a) is a cross-sectional view of a conventional SiC MOSFET device; and (b) is a cross-sectional view of the SiC MOSFET device of the present invention.

[0030] Figure 2 This is a flowchart illustrating the fabrication process of the cellular structure device of the present invention.

[0031] Figure 3 This is a schematic diagram of the epitaxial growth process on a SiC substrate.

[0032] Figure 4 This is a schematic diagram of the PWel lithography and implantation process;

[0033] Figure 5 This is a schematic diagram of the NPlus self-aligned lithography process; where (a) is a schematic diagram of hard mask layer deposition and lithography development; and (b) is a schematic diagram of the formation of the NPlus region and the channel region.

[0034] Figure 6 This is a schematic diagram of the PPlus photolithography and implantation process; (a) is a schematic diagram of hard mask layer deposition and photolithography development; (b) is a schematic diagram of Pplus region formation.

[0035] Figure 7 This is a schematic diagram of the Poly lithography process; where (a) is a schematic diagram of the first gate oxidation and Poly process; and (b) is a schematic diagram of the second gate oxidation and Poly process.

[0036] Figure 8 This is a schematic diagram of source contact lithography and ohmic contact processes;

[0037] Figure 9 This is a schematic diagram of the metalworking process on the front. Detailed Implementation

[0038] Gate oxide thickness is a critical factor in SiC MOSFET fabrication. By increasing the gate oxide thickness only in the JFET region during the process, it is possible to achieve a lower Ron while maintaining a high switching speed, reducing switching losses, and ensuring good robustness and single-event immunity. Figure 1(a) shows a cross-sectional view of a conventional SiC MOSFET, where 13 is the source region, 9 is the gate region, 5 is the Nplus implantation region, 6 is the Pplus implantation region, 8 is the gate oxide layer, 4 is the Pwel 1 implantation region, 2 is the N-type doped drift region, 1 is the N-type doped substrate, 12 is the drain region, and 7 is the JFET region. Conduction capability is one of the key factors in evaluating the performance of a SiC MOSFET, and changes in the thickness of the gate oxide layer 8 have a significant impact on conduction capability. This is mainly because increasing the thickness of the gate oxide layer 8 increases the resistance of the channel region 4 located between the Nplus region 5 and the JFET region 7. This not only makes the device more difficult to turn on, requiring a larger threshold voltage, but also leads to an increase in overall on-resistance and a decrease in device conduction capability. Therefore, reducing the thickness of the gate oxide layer 8 is a common way to reduce on-resistance. However, as the thickness of the gate oxide layer 8 decreases, the electric field strength applied to it increases. When the gate oxide layer 8 shrinks to a certain extent, this will seriously threaten the gate oxide reliability of the device, causing a decrease in its robustness. Furthermore, since the thickness of the gate oxide layer 8 also affects the input capacitance of the device, a decrease in its thickness leads to a larger input capacitance. A larger input capacitance reduces the switching speed and increases switching power consumption, affecting the device's operating frequency. Therefore, improving device performance by reducing the thickness of the gate oxide layer 8 has limitations.

[0039] To avoid the reduced switching speed and robustness caused by decreasing the overall gate oxide layer 8 thickness, this invention adopts the advantages of reducing the gate oxide layer 8 thickness above the channel region (which reduces Ron and input capacitance) and increasing the gate oxide layer 8 thickness above the JFET region 7 (which does not affect Ron while increasing device robustness and single-event immunity). Therefore, a novel SiC MOSFET device cell structure design scheme is proposed, such as… Figure 1As shown in (b), before growing the overall gate oxide layer 8, a thin, arc-shaped gate oxide layer 15 is grown above the JFET region 7 to selectively increase the thickness of the gate oxide layer above the JFET region 7. Subsequently, the polysilicon also exhibits an arc-shaped bulge above the JFET region 7. The device of this invention can selectively increase the gate oxide layer thickness through the newly grown arc-shaped gate oxide layer. Channel resistance, as a component of on-resistance, increases with the increase of the gate oxide layer thickness above the channel region. However, this invention only increases the gate oxide layer thickness above the JFET region, so its impact on Ron is not significant. For the input capacitance, it is composed of the gate-source capacitance Cgs and the gate-drain capacitance Cgd connected in parallel, and is inversely proportional to the gate oxide layer thickness. The greater the gate oxide layer thickness, the smaller the input capacitance. Although this invention only increases the gate oxide layer thickness in the JFET region, the overall input capacitance decreases accordingly, achieving the expected increase in switching speed, reduction in switching losses, and reduction in the device's operating frequency. Furthermore, since the single-event immunity of a device is proportional to the thickness of the gate oxide layer, the single-event immunity of the device of the present invention will also be increased, thereby improving the device performance.

[0040] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments. The embodiments are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Furthermore, the components illustrated in the drawings are not necessarily drawn to scale. The present invention also omits descriptions of well-known components, processing techniques, and processes to avoid unnecessarily limiting the present invention.

[0041] Example:

[0042] A SiC MOSFET device that improves switching speed and robustness (taking a planar gate N-channel enhancement-mode silicon carbide field-effect transistor as an example).

[0043] A comparison of the cell region cross-sections of traditional SiC MOSFET device cell designs and those of the device cell designs in this embodiment is shown below. Figure 1As shown in (a) and (b), the device in this embodiment includes an active region, a gate-controlled bus region, and a termination region. Since the gate-controlled bus region and termination region are consistent with the traditional SiC MOSFET design and fabrication methods, they will not be described in detail here. However, in the active region of this embodiment, the design modifications are mainly made to the gate oxide layer and the gate of the device cell. The active region of this embodiment is constructed by the newly invented cell structure, specifically including a SiC substrate 1, a SiC epitaxial layer 2, a Pwell well region 3, a channel region 4, an Nplus region 5, a Pplus region 6, a JFET region 7, a gate oxide layer 8, a Poly gate 9, an ILD dielectric layer 10, an ohmic contact layer 11, a back electrode metal layer 12, a front electrode metal layer 13, and an ohmic contact layer 14 formed by the laser-annealed substrate and the metal layer deposited on the back side. The newly added structure of this invention is as follows... Figure 1 As shown in (b) 15, the implementation can be achieved by performing an additional gate oxidation, poly deposition, poly photolithography etching, and poly oxidation process in the traditional SiC MOSFET process. The additional arc-shaped gate oxide region 15 formed can effectively improve the switching characteristics and robustness of the device. The following section combines... Figure 2 The fabrication method of the device in this embodiment is described in detail, and the steps are as follows:

[0044] In step 101, based on product requirements, a SiC substrate wafer 1 with appropriate size, thickness, and resistivity is selected. Then, the corresponding epitaxial concentration and thickness are determined, and an epitaxial layer 2 is grown on the substrate wafer to obtain the SiC epitaxial layer 2. The epitaxial concentration and thickness are key factors affecting device performance and need to be within a suitable range, such as... Figure 3 As shown.

[0045] In step 102, marking lithography and marking etching are performed to form a pattern on the wafer surface that can provide alignment marks for subsequent lithography steps.

[0046] In step 103, a hard mask layer 16 is deposited on the surface of the epitaxial layer 2 of the SiC wafer. The material can be silicon dioxide, silicon nitride, polysilicon, etc. After photolithography and etching, Pwel 1 implantation windows 17 and 18 are obtained. Following resist removal, selective high-temperature ion implantation is performed to obtain the Pwel 1 doped region 3, as shown below. Figure 4 As shown.

[0047] In step 104, after obtaining the Pwel injection window in the previous step, a hard mask layer 19 of a certain thickness is deposited on top of it, and Nplus photolithography is used to retain the photoresist 20, as shown. Figure 5 As shown in (a). Simultaneously, after etching the hard mask layer 19 using a self-aligned process, sidewalls 21 are formed on both sides of the steps of the hard mask layer 16. Protected by the photoresist 20, the underlying hard mask layer 22 is also preserved, as shown... Figure 5As shown in (b).

[0048] In step 105, high-temperature ion implantation of N or P is performed. Due to the presence of hard mask layers 16 and 22, selective implantation within the Pwel well region can be achieved, resulting in... Figure 5 The Nplus doped region 5 is shown in (b). The Pwel region below the sidewall 21 forms... Figure 5 (b) shows the trench area 4.

[0049] In step 106, some hard mask layers remain on the wafer surface after step 105, which will affect the Pplus implantation operation. Therefore, it is necessary to first remove all hard mask layers on the wafer surface, redeposit the required hard mask layer 16, and perform photolithography etching of PPlus to obtain the PPlus region implantation window 23, as shown. Figure 6 As shown in (a), after resist removal, high-temperature ion implantation of B or Al was performed, thereby selectively implanting the PPlus doped region 6 into the implantation window 23, as shown. Figure 6 As shown in (b).

[0050] In step 107, the process flow of step 106 is repeated. First, the hard mask layer remaining after step 106 is removed, and then the required hard mask layer is redeposited to obtain the JFET implantation window. After removing the resist, high-temperature ion implantation of N or P is performed to selectively adjust the doping concentration of JFET region 7. After this, all hard mask layers on the wafer surface are removed.

[0051] In step 108, a carbon film is deposited on the wafer surface (to prevent impurities from spreading outwards). After that, high-temperature ion activation is performed on the doped impurities in each implantation region. Finally, the carbon film on the wafer surface is removed.

[0052] In step 109, high-temperature oxidation is performed, and the sacrificial oxide layer is removed by an etching process to obtain a SiC surface with fewer defects.

[0053] In step 110, a field oxide layer is deposited on the wafer surface obtained after step 109, and photolithography is performed to selectively remove the field oxide layer to obtain the active region.

[0054] In step 111, a first Poly process (polysilicon deposition and etching process) is performed to form a gate oxide layer 15 of a certain thickness above the JFET region and deposit a heavily doped polysilicon layer 24 of a certain thickness. Then, photolithography and etching are performed on the polysilicon and gate oxide layers to obtain the polysilicon gate above the JFET region, as shown below. Figure 7 As shown in (a).

[0055] In step 112, the process of step 111 is repeated for a second Poly process. A gate oxide layer 8 of a certain thickness is grown on the surface of the active region of the wafer, and a heavily doped polysilicon layer 9 of a certain thickness is deposited. The polysilicon and gate oxide layers are then etched using photolithography to form a polysilicon gate. Figure 7 As shown in (b).

[0056] In step 113, after completing the Poly process, an ILD dielectric layer 10 is further deposited. The material is typically USG+BPSG, and photolithography etching is performed to form source contact holes. After resist removal, ohmic contact metal is deposited, followed by rapid thermal processing to form an ohmic contact layer 11. Excess ohmic metal is then removed via etching. Figure 8 As shown.

[0057] In step 114, photolithography is performed to etch the ILD based on the previous step, contact holes are opened in the gate control bus area, and then the resist is removed.

[0058] In step 115, a front electrode metal composite layer 13 is deposited on the surface of the wafer. The material is generally Ti / TiN / Al. Photolithography and etching are performed on the metal layer to form the gate and source metal electrodes. Then, the resist is removed. Figure 9 As shown.

[0059] In step 116, a PA passivation dielectric layer is deposited on the surface of the wafer. The material is generally SiO2 / SiN. The passivation layer is then photolithographically etched and etched to open the electrode lead-out area, followed by resist removal.

[0060] In step 117, based on the previous step, a PI passivation layer is coated on the wafer surface, then photolithography is performed to open the PI layer, obtaining the PAD electrode contact area, and then a curing process is performed.

[0061] In step 118, the back side of the wafer is thinned.

[0062] In step 119, an ohmic contact metal layer is deposited on the back side of the wafer. The material is typically Ni. After laser annealing, a drain electrode metal is deposited on the back side. The material is typically Ti / Ni / Ag, resulting in drain electrode 12. Figure 1 As shown in (b). Finally, the film inspection step is performed.

[0063] This invention changes the traditional cell design structure by thickening the gate oxide layer above the JFET region. Specifically, an arc-shaped gate oxide layer structure is first grown above the JFET region before the actual gate oxide layer is grown. This design allows for the selective increase of the gate oxide layer thickness above the JFET region, mitigating problems such as increased input capacitance, decreased switching speed, increased switching power consumption, decreased operating frequency, and decreased robustness that occur when reducing the gate oxide layer thickness to reduce Ron. Furthermore, increasing the gate oxide layer thickness in the JFET region enhances the device's single-event immunity. This performance improvement requires only one additional step of gate oxide layer thickness control. By controlling Ron reduction, a device with low threshold voltage, low input capacitance, high switching speed, and high robustness is obtained, thus reducing R&D and production costs.

[0064] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A device structure for improving the switching speed and robustness of SiC MOS devices, characterized in that: A locally thickened arc-shaped gate oxide layer (15) is provided above the JFET region (7) of the SiC MOSFET cell, and its thickness is greater than that of the gate oxide layer (8) above the channel region (4). The arc-shaped gate oxide layer (15) and the corresponding arc-shaped polysilicon gate (9) together constitute the gate control structure of the JFET region. By selectively increasing the thickness of the gate oxide layer in the JFET region, the gate source capacitance is reduced, thereby reducing the total input capacitance (Ciss) while maintaining a low on-resistance (Ron).

2. A fabrication method for improving the switching speed and robustness of SiC MOS devices, characterized by: Includes the following steps: a. After determining the epitaxial specifications, an epitaxial layer (2) of SiC is grown on the SiC substrate (1); b. Perform selective ion implantation sequentially in the Pwell, Nplus, Pplus, and JFET regions; c. Perform the first local oxidation above the JFET region (7) to form an arc-shaped gate oxide layer (15), and deposit and etch polysilicon (24) to form the arc-shaped gate structure of the JFET region; d. Perform a second overall oxidation and deposition to form the gate oxide layer (8) and polysilicon gate (9) of the main gate; e. Deposit an ILD dielectric layer (10), etch source contact holes and form an ohmic contact layer (11); f. Deposit the front metal electrode (13) and the back drain electrode (12).

3. The preparation method according to claim 2, characterized in that: In step c, the local thickening of the arc-shaped gate oxide layer (15) in the JFET region is achieved through two photolithography etching processes.

4. The preparation method according to claim 2, characterized in that, Step b further includes: after completing the JFET region implantation, depositing a carbon film, activating the doped impurities by high-temperature annealing, and removing the carbon film.

5. The preparation method according to claim 2, characterized in that, Step a is followed by: depositing an oxide layer and defining the active region by photolithography etching.

6. The preparation method according to claim 2, characterized in that, Step e, after depositing the ILD dielectric layer (10), further includes photolithographic etching of the ILD layer to open the contact holes of the gate control bus region.

7. The preparation method according to claim 2, characterized in that, In step b, the Nplus region is implanted through a self-aligned process, which specifically includes: depositing a hard mask layer, photolithography to form an implantation window, etching to generate sidewalls, and using the sidewalls and mask layer to achieve self-alignment between the Nplus region and the channel region.

8. The preparation method according to claim 2, characterized in that, Step f, before depositing the back drain electrode, also includes: thinning the back side of the wafer.

9. The preparation method according to claim 2, characterized in that, Step d is followed by: removing surface damage to the wafer by high-temperature oxidation and etching the sacrificial oxide layer to optimize surface quality.

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