Display panel

Abstract

A display panel is provided that includes a circuit layer and a light emitting element on the circuit layer. The circuit layer includes a semiconductor pattern, a first insulating layer including a first contact hole configured to expose a portion of the semiconductor pattern, a plurality of first connection electrodes on the first insulating layer and electrically connected to the semiconductor pattern through the first contact hole; and a second insulating layer configured to cover the plurality of first connection electrodes and on the first insulating layer. Each of the plurality of first connection electrodes includes a first conductive layer and a second conductive layer. The second insulating layer includes a first sub-insulating layer between the first conductive layers adjacent to each other and a second sub-insulating layer disposed on the first sub-insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0057778, filed with the Korean Intellectual Property Office on April 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display panels and methods of manufacturing display panels, and particularly to enhancing or improving the reliability of display panels. Background Technology

[0004] The display device includes multiple pixels and driving circuitry (e.g., scan driving circuitry and data driving circuitry) for managing or controlling the multiple pixels. Each of the multiple pixels includes a display element and pixel driving circuitry for controlling the display element. The pixel driving circuitry may include multiple transistors interconnected in an organized manner (e.g., organically connected to each other). Connection electrodes are electrically connected or linked to semiconductor patterns of the transistors to transmit or deliver one or more electrical signals to the transistors. Summary of the Invention

[0005] One or more aspects of embodiments of this disclosure relate to a display panel including highly reliable connection electrodes (display panel with highly reliable connection electrodes) and a method for manufacturing the display panel.

[0006] Additional aspects will be set forth in part in the detailed description below, and in part will be apparent from the description or may be learned by practicing the embodiments presented in this disclosure.

[0007] According to embodiments of the present disclosure, a display panel includes a circuit layer and light-emitting elements disposed on the circuit layer, wherein the circuit layer includes: a semiconductor pattern; a first insulating layer defining a portion of the semiconductor pattern through which a first contact hole is exposed (e.g., the first insulating layer has or includes a first contact hole configured to expose a portion of the semiconductor pattern); a plurality of first connection electrodes disposed on the first insulating layer and electrically connected to the semiconductor pattern through the first contact hole; and a second insulating layer configured to cover the plurality of first connection electrodes and disposed on the first insulating layer, wherein each of the plurality of first connection electrodes includes: a first conductive layer comprising aluminum (e.g., made of aluminum); and a second conductive layer disposed on the first conductive layer and comprising aluminum (e.g., also made of aluminum), wherein the second insulating layer includes: a first sub-insulating layer disposed between adjacent first conductive layers (e.g., between a pair of adjacent first conductive layers); and a second sub-insulating layer disposed on the first sub-insulating layer and configured to cover the second conductive layer, wherein the first sub-insulating layer comprises a first organic material and a first inorganic material comprising silicon.

[0008] In one or more embodiments, the first organic material may comprise at least one of siloxane, polyimide, and acrylic polymer, and the first inorganic material may comprise at least one of silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiON).

[0009] In one or more embodiments, the second sub-insulating layer may comprise a second organic material that is different from the first organic material.

[0010] In one or more embodiments, the first sub-insulating layer may contact a side surface of a first conductive layer (e.g., on the side surface of the first conductive layer (e.g., each of the plurality of first conductive layers)) and may include a bottom surface aligned with the bottom surface of the first conductive layer (e.g., each of the plurality of first conductive layers).

[0011] In one or more embodiments, the top surface of the first sub-insulating layer may be disposed below the top surface of the first conductive layer (e.g., each of a plurality of first conductive layers).

[0012] In one or more embodiments, at least a portion of the bottom surface of each of the plurality of second conductive layers may be in contact with the first sub-insulating layer (e.g., on the first sub-insulating layer).

[0013] In one or more embodiments, at least a portion of the top surface of the first conductive layer may be in contact with the second conductive layer (e.g., on the second conductive layer), and the planar area of ​​the top surface of the first conductive layer may be smaller than the planar area of ​​the bottom surface of the second conductive layer.

[0014] In one or more embodiments, in cross-section, the side surfaces of the first conductive layer and the second conductive layer may be misaligned with each other.

[0015] In one or more embodiments, the second sub-insulating layer may contact the side and top surfaces of the second conductive layer (e.g., each of a plurality of second conductive layers).

[0016] In one or more embodiments, the light-emitting element may include a pixel electrode electrically connected to a plurality of first connection electrodes.

[0017] In one or more embodiments, the first conductive layer may include: a first layer disposed on a first insulating layer and comprising titanium; and a second layer disposed on the first layer and comprising aluminum; and the second conductive layer may include: a third layer disposed on the second layer and comprising aluminum; and a fourth layer disposed on the third layer and comprising titanium.

[0018] In one or more embodiments, the third layer may be disposed directly on the second layer, and the sum of the thicknesses of the second and third layers (e.g., total) may be at least about 10,000 angstroms (e.g., or more) and at most about 16,000 angstroms (e.g., or less).

[0019] In one or more embodiments, a plurality of first connection electrodes may be defined in a second insulating layer through their exposed second contact holes (e.g., the second insulating layer includes or has second contact holes configured to expose the plurality of first connection electrodes), wherein the circuit layer may include: second connection electrodes disposed on the second insulating layer and electrically connected to at least a portion of the plurality of first connection electrodes through the second contact holes; and a third insulating layer configured to cover the second connection electrodes and disposed on the second insulating layer.

[0020] In one or more embodiments, the second connection electrode may include: a third conductive layer comprising aluminum; and a fourth conductive layer disposed on the third conductive layer and comprising aluminum, wherein the third insulating layer may include: a third sub-insulating layer configured to cover at least a portion of a side surface of the third conductive layer and comprising a first organic material and a first inorganic material comprising silicon; and a fourth sub-insulating layer disposed on the third sub-insulating layer to cover the fourth conductive layer and comprising a second organic material different from the first organic material.

[0021] In one or more embodiments, the second contact hole may be defined in the second sub-insulating layer (e.g., the second sub-insulating layer may include the second contact hole).

[0022] In one or more embodiments of this disclosure, a display panel includes a circuit layer and light-emitting elements disposed on the circuit layer, wherein the circuit layer includes: a semiconductor pattern; a first insulating layer defining a portion of the semiconductor pattern through which a first contact hole is exposed (e.g., the first insulating layer includes or has a first contact hole configured to expose a portion of the semiconductor pattern); a plurality of first connection electrodes disposed on the first insulating layer and electrically connected to the semiconductor pattern through the first contact hole; and a second insulating layer configured to cover the plurality of first connection electrodes and disposed on the first insulating layer, wherein each of the plurality of first connection electrodes includes: a first conductive layer comprising aluminum; and a second conductive layer disposed on the first conductive layer and comprising aluminum, wherein the second insulating layer includes: a first sub-insulating layer disposed between adjacent first conductive layers (e.g., between a pair of adjacent first conductive layers); and a second sub-insulating layer disposed on the first sub-insulating layer, wherein at least a portion of the bottom surface of the second conductive layer contacts the first sub-insulating layer (e.g., on the first sub-insulating layer).

[0023] In one or more embodiments of this disclosure, a method for manufacturing a display panel includes: providing a semiconductor pattern and a first insulating layer disposed on the semiconductor pattern; forming a plurality of first connection electrodes disposed on the first insulating layer and electrically connected to the semiconductor pattern; and forming a second insulating layer covering the plurality of first connection electrodes, wherein forming the plurality of first connection electrodes and forming the second insulating layer includes: forming a plurality of first conductive layers comprising aluminum on the first insulating layer; providing a filler material between the plurality of first conductive layers to form a first sub-insulating layer covering at least a portion of a side surface of each of the plurality of first conductive layers; forming a plurality of second conductive layers comprising aluminum on the plurality of first conductive layers; and forming a second sub-insulating layer covering the plurality of second conductive layers, wherein the filler material comprises a first organic material and a first inorganic material comprising silicon.

[0024] In one or more embodiments, forming the first sub-insulating layer may further include: after providing a filler material between the plurality of first conductive layers, ashing the top surface of each of the plurality of first conductive layers.

[0025] In one or more embodiments, the top surface of the first sub-insulating layer may (e.g., be formed to be defined) be below the top surface of each of the plurality of first conductive layers.

[0026] In one or more embodiments, forming a plurality of first conductive layers may include: forming a preliminary first layer comprising titanium on a first insulating layer; forming a preliminary second layer comprising aluminum on the preliminary first layer; and patterning the preliminary first layer and the preliminary second layer, wherein forming a plurality of second conductive layers may include: forming a preliminary third layer comprising aluminum on the plurality of first conductive layers; forming a preliminary fourth layer comprising titanium on the preliminary third layer; and patterning the preliminary third layer and the preliminary fourth layer.

[0027] According to one or more embodiments, an electronic device may include a display device that incorporates a display panel of the present disclosure.

[0028] According to one or more embodiments, the electronic device may be a smartphone, television, monitor, tablet computer, electric vehicle, mobile phone, tablet personal computer (PC), mobile communication terminal, electronic notebook, e-book, portable multimedia player (PMP), navigation device, ultra-mobile PC (UMPC), laptop computer, billboard, Internet of Things (IoT) device, smartwatch, wristwatch phone, or head-mounted display (HMD). Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the foregoing and other aspects, features, and advantages of certain embodiments of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0030] Figure 1A This is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0031] Figure 1B This is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 2 This is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0033] Figure 3 This is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 4 This is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0035] Figure 5 This is an enlarged cross-sectional view of a portion of a display panel according to one or more embodiments of the present disclosure;

[0036] Figure 6A This is a cross-sectional view illustrating a portion of the configuration of a display panel according to one or more embodiments of the present disclosure;

[0037] Figure 6B This is a cross-sectional view illustrating a portion of the configuration of a display panel according to one or more embodiments of the present disclosure;

[0038] Figure 7A and Figure 7B This is a flowchart illustrating a method for manufacturing a display panel according to one or more embodiments of the present disclosure; and

[0039] Figures 8A to 8H This is a cross-sectional view illustrating some steps of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. Detailed Implementation

[0040] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be comprehensive and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0041] In this specification, it will also be understood that if a component (or area, layer, part, etc.) is referred to as being "on" another component, "connected" to another component, or "attached to" another component (for example, when a component (or area, layer, part, etc.) is referred to as being "on" another component, "connected" to another component, or "attached to" another component), then a component can be directly connected / attached to another component or directly connected / attached to another component, or there may be an intermediary third component.

[0042] Throughout this specification, similar reference numerals refer to similar elements, and their repeated descriptions are not required. Furthermore, for clarity of illustration, the thickness, scale, and dimensions of components may be exaggerated in the drawings. In other words, since the dimensions and thicknesses of components in the drawings are arbitrarily illustrated for ease of explanation, the following embodiments are not limited thereto.

[0043] The term "and / or" includes any and all combinations of one or more of the related listed items. Expressions such as "at least one of," "one of," "selected from," and "selected from among" modify the entire list of elements when they follow, precede, or are in the middle of it, but do not modify individual elements in the list. For example, throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all or variations thereof of a, b, and c.

[0044] It will be understood that while terms such as “first” and “second” are used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one component from others. For example, an element referred to as a first element in one or more embodiments may be referred to as a second element in one or more embodiments without departing from the scope of the appended claims. Unless otherwise stated, singular terms such as “a,” “an,” and “the” may include plural forms.

[0045] Spatial relative terms such as “below,” “under,” “above,” and “over” are used to explain the related relationships of the components illustrated in the accompanying drawings. The terms may be relative concepts and are described based on the orientations expressed in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” or “over” other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0046] It will also be understood that terms such as “comprising,” “containing,” “including,” “including,” “having,” “possessing,” “with,” and “with” specify a nature, a fixed quantity, a step (e.g., an action or task), an operation, an element, a component, and / or any suitable combination thereof, but do not exclude other natures, fixed quantities, steps, operations, elements, components, and / or one or more (e.g., any suitable combinations thereof).

[0047] In this specification, the phrase "direct arrangement" may refer to a situation where there is no layer, membrane, zone, plate, etc., between one part of a layer, membrane, zone, plate, etc. For example, "direct arrangement" may refer to an arrangement between two layers or two components without the use of additional components (such as adhesive components).

[0048] Unless otherwise specified, all terms used herein (including chemical, technical, and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art, and shall not be interpreted in an overly idealized or overly formal sense unless explicitly stated otherwise.

[0049] Multiple features of one or more suitable embodiments of this disclosure may be combined, either partially or entirely, or combined with each other, and one or more suitable interlocks and drives are technically possible. Multiple embodiments may be implemented independently of each other or may be implemented together in association.

[0050] The term “may” will be understood to refer to “one or more embodiments of this disclosure,” some of which include the described elements, and some of which do not include the described elements and / or include alternative elements. Similarly, alternative language such as “or” refers to “one or more embodiments of this disclosure” that include the corresponding listed items.

[0051] In this context, "mainly composed of" indicates that any additional components do not materially affect the chemical, physical, optical, or electrical properties of the semiconductor film.

[0052] In the following description, a display device and a display panel provided in the display device according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0053] Display device

[0054] Figure 1A This is a perspective view of a display device according to one or more embodiments of the present disclosure. Figure 1B This is an exploded perspective view of a display device according to one or more embodiments of the present disclosure.

[0055] Figure 1A and Figure 1B The illustration shows a mobile phone as an example of a display device DD according to one or more embodiments of the present disclosure.

[0056] exist Figure 1A The accompanying drawings illustrate directions from the first direction DR1 to the third direction DR3, and the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 described herein can be converted to other directions as relative concepts. In this specification, the first direction DR1 and the second direction DR2 may be orthogonal to each other (e.g., perpendicular). The third direction DR3 may be a normal direction relative to the plane defined by the first direction DR1 and the second direction DR2.

[0057] The thickness direction of the display device DD can be a direction parallel to a third direction DR3, which is the normal direction of the plane defined by the first direction DR1 and the second direction DR2. In this specification, the front (or top) and rear (or bottom) surfaces of the components constituting the display device DD can be defined based on the third direction DR3. In this specification, the phrases "on a plane" and "plan view" can refer to a plane parallel to the plane defined by the first direction DR1 and the second direction DR2, for example, a view of the target portion from the top, and the phrase "on a cross-section" can refer to a plane parallel to the third direction DR3, for example, a cross-section formed by vertically cutting the target portion, viewed from the side.

[0058] The display device DD can display the image IM through the active region AA-D. The active region AA-D may include a plane defined by a first direction DR1 and a second direction DR2. The peripheral region NAA-D is adjacent to the active region AA-D. The peripheral region NAA-D may surround the active region AA-D (e.g., around the active region AA-D). However, the peripheral region NAA-D may be arranged to be adjacent to only one side of the active region AA-D, or it may not be provided.

[0059] The display device DD according to one or more embodiments may include a housing HAU and a display module DM. The display module DM according to one or more embodiments may include a display panel DP and a window component WM.

[0060] The window component WM can cover the entire exterior of the display module DM. The window component WM can include a transmissive area TA and a bezel area BZA. The front surface of the window component WM, including the transmissive area TA and the bezel area BZA, can correspond to the front surface of the display device DD. Figure 1A The active areas AA-D of the display device DD shown in the diagram correspond to each other, and the bezel area BZA can be... Figure 1A The peripheral area NAA-D of the display device DD shown in the figure corresponds to this.

[0061] The transmissive region TA can be an optically transparent region. The border region BZA can be a region with a relatively lower light transmittance than the transmissive region TA. The border region BZA can have a set or predetermined color. The border region BZA can be arranged adjacent to the transmissive region TA to surround the transmissive region TA (e.g., around the transmissive region TA). However, the border region BZA can be arranged to be adjacent to only one side of the transmissive region TA, or a portion of the border region BZA may not be provided.

[0062] The display panel DP may include an active region AA and a peripheral region NAA. The active region AA may be an area activated according to an electrical signal. In one or more embodiments, the active region AA may display an image IM (see [link to related documentation]). Figure 1A The active area AA of the display panel DP can be connected to the area. Figure 1A The active areas AA-D of the display device DD in the diagram correspond to each other, and the peripheral area NAA of the display panel DP can be... Figure 1A The peripheral regions NAA-D of the display device DD shown in the diagram correspond to each other. The transmissive region TA may overlap with at least a portion of the active region AA. The peripheral region NAA may be the area covered by the border region BZA.

[0063] In one or more embodiments, an input detection unit may be provided on a display panel DP. The input detection unit can detect external input applied from the outside. External input may be user input. User input may include one or more suitable types (categories) of external input, such as a part of the user's body (e.g., a finger), light, heat, a pen, pressure, etc. The input sensor may be directly disposed on the display panel DP, or it may be attached to the display panel DP via a separate adhesive component.

[0064] In this specification, if a component (or area, layer, section, etc.) is referred to as being "directly arranged" on another component (e.g., when a component (or area, layer, section, etc.) is referred to as being "directly arranged" on another component), it may mean that no third component is arranged between the component and the other component. For example, if a component is "directly arranged" on another component (e.g., when a component is "directly arranged" on another component), it may mean that a component is "in contact" with the other component (e.g., a component is on the other component).

[0065] The housing HAU can accommodate the display panel DP, etc. The housing HAU can be connected to the window component WM.

[0066] Figure 2 This is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. For example, Figure 2 The illustration shows a cross-section of the display panel DP as viewed in the first direction DR1 (e.g., when viewed in the first direction DR1).

[0067] refer to Figure 2 The display panel DP may include a base layer BL, a circuit layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0068] The base layer BL may include the display area DA and the non-display area NDA surrounding the display area DA. The display area DA may be connected to... Figure 1B The active area AA of the display panel DP corresponds to the non-display area NDA, and the non-display area NDA can be associated with... Figure 1B The peripheral area NAA of the display panel DP corresponds to this. The base layer BL may include a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be arranged on the display area DA.

[0069] Multiple pixels may be arranged on a circuit layer DP-CL and a display element layer DP-OLED. Each of the multiple pixels may include a transistor arranged on the circuit layer DP-CL and a light-emitting element arranged on the display element layer DP-OLED and connected to the transistor. In some embodiments, each of the multiple pixels may include connection electrodes CNE11, CNE12, CNE13, and CNE2 electrically connected to the transistor (see...). Figure 5 The pixel configuration is described in more detail elsewhere in this document. "Light-emitting element connected to transistor" can refer to the transistor being electrically connected to the first electrode AE ​​of the light-emitting element (see [link to documentation]). Figure 5 ).

[0070] A thin-film encapsulation layer (TFE) can be disposed on the circuit layer (DP-CL) to cover the display element layer (DP-OLED). The TFE protects the pixels from moisture, oxygen, and external foreign matter.

[0071] Figure 3 This is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0072] refer to Figure 3 The display panel (DP) may include a scan driver (SDV), a data driver (DDV), a transmit driver (EDV), and multiple pads (PD).

[0073] The display panel DP may have a rectangular shape with a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA (e.g., around the display area DA).

[0074] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PL1 and a second power line PL2, and a connecting line CNL. Wherein, m and n are natural numbers of at least 2 (e.g., or greater).

[0075] Pixels PX can be arranged on display area DA. Each of the scan driver SDV and transmit driver EDV can be arranged on a non-display area NDA adjacent to each of the multiple long sides of the display panel DP. Data driver DDV can be arranged on a non-display area NDA adjacent to one of the multiple short sides of the display panel DP. When viewed from a plan view, the data driver DDV can be adjacent to the bottom edge of the display panel DP.

[0076] Scan lines SL1 to SLm can extend in the second direction DR2 and connect to the pixel PX and the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and connect to the pixel PX and the data driver DDV. Transmit lines EL1 to ELm can extend in the second direction DR2 and connect to the pixel PX and the transmit driver EDV.

[0077] The first power line PL1 may extend along the first direction DR1 and may be arranged on the non-display area NDA. The first power line PL1 may be arranged between the display area DA and the transmit driver EDV.

[0078] The connecting line CNL may extend in the second direction DR2 and be arranged in the first direction DR1, connecting to the first power line PL1 and the pixel PX. A first voltage may be applied to the pixel PX through the first power line PL1 and the connecting line CNL connected to each other. The connecting line CNL may be substantially defined as a portion of the first power line PL1 that receives the first voltage.

[0079] The second power line PL2 can be arranged on the non-display area NDA, extending along the long side of the display panel DP and the other short side of the display panel DP on which the data driver DDV is not located. The second power line PL2 can be arranged outside the scan driver SDV and the transmit driver EDV.

[0080] In one or more embodiments, a second power line PL2 may extend toward the display area DA and be connected to the pixel PX. A second voltage having a level lower (e.g., smaller) than the first voltage may be applied to the pixel PX via the second power line PL2.

[0081] The first control line CSL1 can be connected to the scan driver SDV and extend towards the bottom of the display panel DP. The second control line CSL2 can be connected to the transmit driver EDV and extend towards the bottom of the display panel DP. The data driver DDV can be arranged between the first control line CSL1 and the second control line CSL2.

[0082] The pad PD can be positioned on the non-display area NDA adjacent to the lower end of the display panel DP, and can be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1 and the second power line PL2, and the first control line CSL1 and the second control line CSL2 can be connected to the pad PD. Data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0083] In one or more embodiments, the display panel DP may further include a timing controller for controlling the operation of the scan driver SDV, the data driver DDV, and the transmit driver EDV, as well as a voltage generator for generating a first voltage and a second voltage. The timing controller and the voltage generator can be connected to corresponding pads PD via a printed circuit board.

[0084] The scan driver SDV generates multiple scan signals, which are applied to pixel PX via scan lines SL1 to SLm. The data driver DDV generates multiple data voltages, which are applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals, which are applied to pixel PX via transmit lines EL1 to ELm.

[0085] Pixel PX can receive data voltage in response to a scan signal. Pixel PX can also emit light with a brightness corresponding to the data voltage in response to a transmit signal to display an image.

[0086] Figure 4 This is an equivalent circuit diagram of a pixel according to one or more embodiments of this disclosure. For example, Figure 4 The illustration shows an example of a pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi, and the j-th data line DLj. Here, i and j represent natural numbers greater than 0.

[0087] refer to Figure 4 Pixel PXij may include a light-emitting element (OLED) and a pixel driving circuit (PDC) electrically connected to the OLED. The pixel driving circuit (PDC) may include a first transistor T1 to a seventh transistor T7 and a capacitor CAP. The first transistor T1 to the seventh transistor T7 and the capacitor CAP can control the amount of current flowing through the OLED, and the OLED can generate light with a set or predetermined brightness according to the received current.

[0088] The i-th scan line SLi may include the i-th first scan line GWi, the i-th second scan line GCI, and the i-th third scan line GIi. The i-th first scan line GWi, which receives the i-th write scan signal GWSi, may be defined as the i-th write scan line GWi. The i-th second scan line GCI, which receives the i-th compensation scan signal GCSi, may be defined as the i-th compensation scan line GCI. The i-th third scan line GIi, which receives the i-th initialization scan signal GISi, may be defined as the i-th initialization scan line GIi.

[0089] Each of the first transistor T1 to the seventh transistor T7 may include a source electrode, a drain electrode, and a gate electrode. In the following text, the source electrode may be referred to as the source, the drain electrode as the drain, and the gate electrode as the gate.

[0090] In this specification, "electrical connection between a transistor and a signal line or between transistors" may mean "the electrodes of a transistor have a shape integral with the signal line or are connected by connecting electrodes".

[0091] Each of the first transistors T1 to the seventh transistor T7 may be a transistor having an oxide semiconductor layer or a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. Each of the first transistors T1 to the seventh transistor T7 may be an N-type (type) transistor or a P-type (type) transistor. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS transistor having an LTPS semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor having an oxide semiconductor layer. However, examples of the first transistors T1 to the seventh transistor T7 are not limited thereto. In some embodiments, although a pixel driving circuit PDC including seven transistors is illustrated as an example, the number of transistors included in the pixel driving circuit PDC is not limited thereto.

[0092] The light-emitting element (OLED) can be defined as an organic light-emitting element. The OLED may include a first electrode AE ​​and a second electrode CE. For example, the first electrode AE ​​may be an anode, and the second electrode CE may be a cathode. The first electrode AE ​​of the OLED may be electrically connected to a first voltage line VL1 that receives a first driving voltage ELVDD. The second electrode CE of the OLED may be electrically connected to a second voltage line VL2 that receives a second driving voltage ELVSS.

[0093] A first transistor T1 may be electrically connected between a first voltage line VL1 receiving a first driving voltage ELVDD and a light-emitting element OLED. The first transistor T1 may include a source connected to a second node ND2, a drain connected to a third node ND3, and a gate connected to the first node ND1. The first transistor T1 may be turned on by the voltage of the first node ND1. The first transistor T1 may receive a data voltage Vd transmitted by the j-th data line DLj according to the switching operation of the second transistor T2 to supply a driving current Id to the light-emitting element OLED. In one or more embodiments, the first transistor T1 may be defined as a driving transistor.

[0094] The second transistor T2 can be electrically connected between the j-th data line DLj and the first transistor T1. The second transistor T2 may include a source connected to the j-th data line DLj, a drain connected to the second node ND2, and a gate connected to the i-th scan line GWi. The second transistor T2 and the first transistor T1 can be connected via the second node ND2. The second transistor T2 can be turned on by the i-th write scan signal GWSi applied through the i-th scan line GWi. The data voltage Vd applied to the j-th data line DLj can be transmitted to the source of the first transistor T1 by the turned-on second transistor T2. In this embodiment, the second transistor T2 can be defined as a switching transistor.

[0095] A third transistor T3 may be electrically connected between a fourth transistor T4 and a first transistor T1. The third transistor T3 may include a source connected to a first node ND1, a drain connected to a third node ND3, and a gate connected to the i-th second scan line GCI. The third transistor T3 and the first transistor T1 may be connected via the third node ND3. The third transistor T3 may be turned on by an i-th compensation scan signal GCSi applied via the i-th second scan line GCI. The gate and drain of the first transistor T1 may be electrically connected to each other via the turned-on third transistor T3, and the first transistor T1 may be connected by a diode. In this embodiment, the third transistor T3 may be defined as a compensation transistor.

[0096] A fourth transistor T4 may be electrically connected between a first initialization line VIL1, which receives a first initialization voltage Vint1, and a third transistor T3. The fourth transistor T4 may include a source connected to the first initialization line VIL1, a drain connected to the first node ND1, and a gate connected to the (i-th third) scan line GIi. The fourth transistor T4 may be turned on by an i-th initialization scan signal GISi applied through the (i-th third) scan line GIi. The first initialization voltage Vint1 may be transmitted to the first node ND1 by the turned-on fourth transistor T4, and may initialize the potential of the gate of the first transistor T1. In this embodiment, the fourth transistor T4 may be defined as an initialization transistor.

[0097] The fifth transistor T5 may be electrically connected between the first transistor T1 and the first voltage line VL1 that receives the first drive voltage ELVDD. The fifth transistor T5 may include a source connected to the first voltage line VL1, a drain connected to the second node ND2, and a gate connected to the i-th emitter line ELi.

[0098] The sixth transistor T6 may be electrically connected between the first transistor T1 and the light-emitting element OLED. The sixth transistor T6 may include a source connected to the third node ND3, a drain connected to the first electrode AE ​​of the light-emitting element OLED through the fourth node ND4, and a gate connected to the i-th emitter line ELi.

[0099] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal ESi applied through the i-th emission line ELi. The emission time of the light-emitting element OLED can be controlled or selected by the i-th emission signal ESi. When the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current Id can be generated based on the voltage difference between the gate voltage of the gate of the first transistor T1 and the first driving voltage ELVDD, and the driving current Id can be supplied to the light-emitting element OLED through the sixth transistor T6, causing the light-emitting element OLED to emit light. In one or more embodiments, the fifth transistor T5 and the sixth transistor T6 can be defined as emission control transistors.

[0100] A seventh transistor T7 may be electrically connected between the sixth transistor T6 and the second initialization line VIL2, which receives the second initialization voltage Vint2. The seventh transistor T7 may include a source connected to the fourth node ND4, a drain connected to the second initialization line VIL2, and a gate connected to the (i-1)th first scan line GWi-1. The gate of the seventh transistor T7 may be connected to the (i-1)th write scan line GWi-1, which is a write scan line preceding the i-th write scan line GWi. However, one or more embodiments of this disclosure are not limited thereto, and the gate of the seventh transistor T7 may be electrically connected to a separate scan line.

[0101] The seventh transistor T7 can be turned on by the (i-1)th write scan signal GWSi-1 applied through the (i-1)th first scan line GWi-1. The second initialization voltage Vint2 can be transmitted to the fourth node ND4 by the turned-on seventh transistor T7. The second initialization voltage Vint2 may have substantially the same level as the first initialization voltage Vint1, but this disclosure is not limited thereto, and may have a different level than the first initialization voltage Vint1. In this embodiment, the seventh transistor T7 can be defined as an initialization transistor.

[0102] The seventh transistor T7 improves the black representation capability of pixel PXij. A portion of the drive current Id can escape through the seventh transistor T7 as a bypass current. When displaying a black image, the reduced amount of bypass current escaping from the drive current Id through the seventh transistor T7 allows current to be supplied to the light-emitting element OLED, thus enabling clear display of black images. For example, accurate black brightness images can be achieved through the seventh transistor T7, and the display device DD (see...) Figure 1A (contrast)

[0103] The capacitor CAP may include a first electrode receiving a first drive voltage ELVDD and a second electrode connected to a first node ND1. A charge corresponding to the voltage difference between the first and second electrodes may be stored in the capacitor CAP. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 can be determined based on the voltage stored in the capacitor CAP.

[0104] Figure 4 The configuration of the pixel driving circuit PDC shown in the figure is an example, and the configuration of the pixel driving circuit PDC is not limited to this and can be changed and implemented.

[0105] Figure 5 This is an enlarged cross-sectional view illustrating a portion of a display panel according to one or more embodiments of the present disclosure.

[0106] Figure 5The diagram shows the light-emitting element OLED and the pixel driving circuit PDC connected to the light-emitting element OLED (see [link]). Figure 4 Examples of some transistors. The foregoing description can be applied to... Figure 5 The diagram shows the configuration of the Display Panel (DP).

[0107] refer to Figure 5 The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-OLED, and a packaging layer TFE.

[0108] The base layer BL provides a base surface on which the circuit layer DP-CL is disposed. The circuit layer DP-CL may include lower insulating layers BFL and 10 to 50, a first insulating layer ISL1, a second insulating layer ISL2 and a third insulating layer ISL3, transistors TR1 and TR2, and connection electrodes CNE11 to CNE13 and CNE2. The lower insulating layers BFL and 10 to 50 may include a buffer layer BFL and a first lower insulating layer 10 to a fifth lower insulating layer 50 disposed on the buffer layer BFL. However, the lower insulating layers included in the circuit layer DP-CL are not limited to these and may vary depending on the configuration of the pixel driving circuit PDC included in the circuit layer DP-CL and the process of the circuit layer DP-CL.

[0109] A buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may include at least one inorganic layer. For example, the buffer layer BFL may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The buffer layer BFL can improve the bonding strength between the semiconductor patterned layer or conductive patterned layer of the circuit layer DP-CL disposed on the base layer BL and the base layer BL.

[0110] Each of the first to fifth lower insulating layers 10 may include an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic layer is not limited to the foregoing examples. The organic layer may include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. However, the material of the organic layer is not limited to the foregoing examples. In this specification, "a"-based resin refers to resin containing an "a" functional group.

[0111] The light-blocking pattern BML can be disposed on the buffer layer BFL. When the buffer layer BFL is omitted, the light-blocking pattern BML can be disposed directly on the base layer BL. The light-blocking pattern BML may include molybdenum. The light-blocking pattern BML can be used for shielding. The light-blocking pattern BML can block light from being disposed on the first transistor T1 to the seventh transistor T7 (see...). Figure 4 The polarization phenomenon between the first lower insulating layer 10 to the fifth lower insulating layer 50, the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer SIL3 on the light-blocking pattern BML affects the first transistor T1 to the seventh transistor T7 (see...). Figure 4 The effect of the potential.

[0112] Figure 5 The diagram illustrates the pixel drive circuit PDC (see [reference]). Figure 4 The first type (type) transistor TR1 and the second type (type) transistor TR2 are used as examples. In this embodiment, the first type (type) transistor TR1 may be a silicon thin-film transistor, and the second type (type) transistor TR2 may be an oxide thin-film transistor. The first type (type) transistor TR1 may be... Figure 4 The transistor TR2 can be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described herein, and the second type (type) transistor TR2 can be one of the third transistor T3 and the fourth transistor T4. In this embodiment, the first type (type) transistor TR1 and the second type (type) transistor TR2 can be arranged on different layers.

[0113] The semiconductor pattern of the first type (category) transistor TR1 (hereinafter referred to as the first semiconductor pattern SP1) may be arranged on the buffer layer BFL. The first semiconductor pattern SP1 may include silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SP1 may include low-temperature polycrystalline silicon. However, if the first semiconductor pattern SP1 has semiconductor properties, the materials included in the first semiconductor pattern SP1 are not limited to the foregoing examples.

[0114] Figure 5 Only a portion of the first semiconductor pattern SP1 disposed on the buffer layer BFL is illustrated, and the first semiconductor pattern SP1 may also be disposed on other areas. The first semiconductor pattern SP1 may span pixel PX (see [reference]). Figure 3 The first semiconductor pattern SP1 is arranged according to specific rules. The first semiconductor pattern SP1 may have different electrical properties depending on whether it is doped. The first semiconductor pattern SP1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region.

[0115] The conductivity of the first region may be greater than that of the second region, and the first region may be substantially used as an electrode or signal line. The second region may substantially correspond to the active region (or channel) of the first type (type) transistor TR1. For example, a portion of the first semiconductor pattern SP1 may be the active region of the first type (type) transistor TR1, another portion may be the source or drain region of the first type (type) transistor TR1, and yet another portion may be a connecting electrode or a connecting signal line.

[0116] The source region S1, active region A1, and drain region D1 of the first type (category) transistor TR1 can be formed by a first semiconductor pattern SP1. In cross-section, the source region S1 and drain region D1 can extend from the active region A1 in opposite directions.

[0117] A first lower insulating layer 10 may be disposed on a buffer layer BFL. The first lower insulating layer 10 may cover a light-blocking pattern BML. A second lower insulating layer 20 may be disposed on the first lower insulating layer 10. The second lower insulating layer 20 may cover a first semiconductor pattern SP1.

[0118] The gate electrode of the first type (type) transistor TR1 (hereinafter referred to as the first gate electrode GE1) may be disposed on the second lower insulating layer 20. The first gate electrode GE1 may overlap with the active region A1. In one or more embodiments, the first gate electrode GE1 may be used as a mask in the process of doping the first semiconductor pattern SP1.

[0119] Figure 5 The illustration shows an example of a first type (type) transistor TR1 having a top gate structure in which a first gate electrode GE1 is disposed above a first semiconductor pattern SP1, but one or more embodiments of the present disclosure are not limited thereto. In one or more embodiments, the first type (type) transistor TR1 may have a bottom gate structure in which the first gate electrode GE1 is disposed below the first semiconductor pattern SP1.

[0120] The third lower insulating layer 30 may be disposed on the second lower insulating layer 20. The third lower insulating layer 30 may cover the first gate electrode GE1.

[0121] The scan line SL can be arranged on the third lower insulating layer 30. The scan line SL can be connected with the i-th first scan line GWi, the i-th second scan line GCI, and the i-th third scan line GIi described herein (see [link to document]). Figure 4 This corresponds to a part of ).

[0122] The fourth lower insulating layer 40 may be disposed on the third lower insulating layer 30. The fourth lower insulating layer 40 may cover the scan line SL.

[0123] The semiconductor pattern of the second type (category) transistor TR2 (hereinafter referred to as the second semiconductor pattern SP2) may be disposed on the fourth lower insulating layer 40. The second semiconductor pattern SP2 may include an oxide semiconductor comprising a metal oxide. The oxide semiconductor may include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or mixtures (combinations) of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with their oxides (e.g., any suitable). The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc. However, the examples are not necessarily limited to these.

[0124] The second semiconductor pattern SP2 may include multiple regions with different electrical properties depending on whether the metal oxide is reduced. In the second semiconductor pattern SP2, the regions where the metal oxide is reduced (hereinafter referred to as reduced regions) may have a higher conductivity than the regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). The reduced regions may be used in practice as the source or drain regions of the transistor. The non-reduced regions may substantially correspond to the channel (or active region) of the transistor.

[0125] The source region S2, active region A2, and drain region D2 of the second type (category) transistor TR2 can be formed by a second semiconductor pattern SP2. In cross-section, the source region S2 and drain region D2 can extend from the active region A2 in opposite directions.

[0126] The fifth lower insulating layer 50 may be disposed on the fourth lower insulating layer 40. The fifth lower insulating layer 50 may cover the second semiconductor pattern SP2.

[0127] The gate electrode of the second type (type) transistor TR2 (hereinafter referred to as the second gate electrode GE2) may be disposed on the fifth lower insulating layer 50. The second gate electrode GE2 may overlap with the active region A2. In one or more embodiments, the second gate electrode GE2 may be used as a mask in the process of doping the second semiconductor pattern SP2.

[0128] In one or more embodiments, the second semiconductor pattern SP2 may overlap with a portion of a scan line SL disposed below the second semiconductor pattern SP2. The portion of the scan line SL overlapping the second semiconductor pattern SP2 may be used together with the second gate electrode GE2 as the gate of a second type (type) transistor TR2. In this case, the gate of the second type (type) transistor TR2 may be formed as a dual gate to have a sufficient amount of gate charge and perform high-speed switching. In some embodiments, since the scan line SL is arranged to overlap with the second semiconductor pattern SP2, damage to the second semiconductor pattern SP2 from light introduced from the underside of the display panel DP can be prevented or reduced. However, the structure of the second type (type) transistor TR2 is illustrative, and one or more embodiments of this disclosure are not limited thereto.

[0129] The second semiconductor pattern SP2 of the second type (type) transistor TR2 and the first semiconductor pattern SP1 of the first type (type) transistor TR1 can be arranged on different layers. However, this is only an example and is included in the pixel drive circuit PDC (see Figure 4 The semiconductor patterns of all transistors in a given array can be arranged on the same layer.

[0130] The first insulating layer ISL1 may be disposed on the fifth lower insulating layer 50. The first insulating layer ISL1 may cover the second gate electrode GE2.

[0131] The circuit layer DP-CL may include multiple first connection electrodes CNE11, CNE12, and CNE13. These multiple first connection electrodes CNE11, CNE12, and CNE13 may be arranged on the first insulating layer ISL1. For example... Figure 5 As illustrated in the diagram, the first connecting electrodes CNE11, CNE12, and CNE13 may include a first-1 connecting electrode CNE11, a first-2 connecting electrode CNE12, and a first-3 connecting electrode CNE13. The first-1 connecting electrodes CNE11, CNE12, and CNE13 may be arranged on the same layer of the first insulating layer ISL1, spaced apart from each other and / or separated (e.g., spaced apart or separated). In this document, "first" and "first" have equivalent meanings.

[0132] Multiple first connection electrodes CNE11, CNE12, and CNE13 can be electrically connected to a first semiconductor pattern SP1 and a second semiconductor pattern SP2 through contact holes CNT-11, CNT-12a, CNT-12b, and CNT-13 defined in a first insulating layer ISL1. In this specification, contact holes CNT-11, CNT-12a, CNT-12b, and CNT-13, defined in at least the first insulating layer ISL1 for connecting the first semiconductor pattern SP1 and the second semiconductor pattern SP2 to the first connection electrodes CNE11, CNE12, and CNE13, can be defined as first contact holes.

[0133] The first-1 connecting electrode CNE11 can be connected to the drain region D1 of the first type (category) transistor TR1. The first-1 connecting electrode CNE11 can be connected to the drain region D1 through the contact hole CNT-11 passing through the second lower insulating layer 20 to the fifth lower insulating layer 50 and the first insulating layer ISL1.

[0134] The first-second connection electrode CNE12 can be connected to the source region S1 of the first type (category) transistor TR1. The first-second connection electrode CNE12 can be connected to the source region S1 through the contact hole CNT-12a passing through the second lower insulating layer 20 to the fifth lower insulating layer 50 and the first insulating layer ISL1.

[0135] The first-second connection electrode CNE12 can extend in a plane to overlap with the drain region D2 of the second type (type) transistor TR2. The first-second connection electrode CNE12 can be connected to the drain region D2 through a contact hole CNT-12b passing through the fifth lower insulating layer 50 and the first insulating layer ISL1. Therefore, the second semiconductor pattern SP2 of the second type (type) transistor TR2 and the first semiconductor pattern SP1 of the first type (type) transistor TR1, which are arranged on different layers, can be connected to each other through the first-second connection electrode CNE12.

[0136] The first-to-third connecting electrode CNE13 can be connected to the source region S2 of the second type (category) transistor TR2. The first-to-third connecting electrode CNE13 can be connected to the source region S2 through the contact hole CNT-13 passing through the fifth lower insulating layer 50 and the first insulating layer ISL1.

[0137] Each of the plurality of first connecting electrodes CNE11, CNE12 and CNE13 may include first conductive layers CNL-a1 and CNL-a2, each comprising aluminum (see [link to documentation]). Figure 6A ) and second conductive layers CNL-b1 and CNL-b2 disposed on the first conductive layers CNL-a1 and CNL-a2 and both comprising aluminum (see Figure 6AEach of the first-1 connecting electrode CNE11, the first-2 connecting electrode CNE12, and the first-3 connecting electrode CNE13 may include a first conductive layer CNL-a1 and CNL-a2, both comprising aluminum (see...). Figure 6A ) and second conductive layers CNL-b1 and CNL-b2 disposed on the first conductive layers CNL-a1 and CNL-a2 and both comprising aluminum (see Figure 6A (See below for reference) Figure 6A A more detailed description is provided regarding the first conductive layers CNL-a1 and CNL-a2 and the second conductive layers CNL-b1 and CNL-b2 included in the plurality of first connecting electrodes CNE11, CNE12 and CNE13.

[0138] A second insulating layer ISL2 may be disposed on a first insulating layer ISL1. The second insulating layer ISL2 may cover a plurality of first connecting electrodes CNE11, CNE12, and CNE13. The second insulating layer ISL2 may cover first-1 connecting electrode CNE11, first-2 connecting electrode CNE12, and first-3 connecting electrode CNE13. The second insulating layer ISL2 may have a multilayer structure. For example, the second insulating layer ISL2 may have a two-layer structure made of different materials. In one or more embodiments, the second insulating layer ISL2 may include a first sub-insulating layer IL-a disposed on the first insulating layer ISL1 and a second sub-insulating layer IL-b disposed on the first sub-insulating layer IL-a. The first sub-insulating layer IL-a may be disposed on first conductive layers CNL-a1 and CNL-a2, which are described in more detail elsewhere herein (see...). Figure 6A Between the first sub-insulating layer IL-a and the second sub-insulating layer IL-b. The second sub-insulating layer IL-b may be disposed on the first sub-insulating layer IL-a and may cover the second conductive layers CNL-b1 and CNL-b2, which are described in more detail elsewhere in this document (see [link to document]). Figure 6A ).

[0139] In a display panel DP according to one or more embodiments of the present disclosure, each of the plurality of pixels PX may include a second connection electrode CNE2 disposed between each of the plurality of first connection electrodes CNE11, CNE12, and CNE13 and the display element layer DP-OLED, and electrically connected to at least a portion of the plurality of first connection electrodes CNE11, CNE12, and CNE13. The second connection electrode CNE2 may be disposed on a second insulating layer ISL2. In some embodiments, although not shown separately, a portion of a signal line included in the display panel DP may be disposed on the second insulating layer ISL2.

[0140] The second connecting electrode CNE2 can be connected to the first-1 connecting electrode CNE11 through the contact hole CNT-2 of the second sub-insulating layer IL-b passing through the second insulating layer ISL2. The second connecting electrode CNE2 can be connected to the drain region D1 of the first type (category) transistor TR1 through the first-1 connecting electrode CNE11. The first electrode AE ​​and the first-1 connecting electrode CNE11 of the light-emitting element OLED can be connected to each other through the second connecting electrode CNE2. In one or more embodiments, Figure 5 The first type (category) transistor TR1 shown in the diagram can be used with... Figure 4 This corresponds to the sixth transistor T6 connected to the first electrode AE. Embodiments of this disclosure are not limited thereto, and the second connection electrode CNE2 may not be provided, or an additional connection electrode disposed between the second connection electrode CNE2 and the first-1 connection electrode CNE11 may be disposed within the circuit layer DP-CL. In this specification, the contact hole CNT-2 defined at least in the second insulating layer ISL2 for connecting the first-1 connection electrode CNE11 to the second connection electrode CNE2 may be referred to as the second contact hole.

[0141] The second connection electrode CNE2, included in each of the multiple pixels PX, may include a third conductive layer CNL-c comprising aluminum (see [link to documentation]). Figure 6B ) and arranged in the third conductive layer CNL-c (see Figure 6B It also contains a fourth conductive layer CNL-d of aluminum (see...) Figure 6B See other parts of this article for reference. Figure 6B More detailed information is provided regarding the third conductive layer CNL-c and the fourth conductive layer CNL-d included in the second connecting electrode CNE2.

[0142] The display panel DP according to one or more embodiments of the present disclosure may further include a third insulating layer ISL3 disposed on the second insulating layer ISL2. The third insulating layer ISL3 may cover the second connection electrode CNE2.

[0143] The third insulating layer ISL3 may have a multilayer structure. For example, the third insulating layer ISL3 may have a two-layer structure made of different materials. In one or more embodiments, the third insulating layer ISL3 may include a third sub-insulating layer IL-c disposed on the second insulating layer ISL2 and a fourth sub-insulating layer IL-d disposed on the third sub-insulating layer IL-c. The third sub-insulating layer IL-c may cover the third conductive layer CNL-c, which is described in more detail elsewhere herein (see...). Figure 6B At least a portion of the side surface of the third sub-insulating layer IL-c. The fourth sub-insulating layer IL-d may be disposed on the third sub-insulating layer IL-c and may cover the fourth conductive layer CNL-d, which is described in more detail elsewhere in this document (see [link to document]). Figure 6B ).

[0144] The display element layer DP-OLED can be disposed on the circuit layer DP-CL. The display element layer DP-OLED may include a pixel defining layer PDL and a light-emitting element OLED. The light-emitting element OLED may include a first electrode AE, an emitting layer EM, and a second electrode CE.

[0145] The light-emitting element OLED may include organic light-emitting elements, quantum dot light-emitting elements, micro LED light-emitting elements, or nano LED light-emitting elements. However, one or more embodiments of this disclosure are not limited thereto, and the light-emitting element OLED may include one or more suitable embodiments, or control or select the amount of light according to an electrical signal, as long as light is generated.

[0146] The light-emitting element OLED can be electrically connected to the corresponding pixel driving circuit PDC (see Figure 4 ) transistors. Figure 5 The diagram shows the electrical connection between the OLED light-emitting element and the corresponding sixth transistor T6 (see Figure 1). Figure 4 Examples of ).

[0147] The first electrode AE ​​of the OLED light-emitting element can be arranged on the top layer of the circuit layer DP-CL. For example, the first electrode AE ​​can be arranged on the third insulating layer ISL3. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT-3 through the fourth sub-insulating layer IL-d. ​​The first electrode AE ​​can be electrically connected to the first type (category) transistor TR1 through the corresponding second connecting electrode CNE2 and the corresponding first-1 connecting electrode CNE11.

[0148] The pixel defining layer (PDL) can be disposed on the top layer of the circuit layer DP-CL. For example, the pixel defining layer (PDL) can be disposed on the third insulating layer ISL3. The light-emitting opening (PX-OP) exposing a portion of the first electrode AE ​​can be defined in the pixel defining layer (PDL). The display area DA of the display panel DP (see...) Figure 3 The device may include an emitting region PXA and a non-emitting region NPXA. In this embodiment, the area of ​​the first electrode AE ​​exposed by the light-emitting opening PX-OP may correspond to the emitting region PXA. The area on which the pixel defining layer PDL is disposed may correspond to the non-emitting region NPXA. On a plane, the non-emitting region NPXA may surround (e.g., encircle) the emitting region PXA and define the boundary of the emitting region PXA.

[0149] The pixel defining layer (PDL) may include a polymeric resin. For example, the pixel defining layer (PDL) may include a polyacrylate-based resin or a polyimide-based resin. Embodiments of this disclosure are not limited thereto, and the pixel defining layer (PDL) may also include inorganic materials.

[0150] The pixel defining layer (PDL) may also include a light-absorbing material. For example, the PDL may include a black colorant such as a black dye or black pigment. For example, the black colorant may include carbon black, a metal (such as chromium), or an oxide thereof. However, one or more embodiments of this disclosure are not necessarily limited thereto.

[0151] The emitting layer EM can be disposed on the first electrode AE. The emitting layer EM of the light-emitting element OLED can be arranged corresponding to the light-emitting opening PX-OP, and can be provided as an emission pattern in which multiple light-emitting elements OLED are spaced apart and / or separated (e.g., spaced apart or separated) from each other in a plane. However, one or more embodiments of this disclosure are not limited thereto, and in multiple light-emitting elements OLED, the emitting layer EM can be provided as an integrated film and as a common layer. The emitting layer EM can include organic light-emitting materials and / or inorganic light-emitting materials. For example, the emitting layer EM can include fluorescent materials, phosphorescent materials, metal-organic composite light-emitting materials, or quantum dots. The emitting layer EM can emit light of any one of red, green, and blue colors.

[0152] The second electrode CE can be disposed on the emitter layer EM. The second electrode CE can overlap with the emitter region PXA and the non-emitter region NPXA. The second electrode CE can be commonly disposed on multiple pixels PX (see [link to relevant documentation]). Figure 3 This allows a common voltage to be provided to multiple pixel PXs (see above). Figure 3 ).

[0153] The OLED light-emitting element may further include an emission control layer disposed between a first electrode AE ​​and a second electrode CE. For example, the emission control layer may include a hole control layer disposed between the first electrode AE ​​and the emission layer EM, or an electron control layer disposed between the emission layer EM and the second electrode CE. The hole control layer may include a hole injection layer, a hole transport layer, or an electron blocking layer, and the electron control layer may include an electron injection layer, an electron transport layer, or a hole blocking layer.

[0154] A TFE encapsulation layer may be disposed on the DP-OLED display element layer. The TFE encapsulation layer seals the OLED light-emitting element. The TFE encapsulation layer may include at least one thin film comprising an inorganic layer and an organic layer. In one or more embodiments, the TFE encapsulation layer may include an inorganic layer and an organic layer disposed between the inorganic layers.

[0155] The inorganic film of the TFE encapsulation layer protects the OLED light-emitting element from moisture and / or oxygen. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic film is not limited to the foregoing examples.

[0156] The organic film of the TFE encapsulation layer protects the OLED light-emitting element from foreign matter such as dust particles. The organic film may include acrylic resin. However, the materials of the organic film are not limited to the examples described above.

[0157] Figure 6A This is a cross-sectional view illustrating a portion of the configuration of a display panel according to one or more embodiments of the present disclosure. Figure 6A The diagram shows Figure 5 The diagram illustrates the shape of a first insulating layer ISL1, a portion of a plurality of first connection electrodes disposed on the first insulating layer ISL1, and a second insulating layer ISL2 covering the plurality of first connection electrodes in the circuit layer DP-CL of the display panel DP. Figure 6A For ease of explanation, the first contact hole defined in the first insulating layer ISL1 may not be provided. (Referring to...) Figure 6A When describing the first connecting electrodes CNE1-1 and CNE1-2 according to one or more embodiments, the same / similar reference numerals may be used, each of which can be independently associated with... Figures 1A to 5 The same / similar parts described in the text may be excluded, and duplicate descriptions may be omitted.

[0158] refer to Figure 6A A display panel DP according to one or more embodiments of the present disclosure may include a plurality of first connection electrodes CNE1-1 and CNE1-2. The plurality of first connection electrodes CNE1-1 and CNE1-2 may include a first-1 sub-connection electrode CNE1-1 and a first-2 sub-connection electrode CNE1-2. The first-1 sub-connection electrode CNE1-1 and the first-2 sub-connection electrode CNE1-2 may be connected to... Figure 5 Among the plurality of first connection electrodes illustrated in the figure, two first connection electrodes are arranged to be adjacent to each other. For example, the first-1 sub-connection electrode CNE1-1 may correspond to the first-2 connection electrode CNE12 connected to the source region S1 of the first semiconductor pattern SP1, and the first-2 sub-connection electrode CNE1-2 may correspond to the first-1 connection electrode CNE11 connected to the drain region D1 of the second semiconductor pattern SP1, but is not limited thereto.

[0159] refer to Figure 6AEach of the plurality of first connecting electrodes CNE1-1 and CNE1-2 may include sequentially stacked first conductive layers CNL-a1 and CNL-a2 and second conductive layers CNL-b1 and CNL-b2. For example, the first-1 sub-connecting electrode CNE1-1 may include sequentially stacked first-1 conductive layers CNL-a1 and second-1 conductive layers CNL-b1, and the first-2 sub-connecting electrode CNE1-2 may include sequentially stacked first-2 conductive layers CNL-a2 and second-2 conductive layers CNL-b2. Each of the plurality of first connecting electrodes CNE1-1 and CNE1-2 may include an electrode having a structure in which the first conductive layers CNL-a1 and CNL-a2 and the second conductive layers CNL-b1 and CNL-b2 are stacked.

[0160] The first conductive layers CNL-a1 and CNL-a2, respectively included in the plurality of first connecting electrodes CNE1-1 and CNE1-2, may be disposed on the same layer. For example, each of the first conductive layer CNL-a1 and the first conductive layer CNL-a2 may be disposed on the first insulating layer ISL1. Each of the first conductive layer CNL-a1 and the first conductive layer CNL-a2 may have substantially the same thickness. However, one or more embodiments of this disclosure are not limited thereto.

[0161] Each of the first conductive layers CNL-a1 and CNL-a2 may include first layers CL1-1 and CL1-2 and second layers CL2-1 and CL2-2 disposed on the first layers CL1-1 and CL1-2. For example, the first conductive layer CNL-a1 may include a first conductive layer CL1-1 disposed on the first insulating layer ISL1 and a second conductive layer CL2-1 disposed on the first conductive layer CL1-1, and the first conductive layer CNL-a2 may include a first conductive layer CL1-2 disposed on the first insulating layer ISL1 and a second conductive layer CL2-2 disposed on the first conductive layer CL1-2.

[0162] Each of the first layers CL1-1 and CL1-2 and the second layers CL2-1 and CL2-2 may comprise a metallic material. The first layers CL1-1 and CL1-2 and the second layers CL2-1 and CL2-2 may comprise different metallic materials. In one or more embodiments, each of the first layers CL1-1 and CL1-2 may comprise titanium, and each of the second layers CL2-1 and CL2-2 may comprise aluminum.

[0163] In one or more embodiments, the thickness of each of the second layers CL2-1 and CL2-2 may be greater than the thickness of each of the first layers CL1-1 and CL1-2. The thickness of the second-first layer CL2-1 may be greater than the thickness of the first-first layer CL1-1. The thickness of the second-second layer CL2-2 may be greater than the thickness of the first-second layer CL1-2.

[0164] The second layers CL2-1 and CL2-2 included in the first conductive layers CNL-a1 and CNL-a2 may correspond to the uppermost layer in the first conductive layers CNL-a1 and CNL-a2. The second layers CL2-1 and CL2-2 may be the uppermost layers among the multiple layers included in the first conductive layers CNL-a1 and CNL-a2. The top surface of each of the first conductive layers CNL-a1 and CNL-a2 may be defined by the top surface of each of the second layers CL2-1 and CL2-2.

[0165] Each of the plurality of first connecting electrodes CNE1-1 and CNE1-2 may include second conductive layers CNL-b1 and CNL-b2 disposed on first conductive layers CNL-a1 and CNL-a2. The second conductive layers CNL-b1 and CNL-b2 may be disposed directly on the first conductive layers CNL-a1 and CNL-a2, respectively. A second-first conductive layer CNL-b1 may be disposed on the first-first conductive layer CNL-a1. The second-first conductive layer CNL-b1 may be disposed directly on the first-first conductive layer CNL-a1. The bottom surface of the second-first conductive layer CNL-b1 may be in contact with the first-first conductive layer CNL-a1. A second-second conductive layer CNL-b2 may be disposed on the first-second conductive layer CNL-a2. The second-second conductive layer CNL-b2 may be disposed directly on the first-second conductive layer CNL-a2. The bottom surface of the second-second conductive layer CNL-b2 may be in contact with the first-second conductive layer CNL-a2. The second-first conductive layer CNL-b1 and the second-second conductive layer CNL-b2 may have substantially the same thickness, but this disclosure is not limited thereto.

[0166] Each of the second conductive layers CNL-b1 and CNL-b2 may include third layers CL3-1 and CL3-2 disposed on the first conductive layers CNL-a1 and CNL-a2, and fourth layers CL4-1 and CL4-2 disposed on the third layers CL3-1 and CL3-2. For example, the second-first conductive layer CNL-b1 may include a third-first layer CL3-1 disposed on the first-first conductive layer CNL-a1 and a fourth-first layer CL4-1 disposed on the third-first layer CL3-1, and the second-second conductive layer CNL-b2 may include a third-second layer CL3-2 disposed on the first-second conductive layer CNL-a2 and a fourth-second layer CL4-2 disposed on the third-second layer CL3-2.

[0167] The third layers CL3-1 and CL3-2 included in the second conductive layers CNL-b1 and CNL-b2 may correspond to the bottommost layer in the second conductive layers CNL-b1 and CNL-b2. The third layers CL3-1 and CL3-2 may be the layers arranged at the bottommost side among the multiple layers included in the second conductive layers CNL-b1 and CNL-b2. The bottom surface of each of the second conductive layers CNL-b1 and CNL-b2 may be defined by the bottom surface of each of the third layers CL3-1 and CL3-2.

[0168] Each of the third layers CL3-1 and CL3-2 and the fourth layers CL4-1 and CL4-2 may comprise a metallic material. The third layers CL3-1 and CL3-2 and the fourth layers CL4-1 and CL4-2 may comprise different metallic materials. In one or more embodiments, each of the third layers CL3-1 and CL3-2 may comprise aluminum, and each of the fourth layers CL4-1 and CL4-2 may comprise titanium. In one or more embodiments, the second layers CL2-1 and CL2-2 included in the first conductive layers CNL-a1 and CNL-a2 and the third layers CL3-1 and CL3-2 included in the second conductive layers CNL-b1 and CNL-b2 may comprise substantially the same material. Each of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 may comprise aluminum.

[0169] In one or more embodiments, the thickness of each of the third layers CL3-1 and CL3-2 may be greater than the thickness of each of the fourth layers CL4-1 and CL4-2. The thickness of the third-first layer CL3-1 may be greater than the thickness of the fourth-first layer CL4-1. The thickness of the third-second layer CL3-2 may be greater than the thickness of the fourth-second layer CL4-2.

[0170] The third layers CL3-1 and CL3-2 can be directly disposed on the corresponding second layers CL2-1 and CL2-2, respectively. The third-first layer CL3-1 can be directly disposed on the second-first layer CL2-1. The third-second layer CL3-2 can be directly disposed on the second-second layer CL2-2. The second layers CL2-1 and CL2-2 can be layers in direct contact with the bottom surface of each of the third layers CL3-1 and CL3-2. Each of the plurality of first connection electrodes CNE1-1 and CNE1-2 can include an electrode having a four-layer structure in which the first layers CL1-1 and CL1-2, the second layers CL2-1 and CL2-2, the third layers CL3-1 and CL3-2, and the fourth layers CL4-1 and CL4-2 are stacked. Figure 6AIn the diagram, the boundary between each of the second layers CL2-1 and CL2-2 and each of the third layers CL3-1 and CL3-2 can be clearly shown as a straight line, but this is only an example, and in the cross section, the boundary between each of the second layers CL2-1 and CL2-2 and each of the third layers CL3-1 and CL3-2 can be not clearly shown.

[0171] The thickness of each of the second layers CL2-1 and CL2-2 may be substantially the same as the thickness of each of the third layers CL3-1 and CL3-2. The thickness of the second-first layer CL2-1 may be substantially the same as the thickness of the third-first layer CL3-1, and the thickness of the second-second layer CL2-2 may be the same as the thickness of the third-second layer CL3-2. However, one or more embodiments of this disclosure are not limited thereto. The thickness of each of the second layers CL2-1 and CL2-2 may be different from the thickness of each of the third layers CL3-1 and CL3-2.

[0172] In one or more embodiments, the sum (e.g., total) of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 may be at least about 10,000 angstroms. (e.g., or more) and at most about (For example, or less). For example, the sum of the thickness of layer 2-1 CL2-1 and the thickness of layer 3-1 CL3-1 (for example, the total) may be at least approximately (e.g., or more) and at most about (For example, or less). The sum of the thicknesses of the 2nd-2nd CL2-2 and the 3rd-2nd CL3-2 (for example, the total) may be at least approximately (e.g., or more) and at most about (For example, or less). When the sum of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 (for example, the total) is less than approximately At that time, the desired or appropriate resistance reduction effect of the first connecting electrodes CNE1-1 and CNE1-2 may not be expected, and if the sum of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 (e.g., the total) exceeds approximately (For example, when the sum of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 (e.g., the total) exceeds approximately If the thickness of each of the first connecting electrodes CNE1-1 and CNE1-2 is too (or significantly) thick, it becomes difficult to miniaturize the display device DD. When the sum (e.g., total) of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2 meets the range mentioned herein, the resistance of the electrodes can be effectively reduced, and the occurrence of electrode defects in the process can be reduced to improve process reliability. The conductivity of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-1 substantially determines the conductivity of the first connecting electrodes CNE1-1 and CNE1-2. The greater the sum (e.g., total) of the thicknesses of the second layers CL2-1 and CL2-2 and the third layers CL3-1 and CL3-2, the lower the resistance of the first connecting electrodes CNE1-1 and CNE1-2. Therefore, the display panel DP (see Figure 1B It can be driven at high speed, which can improve the display panel's DP (see...). Figure 1B It offers display characteristics and reduces power consumption.

[0173] For example, when the combined thickness of the second layer (e.g., second layers CL2-1 and CL2-2) and the third layer (e.g., third layers CL3-1 and CL3-2) is less than approximately In this case, the first connecting electrodes (e.g., first connecting electrodes CNE1-1 and CNE1-2) may not achieve the desired resistance reduction. Conversely, if the combined thickness exceeds approximately The first connecting electrode could become too thick, complicating the miniaturization of the display device. Maintaining the combined thickness within this range effectively reduces electrode resistance and minimizes defects during manufacturing, thereby enhancing process reliability. The conductivity of the second and third layers significantly affects the conductivity of the first connecting electrode. Increasing the combined thickness of these layers reduces the resistance of the first connecting electrode, thus enabling the display panel (e.g., display panel DP, see...) Figure 1B It offers high-speed operation, improved display characteristics, and reduced power consumption.

[0174] A second insulating layer ISL2 may be disposed on the first insulating layer ISL1 to cover a plurality of first connecting electrodes CNE1-1 and CNE1-2. The second insulating layer ISL2 may include a first sub-insulating layer IL-a disposed on the first insulating layer ISL1 and a second sub-insulating layer IL-b disposed on the first sub-insulating layer IL-a. In one or more embodiments, the first sub-insulating layer IL-a may be disposed between adjacent first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may be disposed between the first conductive layers CNL-a1 and CNL-a2 to fill the space between the first conductive layers CNL-a1 and CNL-a2.

[0175] A first sub-insulating layer IL-a may be disposed between and in contact with each of the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may be disposed between the first conductive layers CNL-a1 and CNL-a2 to cover at least a portion of the side surfaces CNLa-S1 and CNLa-S2 of each of the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may cover each of the first-1 electrode side surface CNLa-S1 of the first-1 conductive layer CNL-a1 and the first-2 electrode side surface CNLa-S2 of the first-2 conductive layer CNL-a2. The first sub-insulating layer IL-a may be in contact with each of the first-1 electrode side surface CNLa-S1 of the first-1 conductive layer CNL-a1 and the first-2 electrode side surface CNLa-S2 of the first-2 conductive layer CNL-a2.

[0176] The first sub-insulating layer IL-a may contact each of the first layers CL1-1 and CL1-2 and the second layers CL2-1 and CL2-2 of the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may contact the side surface of each of the first conductive layers CNL-a1 and CNL-a2 to cover at least a portion of the side surface of each of the first layers CL1-1 and CL1-2 and the second layers CL2-1 and CL2-2. In one or more embodiments, the first sub-insulating layer IL-a may integrally cover the side surfaces of the first layers CL1-1 and CL1-2, and may cover a portion of the side surfaces of the second layers CL2-1 and CL2-2.

[0177] The first sub-insulating layer IL-a may not be disposed on the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may be disposed in contact only with each of the side surfaces CNLa-S1 and CNLa-S2 of the first conductive layers CNL-a1 and CNL-a2, and may not be in contact with each of the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may not be disposed on any of the top surfaces CNLa-U1 of the first electrode of the first-1 conductive layer CNL-a1 and CNLa-U2 of the first-2 conductive layer CNL-a2. The first sub-insulating layer IL-a may not be disposed on the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2, but the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2 may be exposed, so that the second conductive layers CNL-b1 and CNL-b2 are disposed directly on the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2.

[0178] The top surface I1-U of the first sub-insulating layer IL-a may be disposed below the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. For example, the top surface I1-U of the first sub-insulating layer IL-a may be defined to be closer to the first insulating layer ISL1 than the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. The top surface I1-U of the first insulating layer ISL1 may be disposed below the top surface CNLa-U1 of the first electrode of the first-1 conductive layer CNL-a1 and the top surface CNLa-U2 of the first-2 electrode of the first-2 conductive layer CNL-a2.

[0179] The top surface I1-U of the first sub-insulating layer IL-a may have a flat shape. The top surface I1-U of the first sub-insulating layer IL-a may be parallel to the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. The top surface I1-U of the first sub-insulating layer IL-a may be parallel to each of the top surfaces CNLa-U1 of the first electrode of the first-1 conductive layer CNL-a1 and the top surfaces CNLa-U2 of the first-2 conductive layer CNL-a2. However, one or more embodiments are not limited thereto, and the top surface I1-U of the first sub-insulating layer IL-a may have a bent shape. The top surface I1-U of the first sub-insulating layer IL-a may be disposed below the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2, and may have a bent shape recessed adjacent to the first insulating layer ISL1. For example, as the top surface I1-U of the first sub-insulating layer IL-a gradually moves away from the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2, the top surface I1-U may have a concave, bent shape adjacent to the first insulating layer ISL1.

[0180] The first sub-insulating layer IL-a may fill the space defined between the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may fill at least a portion of the space defined between the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a may cover the entire side surface of the first layers CL1-1 and CL1-2 of the first conductive layers CNL-a1 and CNL-a2, and a portion of the second layers CL2-1 and CL2-2, and may fill the space defined between the first conductive layers CNL-a1 and CNL-a2. However, one or more embodiments are not limited thereto, and the first sub-insulating layer IL-a may completely fill the space defined between the first conductive layers CNL-a1 and CNL-a2. For example, the first sub-insulating layer IL-a can completely cover the side surfaces of each of the first layers CL1-1 and CL1-2 and the second layers CL2-1 and CL2-2 of the first conductive layers CNL-a1 and CNL-a2, and can completely fill the space between the first conductive layers CNL-a1 and CNL-a2, such that the top surface I1-U of the first sub-insulating layer IL-a is parallel to the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2.

[0181] The first sub-insulating layer IL-a may include a first organic material and a first inorganic material. The first inorganic material included in the first sub-insulating layer IL-a may be an inorganic material containing silicon. The first inorganic material included in the first sub-insulating layer IL-a may include at least one of silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiON). For example, the first inorganic material may be silicon dioxide (SiO2). The first organic material included in the first sub-insulating layer IL-a may include at least one of siloxanes, polyimides, and acrylic polymers. The first organic material may be, for example, a siloxane. The first sub-insulating layer IL-a may be made of the first inorganic material and the first organic material.

[0182] Regarding the first organic material and the first inorganic material included in the first sub-insulating layer IL-a, the content (e.g., amount) of the first inorganic material may be greater than the content of the first organic material compared to the total content (e.g., amount) of the first sub-insulating layer IL-a. The content (e.g., amount) of the first organic material may be about 10 wt% or more and less than about 50 wt% compared to the total content (e.g., amount) of the first sub-insulating layer IL-a. When the content (e.g., amount) of the first organic material in the first sub-insulating layer IL-a is less than about 10 wt%, the coating properties of the filler material can be reduced in the process of forming the first sub-insulating layer IL-a, and therefore, the first sub-insulating layer IL-a can be disposed not only between the first conductive layers CNL-a1 and CNL-a2, but also on the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2. When the content (e.g., amount) of the first organic material in the first sub-insulating layer IL-a is about 50 wt% or more, the first sub-insulating layer IL-a may not be patterned to be arranged only between the first conductive layers CNL-a1 and CNL-a2.

[0183] The first sub-insulating layer IL-a may be disposed on the same layer as the first conductive layers CNL-a1 and CNL-a2. The first sub-insulating layer IL-a, as well as the first conductive layers CNL-a1 and CNL-a2, may be disposed on the first insulating layer ISL1. The first sub-insulating layer IL-a may cover a portion of the top surface of the first insulating layer ISL1 that is exposed due to the absence of the first conductive layers CNL-a1 and CNL-a2. The bottom surface I1-L of the first sub-insulating layer IL-a may define a surface disposed on the same layer as each of the bottom surfaces CNLa-L1 and CNLa-L2 of the first conductive layers CNL-a1 and CNL-a2, and aligned with each of the bottom surfaces CNLa-L1 and CNLa-L2 of the first conductive layers CNL-a1 and CNL-a2. The bottom surface I1-L of the first sub-insulating layer IL-a can be defined as a surface aligned with each of the bottom surfaces of the first electrode of the first conductive layer CNL-a1 CNL-a1 and the bottom surfaces of the first electrode of the first conductive layer CNL-a2 CNL-a2.

[0184] At least a portion of the bottom surface of each of the second conductive layers CNL-b1 and CNL-b2 may contact the first sub-insulating layer IL-a. The bottom surfaces of the second conductive layers CNL-b1 and CNL-b2 corresponding to their edges may contact the first sub-insulating layer IL-a. At least a portion of the bottom surface of each of the second-1 conductive layer CNL-b1 and the second-2 conductive layer CNL-b2 may contact the first sub-insulating layer IL-a.

[0185] The side surfaces CNLa-S1 and CNLa-S2 of the first conductive layers CNL-a1 and CNL-a2 may not be aligned with the side surfaces CNLb-S1 and CNLb-S2 of the second conductive layers CNL-b1 and CNL-b2. The top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2 may not be aligned with the bottom surfaces CNLb-L1 and CNLb-L2 of the second conductive layers CNL-b1 and CNL-b2. The first electrode side surface CNLa-S1 of the first-1 conductive layer CNL-a1 may not be aligned with the second electrode side surface CNLb-S1 of the second-1 conductive layer CNL-b1. The first electrode side surface CNLa-S2 of the first-2 conductive layer CNL-a2 may not be aligned with the second electrode side surface CNLb-S2 of the second-2 conductive layer CNL-b2.

[0186] At least a portion of the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2 may contact the second conductive layers CNL-b1 and CNL-b2. The second layers CL2-1 and CL2-2 included in the first conductive layers CNL-a1 and CNL-a2 may contact the corresponding second conductive layers CNL-b1 and CNL-b2. The second-first layer CL2-1 of the first-first conductive layer CNL-a1 may contact the second-first conductive layer CNL-b1, and the second-second layer CL2-2 of the first-second conductive layer CNL-a2 may contact the second-second conductive layer CNL-b2.

[0187] The planar area of ​​each of the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2 may be smaller than the planar area of ​​each of the bottom surfaces CNLb-L1 and CNLb-L2 of the second conductive layers CNL-b1 and CNL-b2. The planar area of ​​the top surface CNLa-U1 of the first electrode of the first-1 conductive layer CNL-a1 may be smaller than the planar area of ​​the bottom surface CNLb-L1 of the second-1 electrode of the second-1 conductive layer CNL-b1. The planar area of ​​the top surface CNLa-U2 of the first-2 electrode of the first-2 conductive layer CNL-a2 may be smaller than the planar area of ​​the bottom surface CNLb-L2 of the second-2 electrode of the second-2 conductive layer CNL-b2. The planar area of ​​each of the bottom surfaces CNLb-L1 and CNLb-L2 of the second conductive layers CNL-b1 and CNL-b2 may be larger than the planar area of ​​each of the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2, and each of the top surfaces CNLa-U1 and CNLa-U2 of the first conductive layers CNL-a1 and CNL-a2 may be completely covered by the second conductive layers CNL-b1 and CNL-b2. However, one or more embodiments of this disclosure are not limited thereto.

[0188] A second sub-insulating layer IL-b may be disposed on the first sub-insulating layer IL-a to cover the second conductive layers CNL-b1 and CNL-b2. The second sub-insulating layer IL-b may cover each of the second conductive layers CNL-b1 and CNL-b2 and may be in contact with each of the second conductive layers CNL-b1 and CNL-b2. The second sub-insulating layer IL-b may cover the side surfaces CNLb-S1 and CNLb-S2 and the top surfaces CNLb-U1 and CNLb-U2 of the second conductive layers CNL-b1 and CNL-b2. The second sub-insulating layer IL-b may cover each of the second-first electrode side surface CNLb-S1 and the second-first electrode top surface CNLb-U1 of the second-first conductive layer CNL-b1, and the second-second electrode side surface CNLb-S2 and the second-second electrode top surface CNLb-U2 of the second-second conductive layer CNL-b2.

[0189] The second sub-insulating layer IL-b may contact each of the third layers CL3-1 and CL3-2 and the fourth layers CL4-1 and CL4-2 of the second conductive layers CNL-b1 and CNL-b2. The second sub-insulating layer IL-b may contact the side surfaces CNLb-S1 and CNLb-S2 and the top surfaces CNLb-U1 and CNLb-U2 of the second conductive layers CNL-b1 and CNL-b2 to cover the side surfaces of the third layers CL3-1 and CL3-2 and the side and top surfaces of the fourth layers CL4-1 and CL4-2. The second sub-insulating layer IL-b may integrally cover the side surfaces of the third layers CL3-1 and CL3-2 and the side and top surfaces of the fourth layers CL4-1 and CL4-2.

[0190] The second sub-insulating layer IL-b may fill the space defined between the second conductive layers CNL-b1 and CNL-b2 to cover the second conductive layers CNL-b1 and CNL-b2. The second sub-insulating layer IL-b may completely fill the space defined between the second conductive layers CNL-b1 and CNL-b2 to integrally cover the side surfaces of each of the third layers CL3-1 and CL3-2 and the fourth layers CL4-1 and CL4-2 of the second conductive layers CNL-b1 and CNL-b2, as well as the top surface of each of the fourth layers CL4-1 and CL4-2.

[0191] The second sub-insulating layer IL-b may include a second organic material. The second organic material included in the second sub-insulating layer IL-b may be different from the first organic material included in the first sub-insulating layer IL-a. The second organic material may include at least one selected from acrylic resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins. For example, the second organic material may include a polyimide resin. The second sub-insulating layer IL-b may be made of the second organic material.

[0192] A display panel according to one or more embodiments may include a first conductive layer and a second conductive layer forming a first connection electrode, and may include a first sub-insulating layer disposed between the first conductive layers. The first sub-insulating layer may include a first organic material such as a siloxane, polyimide, and / or acrylic polymer, and a first inorganic material such as silicon dioxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiON). Since the first and second conductive layers, both comprising aluminum, form a first connection electrode, a low-resistance line with a large thickness can be achieved. In some embodiments, a structure in which the first sub-insulating layer fills a stepped portion may be provided between the first conductive layers to facilitate the film formation process and photolithography process of the second conductive layer, and thus, as the introduction of an organic planar film between the first and second conductive layers becomes unnecessary, the number of masks desired or required by the process can be reduced, and the process can be simplified to reduce process costs.

[0193] Figure 6B This is a cross-sectional view illustrating a portion of the configuration of a display panel according to one or more embodiments of the present disclosure. Figure 6B The diagram shows Figure 5 The configuration of the display panel DP illustrated in the diagram includes a first insulating layer ISL1 in the circuit layer DP-CL, a portion of a plurality of first connection electrodes disposed on the first insulating layer ISL1, a second insulating layer ISL2 covering the first connection electrodes, a second connection electrode CNE2 disposed on the second insulating layer ISL2 and electrically connected to the first connection electrodes, and a third insulating layer ISL3 covering the second connection electrode CNE2. Figure 6B For ease of explanation, the first contact hole defined in the first insulating layer ISL1 may not be provided. (Referring to...) Figure 6B When describing the first connecting electrode CNE1 and the second connecting electrode CNE2 according to one or more embodiments, the same / similar reference numerals may be used, each of which can be independently associated with... Figures 1A to 6A The same / similar parts described in the text may be excluded, and duplicate descriptions may be omitted.

[0194] For reference Figure 5and Figure 6B Each of the multiple pixels PX may include a connection electrode electrically connected to a transistor. For example... Figure 6B The diagram shows that each of the multiple pixels PX in the display panel DP may include a first connection electrode CNE1 and a second connection electrode CNE2. Figure 6B The first connecting electrode CNE1 and the second connecting electrode CNE2 shown in the figure can be connected to... Figure 5 The first and second connecting electrodes, which are electrically connected to each other, correspond to each other. For example, Figure 6B The first connecting electrode CNE1 shown in the figure can be connected to Figure 5 The first-to-first connection electrode CNE11 in the diagram corresponds to this, and Figure 6B The second connecting electrode CNE2 shown in the diagram can be connected to... Figure 5 The second connecting electrode CNE2 in the diagram corresponds to this.

[0195] about Figure 6B The first connecting electrode CNE1 shown in the diagram can be substantially applied in the same way as described in this article. Figure 6A The first connecting electrode CNE1-1 and CNE1-2 are present. For example, the first connecting electrode CNE1 may include a first conductive layer CNL-a disposed on the first insulating layer ISL1 and a second conductive layer CNL-b disposed on the first conductive layer CNL-a. The first connecting electrode CNE1 may include an electrode in which the first conductive layer CNL-a and the second conductive layer CNL-b are sequentially stacked. The first conductive layer CNL-a may include a first layer CL1 disposed on the first insulating layer ISL1 and a second layer CL2 disposed on the first layer CL1. The second conductive layer CNL-b may include a third layer CL3 disposed on the first conductive layer CNL-a and a fourth layer CL4 disposed on the third layer CL3.

[0196] As in this article about Figure 6A The content (e.g., amount) described in the second insulating layer ISL2 can be applied substantially in the same way to Figure 6BThe diagram illustrates a second insulating layer ISL2. For example, the second insulating layer ISL2 may be disposed on the first insulating layer ISL1 to cover the first connection electrode CNE1. The second insulating layer ISL2 may include a first sub-insulating layer IL-a disposed on the first insulating layer ISL1 and a second sub-insulating layer IL-b disposed on the first sub-insulating layer IL-a. The first sub-insulating layer IL-a may be disposed between adjacent first conductive layers CNL-a. The first sub-insulating layer IL-a may cover at least a portion of the side surfaces CNLa-S of the first conductive layer CNL-a. The first sub-insulating layer IL-a may not be disposed on the top surface CNLa-U of the first conductive layer CNL-a. The top surface I1-U of the first sub-insulating layer IL-a may be disposed below the top surface CNLa-U of the first conductive layer CNL-a. The first sub-insulating layer IL-a may include a first organic material and a first inorganic material comprising silicon. The second sub-insulating layer IL-b may be disposed on the first sub-insulating layer IL-a to cover the second conductive layer CNL-b. The second sub-insulating layer IL-b may include a second organic material. The bottom surface CNLa-L of the first conductive layer CNL-a may be defined by the bottom surface of the first layer CL1. The bottom surface CNLb-L of the second conductive layer CNL-b may be defined by the bottom surface of the third layer CL3. The bottom surface I1-LF of the first sub-insulating layer IL-a may define a surface disposed on the same layer as the bottom surface CNLa-L of the first conductive layer CNL-a and aligned with the bottom surface CNLa-L of the first conductive layer CNL-a.

[0197] refer to Figure 6B The second connecting electrode CNE2 may be disposed on the second insulating layer ISL2. The second connecting electrode CNE2 may include a third conductive layer CNL-c and a fourth conductive layer CNL-d sequentially stacked. The third conductive layer CNL-c may include a fifth layer CL5 disposed on the second sub-insulating layer IL-b and a sixth layer CL6 disposed on the fifth layer CL5. The second connecting electrode CNE2 may include an electrode having a structure in which the third conductive layer CNL-c and the fourth conductive layer CNL-d are stacked.

[0198] Each of the fifth layer CL5 and the sixth layer CL6 may include a metallic material. The fifth layer CL5 and the sixth layer CL6 may include different metallic materials. In one or more embodiments, the fifth layer CL5 may include titanium, and the sixth layer CL6 may include aluminum.

[0199] The sixth layer CL6 included in the third conductive layer CNL-c may correspond to the uppermost layer of the third conductive layer CNL-c. The sixth layer CL6 may be the uppermost layer among multiple layers included in the third conductive layer CNL-c. The top surface CNLc-U of the third conductive layer CNL-c may be defined by the top surface of the sixth layer CL6.

[0200] The second connecting electrode CNE2 may include a fourth conductive layer CNL-d disposed on the third conductive layer CNL-c. The fourth conductive layer CNL-d may be directly disposed on the third conductive layer CNL-c. The bottom surface CNLd-L of the fourth conductive layer CNL-d may be in contact with the third conductive layer CNL-c. The fourth conductive layer CNL-d may include a seventh layer CL7 disposed on the third conductive layer CNL-c and an eighth layer CL8 disposed on the seventh layer CL7. The eighth layer CL8 may be directly disposed on the seventh layer CL7. The seventh layer CL7 may be a layer in direct contact with the bottom surface of the eighth layer CL8.

[0201] The seventh layer CL7 included in the fourth conductive layer CNL-d may correspond to the bottommost layer in the fourth conductive layer CNL-d. The seventh layer CL7 may be the bottommost layer among multiple layers included in the fourth conductive layer CNL-d. The bottom surface CNLd-L of the fourth conductive layer CNL-d may be defined by the bottom surface of the seventh layer CL7.

[0202] Each of the seventh layer CL7 and the eighth layer CL8 may include a metallic material. The seventh layer CL7 and the eighth layer CL8 may include different metallic materials. In one or more embodiments, the seventh layer CL7 may include aluminum, and the eighth layer CL8 may include titanium. In one or more embodiments, the sixth layer CL6 included in the third conductive layer CNL-c and the seventh layer CL7 included in the fourth conductive layer CNL-d may include substantially the same material. Each of the sixth layer CL6 and the seventh layer CL7 may include aluminum.

[0203] The second connecting electrode CNE2 may include an electrode having a four-layer structure in which a fifth layer CL5, a sixth layer CL6, a seventh layer CL7, and an eighth layer CL8 are stacked. Figure 6B In the diagram, the boundary between the sixth layer CL6 and the seventh layer CL7 can be clearly shown as a straight line, but this is only an example, and in the cross-section, the boundary between the sixth layer CL6 and the seventh layer CL7 may not be clearly shown.

[0204] The thickness of the sixth layer CL6 and the seventh layer CL7 may be the same. However, one or more embodiments of this disclosure are not limited thereto. The thickness of the sixth layer CL6 and the seventh layer CL7 may be different from each other.

[0205] In one or more embodiments, the sum (e.g., total) of the thickness of the sixth layer CL6 and the seventh layer CL7 may be at least approximately (e.g., or more) and at most about (For example, or less). When the sum of the thicknesses of the sixth layer CL6 and the seventh layer CL7 (for example, the total) is less than approximately At that time, the desired or appropriate resistance reduction effect of the second connecting electrode CNE2 may not be expected, and if the sum of the thicknesses of the sixth layer CL6 and the seventh layer CL7 (e.g., the total) exceeds approximately (For example, when the sum of the thickness of the sixth layer CL6 and the seventh layer CL7 (e.g., the total) exceeds approximately If the thickness of the second connecting electrode CNE2 is too large (or significantly large), it becomes difficult to miniaturize the display device DD. Since the sum (e.g., total) of the thicknesses of the sixth layer CL6 and the seventh layer CL7 meets the range mentioned herein, the electrode resistance can be effectively reduced, and electrode defects in the process can be reduced to improve process reliability. The conductivity of each of the sixth layer CL6 and the seventh layer CL7 substantially determines the conductivity of the second connecting electrode CNE2. Because the sum (e.g., total) of the thicknesses of the sixth layer CL6 and the seventh layer CL7 increases, a second connecting electrode CNE2 with low resistance characteristics can be formed. Therefore, the display panel DP (see...) Figure 1B It can be driven at high speed, which can improve the display panel's DP (see...). Figure 1B It offers display characteristics and reduces power consumption.

[0206] The third insulating layer ISL3 may be disposed on the second insulating layer ISL2 to cover the second connection electrode CNE2. The third insulating layer ISL3 may include a third sub-insulating layer IL-c disposed on the second sub-insulating layer IL-b and a fourth sub-insulating layer IL-d disposed on the third sub-insulating layer IL-c.

[0207] The third sub-insulating layer IL-c may contact the third conductive layer CNL-c. The third sub-insulating layer IL-c may cover a portion of the side surface CNLc-S of the third conductive layer CNL-c. The third sub-insulating layer IL-c may contact each of the fifth layer CL5 and the sixth layer CL6 of the third conductive layer CNL-c. The third sub-insulating layer IL-c may entirely cover the side surface of the fifth layer CL5 to partially cover the side surface of the sixth layer CL6.

[0208] The third sub-insulating layer IL-c may not be disposed on the top surface CNLc-U of the third conductive layer CNL-c. The third sub-insulating layer IL-c may be arranged to contact only the side surface CNLc-S of the third conductive layer CNL-c, and may not contact the top surface CNLc-U of the third conductive layer CNL-c. Alternatively, the third sub-insulating layer IL-c may not be disposed on the top surface CNLc-U of the third conductive layer CNL-c, but may expose the top surface CNLc-U of the third conductive layer CNL-c. Therefore, the fourth conductive layer CNL-d may be directly disposed on the top surface CNLc-U of the third conductive layer CNL-c.

[0209] The top surface I2-U of the third sub-insulating layer IL-c may be disposed below the top surface CNLc-U of the third conductive layer CNL-c. For example, the top surface I2-U of the third sub-insulating layer IL-c may be defined to be closer to the second insulating layer ISL2 than the top surface CNLc-U of the third conductive layer CNL-c. However, one or more embodiments of this disclosure are not limited thereto. The top surface I2-U of the third sub-insulating layer IL-c may be parallel to the top surface CNLc-U of the third conductive layer CNL-c. For example, the top surface I2-U of the third sub-insulating layer IL-c may define a surface aligned with the top surface CNLc-U of the third conductive layer CNL-c. The bottom surface I2-L of the third sub-insulating layer IL-c may define a surface aligned with a portion of the bottom surface of the third conductive layer CNL-c.

[0210] Although Figure 6B The illustration shows an example in which the top surface I2-U of the third sub-insulating layer IL-c has a flat shape, but one or more embodiments of this disclosure are not limited thereto. The top surface I2-U of the third sub-insulating layer IL-c may have a bent shape. For example, the top surface I2-U of the third sub-insulating layer IL-c may have a bent shape with a recess to be adjacent to the second insulating layer ISL2.

[0211] The third sub-insulating layer IL-c may be disposed on the same layer as the third conductive layer CNL-c. The third sub-insulating layer IL-c and the third conductive layer CNL-c may be disposed on the second sub-insulating layer IL-b. The third sub-insulating layer IL-c may cover a portion of the top surface of the second sub-insulating layer IL-b that is exposed due to the absence of the third conductive layer CNL-c.

[0212] At least a portion of the bottom surface CNLd-L of the fourth conductive layer CNL-d can contact the third sub-insulating layer IL-c. The bottom surface CNLd-L of the fourth conductive layer CNL-d corresponding to the edge of the fourth conductive layer CNL-d can contact the third sub-insulating layer IL-c.

[0213] The side surface CNLc-S of the third conductive layer CNL-c may not be aligned with the side surface CNLd-S of the fourth conductive layer CNL-d. For example, the top surface CNLc-U of the third conductive layer CNL-c may not be aligned with the bottom surface CNLd-L of the fourth conductive layer CNL-d.

[0214] At least a portion of the top surface CNLc-U of the third conductive layer CNL-c may contact the fourth conductive layer CNL-d. The planar area of ​​the top surface CNLc-U of the third conductive layer CNL-c may be smaller than the planar area of ​​the bottom surface CNLd-L of the fourth conductive layer CNL-d. The planar area of ​​the bottom surface CNLd-L of the fourth conductive layer CNL-d may be larger than the planar area of ​​the top surface CNLc-U of the third conductive layer CNL-c, and the top surface CNLc-U of the third conductive layer CNL-c may be completely covered by the fourth conductive layer CNL-d. However, one or more embodiments of this disclosure are not limited thereto.

[0215] The fourth sub-insulating layer IL-d can be disposed on the third sub-insulating layer IL-c and cover the fourth conductive layer CNL-d. The fourth sub-insulating layer IL-d can cover the fourth conductive layer CNL-d and can be in contact with the third conductive layer CNL-c. The fourth sub-insulating layer IL-d can cover the side surface CNLd-S and the top surface CNLd-U of the fourth conductive layer CNL-d. The fourth sub-insulating layer IL-d can cover the side surface of the seventh layer CL7 and the side surface and top surface of the eighth layer CL8 of the fourth conductive layer CNL-d. The fourth sub-insulating layer IL-d can completely cover the side surface and top surface of the seventh layer CL7 and the eighth layer CL8.

[0216] In one or more embodiments, each of the plurality of pixels PX included in the display panel DP may include a second connection electrode. Each of the plurality of second connection electrodes included in the plurality of pixels PX may have a connection electrode with the second connection electrode in the display panel DP. Figure 6B The structure of the second connecting electrode CNE2 shown in the figure is substantially the same. For example, each of the plurality of second connecting electrodes may include a third conductive layer CNL-c and a fourth conductive layer CNL-d stacked sequentially.

[0217] The third sub-insulating layer IL-c may be disposed between adjacent third conductive layers CNL-c. The third sub-insulating layer IL-c may be disposed between the third conductive layers CNL-c to fill the space between the third conductive layers CNL-c. The third sub-insulating layer IL-c may fill the space defined between the third conductive layers CNL-c. The third sub-insulating layer IL-c may fill a portion of the space defined between the third conductive layers CNL-c. The third sub-insulating layer IL-c may cover a portion of the entire side surface of the fifth layer CL5 and a portion of the side surface of the sixth layer CL6 to fill the space defined between the third conductive layers CNL-c. However, one or more embodiments of this disclosure are not limited thereto, and the third sub-insulating layer IL-c may completely fill the space defined between the third conductive layers CNL-c. For example, the third sub-insulating layer IL-c can completely cover the side surfaces of each of the fifth layer CL5 and the sixth layer CL6 of the third conductive layer CNL-c and can completely fill the space between the third conductive layers CNL-c, such that the top surface I2-U of the third sub-insulating layer IL-c is parallel to the top surface CNLc-U of the third conductive layer CNL-c.

[0218] The fourth sub-insulating layer IL-d can fill the space defined between the fourth conductive layers CNL-d to cover the fourth conductive layers CNL-d. The fourth sub-insulating layer IL-d can completely fill the space defined between the fourth conductive layers CNL-d to integrally cover the side surface CNLd-S and top surface CNLd-U of each of the plurality of fourth conductive layers CNL-d.

[0219] The third sub-insulating layer IL-c may include a first organic material and a first inorganic material. The first inorganic material included in the third sub-insulating layer IL-c may be a silicon-containing inorganic material. The first inorganic material included in the third sub-insulating layer IL-c may include at least one of silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiON). For example, the first inorganic material may be silicon dioxide (SiO2). The first organic material included in the third sub-insulating layer IL-c may include at least one of siloxanes, polyimides, and acrylic polymers. The first organic material may be, for example, a siloxane. The third sub-insulating layer IL-c may be made of the first inorganic material and the first organic material.

[0220] Regarding the first organic material and the first inorganic material included in the third sub-insulating layer IL-c, the content (e.g., amount) of the first inorganic material may be greater than the content of the first organic material compared to the total content (e.g., amount) of the third sub-insulating layer IL-c. The content (e.g., amount) of the first organic material may be about 10 wt% or more and less than about 50 wt% compared to the total content (e.g., amount) of the third sub-insulating layer IL-c. When the content (e.g., amount) of the first organic material in the third sub-insulating layer IL-c is less than about 10 wt%, the coating properties of the filler material in the process of forming the third sub-insulating layer IL-c can be reduced, and therefore, the third sub-insulating layer IL-c may be arranged not only between the third conductive layers CNL-c, but also on the top surface CNLc-U of each of the plurality of third conductive layers CNL-c. When the content (e.g., amount) of the first organic material in the third sub-insulating layer IL-c is about 50 wt% or more, the third sub-insulating layer IL-c may not be patterned to be arranged only between the third conductive layers CNL-c.

[0221] The fourth sub-insulating layer IL-d may include a second organic material. The second organic material included in the fourth sub-insulating layer IL-d may differ from the first organic material included in the third sub-insulating layer IL-c. The second organic material may include at least one selected from acrylic resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins. For example, the second organic material may include a polyimide resin. The fourth sub-insulating layer IL-d may be made of the second organic material.

[0222] In one or more embodiments, the display device DD may be a component of an electronic device and / or applied to an electronic device such as a smartphone, television, monitor, tablet computer, electric vehicle, mobile phone, tablet PC, mobile communication terminal, e-notebook, e-reader, portable multimedia player (PMP), navigation device, ultra-mobile PC (UMPC), laptop computer, billboard, Internet of Things (IoT) device, smartwatch, wristwatch phone, or head-mounted display (HMD). For example, the display device DD may be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Alternatively, in one or more embodiments, the display device DD may be applied to a smartwatch, wristwatch phone, and / or head-mounted display (HMD) for implementing virtual reality and / or augmented reality.

[0223] In the following description, a method for manufacturing a display panel according to one or more embodiments will be described with reference to the accompanying drawings. In the description of the method for manufacturing a display panel according to one or more embodiments, content that overlaps with the content of the display panels of the embodiments described herein will not be provided.

[0224] Figure 7A and Figure 7B This is a flowchart illustrating a method for manufacturing a display panel according to one or more embodiments of the present disclosure. Specifically, Figure 7B This is a flowchart illustrating the steps of forming a plurality of first connecting electrodes and a second insulating layer according to one or more embodiments of the present disclosure.

[0225] refer to Figure 7A A method for manufacturing a display panel according to one or more embodiments of the present disclosure may include: the steps (e.g., actions or tasks) of providing a semiconductor pattern and a first insulating layer disposed on the semiconductor pattern (S100); and the steps (e.g., actions or tasks) of forming a plurality of first connection electrodes disposed on the first insulating layer and electrically connected to the semiconductor pattern and a second insulating layer covering the plurality of first connection electrodes (S200).

[0226] refer to Figure 7B In a method for manufacturing a display panel according to one or more embodiments, the step (e.g., action or task) of forming a plurality of first connecting electrodes and second insulating layers (S200) may include: forming a plurality of first conductive layers comprising aluminum on the first insulating layers (e.g., action or task) (S201); providing a filler material between the plurality of first conductive layers to form a first sub-insulating layer covering at least a portion of the side surface of each of the plurality of first conductive layers (e.g., action or task) (S202); forming a plurality of second conductive layers comprising aluminum on the plurality of first conductive layers (e.g., action or task) (S203); and forming a second sub-insulating layer covering the plurality of second conductive layers (e.g., action or task) (S204).

[0227] Figures 8A to 8H This is a cross-sectional view illustrating some steps (e.g., actions or tasks) of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. Figures 8A to 8H respectively with Figure 6B The corresponding cross-sectional diagrams illustrate the states of some steps (e.g., actions or tasks) in the method for manufacturing the display panel. For ease of explanation, Figures 8A to 8H The steps (e.g., actions or tasks) of forming a first connection electrode CNE1 on the first insulating layer ISL1 can be illustrated. All of the plurality of first connection electrodes CNE1 formed on the first insulating layer ISL1 can be formed by a process substantially the same as the process described in more detail later.

[0228] refer to Figure 8A A method for manufacturing a display panel according to one or more embodiments of the present disclosure may include: providing a first semiconductor pattern SP1 and a second semiconductor pattern SP2 (see...). Figure 5 ) and arranged in the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (see Figure 5 Steps (e.g., actions or tasks) of the initial display panel on the first insulating layer ISL1 of the initial display panel. In some embodiments, an exposed first semiconductor pattern SP1 and a second semiconductor pattern SP2 may be defined in the first insulating layer ISL1 of the initial display panel (see Figure 5 The first contact hole is part of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (see [reference]). The first conductive layer CNL-a, described in more detail elsewhere herein, may be formed corresponding to the first contact hole and may be electrically connected via the first contact hole to the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (see [reference]). Figure 5 ).

[0229] refer to Figure 8A and Figure 8B A method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the step of forming a plurality of first conductive layers CNL-a on a first insulating layer ISL1 (e.g., an action or task). The step of forming the plurality of first conductive layers CNL-a (e.g., an action or task) may include the step of forming a preliminary first conductive layer DCL1 on the first insulating layer ISL1 (e.g., an action or task); and the step of patterning the preliminary first conductive layer DCL1 (e.g., an action or task). The step of forming the preliminary first conductive layer DCL1 (e.g., an action or task) may include the step of forming a first conductive film DF1 on the first insulating layer ISL1 (e.g., an action or task); and the step of forming a second conductive film DF2 on the first conductive film DF1 (e.g., an action or task). In this specification, the first conductive film DF1 may be referred to as the preliminary first layer, and the second conductive film DF2 may be referred to as the preliminary second layer.

[0230] Each of the first conductive film DF1 and the second conductive film DF2 may include a metallic material. The first conductive film DF1 and the second conductive film DF2 may include different metallic materials. In one or more embodiments, the first conductive film DF1 may include titanium, and the second conductive film DF2 may include aluminum. Therefore, each of the plurality of first conductive layers CNL-a may have a structure in which titanium (Ti) / aluminum (Al) layers are stacked.

[0231] After the step (e.g., action or task) of forming the preliminary first conductive layer DCL1 on the first insulating layer ISL1, the step (e.g., action or task) of patterning the first conductive film DF1 and the second conductive film DF2 can be performed. The step (e.g., action or task) of patterning the first conductive film DF1 and the second conductive film DF2 can be a dry etching step or a wet etching step of the first conductive film DF1 and the second conductive film DF2. For example, the first conductive film DF1 and the second conductive film DF2 can be dry etched.

[0232] In the step (e.g., action or task) of patterning the first conductive film DF1 and the second conductive film DF2, after patterning the first photoresist pattern on the second conductive film DF2, the first conductive film DF1 and the second conductive film DF2 may be etched to form a plurality of first conductive layers CNL-a including a first layer CL1 and a second layer CL2. Thereafter, the first photoresist pattern may be removed from the first conductive layers CNL-a to expose the top surface of each of the plurality of first conductive layers CNL-a. In some embodiments, in the step (e.g., action or task) of patterning the first conductive film DF1 and the second conductive film DF2, a portion of the top surface of the first insulating layer ISL1 may be exposed.

[0233] Each of the plurality of first conductive layers CNL-a may include a first layer CL1 and a second layer CL2 formed by patterning a first conductive film DF1 and a second conductive film DF2. Each of the plurality of first conductive layers CNL-a may include a first layer CL1 and a second layer CL2 stacked sequentially.

[0234] refer to Figure 6A and Figures 8C to 8E A method for manufacturing a display panel according to one or more embodiments of the present disclosure may provide a filling material between a plurality of first conductive layers CNL-a, and therefore may also include the step (e.g., action or task) of forming a first sub-insulating layer IL-a covering at least a portion of the side surfaces CNLa-S of each of the plurality of first conductive layers CNL-a. The first sub-insulating layer IL-a may be formed between the first conductive layers CNL-a. The first sub-insulating layer IL-a may be disposed between the first conductive layers CNL-a to cover at least a portion of the side surfaces CNLa-S of each of the plurality of first conductive layers CNL-a.

[0235] In one or more embodiments, the filler material for forming the first sub-insulating layer IL-a may not only be patterned and provided between the first conductive layers CNL-a, but may also be commonly provided on the upper portion of each of the plurality of first conductive layers CNL-a and between the first conductive layers CNL-a (e.g., may be commonly provided simultaneously on the upper portion of each of the plurality of first conductive layers CNL-a and between the first conductive layers CNL-a). Due to the fluidity of the filler material, the filler material provided on the upper portion of each of the plurality of first conductive layers CNL-a may move between the first conductive layers CNL-a and then be cured to form the first sub-insulating layer IL-a.

[0236] The filler material may include a first organic material and a second organic material. The first inorganic material included in the filler material may be a silicon-containing inorganic material. The first inorganic material included in the filler material may include at least one of silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiON). For example, the first inorganic material may be silicon dioxide (SiO2). The first organic material included in the filler material may include at least one of siloxanes, polyimides, and acrylic polymers. The first organic material may be, for example, a siloxane. The first sub-insulating layer IL-a may be made of the first inorganic material and the first organic material.

[0237] Regarding the first organic material and the first inorganic material included in the filler material, the content (e.g., amount) of the first inorganic material may be greater than the content (e.g., amount) of the first organic material compared to the combined content (e.g., amount) of the first organic material and the second organic material included in the filler material. The content (e.g., amount) of the first organic material may be about 10 wt% or more and less than about 50 wt% compared to the combined content (e.g., amount) of the first organic material and the second organic material included in the filler material.

[0238] The weight percentage of solids included in the filler material may be up to about 2 wt% (e.g., or less). In addition to the first organic and first inorganic materials described herein, the filler material may also include a solvent. With respect to the entire filler material, the sum of the solids content of the first organic and first inorganic materials may be up to about 2 wt% (e.g., or less). When the weight percentage of solids included in the filler material (e.g., amount) exceeds about 2 wt%, the flowability of the filler material may decrease, and the filler material provided on the upper portion of each of the plurality of first conductive layers CNL-a may not move between the first conductive layers CNL-a, but may remain.

[0239] The filler material may be made from a first organic material, a first inorganic material, and a solvent. The filler material may be a material that does not contain or excludes any other materials besides the first organic material, the first inorganic material, and the solvent. In one or more embodiments, the filler material may not contain (e.g., may exclude) a photosensitizer. In the process of curing the filler material to form the first sub-insulating layer IL-a, since the filler material does not contain a photosensitizer, a separate exposure process may not be provided. The filler material may be naturally cured or thermally cured to form the first sub-insulating layer IL-a.

[0240] refer to Figure 8C and Figure 8D In the step (e.g., action or task) of providing filler material between the first conductive layers CNL-a, a first preliminary sub-insulating layer P-IL-a may be formed on the first insulating layer ISL1. The first preliminary sub-insulating layer P-IL-a may integrally cover the side surfaces CNLa-S and top surface CNLa-U of the first conductive layer CNL-a to cover at least a portion of the top surface CNLa-U of the first conductive layer CNL-a. Figure 8C As illustrated, if a filler material is provided on the upper portion of the first conductive layer CNL-a (e.g., when the filler material is provided on the upper portion of the first conductive layer CNL-a), a portion of the filler material may not move between the first conductive layers CNL-a, but may remain on the top surface CNLa-U of each of the plurality of first conductive layers CNL-a, and then be cured. Therefore, a first preliminary insulating layer P-IL-a may be disposed on at least a portion of the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. Figure 8C As illustrated in the figure, the first preliminary sub-insulating layer P-IL-a may completely (e.g., integrally) cover the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. However, one or more embodiments of the present disclosure are not limited thereto, and the first preliminary sub-insulating layer P-IL-a may be formed on the top surface CNLa-U of each of the plurality of first conductive layers CNL-a in one or more suitable patterned shapes.

[0241] A method for manufacturing a display panel according to one or more embodiments of the present disclosure may further include: after a step (e.g., an action or task) of providing a filler material between the first conductive layers CNL-a, a step (e.g., an action or task) of ashing the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. In the step (e.g., an action or task) of ashing the top surface CNLa-U of each of the plurality of first conductive layers CNL-a, a portion of the first conductive layers CNL-a and the first preliminary sub-insulating layer P-IL-a may be removed. In the ashing process, the first preliminary sub-insulating layer P-IL-a formed on the top surface CNLa-U of each of the plurality of first conductive layers CNL-a may be removed by plasma (PS) to expose the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. The first preliminary sub-insulating layer P-IL-a formed on the top surface CNLa-U of each of the plurality of first conductive layers CNL-a may be removed to form a first sub-insulating layer IL-a arranged to contact only the side surfaces CNLa-S of each of the plurality of first conductive layers CNL-a. The first sub-insulating layer IL-a may be formed to contact only the side surfaces CNLa-S of each of the plurality of first conductive layers CNL-a and may not contact the top surface CNLa-U. The first sub-insulating layer IL-a may be formed not disposed on the top surface CNLa-U of the first conductive layers CNL-a. However, one or more embodiments of this disclosure are not limited thereto, and the filler material used to form the first sub-insulating layer IL-a may be patterned and provided only between the first conductive layers CNL-a, so as not disposed on the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. In this case, the step (e.g., action or task) of ashing the first conductive layers CNL-a may not be provided.

[0242] refer to Figure 8EThe top surface I1-U of the first sub-insulating layer IL-a may be disposed below the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. The top surface I1-U of the first sub-insulating layer IL-a may be defined to be closer (e.g., more) to the first insulating layer ISL1 than the top surface CNLa-U of each of the plurality of first conductive layers CNL-a. In the step (e.g., action or task) of ashing the top surface CNLa-U of each of the plurality of first conductive layers CNL-a, the etching rate of the first conductive layer CNL-a and the etching rate of the first preliminary sub-insulating layer P-IL-a may be different from each other. The first conductive layer CNL-a may be etched at a first etching rate, and the first preliminary sub-insulating layer P-IL-a may be etched at a second etching rate different from the first etching rate. The second etching rate may be greater than the first etching rate. Therefore, in the step (e.g., action or task) of ashing (removing or etching) the first conductive layer CNL-a, the top surface of the first preliminary sub-insulating layer P-IL-a will be etched (removed) more than the top surface CNLa-U of the first conductive layer CNL-a. The subsequently formed top surface I1-U of the first sub-insulating layer IL-a can be formed to be disposed below the top surface CNLa-U of the first conductive layer CNL-a. In this specification, "etch rate" may refer to the amount of etching per second in the film thickness direction. "Etching rate" may refer to the etching rate at room temperature (approximately 25°C). The unit of etching rate may be expressed as angstroms per second.

[0243] refer to Figure 8F and Figure 8G A method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the step of forming a plurality of second conductive layers CNL-b comprising aluminum on a plurality of first conductive layers CNL-a (e.g., an action or task). The step of forming the plurality of second conductive layers CNL-b (e.g., an action or task) may include the step of forming a preliminary second conductive layer DCL2 on the plurality of first conductive layers CNL-a and a first sub-insulating layer IL-a (e.g., an action or task); and the step of patterning the preliminary second conductive layer DCL2 (e.g., an action or task). The step of forming the preliminary second conductive layer DCL2 (e.g., an action or task) may include the step of forming a third conductive film DF3 on the plurality of first conductive layers CNL-a and the first sub-insulating layer IL-a (e.g., an action or task); and the step of forming a fourth conductive film DF4 on the third conductive film DF3 (e.g., an action or task). In this specification, the third conductive film DF3 may be referred to as the preliminary third layer, and the fourth conductive film DF4 may be referred to as the preliminary fourth layer.

[0244] Each of the third conductive film DF3 and the fourth conductive film DF4 may include a metallic material. The third conductive film DF3 and the fourth conductive film DF4 may include different metallic materials. In one or more embodiments, the third conductive film DF3 may comprise aluminum, and the fourth conductive film DF4 may comprise titanium. Therefore, the second conductive layer CNL-b may have a structure in which aluminum (Al) / titanium (Ti) layers are stacked.

[0245] After forming the preliminary second conductive layer DCL2 on the first conductive layer CNL-a and the first sub-insulating layer IL-a, the step (e.g., action or task) of patterning the third conductive film DF3 and the fourth conductive film DF4 can be performed. The step (e.g., action or task) of patterning the third conductive film DF3 and the fourth conductive film DF4 can be either dry etching or wet etching of the third conductive film DF3 and the fourth conductive film DF4. For example, the third conductive film DF3 and the fourth conductive film DF4 can be dry etched.

[0246] In the step (e.g., action or task) of patterning the third conductive film DF3 and the fourth conductive film DF4, after patterning the second photoresist pattern on the fourth conductive film DF4, the third conductive film DF3 and the fourth conductive film DF4 may be etched to form a plurality of second conductive layers CNL-b including a third layer CL3 and a fourth layer CL4. Thereafter, the second photoresist pattern may be removed from the second conductive layers CNL-b to expose the top surface of each of the plurality of second conductive layers CNL-b. In some embodiments, in the step (e.g., action or task) of patterning the third conductive film DF3 and the fourth conductive film DF4, a portion of the top surface I1-U of the first sub-insulating layer IL-a may be exposed.

[0247] Each of the plurality of second conductive layers CNL-b may include a third layer CL3 and a fourth layer CL4 formed by patterning a third conductive film DF3 and a fourth conductive film DF4. Each of the plurality of second conductive layers CNL-b may include a third layer CL3 and a fourth layer CL4 sequentially stacked. The third layer CL3 may be formed to contact the top surface of the second layer CL2.

[0248] refer to Figure 8HA method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the step (e.g., an action or task) of forming a second sub-insulating layer IL-b covering a plurality of second conductive layers CNL-b. A material for forming the second sub-insulating layer IL-b may be provided on the plurality of second conductive layers CNL-b to form the second sub-insulating layer IL-b covering the second conductive layers CNL-b. The second sub-insulating layer IL-b may cover both the side surface CNLb-S and the top surface CNLb-U of each of the plurality of second conductive layers CNL-b (e.g., simultaneously covering both the side surface CNLb-S and the top surface CNLb-U of each of the plurality of second conductive layers CNL-b). The material used to form the second sub-insulating layer IL-b may not only be patterned and provided between the second conductive layers CNL-b, but may also be commonly provided on top of each of the plurality of second conductive layers CNL-b and between the second conductive layers CNL-b (e.g., simultaneously provided on top of each of the plurality of second conductive layers CNL-b and between the second conductive layers CNL-b).

[0249] The material forming the second sub-insulating layer IL-b may include a second organic material. The second organic material may differ from the first organic material included in the first sub-insulating layer IL-a. The second organic material may include at least one selected from acrylic resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins. For example, the second organic material may include a polyimide resin.

[0250] The material forming the second sub-insulating layer IL-b may include a second organic material and a solvent. In some embodiments, in addition to the second organic material and solvent, the material forming the second sub-insulating layer IL-b may also include a photosensitizer. Because the material forming the second sub-insulating layer IL-b includes a photosensitizer, an exposure process can be provided in the step (e.g., action or task) of forming contact holes in the second sub-insulating layer IL-b.

[0251] In one or more embodiments, after the step (e.g., action or task) of forming the second sub-insulating layer IL-b, the step (e.g., action or task) of forming a second contact hole exposing at least a portion of the plurality of first connection electrodes CNE1 to the second sub-insulating layer IL-b may be performed. After forming a third photoresist pattern on the second sub-insulating layer IL-b, the third photoresist pattern may be used as a mask to etch the second sub-insulating layer IL-b to form the second contact hole. Subsequently, after the step (e.g., action or task) of forming the second contact hole, the third photoresist pattern may be removed. The first connection electrode CNE1 and the first electrode AE ​​of the light-emitting element (see...) Figure 5 The first connecting electrode CNE1 and the second connecting electrode CNE2 (see...) can be electrically connected to each other through the second contact hole. In one or more embodiments, the first connecting electrode CNE1 and the second connecting electrode CNE2 (see...) Figure 5 They can be electrically connected to each other through the second contact hole.

[0252] In one or more embodiments, the method for manufacturing a display panel may further include the steps of: forming a second connection electrode CNE2 electrically connected to at least a portion of a plurality of first connection electrodes CNE1 (e.g., an action or task); and forming a third insulating layer ISL3 covering the second connection electrode CNE2 (e.g., an action or task). The second connection electrode CNE2 may be formed on the second sub-insulating layer IL-b after forming a second contact hole exposing at least a portion of the plurality of first connection electrodes CNE1 in the second sub-insulating layer IL-b. The process for forming the second connection electrode CNE2 may be referenced. Figures 8A to 8H The process for forming the first connecting electrode CNE1 is substantially the same as described. Therefore, it is possible to form a process including... Figure 5 The diagram shows a plurality of first connecting electrodes CNE11, CNE12 and CNE13, a second insulating layer ISL2 covering the plurality of first connecting electrodes CNE11, CNE12 and CNE13 and disposed on a first insulating layer ISL1, a second connecting electrode CNE2 electrically connected to at least a portion of the plurality of first connecting electrodes CNE11, CNE12 and CNE13, and a third insulating layer ISL3 covering the second connecting electrode CNE2 and disposed on the second insulating layer ISL2, forming a display panel DP.

[0253] Aluminum possesses excellent or suitable etchability and can be used as a connection electrode in display panels. However, to achieve high-resolution display panels, low resistance characteristics of the lines are consistently desired or required. To achieve this characteristic, the line thickness can be increased, or the conductive layers can be interconnected via contact holes in a structure comprising multiple conductive layers containing aluminum and an organic planarization layer disposed between the multiple conductive layers, thereby forming an electrode. However, if the thickness of the aluminum film is increased (e.g., when increasing the thickness of the aluminum film), etching delays can occur above a certain thickness, and if a thick film is sputtered (e.g., when sputtering a thick film), the substrate can be heated by plasma heat, which may cause the substrate to bend, and therefore, there may be limitations to increasing the thickness of the aluminum film. Therefore, a method of electrically connecting multiple conductive layers by introducing an organic planarization layer without increasing the thickness of the aluminum film can be considered. However, in this case, the masking process used to form the contact holes may involve increased manufacturing time and cost, and also increase the occurrence of defects, thereby degrading process efficiency.

[0254] According to one or more embodiments of this disclosure, a first conductive layer and a second conductive layer comprising (e.g., constituting) a first connection electrode can be formed by different processes. Since the first and second conductive layers are formed by separate processes, limitations caused by substrate bending due to plasma heat during sputtering processes can be prevented or reduced. In some embodiments, since both the first and second conductive layers, which both comprise aluminum, form a first connection electrode, a low-resistance line with a large thickness can be achieved. In some embodiments of this disclosure, according to one or more embodiments, the step (e.g., action or task) of forming a first sub-insulating layer disposed between the first conductive layers can be performed between the first conductive layer formation process and the second conductive layer formation process. The first sub-insulating layer may comprise a first organic material such as a siloxane, polyimide, and / or acrylic polymer, and a first inorganic material such as silicon dioxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiON). Therefore, the structure in which the first sub-insulating layer fills the stepped portion can be provided between the first conductive layers to facilitate the film formation process and photolithography process of the second conductive layer, and thus, since the introduction of the organic planar film between the first conductive layer and the second conductive layer becomes unnecessary, the number of masks desired or required by the process can be reduced, and the process can be simplified to reduce process costs.

[0255] In a display panel according to one or more embodiments of the present disclosure, the resistance of the connecting electrodes can be reduced to improve the display characteristics of the display panel and provide a high-resolution display panel.

[0256] In a method for manufacturing a display panel according to one or more embodiments of the present disclosure, the number of mask processes desired or required during the process can be reduced to improve process efficiency and process reliability.

[0257] Terms such as “substantially,” “about,” and “approximately” are used as relative terms, not terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account the limitations and errors associated with the measurement of the quantity, terms such as “substantially,” “about,” and “approximately” may include the value and an acceptable range of deviation as determined by one of ordinary skill in the art. For example, “about” may refer to one or more standard deviations, or ±30%, 20%, 10%, or 5% of the value.

[0258] The numerical ranges disclosed herein include, and are intended to be disclosed, all included subranges with the same numerical precision. For example, the range “1.0 to 10.0” includes all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly list any subranges falling within the ranges expressly listed herein.

[0259] The display panel, display device, manufacturing apparatus, and / or any other related device or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, one or more suitable components of the display panel and / or display device may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, one or more suitable components of the display panel and / or display device may be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Additionally, one or more suitable components of the display panel and / or display device may be a process or thread that runs on one or more processors in one or more computing devices, executes computer program instructions, and interacts with other system components to perform one or more suitable functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art should recognize that the functions of one or more suitable computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of the embodiments of this disclosure.

[0260] In the context of this application and unless otherwise specified, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0261] In view of the entire contents of this disclosure, those skilled in the art will recognize that, unless otherwise stated or implied, multiple suitable features of one or more suitable embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in one or more suitable ways, and the multiple embodiments may be implemented independently or in combination with each other in any suitable way.

[0262] Those skilled in the art will recognize that one or more suitable modifications and variations are possible in this disclosure. Therefore, this disclosure is intended to cover modifications and variations of the invention provided within the scope of the appended claims and their equivalents. Consequently, the actual scope of protection of this disclosure should be determined by the technical scope of the appended claims and their equivalents.

Claims

1. A display panel, comprising: Circuit layer; as well as Light-emitting element, the light-emitting element is on the circuit layer, The circuit layer includes: Semiconductor patterns; A first insulating layer, the first insulating layer including a first contact hole configured to expose a portion of the semiconductor pattern; A plurality of first connection electrodes, the plurality of first connection electrodes being on the first insulating layer and electrically connected to the semiconductor pattern through the first contact hole; and A second insulating layer, configured to cover the plurality of first connection electrodes and on the first insulating layer. Each of the plurality of first connecting electrodes includes: A first conductive layer, the first conductive layer comprising aluminum; and A second conductive layer, which is on top of the first conductive layer and comprises aluminum, is also present. The second insulating layer includes: A first sub-insulating layer, the first sub-insulating layer being located between a pair of adjacent first conductive layers; and A second sub-insulating layer, which is on top of the first sub-insulating layer and configured to cover the second conductive layer, and The first sub-insulating layer includes: A first inorganic material, comprising silicon; and The first organic material.

2. The display panel according to claim 1, wherein, The first organic material comprises at least one of siloxane, polyimide, and acrylic polymer, and The first inorganic material contains at least one of SiO2, Si3N4 and SiON.

3. The display panel according to claim 1, wherein, The second sub-insulating layer contains a second organic material that is different from the first organic material.

4. The display panel according to claim 1, wherein, The first sub-insulating layer is on the side surface of each of the plurality of first conductive layers, and includes a bottom surface aligned with the bottom surface of each of the plurality of first conductive layers. The top surface of the first sub-insulating layer is below the top surface of each of the plurality of first conductive layers.

5. The display panel according to claim 1, wherein, At least a portion of the bottom surface of each of the plurality of second conductive layers is on the first sub-insulating layer, and The planar area of ​​the top surface of the first conductive layer is smaller than the planar area of ​​the bottom surface of the second conductive layer.

6. The display panel according to claim 1, wherein, The light-emitting element includes a pixel electrode electrically connected to the plurality of first connection electrodes.

7. The display panel according to claim 1, wherein, The first conductive layer comprises: a first layer, which is on the first insulating layer and comprises titanium; and a second layer, which is on the first layer and comprises aluminum. The second conductive layer includes: a third layer, which is on the second layer and comprises aluminum; and a fourth layer, which is on the third layer and comprises titanium.

8. The display panel according to claim 7, wherein, The third layer is directly on top of the second layer, and The sum of the thickness of the second layer and the thickness of the third layer is at least 10,000 angstroms and at most 16,000 angstroms.

9. The display panel according to claim 1, wherein, A second contact hole is defined in the second insulating layer, through which the plurality of first connection electrodes are exposed. The circuit layer includes: A second connecting electrode, the second connecting electrode being on the second insulating layer and electrically connected to at least a portion of the plurality of first connecting electrodes through the second contact hole; and A third insulating layer is configured to cover the second connection electrode and is on the second insulating layer.

10. The display panel according to claim 9, wherein, The second connection electrode includes: a third conductive layer comprising aluminum; and a fourth conductive layer on the third conductive layer and comprising aluminum. The third insulating layer includes: A third sub-insulating layer, configured to cover at least a portion of the side surface of the third conductive layer, and comprising a first organic material and a first inorganic material comprising silicon; and A fourth sub-insulating layer, which is on the third sub-insulating layer, configured to cover the fourth conductive layer, and includes a second organic material that is different from the first organic material.

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