Back contact cell, cell assembly and photovoltaic system

Abstract

The invention relates to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system, in the back contact cell, a plurality of first hollow grooves arranged at intervals along a second direction are formed in at least one first doping layer, and silicon wafers are exposed from the first hollow grooves. All the first hollow grooves do not penetrate through the first side surface and the second side surface in the first direction; or all the first hollow grooves penetrate through the first side surface or the second side surface in the first direction; or part of the first hollowed-out grooves do not penetrate through the first side face and the second side face in the first direction, and the other first hollowed-out grooves penetrate through one of the first side face and the second side face in the first direction. Therefore, the parasitic absorption of the first doping layer on the back surface to light can be reduced, the absorption efficiency of the back contact cell to back surface light can be improved, and the double-sided rate of the back contact cell can be improved.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0002] In solar cells, a back-contact cell is a type of cell in which both the emitter and base contact electrodes are placed on the back of the cell. The light-receiving surface of this cell is not obstructed by any metal electrodes, resulting in higher power generation efficiency.

[0003] In related technologies, the doped layer and electrodes of the back contact battery are designed on the back side. The doped layer on the back side has a large parasitic absorption of light from the back side, resulting in a low bifaciality of the back contact battery. Summary of the Invention

[0004] This application provides a back-contact battery, a battery module, and a photovoltaic system.

[0005] This application is implemented as follows: the back contact battery in the embodiments of this application includes:

[0006] A silicon wafer having opposing front and back sides; and

[0007] A plurality of first doped layers and a plurality of second doped layers are stacked on the back side, the plurality of first doped layers and the plurality of second doped layers are alternately arranged along a first direction and all extend along a second direction, the second direction intersecting the first direction;

[0008] The first doped layer has opposing first and second sides in the first direction, and at least one of the first doped layers has a plurality of first hollow grooves arranged at intervals along the second direction, and the silicon wafer is exposed from the first hollow grooves.

[0009] Wherein, none of the first hollowed-out slots penetrate the first side and the second side in the first direction; or

[0010] All of the first hollowed-out slots penetrate the first side or the second side in the first direction; or

[0011] Some of the first hollowed-out grooves do not penetrate the first side and the second side in the first direction, while the remaining first hollowed-out grooves penetrate one of the first side and the second side in the first direction.

[0012] This application also provides a battery assembly, which includes a plurality of back contact batteries as described in the embodiments of this application.

[0013] This application also provides a photovoltaic system, which includes the above-described battery components.

[0014] In the back-contact battery, battery module, and photovoltaic system of this application embodiment, a first doped layer and a second doped layer are alternately arranged in a first direction, and the first doped layer has opposing first and second sides in the first direction. At least one first doped layer has a plurality of first perforated grooves spaced apart along a second direction, through which the silicon wafer is exposed. All first perforated grooves do not penetrate the first and second sides in the first direction; or all first perforated grooves penetrate either the first or second side in the first direction; or some first perforated grooves do not penetrate the first and second sides in the first direction, while the remaining first perforated grooves penetrate one of the first and second sides in the first direction. Thus, by forming first perforated grooves on the first doped layer, the parasitic absorption of light by the first doped layer on the back side can be reduced, improving the absorption efficiency of back-contact battery light from the back side, thereby improving the bifaciality of the back-contact battery. Simultaneously, the fact that the first perforated grooves only penetrate the first or second side, or that none of the first perforated grooves penetrate the first and second sides, ensures that the first doped layer is not broken at the location of the first perforated groove, guaranteeing carrier collection efficiency.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a photovoltaic system module provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this application;

[0019] Figure 4 This is another planar structural schematic diagram of the back contact battery provided in the embodiments of this application;

[0020] Figure 5 This is a schematic diagram of the planar structure of the back contact battery provided in the embodiments of this application;

[0021] Figure 6 yes Figure 3 A cross-sectional view of the back contact battery along line VI-VI;

[0022] Figure 7 yes Figure 3 A cross-sectional view of the back contact battery along line VII-VII;

[0023] Figure 8This is a schematic diagram of the structure of the first doped layer and the first gate electrode of the back contact battery provided in the embodiments of this application;

[0024] Figure 9 This is another structural schematic diagram of the first doped layer and the first gate electrode of the back contact battery provided in the embodiments of this application;

[0025] Figure 10 This is a schematic diagram of the structure of the second doped layer and the second gate electrode of the back contact battery provided in the embodiments of this application;

[0026] Figure 11 This is another structural schematic diagram of the second doped layer and the second gate electrode of the back contact battery provided in the embodiments of this application;

[0027] Figure 12 This is a schematic diagram of the structure of the back contact battery provided in the embodiments of this application, which is provided with a first conductive connector and a second conductive connector;

[0028] Figure 13 This is another structural schematic diagram of the back contact battery provided in the embodiments of this application, which is provided with a first conductive connector and a second conductive connector;

[0029] Figure 14 This is another planar structural schematic diagram of the back contact battery provided in the embodiments of this application.

[0030] Explanation of key component symbols:

[0031] Photovoltaic system 1000, battery module 200, back contact cell 100, silicon wafer 10, front side 11, back side 12, first doped layer 20, first side 201, second side 202, first hollow groove 21, first main body segment 22, first connecting segment 23, second doped layer 30, third side 301, fourth side 302, second hollow groove 31, second main body segment 32, second connecting segment 33, back passivation layer 40, first grid line electrode 50, first electrode segment 51, second electrode segment 52, third electrode segment 53, second grid line electrode 60, fourth electrode segment 61, fifth electrode segment 62, sixth electrode segment 63, first conductive connector 70, second conductive connector 80. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0033] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0037] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] Please see Figures 1-2 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment, and the battery module 200 in this application embodiment may include a plurality of back contact batteries 100 in this application embodiment.

[0039] In embodiments of this application, multiple back-contact batteries 100 in the battery assembly 200 can be connected in series to form multiple battery strings. These battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual battery cells can be achieved by welding conductive connectors, or the connection between battery strings can be achieved by busbars. In some embodiments, the battery strings can form a battery cell array, and then be packaged together using a front panel, a front adhesive film, a rear adhesive film, and a back panel to form the battery assembly 200.

[0040] Please see Figures 3-6 The back contact battery 100 in this application embodiment may include a silicon wafer 10, a plurality of first doped layers 20 and a plurality of second doped layers 30.

[0041] The silicon wafer 10 has a front side 11 and a back side 12. A first doped layer 20 and a second doped layer 30 are both stacked on the back side 12. A plurality of first doped layers 20 and second doped layers 30 are arranged alternately along a first direction and all extend along a second direction, which intersects with the first direction.

[0042] The first doped layer 20 has a first side 201 and a second side 202 opposite to each other in a first direction. Among the plurality of first doped layers 20, at least one first doped layer 20 has a plurality of first hollow grooves 21 arranged at intervals along a second direction, and the silicon wafer 10 is exposed from the first hollow grooves 21.

[0043] Among them, such as Figure 3 As shown, none of the first hollowed-out slots 21 penetrate the first side surface 201 and the second side surface 202 in the first direction; or as... Figure 4As shown, all the first hollowed-out slots 21 penetrate the first side surface 201 or the second side surface 202 in the first direction; or as shown in the figure. Figure 5 As shown, some of the first hollowed-out grooves 21 do not penetrate the first side 201 and the second side 202 in the first direction, while the remaining first hollowed-out grooves 21 penetrate one of the first side 201 and the second side 202 in the first direction.

[0044] Specifically, such as Figures 3-5 As shown, the first doped layer 20 and the second doped layer 30 can be arranged alternately along the longitudinal direction of the silicon wafer 10, and the first perforated grooves 21 on the same first doped layer 20 are arranged at intervals along the transverse direction. That is, the first direction can be the longitudinal direction of the back contact cell 100, and the second direction can be the transverse direction of the back contact cell 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon wafer 10, and there is no specific limitation here.

[0045] Please see Figures 3-6 In some embodiments, the back contact battery 100 may further include a back passivation layer 40, a first gate electrode 50, and a second gate electrode 60. The back passivation layer 40 at least covers the first doped layer 20 and the second doped layer 30.

[0046] Specifically, in this application, the back passivation layer 40 can preferably cover the entire back surface 12 and be located above the first doped layer 20, the second doped layer 30 and the portion not covered by the first doped layer 20 and the second doped layer 30. That is to say, the back passivation layer 40 is also covered on the first hollow groove 21 and other areas not covered by the first doped layer 20 and the second doped layer 30.

[0047] The back passivation layer 40 is the outermost film layer on the back surface 12, and it covers both the first doped layer 20 and the second doped layer 30. In some possible embodiments, the first doped layer 20 and the second doped layer 30 may be arranged alternately along a first direction, and the back passivation layer 40 may also cover the area between them. In general, the back passivation layer 40 may be uniformly covered on the entire back surface 12.

[0048] The first gate electrode 50 is disposed above the first doped layer 20, and the first gate electrode 50 at least partially penetrates the back passivation layer 40 to conduct electricity with the first doped layer 20 (conductive contact). That is, the first gate electrode 50 penetrates the back passivation layer 40 above the first doped layer 20 at all locations or only at some locations to conduct electricity with the first doped layer 20, thereby achieving carrier collection.

[0049] The second gate electrode 60 is disposed above the second doped layer 30, and the second gate electrode 60 at least partially penetrates the back passivation layer 40 to conduct electricity with the second doped layer 30 (conductive contact). That is, the second gate electrode 60 penetrates the back passivation layer 40 above the second doped layer 30 at all locations or only at some locations to conduct electricity with the second doped layer 30, thereby achieving carrier collection.

[0050] like Figure 6 and Figure 7 As shown, in some embodiments, the first gate electrode 50 may form a point contact or line contact with the first doped layer 20 through a local opening in the region directly above the first doped layer 20. The second gate electrode 60 may form a point contact or line contact with the second doped layer 30 through a local opening in the region directly above the second doped layer 30.

[0051] It should be noted that in this article, when a certain membrane layer is stacked or covered on a certain surface or a certain area of ​​a certain membrane layer, it can mean that the membrane layer is directly stacked on the surface or a certain membrane layer, or that other membrane layers are disposed between the membrane layer and the surface or membrane layer. Covering is only used to define the specific setting range of the membrane layer.

[0052] In the back contact battery 100, battery module 200, and photovoltaic system 1000 of this application embodiment, the first doped layer 20 and the second doped layer 30 are alternately arranged in a first direction, and the first doped layer 20 has opposing first side surface 201 and second side surface 202 in the first direction. At least one first doped layer 20 has a plurality of first hollow grooves 21 arranged at intervals along a second direction, and the silicon wafer 10 is exposed from the first hollow grooves 21. All the first hollow grooves 21 do not penetrate the first side surface 201 and the second side surface 202 in the first direction; or all the first hollow grooves 21 penetrate the first side surface 201 or the second side surface 202 in the first direction; or some of the first hollow grooves 21 do not penetrate the first side surface 201 and the second side surface 202 in the first direction, and the remaining first hollow grooves 21 penetrate one of the first side surface 201 and the second side surface 202 in the first direction.

[0053] Thus, by creating the first perforated groove 21 on the first doped layer 20, the parasitic absorption of light by the first doped layer 20 on the back side 12 can be reduced, improving the absorption efficiency of the back contact cell 100 on the back side 12, thereby increasing the bifaciality of the back contact cell 100. Simultaneously, the fact that the first perforated groove 21 only penetrates the first side 201 or the second side 202, or that the first perforated groove 21 does not penetrate either the first side 201 or the second side 202, ensures that the first doped layer 20 will not be broken at the location of the first perforated groove 21, thus guaranteeing the carrier collection efficiency.

[0054] Specifically, in the embodiments of this application, the first doped layer 20 refers to a doped structure with a specific conductivity type, which can be formed by phosphorus diffusion or boron diffusion to form a P-type or N-type semiconductor doped layer, used to form a carrier transport channel. The second doped layer 30 is a doped structure with the opposite conductivity type to the first doped layer 20, forming a complementary carrier collection path. The silicon wafer 10 can be an N-type silicon wafer or a P-type silicon wafer, that is, the doping type of the silicon wafer 10 can be P-type doped or N-type doped, and there is no specific limitation here.

[0055] In some possible embodiments, the first doped layer 20 may be an emitter doped layer, and its doping type may be opposite to that of the silicon wafer 10. The second doped layer 30 may be a base region doped layer, and its doping type may be the same as that of the silicon wafer 10. For example, when the silicon wafer 10 is an N-type silicon wafer, the first doped layer 20 is a P-type doped layer and the second doped layer 30 is an N-type doped layer; when the silicon wafer 10 is a P-type silicon wafer, the first doped layer 20 is an N-type doped layer and the second doped layer 30 is a P-type doped layer.

[0056] The back passivation layer 40 is an insulating dielectric layer covering the back surface 12 of the silicon wafer 10, which may be, for example, a film layer of silicon oxide, silicon nitride, or aluminum oxide. The first gate electrode 50 and the second gate electrode 60 are metal conductive electrodes, both of which may be formed using metal materials such as silver paste, copper, or aluminum through processes such as printing, vapor deposition, or electroplating.

[0057] The silicon wafer 10 being exposed from the first cutout groove 21 means that the first doped layer 20 is not present at the first cutout groove 21, and a portion of the first doped layer 20 has been removed at the first cutout groove 21. Specifically, the first cutout groove 21 can be formed on the first doped layer 20 after a complete first doped layer 20 and second doped layer 30 have been formed on the back side 12 of the silicon wafer 10, by means of laser etching or other methods.

[0058] The shape of the first hollow groove 21 can be a regular or irregular shape such as a rectangle, circle, triangle, or hexagon. No specific restrictions are imposed here. Of course, in order to reduce manufacturing difficulty, it can preferably be a regular shape, such as a rectangle.

[0059] Please see Figures 3-5 In some embodiments, all first doped layers 20 may have a plurality of first hollow grooves 21, and all the first hollow grooves 21 on the back contact battery 100 may be arranged in a rectangular array.

[0060] Thus, arranging all the first hollow grooves 21 in a rectangular array can make the first hollow grooves 21 arranged in several columns. When forming the first hollow grooves 21 by laser etching, the difficulty of the laser etching process can be reduced and the laser etching process can be simplified.

[0061] Please see Figures 3-5 In some embodiments, the first gate electrode 50 overlaps with the first cutout groove 21, that is, the first gate electrode 50 is located above the position of the first cutout groove 21. In this case, the first gate electrode 50 can be basically straight, and at least part of the first cutout groove 21, the first gate electrode 50 does not penetrate the back passivation layer 40.

[0062] Thus, the first doped layer 20 is not present at the first slot 21, and the first gate electrode 50 does not penetrate the back passivation layer 40 at least a portion of the first slot 21. The first gate electrode 50 either does not penetrate the back passivation layer 40 at all in the first slot 21, or only has points penetrating the back passivation layer 40 in a small portion of the first slot 21. This reduces the metallization contact area between the first gate electrode 50 and the first doped layer 20, thereby effectively reducing metallization recombination and improving the efficiency of the back contact cell 100. Simultaneously, it also reduces the contact area between the first gate electrode 50 and the silicon wafer 10 at the first slot 21, reducing recombination.

[0063] Specifically, "the first grid line electrode 50 overlaps with the first hollow groove 21" means that the first grid line electrode 50 and the first hollow groove 21 have an overlapping portion in the thickness direction, the first grid line electrode 50 passes through the first hollow groove 21 along the second direction, and the first hollow groove 21 has the first grid line electrode 50.

[0064] In such an embodiment, it is preferable that the first gate electrode 50 does not penetrate the back passivation layer 40 at all the first hollow slots 21. That is, the first gate electrode 50 only penetrates the back passivation layer 40 and makes conductive contact with the first doped layer 20 in at least a portion of the area on both sides of the first hollow slot 21, and the back passivation layer 40 remains intact and is not penetrated at the first hollow slot 21.

[0065] Of course, it is understandable that in the actual manufacturing process, there may be a phenomenon where the first grid line electrode 50 penetrates the back passivation layer 40 at some of the first hollow grooves 21. In such cases, the first grid line electrode 50 only has a few burn-through points at the first hollow grooves 21.

[0066] In some embodiments, the width (i.e., the length in the first direction) of the portion where the first gate electrode 50 overlaps with the first cutout groove 21 (i.e., the portion of the first gate electrode 50 located on the first cutout groove 21) is smaller than the width (i.e., the length in the first direction) of the remaining portion of the first gate electrode 50.

[0067] In this way, the area of ​​the first gate electrode 50 blocking the first slot 21 can be reduced, thereby further improving the bifaciality.

[0068] Please see Figure 8 and Figure 9 In some embodiments, the first gate electrode 50 may also be a bent gate electrode. In such an embodiment, the first doped layer 20 includes a first main body segment 22 located on both sides of the first hollow groove 21 in the second direction and a first connecting segment 23 corresponding to the first hollow groove 21 in the first direction. The first connecting segment 23 connects two adjacent first main body segments 22.

[0069] The first grid electrode 50 includes a first electrode segment 51, a second electrode segment 52, and a third electrode segment 53. The first electrode segment 51 is disposed on the first main body segment 22 and is electrically connected to the first main body segment 22. The second electrode segment 52 is spaced apart from the first electrode segment 51 in a first direction and is disposed on the first connecting segment 23. Each first electrode segment 51 and each second electrode segment 52 are connected through the third electrode segment 53. One end of the third electrode segment 53 is connected to the first electrode segment 51, and the other end is connected to the second electrode segment 52.

[0070] Thus, the first grid line electrode 50 is configured to include a first electrode segment 51, a second electrode segment 52, and a third electrode segment 53. The first grid line electrode 50 is bent at the location of the first hollow groove 21. The second electrode segment 52 can efficiently collect the charge carriers at the first connection segment 23, shorten the collection path of the charge carriers, and improve efficiency.

[0071] Specifically, such as Figure 8 and Figure 9 As shown, in such an embodiment, the first connecting segment 23 connects two adjacent first main body segments 22. The first connecting segment 23 corresponds to the first hollow groove 21. The width of the first connecting segment 23 (i.e., the length in the first direction) is smaller than the width of the first main body segment 22 (i.e., the length in the first direction). In this way, the carrier collection efficiency can be guaranteed while improving the bifaciality.

[0072] like Figure 8 As shown, in some embodiments, the first electrode segment 51 can be basically centered on the first main body segment 22, the second electrode segment 52 is parallel to the first electrode segment 51 and spaced apart and located on the first connecting segment 23, and the third electrode segment 53 can be perpendicular to the first electrode segment 51 and the second electrode segment 52 and its two ends are respectively connected to the first electrode segment 51 and the second electrode segment 52.

[0073] Please see Figure 8 In some embodiments, where none of the first hollowed-out grooves 21 penetrate the first side surface 201 and the second side surface 202 in the first direction, each side of the first hollowed-out groove 21 has a first connecting section 23 in the first direction, and at least one of the two first connecting sections 23 on each side of the first hollowed-out groove 21 is provided with a second electrode section 52. That is to say, in Figure 8In the embodiment shown, the outer contour of the first hollow groove 21 is a closed shape, and both sides of the first hollow groove 21 are provided with a first connecting segment 23.

[0074] Of course, in this case, the second electrode segment 52 can be provided on only one of the first connection segments 23 to improve the carrier collection efficiency. Alternatively, the second electrode segment 52 can be provided on both first connection segments 23; the specific method is not limited here.

[0075] In this embodiment, the first hollow groove 21 can be centrally disposed on the first doped layer 20, and the two first connecting segments 23 can be symmetrically disposed about the center line of the first doped layer 20. The second electrode segments 52 on the two first connecting segments 23 are also symmetrically disposed, and the widths of the two first connecting segments 23 are the same. In this way, the uniformity of carrier collection can be improved.

[0076] Of course, such as Figure 9 As shown, in some embodiments, when all the first cutouts 21 penetrate through the first side 201 or the second side 202 in the first direction, the number of first connecting segments 23 at the location of the first cutout 21 is a single one.

[0077] In some embodiments, the area of ​​the back surface 12 exposed from the first cutout 21 is a velvet area.

[0078] Thus, the area exposed from the first hollowed-out groove 21 is a velvety area, which can reduce the reflection of light on the back side 12 and further improve the bifaciality of the back contact battery 100.

[0079] In some embodiments, the area of ​​the back surface 12 covered by the first doped layer 20 is a polished area.

[0080] Thus, setting the area covered by the first doped layer 20 as a polished surface can improve the passivation effect at the first doped layer 20, while also reducing the surface defect density.

[0081] In some embodiments, the length of the first perforated groove 21 in the second direction (i.e., the length of the first perforated groove 21) is 50μm-500μm.

[0082] In this way, by optimizing the length range of the first hollow groove 21, the bifaciality can be improved while minimizing the impact on the carrier collection efficiency due to excessively long carrier collection paths.

[0083] Specifically, in such an embodiment, the length of the first hollow groove 21 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm or 50μm-500μm, and is not limited here.

[0084] In some embodiments, the ratio between the width of the first hollow groove 21 in the first direction (i.e., the width of the first hollow groove 21) and the width of the first doped layer 20 in the first direction (i.e., the width of the first doped layer 20) is 50%-95%.

[0085] In this way, it avoids the situation where the width of the first hollow groove 21 is too wide, resulting in the width of the portion of the first doped layer 20 at the first hollow groove 21 (the first connecting segment 23 mentioned above) being too small, which would compromise the carrier collection efficiency. Simultaneously, it ensures that the first connecting segment 23 has sufficient width to accommodate the second electrode segment 52, while also preventing the first hollow groove 21 from being too narrow, which would lead to a poor bifaciality improvement. In other words, by reasonably setting this ratio, the relationship between bifaciality and carrier collection efficiency can be effectively balanced, ensuring carrier collection efficiency while improving bifaciality.

[0086] Specifically, in such embodiments, the ratio can be, for example, any value between 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 50%-95%, without any specific limitation.

[0087] Please see Figure 3 In some embodiments, the first hollow groove 21 does not penetrate the first side surface 201 and the second side surface 202 in the first direction, and the distance between the first hollow groove 21 and the first side surface 201 is 2.5μm-50μm; and / or the distance between the first hollow groove 21 and the second side surface 202 is 2.5μm-50μm.

[0088] In this way, the width of the two first connecting sections 23 on both sides of the first hollow groove 21 is too narrow, which would not guarantee the collection efficiency of charge carriers and would not meet the setting requirements of the second electrode section 52. It can also avoid the effect of poor bifaciality improvement caused by the width of the first hollow groove 21 being too narrow.

[0089] Specifically, in such an embodiment, the distance between the first hollowed-out groove 21 and the first side surface 201 can be, for example, any value between 2.5μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, or 2.5μm-50μm, and is not limited herein. The distance between the first hollowed-out groove 21 and the second side surface 202 can also be, for example, any value between 2.5μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, or 2.5μm-50μm, and is not limited herein.

[0090] Similarly, please refer to Figure 4 In some embodiments, the first cutout groove 21 penetrates one of the first side surface 201 and the second side surface 202 in a first direction. The distance between the first cutout groove 21 and the side surface 201 or the second side surface 202 that is not penetrated is 5μm-100μm.

[0091] In this way, the bifaciality can be improved while ensuring the carrier collection efficiency and meeting the requirements for setting the second electrode segment 52.

[0092] Specifically, in such an embodiment, the distance between the first hollowed-out groove 21 and the side that is not penetrated in the first side surface 201 and the second side surface 202 can be, for example, any value between 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm or 5μm-100μm, and is not limited here.

[0093] In some embodiments, in the first doped layer 20, the spacing between two adjacent first hollowed-out grooves 21 in the second direction is 50μm-1000μm.

[0094] In this way, the distance between two adjacent first hollow slots 21 is too close, which would result in poor carrier collection efficiency. It can also avoid the distance between two adjacent first hollow slots 21 being too large, which would result in too few first hollow slots 21 on a single first doped layer 20, leading to poor bifaciality improvement.

[0095] Specifically, in such an embodiment, the spacing between two adjacent first hollow slots 21 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm or 50μm-1000μm, and is not limited here.

[0096] Please see Figures 3-5 In some embodiments, the second doped layer 30 has opposing third side surface 301 and fourth side surface 302 in the first direction. In a plurality of second doped layers 30, at least one second doped layer 30 has a plurality of second cutout grooves 31 arranged at intervals along the second direction, and the silicon wafer 10 is exposed from the second cutout grooves 31.

[0097] Among them, such as Figure 3As shown, none of the second hollowed-out slots 31 penetrate the third side 301 and the fourth side 302 in the first direction; or as... Figure 4 As shown, all the second hollowed-out slots 31 penetrate the third side 301 or the fourth side 302 in the first direction; or as shown in the figure. Figure 5 As shown, some of the second hollowed-out grooves 31 do not penetrate the third side 301 and the fourth side 302 in the first direction, while the remaining second hollowed-out grooves 31 penetrate one of the third side 301 and the fourth side 302 in the first direction.

[0098] The silicon wafer 10 being exposed from the second cutout 31 means that the second doped layer 30 is not present at the second cutout 31, and a portion of the second doped layer 30 has been removed at the second cutout 31. Specifically, the second cutout 31 can be formed on the second doped layer 30 after a complete second doped layer 30 has been formed on the back side 12 of the silicon wafer 10, by means of laser etching or the like.

[0099] The shape of the second hollow groove 31 can be a regular or irregular shape such as a rectangle, circle, triangle, or hexagon. There is no specific limitation here. Of course, to reduce manufacturing difficulty, it is preferable to be a regular shape, such as a rectangle. The shape of the second hollow groove 31 can be the same as or different from the shape of the first hollow groove 21. There is no specific limitation here.

[0100] Thus, by creating a second perforated groove 31 on the second doped layer 30, the parasitic absorption of light by the second doped layer 30 on the back side 12 can be reduced, improving the absorption efficiency of the back contact cell 100 on the back side 12, thereby increasing the bifaciality of the back contact cell 100. Simultaneously, the fact that the second perforated groove 31 only penetrates the third side 301 or the fourth side 302, or that the second perforated groove 31 does not penetrate either the third side 301 or the fourth side 302, ensures that the second doped layer 30 does not break at the location of the second perforated groove 31, thus guaranteeing the carrier collection efficiency.

[0101] Please see Figures 3-5 In some embodiments, the second gate electrode 60 overlaps with the second cutout groove 31, that is, the second gate electrode 60 is provided above the location of the second cutout groove 31. In this case, the second gate electrode 60 can be substantially straight, and at least part of the second cutout groove 31, the second gate electrode 60 does not penetrate the back passivation layer 40.

[0102] Thus, the second doped layer 30 is not present at the second slot 31, and the second gate electrode 60 does not penetrate the back passivation layer 40 at least a portion of the second slot 31. The second gate electrode 60 either does not penetrate the back passivation layer 40 at all in the second slot 31, or only has points penetrating the back passivation layer 40 in a small portion of the second slot 31. This reduces the metallization contact area between the second gate electrode 60 and the second doped layer 30, thereby effectively reducing metallization recombination and improving the efficiency of the back contact cell 100. Simultaneously, it also reduces the contact area between the second gate electrode 60 and the silicon wafer 10 at the second slot 31, reducing recombination.

[0103] Specifically, "the second gate electrode 60 overlaps with the second hollow groove 31" means that the second gate electrode 60 and the second hollow groove 31 have an overlapping portion in the thickness direction, the second gate electrode 60 passes through the second hollow groove 31 along the second direction, and the second hollow groove 31 has the second gate electrode 60.

[0104] In such an embodiment, it is preferable that the second gate electrode 60 does not penetrate the back passivation layer 40 at all the second cutouts 31. That is, the second gate electrode 60 only penetrates the back passivation layer 40 and the second doped layer 30 in at least a portion of the area on both sides of the second cutouts 31 to achieve conductive contact, and the back passivation layer 40 remains intact and is not penetrated at the second cutouts 31.

[0105] Of course, it is understandable that in the actual manufacturing process, there may be a phenomenon where the second grid line electrode 60 penetrates the back passivation layer 40 at some of the second hollow grooves 31. In such cases, the second grid line electrode 60 only has a few burn-through points at the second hollow grooves 31.

[0106] In some embodiments, the width (i.e., the length in the first direction) of the portion of the second gate electrode 60 that overlaps with the second cutout groove 31 (i.e., the portion of the second gate electrode 60 located on the second cutout groove 31) is smaller than the width (i.e., the length in the first direction) of the remaining portion of the second gate electrode 60.

[0107] In this way, the area of ​​the second gate electrode 60 blocking the second slot 31 can be reduced, thereby further improving the bifaciality.

[0108] Please see Figure 10 and Figure 11 In some embodiments, the second gate electrode 60 may also be a bent gate electrode. In such an embodiment, the second doped layer 30 includes a second main body segment 32 located on both sides of the second hollow groove 31 in the second direction and a second connecting segment 33 corresponding to the second hollow groove 31 in the first direction. The second connecting segment 33 connects two adjacent second main body segments 32.

[0109] The second grid line electrode 60 includes a fourth electrode segment 61, a fifth electrode segment 62, and a sixth electrode segment 63. The fourth electrode segment 61 is disposed on the second main body segment 32 and is electrically connected to the second main body segment 32. The fifth electrode segment 62 is spaced apart from the fourth electrode segment 61 in a first direction and is disposed on the second connecting segment 33. Each fourth electrode segment 61 and each fifth electrode segment 62 are connected through the sixth electrode segment 63. One end of the sixth electrode segment 63 is connected to the fourth electrode segment 61, and the other end is connected to the fifth electrode segment 62.

[0110] Thus, the second grid line electrode 60 is configured to include a fourth electrode segment 61, a fifth electrode segment 62, and a sixth electrode segment 63. The second grid line electrode 60 is bent at the location of the second hollow groove 31. The fifth electrode segment 62 can efficiently collect the charge carriers at the second connecting segment 33, shorten the collection path of the charge carriers, and improve efficiency.

[0111] Specifically, such as Figure 10 and Figure 11 As shown, in such an embodiment, the second connecting segment 33 connects two adjacent second main body segments 32. The second connecting segment 33 corresponds to the second hollowed-out groove 31. The width of the second connecting segment 33 (i.e., the length in the first direction) is smaller than the width of the second main body segment 32 (i.e., the length in the first direction). In this way, the carrier collection efficiency can be guaranteed while improving the bifaciality.

[0112] like Figure 10 and Figure 11 As shown, in some embodiments, the fourth electrode segment 61 can be basically centered on the second main body segment 32, the fifth electrode segment 62 is parallel to the fourth electrode segment 61 and spaced apart and located on the second connecting segment 33, and the sixth electrode segment 63 can be perpendicular to the fourth electrode segment 61 and the fifth electrode segment 62 and its two ends are respectively connected to the fourth electrode segment 61 and the fifth electrode segment 62.

[0113] Please see Figure 10 In some embodiments, where none of the second hollowed-out grooves 31 penetrate the third side surface 301 and the fourth side surface 302 in the first direction, each side of the second hollowed-out groove 31 has a second connecting section 33 in the first direction, and at least one of the two second connecting sections 33 on each side of the second hollowed-out groove 31 is provided with a fifth electrode section 62. That is to say, in Figure 10 In the embodiment shown, the outer contour of the second hollow groove 31 is a closed shape, and each side of the second hollow groove 31 has a second connecting segment 33.

[0114] In this case, the fifth electrode segment 62 can be provided on only one of the second connecting segments 33 to improve the carrier collection efficiency. Alternatively, the fifth electrode segment 62 can be provided on both second connecting segments 33, and the specific method is not limited here.

[0115] In this embodiment, the second hollow groove 31 can be centrally disposed on the second doped layer 30, and the two second connecting segments 33 can be symmetrically disposed about the center line of the second doped layer 30. The fifth electrode segments 62 on the two second connecting segments 33 are also symmetrically disposed, and the widths of the two second connecting segments 33 are the same. In this way, the uniformity of carrier collection can be improved.

[0116] Of course, such as Figure 11 As shown, in some embodiments, when all the second cutouts 31 penetrate through the third side 301 or the fourth side 302 in the first direction, the number of second connecting segments 33 at the location of the second cutouts 31 is a single one.

[0117] In some embodiments, the area of ​​the back surface 12 exposed from the second cutout 31 is a velvety area.

[0118] Thus, the area exposed from the second hollowed-out groove 31 is a velvety area, which can reduce the reflection of light on the back side 12 and further improve the bifaciality of the back contact battery 100.

[0119] In some embodiments, the area of ​​the back surface 12 covered by the second doped layer 30 is a polished area.

[0120] Thus, setting the area covered by the second doped layer 30 as a polished surface can improve the passivation effect at the second doped layer 30, while also reducing the surface defect density.

[0121] In some embodiments, the length of the second hollow groove 31 in the second direction (i.e., the length of the second hollow groove 31) is 50μm-500μm.

[0122] In this way, by optimizing the length range of the second hollow groove 31, the bifaciality can be improved while minimizing the impact on the carrier collection efficiency due to excessively long carrier collection paths.

[0123] Specifically, in such an embodiment, the length of the second hollow groove 31 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm or 50μm-500μm, and is not limited here.

[0124] In some embodiments, the ratio between the width of the second hollow groove 31 in the first direction (i.e., the width of the second hollow groove 31) and the width of the second doped layer 30 in the first direction (i.e., the width of the second doped layer 30) is 50%-95%.

[0125] In this way, the width of the second hollow groove 31 can be avoided from being too wide, which would result in the width of the portion of the second doped layer 30 at the second hollow groove 31 (the second connecting segment 33 mentioned above) being too small, thus failing to guarantee the carrier collection efficiency. At the same time, it can also ensure that the second connecting segment 33 has sufficient width to accommodate the fifth electrode segment 62, and it can also avoid the second hollow groove 31 being too narrow, which would lead to a poor bifaciality improvement effect. In other words, by reasonably setting this ratio, the relationship between bifaciality and carrier collection efficiency can be effectively balanced, ensuring carrier collection efficiency while improving bifaciality.

[0126] Specifically, in such embodiments, the ratio can be, for example, any value between 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 50%-95%, without any specific limitation.

[0127] Please see Figure 3 In some embodiments, the second perforated groove 31 does not penetrate the third side 301 and the fourth side 302 in the first direction, and the distance between the second perforated groove 31 and the third side 301 is 2.5μm-50μm; and / or the distance between the second perforated groove 31 and the fourth side 302 is 2.5μm-50μm.

[0128] In this way, the width of the two second connecting sections 33 on both sides of the second hollow groove 31 is too narrow, which would not guarantee the collection efficiency of charge carriers and would not meet the setting requirements of the fifth electrode section 62. It can also avoid the effect of poor bifaciality improvement caused by the width of the second hollow groove 31 being too narrow.

[0129] Specifically, in such an embodiment, the distance between the second hollowed-out groove 31 and the third side surface 301 can be, for example, any value between 2.5μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, or 2.5μm-50μm, and is not limited herein. The distance between the second hollowed-out groove 31 and the fourth side surface 302 can also be, for example, any value between 2.5μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, or 2.5μm-50μm, and is not limited herein.

[0130] Please see Figure 4 In some embodiments, the second perforated groove 31 penetrates one of the third side surface 301 and the fourth side surface 302 in a first direction. The distance between the second perforated groove 31 and the side surface 301 or the fourth side surface 302 that is not penetrated is 5μm-100μm.

[0131] In this way, the bifaciality can be improved while ensuring the carrier collection efficiency and meeting the requirements for setting the fifth electrode segment 62.

[0132] Specifically, in such an embodiment, the distance between the second hollowed-out groove 31 and the non-penetrated sides of the third side 301 and the fourth side 302 can be, for example, any value between 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm or 5μm-100μm, and is not limited here.

[0133] In some embodiments, in the second doped layer 30, the spacing between two adjacent second hollowed-out grooves 31 in the second direction is 50μm-1000μm.

[0134] In this way, the distance between two adjacent second hollow slots 31 is not too close, which would result in poor carrier collection efficiency. It can also avoid the distance between two adjacent second hollow slots 31 being too large, which would result in too few second hollow slots 31 on a single second doped layer 30, leading to poor bifaciality improvement.

[0135] Specifically, in such an embodiment, the spacing between two adjacent second hollow slots 31 in the second direction can be, for example, any value between 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm, 1000μm or 50μm-1000μm, and is not limited here.

[0136] Please see Figure 3 and Figure 4 In some possible embodiments, the second cutout groove 31 is aligned with the first cutout groove 21 in a first direction (that is, all the second cutout grooves 31 and all the first cutout grooves 21 are arranged in a rectangular array), and the shape and size of the second cutout groove 31 are the same as those of the first cutout groove 21.

[0137] Thus, on the back contact battery 100, the first hollow groove 21 and the second hollow groove 31 are arranged in a rectangular array, which can simplify the process and reduce costs in the laser etching process during manufacturing.

[0138] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the length of the first slot 21 in the second direction is less than the length of the second slot 31 in the second direction.

[0139] Thus, the P-type doped layer has a poor ability to collect carriers. By making the length of the first hollow groove 21 shorter than the length of the second hollow groove 31, the carrier collection path of the first doped layer 20 can be shortened, thereby improving the carrier collection efficiency of the first doped layer 20 and avoiding excessive carrier loss due to the excessive length of the first hollow groove 21.

[0140] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the spacing between two adjacent first slots 21 in the first doped layer 20 is smaller than the spacing between two adjacent second slots 31 in the second doped layer 30.

[0141] Thus, the carrier collection capability of the P-type doped layer is poor. By setting the spacing between the first hollow grooves 21 in the first doped layer 20 to be smaller, the carrier collection efficiency of the first doped layer 20 can be improved.

[0142] In some embodiments, the first doped layer 20 is a P-type doped layer, the second doped layer 30 is an N-type doped layer, and the length of the first slot 21 in the first direction (i.e., the width of the first slot 21) is less than the length of the second slot 31 in the first direction (i.e., the width of the second slot 31).

[0143] Thus, the carrier collection capability of the P-type doped layer is poor. By setting the width of the first hollow groove 21 in the first doped layer 20 to be smaller, the carrier collection efficiency of the first doped layer 20 can be improved.

[0144] In some embodiments, the doping type of the first doped layer 20 is opposite to that of the silicon wafer 10, and the doping type of the second doped layer 30 is the same as that of the silicon wafer 10. The sum of the projected areas of all the first doped layers 20 on the back surface 12 is greater than the sum of the projected areas of all the second doped layers 30 on the back surface 12. That is, the first doped layer 20 serves as the emitter doped layer, the second doped layer 30 serves as the base doped layer, and the total area of ​​the emitter doped layer is greater than the total area of ​​the base doped layer.

[0145] Thus, the emitter doped layer has a larger area, which can improve the efficiency of the back contact cell 100.

[0146] In some embodiments, the first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer. In adjacent first doped layers 20 and second doped layers 30, the distribution density of the first slots 21 in the first doped layer 20 in the second direction is greater than the distribution density of the second slots 31 in the second doped layer 30 in the second direction.

[0147] It should be noted that "distribution density in the second direction" refers to the number of the first hollow groove 21 and the second hollow groove 31 per unit length (in mm) in the second direction. That is to say, within the same length range, the number of the first hollow groove 21 is greater than the number of the second hollow groove 31.

[0148] Thus, by setting the density of the slots on the first doped layer 20 of the P-type doping type to be relatively dense, the carrier collection efficiency of the first doped layer 20 can be improved.

[0149] Specifically, the carrier collection capability of the first doped layer 20 of the P-type doped type is relatively poor. If the first hollow grooves 21 on the first doped layer 20 are arranged too dispersedly, the carrier collection efficiency will be even worse. Therefore, by setting it in this way, the carrier collection efficiency of the first doped layer 20 can be improved.

[0150] Furthermore, in such an embodiment, in the first doped layer 20, the distribution density of the first perforated groove 21 in the second direction can be 3-60 per mm; in the second doped layer 30, the distribution density of the second perforated groove 31 in the second direction can be 2-50 per mm.

[0151] Thus, by controlling the distribution density of the first hollowed-out groove 21 and the second hollowed-out groove 31 within the aforementioned ranges, the collection efficiency of holes and electrons can be guaranteed, avoiding excessively low collection efficiencies that would affect overall efficiency. In other words, this configuration balances the relationship between bifaciality and carrier collection efficiency, improving bifaciality while maintaining the efficiency of the back-contact battery 100.

[0152] Please see Figure 8 In some embodiments, the back surface 12 of the silicon wafer 10 has a plurality of first serial connection areas 101 and a plurality of second serial connection areas 102, the plurality of first serial connection areas 101 and the plurality of second serial connection areas 102 being alternately arranged along a second direction and all extending along a first direction.

[0153] The first series connection area 101 is used to set a first conductive connector 70 that is electrically connected to the first grid line electrode 50 and insulated from the second grid line electrode 60. The second series connection area 102 is used to set a second conductive connector 80 that is electrically connected to the second grid line electrode 60 and insulated from the first grid line electrode 50. The number of first series connection areas 101 is less than the number of second hollow slots 31, and the number of second series connection areas 102 is less than the number of first hollow slots 21.

[0154] Thus, the series connection between the back contact batteries 100 can be achieved through the first conductive connector 70 and the second conductive connector 80.

[0155] Specifically, the first series connection area 101 refers to a specific area on the back side 12 of the silicon wafer 10 used to set the first conductive connector 70 (e.g., main gate and / or solder ribbon). By setting the first conductive connector 70 at the first series connection area 101, conductive contact with the first gate electrode 50 is achieved. The second series connection area 102 refers to a specific area on the back side 12 of the silicon wafer 10 used to set the second conductive connector 80 (e.g., solder ribbon). By setting the second conductive connector 80 at the second series connection area 102, conductive contact with the second gate electrode 60 is achieved, thereby realizing the overall current conduction. The number of first series connection areas 101 is less than the number of second cutout slots 31, and the number of second series connection areas 102 is less than the number of first cutout slots 21, which can avoid the risk of leakage caused by the excessively dense arrangement of the first conductive connector 70 and the second conductive connector. When the back contact battery 100 is a gridless back contact battery, both the first conductive connector 70 and the second conductive connector 90 can be solder strips. When the back contact battery 100 is a grid-supported back contact battery, the first conductive connector 70 and the second conductive connector 80 are the grid and the solder strip, respectively.

[0156] In some possible embodiments, in order to achieve insulation between the first conductive connector 70 and the second gate electrode 60, insulating adhesive can be provided at the position where the second gate electrode 60 overlaps with the first series connection area 101. In order to achieve insulation between the second conductive connector 80 and the first gate electrode 50, insulating adhesive can be provided at the position where the first gate electrode 50 overlaps with the second series connection area 102.

[0157] Of course, in some embodiments, in order to achieve insulation between the first conductive connector 70 and the second gate electrode 60 and insulation between the second conductive connector 80 and the first gate electrode 50, the second gate electrode 60 can be set to be disconnected at the first serial connection area 101 and the first gate electrode 50 can be set to be disconnected at the second serial connection area 102.

[0158] Please see Figure 12 In some embodiments, the first serial connection area 101 and the second serial connection area 102 do not have the first hollow groove 21 and the second hollow groove 31.

[0159] Thus, after the component is formed, the first conductive connector 70 in the first serial connection area 101 and the second conductive connector 80 in the second serial connection area 102 will not block the first cutout groove 21 and the second cutout groove 31, thereby ensuring the double-sidedness of the component.

[0160] Of course, please see Figure 13 In some embodiments, the second slot 31 and the first slot 21 may also be offset from each other in the first direction. The first serial connection area 101 corresponds to one second slot 31, and the second serial connection area 102 corresponds to one first slot 21. The first gate electrode 50 is disconnected at the first slot 21 corresponding to the second serial connection area 102, and the second gate electrode 60 is disconnected at the second slot 31 corresponding to the first serial connection area 101. The first serial connection area 101 corresponds to one second slot 31; that is, each first serial connection area 101 corresponds to one second slot 31, and the positions corresponding to a portion of the second slot 31 are the first serial connection areas 101. The second serial connection area 102 corresponds to one first slot 21; that is, each second serial connection area 102 corresponds to one first slot 21, and the positions corresponding to a portion of the first slot 21 are the second serial connection areas 102.

[0161] The first grid electrode 50 is disconnected at the first slot 21 corresponding to the second serial connection area 102, and the second grid electrode 60 is disconnected at the second slot 31 corresponding to the first serial connection area 101. That is, the first grid electrode 50 is disconnected at part of the first slot 21, and the second grid electrode 60 is disconnected at part of the second slot 31.

[0162] Specifically, the first gate electrode 50 being disconnected means that the continuity of the first gate electrode 50 is interrupted at the first hollowed-out groove 21 corresponding to the second serial connection area 102, so as to prevent the first gate electrode 50 from contacting the second conductive connector 80 in the second serial connection area 102. The second gate electrode 60 being disconnected means that the continuity of the second gate electrode 60 is interrupted at the second hollowed-out groove 31 corresponding to the first serial connection area 101, so as to prevent the second gate electrode 60 from contacting the first conductive connector 70 in the first serial connection area 101.

[0163] In this way, a portion of the first hollowed-out groove 21 can be used as the second serial connection area 102, and a portion of the second hollowed-out groove 31 can be used as the first serial connection area 101. It is only necessary to set the first grid line electrode 50 to be discontinuous in the portion of the first hollowed-out groove 21 and the second grid line electrode 60 to be discontinuous in the portion of the second hollowed-out groove 31 to achieve insulation between the grid line electrode and conductive connectors of different polarities.

[0164] Furthermore, in such an embodiment, the length of the second hollow groove 31 corresponding to the first serial connection area 101 in the second direction may be greater than the length of the other second hollow grooves 31 in the second direction.

[0165] The length of the first hollowed-out groove 21 corresponding to the second serial connection area 102 in the second direction can be greater than the length of the other first hollowed-out grooves 21 in the second direction.

[0166] Thus, making the slots for setting the conductive connectors wider allows them to accommodate wider main grids and / or solder strips without the need for extremely fine main grids and / or solder strips, reducing the difficulty of the manufacturing process.

[0167] In some embodiments, in a single first hollow slot 21, the area covered by the first conductive connector 70 or the second conductive connector 80 accounts for less than 10% of the total area. That is, the ratio between the area of ​​the first hollow slot 21 covered by the first conductive connector 70 or the second conductive connector 80 and the total area of ​​the first hollow slot 21 is less than 10%, for example, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, or other percentages less than 10%, without specific limitations herein; and / or

[0168] In a single second hollow groove 31, the area covered by the first conductive connector 70 or the second conductive connector 80 accounts for less than 10% of the total area. That is, the ratio between the area of ​​the second hollow groove 31 covered by the first conductive connector 70 or the second conductive connector 80 and the area of ​​the entire first hollow groove 21 is less than 10%, such as 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, or other percentages less than 10%, which are not specifically limited here.

[0169] Thus, when the first conductive connector 70 and the second conductive connector 80 are respectively disposed at the first hollow groove 21 and the second hollow groove 31, the proportion of the area of ​​the first hollow groove 21 and the second hollow groove 31 that is blocked is set to be less than 10%. This can avoid the first conductive connector 70 and the second conductive connector 80 blocking too large an area, which would result in a poor double-sided ratio improvement effect.

[0170] Specifically, in such an embodiment, the first hollow groove 21 and the second hollow groove 31 may be aligned in a first direction, and the first conductive connector 70 and the second conductive connector 80 may each have a corresponding first hollow groove 21 and a second hollow groove 31. The second grid electrode 60 may be disconnected at the first hollow groove 21 where the first conductive connector 70 is provided, or an insulating adhesive may be provided at that position. The first grid electrode 50 may be disconnected at the second hollow groove 31 where the second conductive connector 80 is provided, or an insulating adhesive may be provided at that position.

[0171] Of course, in some embodiments, the first hollow groove 21 and the second hollow groove 31 may be staggered in the first direction, and the position of the first conductive connector 70 may only have the second hollow groove 31. The second grid electrode 60 may be disconnected at the second hollow groove 31 corresponding to the first conductive connector 70 or an insulating adhesive may be provided at that position. The position of the second conductive connector 80 may only have the first hollow groove 21, and the first grid electrode 50 may be disconnected at the first hollow groove 21 corresponding to the second conductive connector 80 or an insulating adhesive may be provided at that position.

[0172] In some embodiments, in the same first doped layer 20, the proportion of first hollowed-out grooves 21 that are at least partially blocked by the first conductive connector 70 or the second conductive connector 80 is less than 50%; and / or

[0173] In the same second doped layer 30, the number of second hollow grooves 31 that are at least partially blocked by the first conductive connector 70 or the second conductive connector 80 accounts for less than 50%.

[0174] Thus, by controlling the number of the first cutout groove 21 and the second cutout groove 31 that are blocked to be less than 50%, the double-sided ratio can be effectively improved.

[0175] Specifically, in such embodiments, the percentage of the number of first hollow slots 21 at least partially blocked by the first conductive connector 70 or the second conductive connector 80 may be, for example, 49%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, or other values ​​less than 50%, and no specific limitation is imposed here. Similarly, in such embodiments, the percentage of the number of second hollow slots 31 at least partially blocked by the first conductive connector 70 or the second conductive connector 80 may be, for example, 49%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, or other values ​​less than 50%, and no specific limitation is imposed here.

[0176] In some embodiments, the first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer. Specifically, in adjacent first doped layers 20 and second doped layers 30, the number of first slots 21 at least partially blocked by the first conductive connector 70 and the second conductive connector 80 is greater than the number of second slots 31 at least partially blocked by the first conductive connector 70 and the second conductive connector 80.

[0177] This configuration allows for a higher distribution density of the first hollowed-out groove 21 on the P-type doped layer, which can improve the carrier collection efficiency.

[0178] In some embodiments, the back surface 12 of the silicon wafer 10 may not have a first interconnection area 101 and a second interconnection area 102, but instead, a first wire is correspondingly provided on each first gate electrode 50, and a second wire is correspondingly provided on each second gate electrode 60. That is, in the thickness direction of the back contact cell 100, a first wire is correspondingly provided on the first gate electrode 50 and the first wire is welded to the first gate electrode 50, and a second wire is correspondingly provided on the second gate electrode 60 and the second wire is welded to the second gate electrode 60;

[0179] In this case, in the thickness direction of the back contact battery 100, the first wire and the first hollow groove 21 do not overlap; and / or the second wire and the second hollow groove 31 do not overlap.

[0180] Specifically, in this embodiment, each first doped layer 20 is provided with a first gate electrode 50 and a first conductive wire, and each second doped layer 30 is provided with a second gate electrode 60 and a second conductive wire. That is, the first conductive wire is stacked on the first gate electrode 50, and the second conductive wire is stacked on the second gate electrode 60. In the battery assembly 200, the back contact batteries 100 in the battery string are connected in series through the first conductive wire and the second conductive wire.

[0181] In this way, the back contact battery 100 in the battery string can be directly connected in series through the first and second wires stacked on the grid line electrodes, without the need for additional first conductive connector 70 and second conductive connector 80 as described above, reducing the area of ​​the back side 12 that is blocked and improving the bifaciality. At the same time, the first and second wires will not block the first hollow groove 21 and the second hollow groove 31, further improving the bifaciality.

[0182] Please see Figure 14 In some embodiments, the first doped layer 20 and the second doped layer 30 are alternately arranged along a first direction and both extend along a second direction. The back contact battery 100 also includes a third doped layer 110 and a fourth doped layer 120 alternately arranged along the second direction, and both the third doped layer 110 and the fourth doped layer 120 extend along the first direction. The third doped layer 110 is connected to the first doped layer 20 and disconnected at the second doped layer 30. The third doped layer 110 and the first doped layer 20 have the same doping type. The fourth doped layer 120 is connected to the second doped layer 30 and disconnected at the first doped layer 20. The fourth doped layer 120 and the second doped layer 30 have the same doping type. Figure 14 As shown, the first doped layer 20 and the third doped layer 110 constitute doped layers of the same polarity, while the second doped layer 30 and the fourth doped layer 120 constitute doped layers of the opposite polarity. The first cutout groove 21 can be formed in... Figure 14 The second hollowed-out groove 31 can be formed on the first doped layer 20 shown. Figure 14 On the second doped layer 30 shown.

[0183] Specifically, in some possible embodiments, in Figure 14 Fine gates can be provided on the third doped layer 110 and the fourth doped layer 120, and main gates can be provided on the first doped layer 20 and the second doped layer 30. The main gate on the first doped layer 20 is connected to the fine gate on the third doped layer 110, and the main gate on the second doped layer 30 is connected to the fine gate on the fourth doped layer 120.

[0184] In some possible embodiments, the main gate on the first doped layer 20 may not overlap with the first cutout 21; that is, in the thickness direction, the main gate on the first doped layer 20 does not overlap with the first cutout 21. This avoids the main gate obstructing the first cutout 21.

[0185] In some embodiments, the main gate on the second doped layer 30 may not overlap with the second cutout 31; that is, in the thickness direction, the main gate on the second doped layer 30 does not overlap with the second cutout 31. This avoids the main gate obstructing the second cutout 31.

[0186] In the description of this specification, the use of terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., refers to specific features, structures, materials, or characteristics described in connection with the embodiments or examples, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0187] Furthermore, the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back-contact battery, characterized in that, include: A silicon wafer having opposing front and back sides; and A plurality of first doped layers and a plurality of second doped layers are stacked on the back side, the plurality of first doped layers and the plurality of second doped layers are alternately arranged along a first direction and all extend along a second direction, the second direction intersecting the first direction; The first doped layer has opposing first and second sides in the first direction, and at least one of the first doped layers has a plurality of first hollow grooves arranged at intervals along the second direction, and the silicon wafer is exposed from the first hollow grooves. Wherein, none of the first hollowed-out slots penetrate the first side and the second side in the first direction; or All of the first hollowed-out slots penetrate the first side or the second side in the first direction; or Some of the first hollowed-out grooves do not penetrate the first side and the second side in the first direction, while the remaining first hollowed-out grooves penetrate one of the first side and the second side in the first direction.

2. The back contact battery according to claim 1, characterized in that, The area exposed on the back from the first perforated groove is a velvety surface; and / or The area on the back side covered by the first doped layer is the polished area.

3. The back contact battery according to claim 1, characterized in that, The length of the first hollowed-out groove in the second direction is 50μm-500μm; and / or In the first doped layer, the spacing between two adjacent first hollow slots in the second direction is 50μm-1000μm.

4. The back contact battery according to claim 1, characterized in that, The ratio between the length of the first hollow groove in the first direction and the length of the first doped layer in the first direction is 50%-95%.

5. The back contact battery according to claim 1, characterized in that, The first hollowed-out groove does not penetrate the first side and the second side in the first direction; The distance between the first hollowed-out groove and the first side surface is 2.5μm-50μm; and / or The distance between the first hollowed-out groove and the second side is 2.5μm-50μm.

6. The back contact battery according to claim 1, characterized in that, The first hollowed-out groove penetrates one of the first side surface and the second side surface in the first direction; The distance between the first hollowed-out groove and the side that is not penetrated in the first side and the second side is 5μm-100μm.

7. The back contact battery according to claim 1, characterized in that, At least a back passivation layer is stacked over the first doped layer and the second doped layer; A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer. The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.

8. The back contact battery according to claim 7, characterized in that, The first gate electrode overlaps with the first hollowed-out groove; Wherein, at least in a portion of the first cutout, the first gate electrode does not penetrate the back passivation layer; and / or The width of the portion where the first gate electrode overlaps with the first hollow groove is smaller than the width of the remaining portion.

9. The back contact battery according to claim 7, characterized in that, The first doped layer includes a first main body segment located on both sides of the first hollow groove in the second direction and a first connecting segment corresponding to the first hollow groove in the first direction, wherein the first connecting segment connects two adjacent first main body segments; The first grid line electrode includes a first electrode segment, a second electrode segment, and a third electrode segment. The first electrode segment is disposed on the first main body segment and is electrically connected to the first main body segment. The second electrode segment is spaced apart from the first electrode segment in the first direction and is disposed on the first connecting segment. Each first electrode segment and each second electrode segment are connected through the third electrode segment. One end of the third electrode segment is connected to the first electrode segment, and the other end is connected to the second electrode segment.

10. The back contact battery according to claim 9, characterized in that, All of the first hollowed-out grooves do not penetrate the first side and the second side in the first direction. In the first direction, both sides of the first hollowed-out groove have the first connecting section, and at least one of the two first connecting sections on both sides of the first hollowed-out groove is provided with the second electrode section.

11. The back contact battery according to claim 1, characterized in that, All of the first doped layers are provided with a plurality of first hollow grooves, and all the first hollow grooves on the back contact battery are arranged in a rectangular array.

12. The back contact battery according to claim 1, characterized in that, At least one of the second doped layers has a plurality of second cutouts spaced apart along the second direction, the silicon wafer is exposed from the second cutouts, and the second doped layer has opposing third and fourth sides in the first direction. Wherein, none of the second hollowed-out slots penetrate the third side and the fourth side in the first direction; or All the second hollowed-out slots penetrate the third side or the fourth side in the first direction; or Some of the second hollowed-out grooves do not penetrate the third side and the fourth side in the first direction, while the remaining second hollowed-out grooves penetrate one of the third side and the fourth side in the first direction.

13. The back contact battery according to claim 12, characterized in that, The area exposed on the back from the second perforation is a velvety surface; and / or The area on the back side covered by the second doped layer is the polished area.

14. The back contact battery according to claim 12, characterized in that, The length of the second hollowed-out groove in the first direction is 50μm-500μm; and / or In the second doped layer, the spacing between two adjacent second hollow slots in the second direction is 50μm-1000μm.

15. The back contact battery according to claim 12, characterized in that, The ratio between the width of the second hollow groove in the first direction and the width of the second doped layer in the first direction is 50%-95%.

16. The back contact battery according to claim 12, characterized in that, The second hollowed-out groove does not penetrate the third and fourth side surfaces in the first direction; The distance between the second hollowed-out groove and the third side surface is 2.5μm-50μm; and / or The distance between the second hollowed-out groove and the fourth side surface is 2.5μm-50μm.

17. The back contact battery according to claim 12, characterized in that, The second hollowed-out groove penetrates one of the third side and the fourth side in the first direction; The distance between the second hollowed-out groove and the side that is not penetrated among the third and fourth side surfaces is 5μm-100μm.

18. The back contact battery according to claim 12, characterized in that, At least a back passivation layer is stacked over the first doped layer and the second doped layer; A first gate electrode is disposed above the first doped layer, and the first gate electrode at least partially penetrates the back passivation layer and is electrically connected to the first doped layer. The second gate electrode is disposed above the second doped layer and is conductively connected to the second doped layer by at least partially penetrating the back passivation layer.

19. The back contact battery according to claim 18, characterized in that, The second gate electrode overlaps with the second hollowed-out groove; Wherein, at least in a portion of the second cutout, the second gate electrode does not penetrate the back passivation layer; and / or The width of the portion where the second gate electrode overlaps with the second hollow groove is smaller than the width of the remaining portion.

20. The back contact battery according to claim 18, characterized in that, The second doped layer includes a second main body segment located on both sides of the second hollow groove in the second direction and a second connecting segment corresponding to the second hollow groove in the first direction, wherein the second connecting segment connects two adjacent second main body segments; The second grid line electrode includes a fourth electrode segment, a fifth electrode segment, and a sixth electrode segment. The fourth electrode segment is disposed on the second main body segment and is electrically connected to the second main body segment. The fifth electrode segment is spaced apart from the fourth electrode segment in the first direction and is disposed on the second connecting segment. Each fourth electrode segment and each fifth electrode segment are connected through the sixth electrode segment. One end of the sixth electrode segment is connected to the fourth electrode segment, and the other end is connected to the fifth electrode segment.

21. The back contact battery according to claim 20, characterized in that, All the second hollow slots do not penetrate the third side and the fourth side in the first direction. In the first direction, both sides of the second hollow slot have the second connecting section, and at least one of the two second connecting sections on both sides of the second hollow slot is provided with the fifth electrode section.

22. The back contact battery according to claim 12, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; Wherein, the length of the first hollow groove in the second direction is less than the length of the second hollow groove in the second direction; and / or The spacing between two adjacent first hollow slots in the first doped layer is smaller than the spacing between two adjacent second hollow slots in the second doped layer; and / or The length of the first hollow groove in the first direction is less than the length of the second hollow groove in the first direction.

23. The back contact battery according to claim 12, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; In the adjacent first doped layer and second doped layer, the distribution density of the first hollow groove on the first doped layer in the second direction is greater than the distribution density of the second hollow groove on the second doped layer in the second direction.

24. The back contact battery according to claim 12, characterized in that, The second hollowed-out groove is aligned with the first hollowed-out groove in the first direction, and the shape of the second hollowed-out groove is the same as that of the first hollowed-out groove.

25. The back contact battery according to claim 18, characterized in that, The back side of the silicon wafer has a plurality of first serial connection areas and a plurality of second serial connection areas. The plurality of first serial connection areas and the plurality of second serial connection areas are alternately arranged along the second direction and all extend along the first direction. The first serial connection areas are used to provide a first conductive connector electrically connected to the first gate electrode and insulated from the second gate electrode. The second serial connection areas are used to provide a second conductive connector electrically connected to the second gate electrode and insulated from the first gate electrode. The number of first serial connection areas is less than the number of second cutouts, and the number of second serial connection areas is less than the number of first cutouts.

26. The back contact battery according to claim 25, characterized in that, The first serial connection area and the second serial connection area do not have the first hollow slot and the second hollow slot.

27. The back contact battery according to claim 25, characterized in that, The second hollowed-out groove and the first hollowed-out groove are offset from each other in the first direction; The first serial connection area corresponds to one second hollow slot, the second serial connection area corresponds to one first hollow slot, the first gate electrode is disconnected at the first hollow slot corresponding to the second serial connection area, and the second gate electrode is disconnected at the second hollow slot corresponding to the first serial connection area.

28. The back contact battery according to claim 27, characterized in that, The length of the second hollowed-out groove corresponding to the first serial connection area in the second direction is greater than the length of the other second hollowed-out grooves in the second direction; The length of the first hollowed-out groove corresponding to the second serial connection area in the second direction is greater than the length of the other first hollowed-out grooves in the second direction.

29. The back contact battery according to claim 25, characterized in that, In a single first hollow slot, the area covered by the first conductive connector or the second conductive connector accounts for less than 10% of the total area; and / or In a single second hollowed-out groove, the area covered by the first conductive connector or the second conductive connector accounts for less than 10% of the total area.

30. The back contact battery according to claim 25, characterized in that, In the same first doped layer, the proportion of the first hollowed-out grooves that are at least partially blocked by the first conductive connector or the second conductive connector is less than 50%; and / or In the same second doped layer, the proportion of the second hollowed-out grooves that are at least partially blocked by the first conductive connector or the second conductive connector is less than 50%.

31. The back contact battery according to claim 25, characterized in that, The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; In the adjacent first doped layer and second doped layer, the number of first hollow slots that are at least partially blocked by the first conductive connector and the second conductive connector is greater than the number of second hollow slots that are at least partially blocked by the first conductive connector and the second conductive connector.

32. The back contact battery according to claim 18, characterized in that, In the thickness direction of the back contact battery, a first wire is correspondingly provided on the first grid line electrode, and the first wire is welded to the first grid line electrode; a second wire is correspondingly provided on the second grid line electrode, and the second wire is welded to the second grid line electrode. Specifically, in the thickness direction of the back contact battery, the first wire and the first hollow groove do not overlap; and / or the second wire and the second hollow groove do not overlap.

33. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1-32.

34. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 33.

Images