Photonic logic gate devices and logic circuits based on lateral heterojunctions

Abstract

The application provides a kind of photoelectric logic gate device and logic circuit based on lateral heterojunction, belongs to photoelectric technology field.The photoelectric logic gate device includes substrate, functional layer, first electrode and second electrode.Functional layer is arranged on substrate, functional layer includes first material area and second material area, first material area includes SnS, second material area includes SnS2, and there is lateral heterojunction between first material area and second material area;First electrode is arranged on first material area;Second electrode is arranged on second material area.Photoelectric logic gate device generates photoelectric current with opposite polarity under the irradiation of first excitation light and second excitation light respectively, the wavelength of first excitation light is 280nm~564nm, and the wavelength of second excitation light is 564nm~1033nm.The photoelectric logic gate device of the application successfully constructs all-optical logic gate and hybrid photoelectric logic gate on a single device, thereby effectively reducing the complexity of photonic integrated circuit, and avoiding the transmission delay and crosstalk noise of multi-device interconnection.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic technology, and more specifically to an optoelectronic logic gate device and logic circuit based on a lateral heterojunction. Background Technology

[0002] Optoelectronic logic gates (OELGs) utilize the synergistic effect of photoelectric signals for data transmission. They possess the unique ability to perform high-precision calculations at a rapidly evolving pace, overcoming the limitations of traditional electronic logic gates in operation and decision-making. They offer greater flexibility and reliability when faced with complex data and multitasking. OELGs provide a promising path for developing next-generation electronic devices and are a key component in the development of next-generation logic devices.

[0003] However, current optoelectronic logic gates are limited by the characteristic that charge carriers can only be transmitted in one direction in a single device. This unipolar transmission means that the device can only implement simple and fixed logic functions (such as logical NOT and OR). Complex logic functions (such as XOR and XNOR) and compound logic operations require interconnected logic gates to form a complex network, which greatly increases the complexity of the system. As a result, the system is prone to transmission delay, noise crosstalk and increased power consumption due to the interconnection of multiple devices.

[0004] Therefore, it is necessary to design an optoelectronic logic gate device and logic circuit based on a lateral heterojunction to improve the above problems. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a photoelectric logic gate device and logic circuit based on a lateral heterojunction to improve the technical problem that traditional photoelectric logic gates are limited by the unidirectional transmission of charge carriers and cannot independently realize complex logic functions.

[0006] To achieve the above and other related objectives, the present invention provides an optoelectronic logic gate device based on a lateral heterojunction, the optoelectronic logic gate device comprising a substrate, a functional layer, a first electrode, and a second electrode.

[0007] The functional layer is disposed on the substrate and includes a first material region and a second material region. The first material region includes SnS, and the second material region includes SnS2. A lateral heterojunction exists between the first material region and the second material region. A first electrode is disposed on the first material region, and a second electrode is disposed on the second material region. The optoelectronic logic gate device generates photocurrents of opposite polarities under the illumination of a first excitation light and a second excitation light, respectively. The wavelength of the first excitation light is 280nm~564nm, and the wavelength of the second excitation light is 564nm~1033nm.

[0008] In one example of the present invention, the optoelectronic logic gate device generates a negative photocurrent under the irradiation of the first excitation light, and the optoelectronic logic gate device generates a positive photocurrent under the irradiation of the second excitation light.

[0009] In one example of the present invention, when the optoelectronic logic gate device is irradiated by the first excitation light or without excitation light, the lateral heterojunction is a type II band alignment structure; when the optoelectronic logic gate device is irradiated by the second excitation light, the lateral heterojunction is a type Z band alignment structure.

[0010] In one example of the present invention, when a positive bias voltage is applied, the saturated photocurrent value generated by the opto-logic gate device under the first excitation light is greater than the saturated photocurrent value generated under the second excitation light; and under the first excitation light, the negative photocurrent value generated by the opto-logic gate device when a positive bias voltage is applied is greater than the negative photocurrent value generated when no bias voltage is applied.

[0011] In one example of the present invention, when no bias voltage is applied, the photocurrent generated by the optoelectronic logic gate device under the irradiation of one of the first excitation light and the second excitation light can be quenched under the irradiation of the other of the first excitation light and the second excitation light.

[0012] In one example of the present invention, the optoelectronic logic gate device is used to implement logic operations, the logic operations including at least one of "OR", "XOR", "NOT", "AND", "NOR", "XNOR" and "NAND".

[0013] In one example of the present invention, when the optoelectronic logic gate device performs an OR operation, an XOR operation, or a NOT operation, the first excitation light is used as the first logic input signal, the second excitation light is used as the second logic input signal, and the photocurrent value is used as the logic output signal.

[0014] In one example of the present invention, when the optoelectronic logic gate device implements AND, NOR, XNOR, or NAND operations, the first excitation light and / or the second excitation light are used as the first logic input signal, the bias voltage applied to the optoelectronic logic gate device is used as the second logic input signal, and the photocurrent value is used as the logic output signal.

[0015] In one example of the present invention, the logical operation includes a combinational logical operation of a first logical operation and a second logical operation. The first logical operation includes an "OR" operation or an "XOR" operation, and the second logical operation includes an "AND" operation, an "OR NOT" operation, an "XNOR" operation, and an "AND NOT" operation.

[0016] In one example of the present invention, when the optoelectronic logic gate device implements the combinational logic operation, the first excitation light is used as the first logic input signal, the second excitation light is used as the second logic input signal, the bias voltage applied to the optoelectronic logic gate device is used as the third logic input signal, and the photocurrent value is used as the logic output signal.

[0017] The present invention also provides a logic circuit comprising the optoelectronic logic gate devices described in any of the above examples.

[0018] This invention provides an optoelectronic logic gate device. Due to the suitable valence conduction band offset of the type II heterojunction formed by the bonding of two-dimensional materials, this device can undergo varying degrees of band bending and shifting under excitation light of different wavelengths, thereby generating inversion symmetry in the carrier group. This inversion can drive carrier transport in the optoelectronic logic gate device to generate a bipolar photoelectric response. Based on this bipolar photoelectric response, the optoelectronic logic gate device can control the logic relationship at the output terminal by combining optical / electrical input signals, thus replacing the traditional multi-device series-parallel connection scheme and realizing seven basic logic functions and multi-layer composite logic operations on a single device.

[0019] Compared to traditional optoelectronic logic gates that require multiple gates to be connected in series and parallel to achieve complex logic functions, the optoelectronic logic gate device of this invention successfully constructs all-optical logic gates and hybrid optoelectronic logic gates on a single device, thereby effectively reducing the complexity of photonic integrated circuits and avoiding transmission delay and crosstalk noise from multi-device interconnection. At the same time, its wavelength-dependent synaptic plasticity simulation capability (such as long-term enhancement / suppression) provides a hardware foundation for neuromorphic optical computing. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of an optoelectronic logic gate device in one embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram illustrating the bipolar photoresponse mechanism of the optoelectronic logic gate device of the present invention under photoinduced band bending; wherein... Figure 2 (a) shows a schematic diagram of the band structure of SnS and SnS2 materials. Figure 2 (b) shows a schematic diagram of the band structure of the SnS and SnS2 material contact heterojunction in an optoelectronic logic gate device after the valence conduction band is shifted. Figure 2 (c) shows a schematic diagram of the band structure and carrier migration of the optoelectronic logic gate device under 532nm excitation light; Figure 2 (d) shows a schematic diagram of the band structure and carrier migration of the optoelectronic logic gate device under 808nm excitation light.

[0023] Figure 3 This is a photocurrent-time relationship diagram of the optoelectronic logic gate device under light illumination with wavelengths of 532nm and 808nm, respectively, in one embodiment of the present invention;

[0024] Figure 4 This is a logic test diagram and truth table for implementing "OR", "XOR", and "NOT" operations using optoelectronic logic gate devices in one embodiment of the present invention. Figure 4 (a) is a logic test diagram of an optoelectronic logic gate device implementing "OR", "XOR" and "NOT" operations in an embodiment of the present invention; Figure 4 (b) is a truth table for implementing "OR", "XOR", and "NOT" operations using optoelectronic logic gate devices in one embodiment of the present invention;

[0025] Figure 5 This is a logic test diagram and truth table for implementing an AND operation using optoelectronic logic gate devices in one embodiment of the present invention;

[0026] Figure 6 This is a logic test diagram and truth table for implementing "AND-OR" operations using optoelectronic logic gate devices in one embodiment of the present invention;

[0027] Figure 7 This is a logic test diagram and truth table for implementing the "XNOR" operation using optoelectronic logic gate devices in one embodiment of the present invention;

[0028] Figure 8 This is a logic test diagram and truth table for implementing NAND operations using optoelectronic logic gate devices in one embodiment of the present invention;

[0029] Figure 9 This is a logic test diagram and truth table for implementing multi-layer composite logic operation Y=(A+B)·C using optoelectronic logic gate devices in one embodiment of the present invention.

[0030] Component designation explanation

[0031] 100, Substrate; 200, Functional layer; 210, First material region; 220, Second material region; 230, Lateral heterojunction; 300, First electrode; 400, Second electrode. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0035] On the one hand, please see Figures 1 to 3 This application provides a photoelectric logic gate device based on a lateral heterojunction. This device, based on the matching relationship between the band structure parameters of SnS and SnS2 heterojunction materials and incident light of different wavelengths, breaks the fixed carrier orientation of traditional type II heterojunctions. This allows for the induction of carrier path reversal through photoinduced band bending, generating a bipolar photoresponse. Utilizing its bipolar photoresponse characteristics, the photoelectric logic gate device can control the logic output relationship of the device by combining incident excitation light and an external bias electric field, thus replacing the traditional multi-device series-parallel scheme and implementing seven basic logic functions and multi-layer composite logic operations on a single device.

[0036] Please see Figure 1The aforementioned optoelectronic logic gate device includes a substrate 100, a functional layer 200, a first electrode 300, and a second electrode 400. The substrate 100 can be made of a semiconductor material or an insulating material. The semiconductor material can be, for example, single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (SiGe), or silicon carbide (SiC). The insulating material can be an organic insulator, an inorganic insulator, or a combination thereof; for example, the insulating material can be silicon oxide (SiO2). The functional layer 200 is disposed on the substrate 100 and includes a first material region 210 and a second material region 220. The first material region 210 includes SnS material, and the second material region 220 includes SnS2 material. A lateral heterojunction 230 of SnS and SnS2 materials is formed between the first material region 210 and the second material region 220. This lateral heterojunction 230 accumulates electrons at the SnS material interface and holes at the SnS2 material interface. The built-in electric field provided by the lateral heterojunction 230 points from the second material region 220 to the first material region 210. The first electrode 300 is disposed on the first material region 210, and the second electrode 400 is disposed on the second material region 220. The first electrode 300 and the second electrode 400 are used to apply a bias voltage to the optoelectronic logic gate device and to extract the photocurrent generated by the functional layer 200 in response to illumination. It should be noted that the arrangement of the first electrode 300 and the second electrode 400 is not limited, and the first electrode 300 and the second electrode 400 can be in various forms such as interdigitated electrodes, counter electrodes, or external lead electrodes.

[0037] Please see Figures 1 to 3 The optoelectronic logic gate device generates photocurrents of opposite polarities under irradiation by a first excitation light and a second excitation light, thus exhibiting a bipolar photoresponse. The wavelength of the first excitation light is any value within the range of 280nm to 564nm, and the single photon energy of the first excitation light is greater than the bandgap of the SnS2 material (≈2.2eV). Under the irradiation of the first excitation light, the optoelectronic logic gate device generates a negative photocurrent. The wavelength of the second excitation light is any value within the range of 564nm to 1033nm, and the single photon energy of the second excitation light is greater than the bandgap of the SnS material (≈1.2eV) and less than the bandgap of the SnS2 material (≈2.2eV). Under the irradiation of the second excitation light, the optoelectronic logic gate device generates a positive photocurrent.

[0038] like Figure 2 (a) and Figure 2 As shown in (b), in functional layer 200, the transverse heterojunction 230 (i.e., SnS / SnS2 heterojunction) between the first material region 210 and the second material region 220 has a special type II heterojunction band arrangement. When SnS and SnS2 materials form a heterojunction at contact, a large valence conduction band shift will occur. E v ≈1.1 eV, E c The valence conduction band shift of the SnS / SnS2 heterojunction is larger than that of the traditional type II heterojunction (≈0.7 eV), while the valence conduction band shift of the GeSe / MoS2 heterojunction is only... E c ≈0.1eV E v ≈0.2eV. Optoelectronic logic gate devices are based on special type II heterojunctions, which can easily control their carrier transport paths through external excitation, thereby inducing them to produce bipolar responses.

[0039] like Figure 2 As shown in (c), since the single-photon energy of the first excitation light is greater than the band gap of both SnS and SnS2 materials, both the first material region 210 and the second material region 220 in the functional layer 200 can generate photogenerated carriers under the irradiation of the first excitation light. The first material region 210 and the second material region 220 will not experience a large change in carrier concentration. The energy barrier of the band arrangement at the transverse heterojunction 230 will not change, and the energy band structure of the traditional type II heterojunction will still be maintained. This ensures that the carrier transport path of the functional layer 200 is the same as that of the traditional type II heterojunction, that is, electrons flow from the high conduction band of SnS material to the low conduction band of SnS2 material, and holes flow from the low valence band of SnS2 material to the high valence band of SnS material. At this time, the optoelectronic logic gate device generates a negative photocurrent.

[0040] like Figure 2 As shown in (d), since the single photon energy of the second excitation light is greater than the band gap of SnS material and less than the band gap of SnS2 material, under the irradiation of the second excitation light, the SnS2 material in the second material region 220 is in the absorption cutoff region and cannot generate photogenerated carriers, while the SnS material in the first material region 210 can absorb photon energy to generate interband transitions. This causes the band structure at the lateral heterojunction 230 to bend and shift, causing the valence band of the SnS material to approach the conduction band of the SnS2 material, forming a "Z"-shaped electron-hole recombination path at the lateral heterojunction 230. This causes the band structure of the lateral heterojunction 230 to change from a traditional type II heterojunction to a Z-type heterojunction, which in turn causes the carrier transport path of the functional layer 200 to be opposite to that of a traditional type II heterojunction. That is, electrons jump from the conduction band of SnS2 material to the valence band of SnS material, and then from the valence band of SnS material to the conduction band. At this time, the optoelectronic logic gate device generates a forward photocurrent.

[0041] like Figure 3As shown, in one example, the optoelectronic logic gate device generates photocurrents of opposite polarities under laser irradiation with wavelengths of 532nm and 808nm, respectively. The optoelectronic logic gate device generates a negative photocurrent (-15.7nA) under laser irradiation with a wavelength of 532nm, and generates a positive photocurrent (33.33nA) under laser irradiation with the same power at a wavelength of 808nm, and the ratio of the positive photocurrent to the negative photocurrent is approximately 2:1.

[0042] Please see Figures 4 to 9 This optoelectronic logic gate device, based on its bipolar photoresponse characteristics, uses incident excitation light or incident excitation light and an external bias electric field as input signals and the photocurrent generated by the optoelectronic logic gate device as the output signal to perform logic operations. The logic operations that the optoelectronic logic gate device can perform include seven basic logic operations and two-level composite logic operations.

[0043] An external bias electric field can be applied to the optoelectronic logic gate device through the first electrode 300 and the second electrode 400. By applying a positive voltage to the first electrode 300 and a negative voltage to the second electrode 400, a positive bias voltage can be applied to the optoelectronic logic gate device; by applying a negative voltage to the first electrode 300 and a positive voltage to the second electrode 400, a negative bias voltage can be applied to the optoelectronic logic gate device.

[0044] like Figure 4 (a) and Figure 4 As shown in (b), in some embodiments, the logic operations that the optoelectronic logic gate device can implement include OR, XOR, and NOT operations. The optoelectronic logic gate device uses a first excitation light as a first logic input signal, a second excitation light as a second logic input signal, and the generated photocurrent value as a logic output signal, thereby implementing OR, XOR, and NOT operations. Specifically, the first logic input signal (IN1) is defined as 1 when the first excitation light illuminates the optoelectronic logic gate device, and as 0 when the first excitation light does not illuminate the optoelectronic logic gate device; the second logic input signal (IN2) is defined as 1 when the second excitation light illuminates the optoelectronic logic gate device, and as 0 when the second excitation light does not illuminate the optoelectronic logic gate device; the logic output signal (OUT) is defined as 1 when the optoelectronic logic gate device generates a photocurrent value, which can be a positive or negative photocurrent, and as 0 when the optoelectronic logic gate device generates a low photocurrent value. Among them, the high photocurrent value is much higher than the low photocurrent value, and the high current value is several to tens of times higher than the low photocurrent value.

[0045] like Figure 4 (a) and Figure 4As shown in (b), under the logic input and output rules of the above embodiment, the optoelectronic logic gate device can perform OR, XOR, and NOT operations when a 0V or negative bias voltage (e.g., -0.1V) is applied. It should be noted that when the optoelectronic logic gate device is simultaneously irradiated by the first excitation light and the second excitation light, i.e., when both the first and second logic input signals are 1, the optoelectronic logic gate device generates both positive and negative carrier flows in response to the illumination. The flow of positive and negative carriers cancels each other out. By controlling the irradiation intensity of the first and second excitation lights, the optoelectronic logic gate device can generate positive and negative carriers that cancel each other out, thus not generating photocurrent (logic output signal is 0). This allows the optoelectronic logic gate device to satisfy the "exclusive OR" (XOR) and "not" (NOT) operation logic. At the same time, it can also cause the optoelectronic logic gate device to generate positive and negative carriers that partially cancel each other out, thus exhibiting positive or negative photocurrent output (logic output signal is 1). This allows the optoelectronic logic gate device to satisfy the "OR" (OR) operation logic.

[0046] like Figures 5 to 8 As shown, in some embodiments, the optoelectronic logic gate devices can perform logic operations including AND, NOR, XNOR, and NAND. The optoelectronic logic gate devices use incident first excitation light, second excitation light, or both as a first logic input signal, an externally applied bias voltage as a second logic input signal, and the generated photocurrent value as a logic output signal, thereby realizing AND, NOR, XNOR, or NAND operations.

[0047] like Figure 5As shown, when the optoelectronic logic gate device performs an AND operation, it uses a first excitation light as the first logic input signal, an externally applied bias voltage as the second logic input signal, and the absolute photocurrent value output by the device as the logic output signal. For example, in one instance, when the optoelectronic logic gate device performs an AND operation, the first logic input signal (IN1) is defined as 1 when the first excitation light illuminates the optoelectronic logic gate device, and as 0 when the first excitation light does not illuminate the device; the second logic input signal (IN2) is defined as 1 when the externally applied bias voltage is a positive high voltage (e.g., 5V), and as 0 when the externally applied bias voltage is 0V; the logic output signal (OUT) is defined as 1 when the optoelectronic logic gate device outputs a high photocurrent value (the photocurrent can be positive or negative), and as 0 when the optoelectronic logic gate device generates a low photocurrent value.

[0048] like Figure 6 and Figure 7 As shown, when the optoelectronic logic gate device implements the "NOR" operation and the "XNOR" operation, the optoelectronic logic gate device uses the first excitation light irradiation or the second excitation light irradiation as the first logic input signal, the externally applied bias voltage as the second logic input signal, and the absolute photocurrent value output by the device as the logic output signal.

[0049] By applying a bias voltage to the optoelectronic logic gate device, the curvature of the band structure and the carrier distribution in the functional layer 200 can be altered, affecting the separation and transport of photogenerated carriers within the device and thus regulating the threshold value of the photoelectric response (i.e., the logic threshold value), thereby achieving a logic output that distinguishes between high and low level currents. Under the first excitation light irradiation, the first material region 210 and the second material region 220 simultaneously generate photogenerated carriers, resulting in a synergistic enhancement effect and a reduction in the band curvature of the lateral heterojunction 230. Under the second excitation light irradiation, since only the first material region 210 generates photogenerated carriers, the reduction in band curvature of the lateral heterojunction 230 on the optoelectronic logic gate device is smaller compared to that under the first excitation light irradiation. Therefore, when a positive bias voltage is applied, the saturated photocurrent value generated by the optoelectronic logic gate device under the first excitation light irradiation is greater than that under the second excitation light irradiation. Similarly, under the first excitation light irradiation, the negative photocurrent value generated by the optoelectronic logic gate device when a positive bias voltage is applied is greater than that when no bias voltage is applied.

[0050] Under the illumination of the first or second excitation light, when a negative bias voltage is applied to the optoelectronic logic gate device, the band bending of the lateral heterojunction 230 of the optoelectronic logic gate device will increase with the increase of the negative bias voltage, and the separation and transport of heterojunction carriers in its functional layer 200 will also be enhanced, thereby realizing enhanced current output.

[0051] like Figure 6 As shown, in one example, when the optoelectronic logic gate device implements the NOR operation, the first logic input signal (IN1) is defined as 1 when the first excitation light illuminates the optoelectronic logic gate device, and is defined as 0 when the second excitation light illuminates the optoelectronic logic gate device; the second logic input signal (IN2) is defined as 1 when the externally applied bias voltage is a negative low voltage (e.g., -0.1V), and is defined as 0 when the externally applied bias voltage is 0V; the logic output signal (OUT) is defined as 1 when the optoelectronic logic gate device outputs a high photocurrent value, and the photocurrent can be a positive photocurrent or a negative photocurrent; the logic output signal (OUT) is defined as 0 when the optoelectronic logic gate device generates a low photocurrent value.

[0052] like Figure 7 As shown, in one example, when the optoelectronic logic gate device implements the XNOR operation, the first logic input signal (IN1) is defined as 1 when the first excitation light illuminates the optoelectronic logic gate device, and is defined as 0 when the second excitation light illuminates the optoelectronic logic gate device; the second logic input signal (IN2) is defined as 1 when the externally applied bias voltage is a positive low voltage (e.g., 0.1V), and is defined as 0 when the externally applied bias voltage is a negative low voltage (e.g., -0.1V); the logic output signal (OUT) is defined as 1 when the optoelectronic logic gate device outputs a high photocurrent value, and the photocurrent can be a positive photocurrent or a negative photocurrent; the logic output signal (OUT) is defined as 0 when the optoelectronic logic gate device generates a low photocurrent value.

[0053] like Figure 8As shown, when the optoelectronic logic gate device implements a NAND operation, it uses a first excitation light and a second excitation light as the first logic input signal, an externally applied bias voltage as the second logic input signal, and the absolute photocurrent value output by the device as the logic output signal. For example, in one example, when the optoelectronic logic gate device implements a NAND operation, the first logic input signal (IN1) is defined as 1 when the second excitation light illuminates the optoelectronic logic gate device, and as 0 when both the first and second excitation lights illuminate the device simultaneously; the second logic input signal (IN2) is defined as 1 when the externally applied bias voltage is a positive high voltage (e.g., 5V), and as 0 when the externally applied bias voltage is a negative high voltage (e.g., -5V); the logic output signal (OUT) is defined as 1 when the optoelectronic logic gate device outputs a high photocurrent value (the photocurrent can be positive or negative), and as 0 when the optoelectronic logic gate device does not generate a photocurrent value.

[0054] like Figure 9 As shown, in some embodiments, the logic operation functions that the optoelectronic logic gate device can implement also include combinational logic operations of the first logic operation and the second logic operation. The first logic operation includes an OR operation or an XOR operation, and the second logic operation includes an AND operation, a NOR operation, an XNOR operation, or a NAND operation. The optoelectronic logic gate device uses a first excitation light as the first logic input signal, a second excitation light as the second logic input signal, an externally applied bias voltage as the third logic input signal, and the generated photocurrent value as the logic output signal, thereby realizing combinational logic operations.

[0055] For example, in one example, the combinational logic operation implemented by the optoelectronic logic gate device is a combination of OR and AND operations, specifically represented as Y=(A+B)·C, that is, the first logic input signal (IN1) and the second logic input signal (IN2) are first ORed, and the result of the OR operation is then ANDed with the third logic input signal (IN3) in a two-level logic operation. The first logic input signal (IN1) is defined as 1 when the first excitation light illuminates the optoelectronic logic gate device, and as 0 when the first excitation light does not illuminate the optoelectronic logic gate device; the second logic input signal (IN2) is defined as 1 when the second excitation light illuminates the optoelectronic logic gate device, and as 0 when the second excitation light does not illuminate the optoelectronic logic gate device; the third logic input signal (IN3) is defined as 1 when a negative bias voltage is applied to the optoelectronic logic gate device, and as 0 when no bias voltage is applied to the optoelectronic logic gate device; the logic output signal (OUT) is 1 when the optoelectronic logic gate device generates photocurrent, which can be a positive or negative photocurrent, and is 0 when the optoelectronic logic gate device does not generate photocurrent. Figure 9 As shown, under the above logic input and output definitions, optoelectronic logic gate devices can implement the two-level logic operations in this example.

[0056] On the other hand, this application also provides a logic circuit, which includes the optoelectronic logic gate device in any of the above embodiments. The optoelectronic logic gate device can independently implement seven basic logic operations and two-layer composite logic operations under the control of incident excitation light of different wavelengths or the combination of incident excitation light and external bias voltage.

[0057] In summary, the optoelectronic logic gate device and logic circuit based on the lateral heterojunction of the present invention utilize a type II heterojunction formed by combining two-dimensional materials, which has a suitable valence conduction band offset. Under excitation light of different wavelengths, it can undergo varying degrees of band bending and shift, thereby generating inversion symmetry in the carrier group. This inversion can drive carrier transport in the optoelectronic logic gate device to generate a bipolar photoelectric response. Based on the bipolar photoelectric response, the optoelectronic logic gate device can control the logic relationship at the device output through a combination of optical / electrical input signals, replacing the traditional multi-device series-parallel connection scheme. It can realize seven basic logic functions and multi-layer composite logic operations on a single device.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A photoelectric logic gate device based on a lateral heterojunction, characterized in that, include: Substrate; A functional layer is disposed on the substrate. The functional layer includes a first material region and a second material region. The first material region includes SnS and the second material region includes SnS2. A lateral heterojunction exists between the first material region and the second material region. A first electrode is disposed on the first material region; The second electrode is disposed on the second material region; The optoelectronic logic gate device generates photocurrents of opposite polarities under the illumination of a first excitation light and a second excitation light, respectively. The wavelength of the first excitation light is 280nm~564nm, and the wavelength of the second excitation light is 564nm~1033nm.

2. The optoelectronic logic gate device according to claim 1, characterized in that, The optoelectronic logic gate device generates a negative photocurrent under the irradiation of the first excitation light, and the optoelectronic logic gate device generates a positive photocurrent under the irradiation of the second excitation light.

3. The optoelectronic logic gate device according to claim 2, characterized in that, When the optoelectronic logic gate device is irradiated by the first excitation light or without excitation light, the lateral heterojunction is a type II band alignment structure; when the optoelectronic logic gate device is irradiated by the second excitation light, the lateral heterojunction is a type Z band alignment structure.

4. The optoelectronic logic gate device according to claim 2, characterized in that, When a positive bias voltage is applied, the saturated photocurrent value generated by the optoelectronic logic gate device under the first excitation light is greater than the saturated photocurrent value generated under the second excitation light; and under the first excitation light, the negative photocurrent value generated by the optoelectronic logic gate device when a positive bias voltage is applied is greater than the negative photocurrent value generated when no bias voltage is applied.

5. The optoelectronic logic gate device according to claim 1, characterized in that, When no bias voltage is applied, the photocurrent generated by the optoelectronic logic gate device under the irradiation of one of the first excitation light and the second excitation light can be quenched under the irradiation of the other of the first excitation light and the second excitation light.

6. The optoelectronic logic gate device according to any one of claims 1 to 5, characterized in that, The optoelectronic logic gate device is used to implement logic operations, which include at least one of "OR", "XOR", "NOT", "AND", "NOR", "XNOR" and "NAND".

7. The optoelectronic logic gate device according to claim 6, characterized in that, When the optoelectronic logic gate device performs an "OR", "XOR", or "NOT" operation, it uses the first excitation light as the first logic input signal, the second excitation light as the second logic input signal, and the photocurrent value as the logic output signal.

8. The optoelectronic logic gate device according to claim 6, characterized in that, When the optoelectronic logic gate device performs AND, NOR, XNOR, or NAND operations, the first excitation light and / or the second excitation light are used as the first logic input signal, the bias voltage applied to the optoelectronic logic gate device is used as the second logic input signal, and the photocurrent value is used as the logic output signal.

9. The optoelectronic logic gate device according to claim 6, characterized in that, The logical operation further includes a combinational logical operation of the first logical operation and the second logical operation. The first logical operation includes an "OR" operation or an "XOR" operation, and the second logical operation includes an "AND" operation, an "OR NOT" operation, an "XNOR" operation, and an "AND NOT" operation. When the optoelectronic logic gate device implements the combinational logic operation, the first excitation light is used as the first logic input signal, the second excitation light is used as the second logic input signal, the bias voltage applied to the optoelectronic logic gate device is used as the third logic input signal, and the photocurrent value is used as the logic output signal.

10. A logic circuit, characterized in that, The logic circuit includes the optoelectronic logic gate device as described in any one of claims 1 to 9.

Images