Single photon avalanche diode and preparation method thereof, photoelectric detection device and electronic equipment

Abstract

The invention provides a single-photon avalanche diode and a preparation method thereof, a photoelectric detection device and electronic equipment. The single-photon avalanche diode comprises a substrate layer, a first doped region, a second doped region, an isolation region, a first electrode and a second electrode, the first doped region is located above the substrate layer, the second doped region is located above the first doped region, and the net doping type of the first doped region is opposite to that of the second doped region, so that a PN junction is formed between the first doped region and the second doped region, and depletion regions are formed on two sides of an interface of the PN junction; the isolation region is attached to the outer sides of the first doped region and the second doped region in the horizontal direction, and is constructed to at least cover the region between the upper interface of the second doped region and the lower interface of the first doped region in the height direction; the first electrode and the second electrode are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. According to the single-photon avalanche diode, the size of a middle strong longitudinal electric field region cannot be affected when the overall size is reduced.

Description

Technical Field

[0001] This application relates to the field of photoelectric detection devices, specifically to a single-photon avalanche diode and its fabrication method, a photoelectric detection device, and an electronic device. Background Technology

[0002] Single-photon avalanche diodes (SPADs) can detect extremely weak light or even single photons. By emitting photons and processing them with photons reflected back from the target object, time-correlated single-photon counting (TCSPC) can be performed to measure the time of flight (ToF) of the photons, thereby enabling distance detection of the target object. In recent years, LiDAR (Light Detection and Ranger) systems that utilize the ToF principle for ranging have been widely used in consumer products for 3D object imaging, modeling, and recognition, particularly in automotive driver assistance or autonomous driving systems, as well as machine 3D vision.

[0003] To achieve two-dimensional imaging or depth detection, one approach is scanning; another is to directly utilize a two-dimensional area array light source and a two-dimensional area array detector to detect optical signals within a specific two-dimensional angle. For two-dimensional area array detection, the imaging resolution can be increased by reducing the size of the single-photon avalanche diode (SPAD) unit in the two-dimensional area array detector.

[0004] The most basic structure of existing single-photon avalanche diodes (SPDBs) includes P-regions and N-regions, which form a PN junction. While the P-regions and N-regions generate a longitudinal electric field along the stacking direction, they also generate a transverse electric field. Due to the presence of this transverse electric field, premature avalanche breakdown can easily occur, preventing the normal output of an electrical signal when a signal photon is incident. This reduces the detection probability of the incident signal light, and consequently, lowers the signal-to-noise ratio (SNR) of the SPDB output signal. Therefore, it is necessary to suppress the transverse electric field formed by the P-regions and N-regions.

[0005] Various methods can be used to suppress the transverse electric field. However, in existing technologies, under the premise that the overall size of the SPAD cell remains unchanged, the suppression of the transverse electric field is mostly achieved by reducing the size of the central avalanche region or by using charge focusing methods. After the central avalanche region is reduced, the probability of edge carriers entering the avalanche region decreases, resulting in a decrease in photoelectric detection efficiency. The charge focusing method requires an additional complex ion implantation doping process, which increases the variability of the device and also increases the timing jitter of the device, leading to a deterioration in the performance of the single-photon avalanche diode. Summary of the Invention

[0006] In view of this, the embodiments of this application aim to provide a single-photon avalanche diode to solve the problem of poor performance of existing single-photon avalanche diodes.

[0007] The first aspect of this application provides a single-photon avalanche diode, comprising:

[0008] basal layer;

[0009] A first doped region and a second doped region, the first doped region being located above the substrate layer and the second doped region being located above the first doped region, with the net doping types of the first doped region and the second doped region being opposite, to form a PN junction between them and a depletion region being formed on both sides of the PN junction interface;

[0010] An isolation region is attached to the outer side of the first doped region and the second doped region in the horizontal direction, and is configured to at least cover the area between the upper interface of the second doped region and the lower interface of the first doped region in the height direction.

[0011] A first electrode and a second electrode, the first electrode being electrically connected to the first doped region and the second electrode being electrically connected to the second doped region, the first electrode and the second electrode being configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region.

[0012] In one embodiment of this application, the isolation region is configured to be filled with polysilicon.

[0013] In one embodiment of this application, the single-photon avalanche diode further includes a third electrode electrically connected to the isolation region to apply a voltage to the isolation region.

[0014] In one embodiment of this application, the isolation region is configured to be filled with a dielectric material.

[0015] In one embodiment of this application, the isolation region includes a high dielectric constant material film located on the sidewalls and bottom wall of the isolation region and a dielectric material filling the remainder of the isolation region.

[0016] An oxide layer is configured to be located at least between the isolation region and the interfaces of the first doped region, the second doped region, and the substrate layer.

[0017] In one embodiment of this application, the first doped region and the second doped region are configured to have equal dimensions extending in the horizontal direction.

[0018] In one embodiment of this application, the second doped region is configured such that its edges extend beyond the horizontal edge of the first doped region to fit against the horizontally outer isolation region, respectively.

[0019] In one embodiment of this application, the first doped region includes a first central doped region and a first edge doped region located at the horizontal outer edge of the first central doped region adjacent to the PN junction interface, wherein the net doping concentration of the first edge doped region is configured to be less than the net doping concentration of the first central doped region.

[0020] And / or,

[0021] The second doped region includes a second central doped region and a second edge doped region located at the horizontal outer edge of the second central doped region near the PN junction interface. The net doping concentration of the second edge doped region is configured to be less than the net doping concentration of the second central doped region.

[0022] In one embodiment of this application, a third doped region is further provided around the horizontal outer side of the isolation region. The impurity concentration of the third doped region is higher than that of the substrate layer, and the net doping type of the third doped region is the same as that of the first doped region.

[0023] The first electrode is configured to be electrically connected to the third doped region.

[0024] In one embodiment of this application, a fourth doped region is further included below the substrate layer, wherein the impurity concentration of the fourth doped region is higher than that of the substrate layer, and the net doping type of the fourth doped region is the same as that of the first doped region.

[0025] The first electrode is configured to be electrically connected to the fourth doped region.

[0026] In one embodiment of this application, the net doping type of the first doped region is P-type, the net doping type of the second doped region is N-type, and the substrate layer is a P-type substrate.

[0027] In one embodiment of this application, the net doping type of the first doped region is N-type, the net doping type of the second doped region is P-type, and the substrate layer includes an N-type buried layer and a P-type substrate located below the N-type buried layer.

[0028] A second aspect of this application provides a method for fabricating a single-photon avalanche diode, comprising:

[0029] A substrate is provided, and corresponding positions of the isolation region on the substrate are etched to obtain a substrate with an annular deep trench;

[0030] The corresponding material is deposited at least within the annular deep trench to form a substrate having the isolation region;

[0031] Ion implantation is performed on the internal region of the isolation region of the substrate to form at least a first doped region and a second doped region, wherein the second doped region is located above the first doped region and the net doping types of the first doped region and the second doped region are opposite to those of the second doped region, so as to form a PN junction between them and depletion regions are formed on both sides of the PN junction interface. The isolation region is attached to the outer side of the first doped region and the second doped region in the horizontal direction and covers at least the region between the upper interface of the second doped region and the lower interface of the first doped region in the height direction.

[0032] At least a first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first doped region, and the second electrode is electrically connected to the second doped region.

[0033] A third aspect of this application provides a photoelectric detection device, including the single-photon avalanche diode, wherein the photoelectric detection device is configured to obtain relevant information by sensing the electrical signal generated corresponding to the optical signal received by the single-photon avalanche diode.

[0034] A fourth aspect of this application provides an electronic device including the aforementioned photodetector, the electronic device being configured to perform a corresponding function based on relevant information obtained by the photodetector sensing an electrical signal.

[0035] During the operation of the single-photon avalanche diode of this application, the first and second electrodes can apply a reverse bias voltage to the PN junction between the first and second doped regions, thereby creating a strong longitudinal electric field in the depletion region of the PN junction. This reverse bias voltage is higher than the avalanche breakdown voltage of the single-photon avalanche diode, thus forming an avalanche region in the depletion region. At this time, the single-photon avalanche diode is in Geiger mode. When the incident photon is absorbed in the depletion region, an electron-hole carrier pair is generated in the depletion region. The carrier gains energy under the influence of the strong longitudinal electric field in the depletion region and generates more carriers through collisions with lattice atoms, thereby triggering the avalanche multiplication effect. This causes the reverse current of the single-photon avalanche diode of this application to rise sharply, eventually forming an avalanche current.

[0036] In the single-photon avalanche diode of this application, an isolation region is formed on the outer side of the first doped region and the second doped region in the horizontal direction. The isolation region covers at least the area between the upper interface of the second doped region and the lower interface of the first doped region in the height direction. The isolation region is attached to the outer region of the depletion region of the second doped region and the PN junction between the first doped region and the second doped region. This is used to suppress the lateral electric field generated on the lateral outer side of the second doped region, so that the carrier avalanche generated by the incident light occurs as much as possible in the strong vertical electric field region and not in the lateral electric field region. This effectively avoids edge breakdown of the single-photon avalanche diode, thereby improving the performance and reliability of the single-photon avalanche diode of this application and extending the service life of the single-photon avalanche diode of this application.

[0037] Therefore, by setting an isolation region, the lateral electric field generated on the outer side of the second doped region can be effectively suppressed without setting a large depletion region on the outer side of the second doped region, and it will not affect the strong longitudinal electric field region in the middle. This allows the single-photon avalanche diode of this application to maintain the size of the strong longitudinal electric field region in the middle when the overall size is reduced. As a result, when the single-photon avalanche diode of this application is applied to a photoelectric detection device, the overall size can be reduced to increase the overall density and improve the resolution of the imaging while ensuring the high photoelectric detection efficiency of a single single-photon avalanche diode, thereby effectively improving the overall performance of the photoelectric detection device. Attached Figure Description

[0038] Figure 1 The diagram shown is a cross-sectional view of an existing avalanche diode.

[0039] Figure 2 The figure shown is a cross-sectional view of the single-photon avalanche diode of this application.

[0040] Figure 3 The diagram shown is a schematic diagram of the top surface structure of the single-photon avalanche diode of this application.

[0041] Figure 4 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0042] Figure 5 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0043] Figure 6 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0044] Figure 7 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0045] Figure 8The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0046] Figure 9 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0047] Figure 10 The diagram shown is a cross-sectional view of another single-photon avalanche diode according to this application.

[0048] Figures 11A-11E As shown Figure 4 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0049] Figures 12A-12E As shown Figure 5 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0050] Figures 13A-13E As shown Figure 6 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0051] Figures 14A-14F As shown Figure 7 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0052] Figures 15A-15E As shown Figure 8 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0053] Figures 16A-16F As shown Figure 9 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0054] Figures 17A-17I As shown Figure 10 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode;

[0055] Figure 18 The diagram shows the steps of the fabrication method of the single-photon avalanche diode of this application.

[0056] Figure labels: 10, substrate; 11, P-type substrate; 12, N-type buried layer; 20, first doped region; 21, first central doped region; 22, first edge doped region; 30, second doped region; 31, second central doped region; 32, second edge doped region; 40, isolation region; 41, polysilicon; 42, dielectric; 43, high dielectric constant material thin film; 44, deep trench; 50, oxide layer; 61, first electrode; 62, second electrode; 63, third electrode; 70, third doped region; 80, fourth doped region; 91, strong longitudinal electric field; 92, transverse electric field. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0059] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

[0060] The terminology used in one or more embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this application. The singular forms “a,” “the,” and “the” used in one or more embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” used in one or more embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.

[0061] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this application, and similarly, second may also be referred to as first. Depending on the context, the word “if” as used herein may be interpreted as “when”, “in response to a determination”, or “upper”, “lower”, “front”, “back”, “left”, “right”, etc., are used only to indicate the relative positional relationship between related parts, and not to limit the absolute position of these related parts. In this document, “equal”, “same”, etc., are not strict mathematical and / or geometric limitations, and also include errors that are understandable to those skilled in the art and permissible in manufacturing or use. Unless otherwise stated, numerical ranges in this document include not only the entire range within its two endpoints, but also several sub-ranges contained therein.

[0062] Figure 1 This is a cross-sectional view of an NP-type single-photon avalanche diode in the prior art. It can be understood that single-photon avalanche diodes can be divided into NP-type and PN-type single-photon avalanche diodes. Figure 1 The single-photon avalanche diode in this paper is an NP-type single-photon avalanche diode. The PN-type single-photon avalanche diode has a similar principle and structure to the NP-type single-photon avalanche diode.

[0063] This single-photon avalanche diode includes a P-region and an N-region, which form a PN junction with each other. To facilitate avalanche multiplication, additional doping is usually performed near the PN junction region to facilitate avalanche multiplication under relatively low bias voltage.

[0064] Among them, such as Figure 1 As shown, the P-region and N-region generate both a longitudinal electric field and a transverse electric field 92. The longitudinal electric field can drift the charge carriers generated by the incident photons to the avalanche region, while the strong longitudinal electric field 91 in the avalanche region causes the charge carriers to collide and ionize with the crystal lattice. When the width of the strong longitudinal electric field 91 is large enough, a self-sustaining avalanche effect can occur, leading to avalanche breakdown.

[0065] The presence of the transverse electric field can easily lead to premature avalanche breakdown, preventing the normal output of an electrical signal when a signal photon is incident. This reduces the detection probability of the incident signal light and consequently lowers the signal-to-noise ratio of the single-photon avalanche diode's output signal. Therefore, it is necessary to suppress the transverse electric field formed in the P-region and N-region.

[0066] Therefore, as Figure 2 and Figure 3As shown, this application provides a single-photon avalanche diode, including a substrate layer 10, a first doped region 20, a second doped region 30, an isolation region 40, a first electrode 61, and a second electrode 62. The first doped region 20 is located above the substrate layer 10, and the second doped region 30 is located above the first doped region 20. The net doping types of the first doped region 20 and the second doped region 30 are opposite to form a PN junction between them, and depletion regions are formed on both sides of the PN junction interface.

[0067] The isolation region 40 is attached to the outer side of the first doped region 20 and the second doped region 30 in the horizontal direction, and is configured to at least cover the area between the upper interface of the second doped region 30 and the lower interface of the first doped region 20 in the height direction. It is understood that the horizontal direction refers to the extension direction of the wafer where the single-photon avalanche diode of this application is located, and the isolation region 40 being attached to the outer side of the first doped region 20 and the second doped region 30 in the horizontal direction means that the isolation region 40 is located outside the first doped region 20 and the second doped region 30 in the horizontal direction, and is directly attached to the outer surface of the first doped region 20 and the second doped region 30 in the horizontal direction. Figure 2 This is a cross-sectional view of the single-photon avalanche diode of this application. Figure 3 This is a top view of the single-photon avalanche diode of this application. For ease of fabrication, the first doped region 20 and the second doped region 30 can both be rectangular regions, and the isolation region 40 can be an annular region disposed on the outer side of the first doped region 20 and the second doped region 30 in the horizontal direction.

[0068] In the first electrode 61 and the second electrode 62, the first electrode 61 is electrically connected to the first doped region 20, and the second electrode 62 is electrically connected to the second doped region 30. The first electrode 61 and the second electrode 62 are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. The electrical connection between the first electrode 61 and the first doped region 20 refers to an indirect or direct electrical connection via other structures. The second electrode 62 is directly electrically connected to the second doped region 30. As previously stated, the portion of the second doped region 30 directly connected to the second electrode 62 can be heavily doped, but this is not shown in the figure.

[0069] It is understood that in the single-photon avalanche diode of this application, the regions where the first electrode 61 and the second electrode 62 are in contact with the corresponding structures can be heavily doped to achieve ohmic contact and reduce on-resistance. This heavily doped region is not shown in the accompanying drawings.

[0070] During the operation of the single-photon avalanche diode of this application, the first electrode 61 and the second electrode 62 can apply a reverse bias voltage to the PN junction between the first doped region 20 and the second doped region 30, thereby forming a strong longitudinal electric field 91 in the depletion region of the PN junction. This reverse bias voltage is higher than the avalanche breakdown voltage of the single-photon avalanche diode, thus forming an avalanche region in the depletion region. At this time, the single-photon avalanche diode is in Geiger mode. When the incident photon is absorbed in the depletion region, an electron-hole carrier pair is generated in the depletion region. The carrier gains energy under the action of the strong longitudinal electric field 91 in the depletion region and generates more carriers through collisions with lattice atoms, thereby triggering the avalanche multiplication effect, that is, causing the reverse current of the single-photon avalanche diode of this application to rise sharply, and finally forming an avalanche current.

[0071] In the single-photon avalanche diode of this application, an isolation region 40 is formed on the outer side of the first doped region 20 and the second doped region 30 in the horizontal direction. The isolation region 40 covers at least the area between the upper interface of the second doped region 30 and the lower interface of the first doped region 20 in the height direction. The isolation region 40 is attached to the outer region of the depletion region of the second doped region 30 and the PN junction between the first doped region 20 and the second doped region 30. This is used to suppress the lateral electric field generated on the lateral outer side of the second doped region 30, so that the carrier avalanche generated by the incident light occurs as much as possible in the region of strong longitudinal electric field 91, and not in the region of lateral electric field. This effectively avoids edge breakdown of the single-photon avalanche diode, thereby improving the performance and reliability of the single-photon avalanche diode of this application and extending the service life of the single-photon avalanche diode of this application.

[0072] Therefore, by setting the isolation region 40, it is possible to effectively suppress the lateral electric field generated on the lateral outer side of the second doped region 30 without setting a large depletion region on the outer side of the second doped region 30, and without affecting the strong longitudinal electric field 91 region in the middle. This allows the single-photon avalanche diode of this application to maintain the size of the strong longitudinal electric field 91 region when reducing the overall size. As a result, when the single-photon avalanche diode of this application is applied to a photoelectric detection device, it can improve the imaging resolution by reducing the overall size and increasing the overall density while ensuring the high photoelectric detection efficiency of a single single-photon avalanche diode, thereby effectively improving the overall performance of the photoelectric detection device.

[0073] It is understood that single-photon avalanche diodes can be divided into NP-type single-photon avalanche diodes and PN-type single-photon avalanche diodes.

[0074] That is, Figure 2 As shown, in one embodiment of this application, the net doping type of the first doped region 20 is P-type, the net doping type of the second doped region 30 is N-type, and the substrate layer 10 is a P-type substrate 11, i.e. Figure 2 The single-photon avalanche diode shown is an NP-type single-photon avalanche diode.

[0075] And such Figure 5 As shown, in another embodiment of this application, the net doping type of the first doped region 20 is N-type, the net doping type of the second doped region 30 is P-type, and the substrate layer 10 includes an N-type buried layer 12 and a P-type substrate 11 located below the N-type buried layer 12, i.e. Figure 5 The single-photon avalanche diode shown is a PN-type single-photon avalanche diode. The working principle of a PN-type single-photon avalanche diode is similar to that of an NP-type single-photon avalanche diode.

[0076] In the semiconductor field, P-type substrates offer more advantages and have a wider range of applications than N-type substrates. Figure 2 Compared to the NP-type single-photon avalanche diode shown, Figure 5 The PN-type single-photon avalanche diode shown has an N-type buried layer 12 added to isolate the first N-type doped region 20 from the P-type substrate 11; it is understood that the electric field strength between the N-type buried layer 12 and the P-type substrate 11 is small and cannot form an avalanche region.

[0077] Of course, such as Figure 4 As shown, in another embodiment of this application, an N-type substrate can also be used directly, with a similar principle, which will not be described in detail here.

[0078] It is understandable that the isolation region 40 can also extend from the upper interface of the second doped region 30 to a position lower than the lower interface of the first doped region 20, thereby covering the area from the upper interface of the second doped region 30 to a certain distance below the lower interface of the first doped region 20 in the height direction. The effect is similar to extending to a position flush with the lower interface of the first doped region 20, which will not be elaborated here.

[0079] In a specific embodiment of this application, the width of the isolation region 40 ranges from 0.1 μm to 1 μm, and the depth ranges from 0.5 μm to 5 μm, to ensure the isolation effect of the isolation region 40. It is understood that the specific width and depth of the isolation region 40 can be selected according to the specific device structure and are not limited herein.

[0080] Understandably, in the single-photon avalanche diode of this application, in order to form the isolation region 40, a corresponding deep trench 44 needs to be etched on the substrate, and then the corresponding material is deposited in the isolation region 40. Among them, lattice defects will be generated at the side interface of the deep trench 44 region, which will generate recombination carriers; these carriers may drift to the strong vertical electric field 91 region in the middle under the action of the weak electric field at the side interface, triggering avalanche, which will lead to an increase in the dark count rate of the single-photon avalanche diode of this application.

[0081] Therefore, as Figure 2 As shown, therefore, in one embodiment of this application, the isolation region 40 is configured to be filled with polysilicon 41. Compared to other materials, polysilicon 41 can effectively reduce lattice defects at the side interface of the deep trench 44, thereby reducing premature breakdown at the side interface of the deep trench 44.

[0082] Furthermore, such as Figure 2 As shown, in one embodiment of this application, the single-photon avalanche diode further includes a third electrode 63, which is electrically connected to the isolation region 40 to apply a voltage to the isolation region 40.

[0083] It is understood that the third electrode 63 can apply a voltage of the same polarity as the first electrode 61 to the isolation region 40, or it can apply a voltage of the opposite polarity to the first electrode 61. The voltage polarity is not limited here; and the voltage magnitude can also be adjusted as needed.

[0084] The third electrode 63 applies a voltage of the same polarity as the first electrode 61 to the isolation region 40. This means that when the first electrode 61 applies a positive voltage to the first doped region 20, the third electrode 63 applies a positive voltage to the isolation region 40; when the first electrode 61 applies a negative voltage to the first doped region 20, the third electrode 63 applies a negative voltage to the isolation region 40.

[0085] It is understood that the third electrode 63 is electrically connected to the polysilicon 41 of the isolation region 40 to apply a voltage to the isolation region 40 as applied to the first electrode 61, thereby modulating the electric field on the side of the isolation region 40. That is, an electric field is formed at the side interface of the deep trench 44 to attract electrons to move to the side interface of the deep trench 44, further repairing the lattice defects at the side interface of the deep trench 44, thereby avoiding lateral breakdown caused by the formation of a lateral electric field on the side of the second doped region 30. Furthermore, the third electrode 63 can modulate the surface potential after being applied to the isolation region 40, thereby reducing the dark count generated by the single-photon avalanche diode in this embodiment during operation.

[0086] It is understood that in the single-photon avalanche diode of this application, the region where the third electrode 63 contacts the polysilicon 41 can be heavily doped to achieve ohmic contact and reduce on-resistance. This heavily doped region is not shown in the attached figure.

[0087] And such Figure 8As shown, in another embodiment of this application, the isolation region 40 is constructed to be filled with dielectric 42. Because dielectric 42 has good insulating properties, the dielectric 42 within the isolation region 40 can effectively suppress the lateral electric field generated on the lateral outer side of the second doped region 30, ensuring that a large lateral electric field is not easily generated in the edge region of the second doped region 30. This, in turn, ensures that the carrier avalanche generated by the incident light occurs in the region of the strong longitudinal electric field 91 formed in the depletion region between the first doped region 20 and the second doped region 30. The dielectric 42 material may include silicon oxide, silicon nitride, etc., and is not limited thereto.

[0088] Furthermore, such as Figure 9 As shown, in one embodiment of this application, the isolation region 40 includes a high dielectric constant material film 43 located on the sidewalls and bottom wall of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40.

[0089] Because the sidewalls and bottomwalls of the isolation region 40 are formed with a high dielectric constant material thin film 43, the high dielectric constant material thin film 43 can form fixed charges on the sidewalls and bottomwalls of the isolation region 40. These fixed charges can also form an electric field at the side interface of the deep trench 44, repairing the lattice defects at the side interface of the deep trench 44, thereby preventing the formation of a lateral electric field on the side of the second doped region 30, which would then lead to lateral breakdown. Then, the remaining isolation region 40 is filled with dielectric 42, which can effectively suppress the generation of a lateral electric field on the lateral outer side of the second doped region 30.

[0090] It is understood that high dielectric constant materials can include various materials and combinations such as alumina, hafnium oxide, and tantalum oxide, and are not limited here.

[0091] like Figure 2 As shown, in one embodiment of this application, the single-photon avalanche diode of this application further includes an oxide layer 50, which is configured to be located at least between the interface of the isolation region 40 and the first doped region 20, the second doped region 30, and the substrate layer 10.

[0092] Understandably, to facilitate the deposition of polysilicon 41, high-dielectric-constant thin film 43, or dielectric material 42 within the deep trench 44, after etching the deep trench 44 during the fabrication of the single-photon avalanche diode in this application, a thin oxide layer can first be grown on the sides, bottom, and substrate of the deep trench 44 using thermal oxidation or atomic layer deposition (ALD) to form a good interface state; then, polysilicon 41, high-dielectric-constant thin film 43, or dielectric material 42 is deposited on the oxide layer, and the excess is removed to obtain the desired isolation region 40. Fewer interface defects between the oxide layer and the polysilicon 41, high-dielectric-constant thin film 43, or substrate 10 help reduce recombination carriers generated by interface defects, thereby effectively reducing the dark count rate of the single-photon avalanche diode in this application. Furthermore, the oxide layer 50 also has a certain insulating effect, which helps to effectively suppress the lateral electric field generated on the lateral outer side of the second doped region 30.

[0093] like Figure 2 As shown, in one embodiment of this application, the first doped region 20 and the second doped region 30 are configured to have equal dimensions extending in the horizontal direction. Equal horizontal extension dimensions of the first doped region 20 and the second doped region 30 mean that the horizontal extension dimensions of the first doped region 20 and the second doped region 30 are equal in each horizontal extension direction of the wafer on which the single-photon avalanche diode of this application is located.

[0094] Since the first doped region 20 and the second doped region 30 have the same horizontal extension size, an avalanche region with an area equal to the interface area between the first doped region 20 and the second doped region 30 can be formed. Under the premise that the size of other regions remains unchanged, the avalanche region area can be expanded as much as possible, thereby effectively improving the photoelectric detection efficiency of the single-photon avalanche diode of this application.

[0095] like Figure 6As shown, in another embodiment of this application, the second doped region 30 is configured such that its edges extend beyond the horizontal edge of the first doped region 20, respectively, to be attached to the horizontally outer isolation region 40. That is, compared to the second doped region 30, the extension dimension of the first doped region 20 is smaller, the central portion of the second doped region 30 is attached vertically to the first doped region 20, and the edge portion is directly attached to the substrate layer 10. In this way, compared to the PN junction between the central regions of the first doped region 20 and the second doped region 30, the potential difference of the built-in electric field of the PN junction between the edge region of the second doped region 30 and the substrate layer 10 is smaller, and the internal electric field strength is also smaller. Thus, the recombination carriers generated by lattice defects at the side interface of the isolation region 40 are less likely to drift to the central region with a strong vertical electric field 91 under the action of the small electric field at the edge, thereby greatly reducing the probability of recombination carriers generated by lattice defects at the side interface of the isolation region 40 reaching the central avalanche region and causing avalanche multiplication, thereby reducing the dark count rate of the single-photon avalanche diode of this application.

[0096] In the fabrication process of the single-photon avalanche diode of this application, the above structure can be achieved by reducing the size relative to the edge of the second doped region 30 during the formation of the first doped region 20 by ion implantation. In one specific embodiment, the first doped region 20 can be reduced by 0.1 μm-0.5 μm relative to the edge of the second doped region 30.

[0097] Similarly, such as Figure 7 As shown, in one embodiment of this application, the first doped region 20 includes a first central doped region 21 and a first edge doped region 22 located at the horizontal outer edge of the first central doped region 21 near the PN junction interface. The net doping concentration of the first edge doped region 22 is configured to be less than the net doping concentration of the first central doped region 21.

[0098] Since the net doping concentration of the first edge doped region 22 is less than that of the first middle doped region 21, the built-in potential difference of the edge region of the PN junction between the first doped region 20 and the second doped region 30 is less than that of the middle region of the PN junction between the first doped region 20 and the second doped region 30. As a result, the recombination carriers generated by lattice defects at the side interface of the isolation region 40 are less likely to drift to the central strong longitudinal electric field 91 region under the action of the small edge electric field. This greatly reduces the probability that the recombination carriers generated by lattice defects at the side interface of the isolation region 40 will reach the central avalanche region and cause avalanche multiplication, thereby reducing the dark count rate of the single-photon avalanche diode of this application.

[0099] Similarly, the second doped region 30 includes a second central doped region 31 and a second edge doped region 32 located at the horizontal outer edge of the second central doped region 31 near the PN junction interface. The net doping concentration of the second edge doped region 32 is configured to be less than the net doping concentration of the second central doped region 31. The principle is similar and no limitation is made here.

[0100] Understandably, since the built-in potential difference of a PN junction is proportional to the product of the net doping concentrations of the two doped regions, in the following three cases: the net doping concentration of the first edge doped region 22 is less than the net doping concentration of the first middle doped region 21 and the net doping concentration of the second edge doped region 32 is less than the net doping concentration of the second middle doped region 31; or, the net doping concentration of the first edge doped region 22 is less than the net doping concentration of the first middle doped region 21 and the net doping concentration of the second doped region 30 is uniform; or, the net doping concentration of the second edge doped region 32 is less than the net doping concentration of the second middle doped region 31 and the net doping concentration of the first doped region 20 is uniform, the product of the net doping concentrations of the first edge doped region 22 and the second edge doped region 32 is less than the product of the net doping concentrations of the second middle doped region 31 and the second middle doped region 31.

[0101] If the net doping concentration of the first edge doping region 22 is greater than that of the first middle doping region 21, but the net doping concentration of the second edge doping region 32 is less than that of the second middle doping region 31, the product of the net doping concentration of the first edge doping region 22 and the net doping concentration of the second edge doping region 32 can be made less than the product of the net doping concentration of the second middle doping region 31 and the net doping concentration of the second middle doping region 31.

[0102] Similarly, if the net doping concentration of the first edge doped region 22 is less than the net doping concentration of the first middle doped region 21, but the net doping concentration of the second edge doped region 32 is greater than the net doping concentration of the second middle doped region 31, the product of the net doping concentration of the first edge doped region 22 and the net doping concentration of the second edge doped region 32 can be less than the product of the net doping concentration of the second middle doped region 31 and the net doping concentration of the second middle doped region 31.

[0103] For both of the above situations, it is only necessary to obtain the following during the fabrication process of the single-photon avalanche diode in this application: Figure 2 After constructing the first doped region 20 and the second doped region 30 as shown, secondary doping is performed simultaneously in the first edge doped region 22 and the second edge doped region 32, wherein the doping type is the same as the one with the higher net doping concentration in the first middle doped region 21 and the second middle doped region 31, thus obtaining the above structure.

[0104] Understandably, most existing detection units with single-photon avalanche diodes are lateral-type devices. For lateral-type devices, to facilitate outward conduction between the first electrode 61 and the second electrode 62, both the first electrode 61 and the second electrode 62 are positioned at... Figure 2 The upper side of the middle.

[0105] Therefore, as Figure 2 As shown, the single-photon avalanche diode of this application further includes a third doped region 70 disposed around the outer side of the isolation region 40 in the horizontal direction. The impurity concentration of the third doped region 70 is higher than that of the substrate layer 10, and the net doping type of the third doped region 70 is the same as that of the first doped region 20. The first electrode 61 is configured to be electrically connected to the third doped region 70. Since the impurity concentration of the third doped region 70 is higher than that of the substrate layer 10, and the net doping type of the third doped region 70 is the same as that of the first doped region 20, the on-resistance of the third doped region 70 can be effectively reduced, effectively ensuring the conduction performance of the single-photon avalanche diode of this application.

[0106] It is understood that the net doping concentration of the third doped region 70 can be lower than that of the substrate layer 10 in order to avoid the generation of a lateral electric field on the side of the third doped region 70 and the second doped region 30 as much as possible; of course, in one embodiment of this application, the net doping concentration of the third doped region 70 can also be higher than that of the substrate layer 10.

[0107] Understandably, for those containing Figure 2 The photodetector device shown is a single-photon avalanche diode (SPAD). The SPAD is formed on the same wafer as quenching, reset, and protection devices. During the operation of this photodetector device, photons travel from... Figure 2 The light is directed downwards into the single-photon avalanche diode to induce avalanche multiplication within the single-photon avalanche diode.

[0108] To improve the distribution efficiency of single-photon avalanche diodes on a wafer, in one embodiment of this application, such as Figure 10 As shown, the single-photon avalanche diode of this application also includes a fourth doped region 80 located below the substrate layer 10. The impurity concentration of the fourth doped region 80 is higher than that of the substrate layer 10, and the net doping type of the fourth doped region 80 is the same as that of the first doped region 20. The first electrode 61 is configured to be directly electrically connected to the fourth doped region 80.

[0109] Right now Figure 10 The single-photon avalanche diode in the image is a vertical device, with the first electrode 61 and the second electrode 62 respectively originating from... Figure 10A reverse bias voltage is applied to the top and bottom sides of the PN junction to form an avalanche region in the depletion region. Since the impurity concentration of the fourth doped region 80 is higher than that of the substrate layer 10, the on-resistance of the fourth doped region 80 can be effectively reduced. Specifically, since the fourth doped region 80 is located below the substrate layer 10, the net doping concentration of the fourth doped region 80 can be higher or lower than that of the first doped region 20.

[0110] Understandably, when Figure 10 When the single-photon avalanche diode in the circuit is a vertical device, the single-photon avalanche diode array can be formed on a separate wafer. The active quenching structure, reset structure, and peripheral driving, control, and signal processing circuits are located on another logic circuit wafer. The two are interconnected at the pixel level through bonding. Each single-photon avalanche diode still requires a separate quenching resistor or protective resistor to quench or limit the avalanche current.

[0111] After bonding, the logic circuit wafer is located Figure 10 Above the single-photon avalanche diode, during the operation of this photoelectric detection device, photons emerge from... Figure 10 The photon is incident from below into the single-photon avalanche diode to induce avalanche multiplication within the diode. Understandably, to ensure photons can pass upwards through the substrate, the substrate can be thinned to a predetermined thickness during the fabrication of the single-photon avalanche diode in this application, thereby ensuring that photons can pass upwards from the substrate. Figure 10 The light is incident from the bottom up into the single-photon avalanche diode to induce avalanche multiplication within the single-photon avalanche diode.

[0112] The above text combined Figures 2 to 10 The present application describes in detail the device embodiments of the single-photon avalanche diode, and the following is in conjunction with... Figures 11A to 17I This document describes in detail an embodiment of the fabrication method for a single-photon avalanche diode according to this application. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments; therefore, any parts not described in detail can be found in the preceding apparatus embodiments. Specifically, Figures 11A-11E As shown Figure 2 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 12A-12E As shown Figure 5 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 13A-13E As shown Figure 6 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 14A-14F As shown Figure 7 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 15A-15E As shown Figure 8 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 16A-16F As shown Figure 9 A schematic diagram illustrating the fabrication process of another single-photon avalanche diode; Figures 17A-17I As shown Figure 10 A schematic diagram of the fabrication process of another single-photon avalanche diode.

[0113] like Figure 18 As shown, this application also provides a method for fabricating a single-photon avalanche diode, comprising:

[0114] Step S101: Provide a substrate and etch the corresponding position of the isolation region 40 on the substrate to obtain a substrate with an annular deep trench 44.

[0115] It is understood that the substrate can be a silicon-based substrate, a germanium-based substrate, or a substrate formed of other materials. The semiconductor substrate can be a high-purity substrate or a doped substrate, such as an N-type or P-type substrate formed through doping. The doping concentration of the semiconductor substrate can vary, ranging from lightly doped (relatively low concentration), moderately doped (medium concentration), to heavily doped (relatively high concentration), and is not limited here.

[0116] Step S102: Deposit the corresponding material at least within the annular deep trench 44 to form a substrate with an isolation region 40.

[0117] Understandably, the corresponding material can be uniformly deposited on the substrate with the annular deep trench 44, and then the excess material can be removed by chemical mechanical polishing (CMP) or etch back to obtain the desired substrate with the isolation region 40.

[0118] Step S103: Ion implantation is performed on the internal region of the isolation region 40 of the substrate to form at least a first doped region 20 and a second doped region 30.

[0119] The second doped region 30 is located above the first doped region 20, and the net doping types of the first doped region 20 and the second doped region 30 are opposite to those of the first doped region 20, so as to form a PN junction between them and form depletion regions on both sides of the PN junction interface. The isolation region 40 is located outside the first doped region 20 and the second doped region 30 in the horizontal direction, and covers at least the area between the upper interface of the second doped region 30 and the lower interface of the first doped region 20 in the height direction.

[0120] Step S104: At least a first electrode 61 and a second electrode 62 are formed, wherein the first electrode 61 is electrically connected to the first doped region 20, and the second electrode 62 is directly electrically connected to the second doped region 30.

[0121] It is understandable that, such as Figures 11A-11C As shown, the depth and width of the material in the isolation region 40 can be controlled by controlling the depth and width of the deep trench 44 formed after etching. It is understood that laser annealing can be performed after the ion implantation process to repair the lattice of the semiconductor material; laser annealing can also be performed after the formation of the first electrode 61 and the second electrode 62 to activate and form a good ohmic contact, which will not be elaborated further here.

[0122] To facilitate the deposition of the corresponding material within the annular deep trench 44, such as Figure 11B As shown, after obtaining a substrate with an annular deep trench 44, a thin oxide layer can be grown on the side surface, bottom surface and substrate of the deep trench 44 by thermal oxidation or atomic layer deposition (ALD) to form a good interface state; then polysilicon 41, a high dielectric constant material thin film 43 or a dielectric material 42 are deposited on the oxide layer, and then the excess is removed to obtain the desired isolation region 40.

[0123] like Figure 12D As shown, for Figure 5 The PN-type single-photon avalanche diode shown requires the simultaneous formation of an N-type buried layer 12 during the ion implantation step to isolate the N-type first doped region 20 from the P-type substrate 11.

[0124] like Figure 13D As shown, the width of the first doped region 20 can be adjusted during the ion implantation step to meet the relevant structural requirements.

[0125] like Figure 14E As shown, in order to obtain the desired first edge-doped region 22 and / or second edge-doped region 32 structure, the following can be achieved during the ion implantation step: Figure 14D After the first doped region 20 and the second doped region 30 shown in the figure are structured, secondary doping is performed simultaneously on the first edge doped region 22 and the second edge doped region 32 to obtain the corresponding structure.

[0126] like Figure 13C As shown, for a single-photon avalanche diode with polysilicon 41 deposited in the isolation region 40, polysilicon 41 is uniformly deposited on a substrate with an annular deep trench 44, and then the excess polysilicon 41 is removed to obtain the corresponding structure with polysilicon 41 deposited in the isolation region 40. Then, in the steps of forming the first electrode 61 and the second electrode 62, the third electrode 63 can be formed simultaneously to facilitate the outward contact of the third electrode 63 and to facilitate the application of a voltage of the same polarity as the first electrode 61 to the isolation region 40 by the third electrode 63.

[0127] like Figure 15CAs shown, for a single-photon avalanche diode with dielectric 42 deposited in the isolation region 40, it is only necessary to uniformly deposit the corresponding dielectric 42 material on the substrate with an annular deep trench 44, and then remove the excess dielectric 42 to obtain the corresponding structure with dielectric 42 deposited in the isolation region 40.

[0128] like Figure 16C and Figure 16D As shown, for a single-photon avalanche diode whose isolation region 40 includes a high-dielectric-constant material film 43 located on the sidewalls and bottom wall of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40, a high-dielectric-constant material film 43 can be uniformly deposited in a substrate with an annular deep trench 44 using atomic layer deposition. Then, the corresponding dielectric 42 material can be uniformly deposited on top of it. Then, the excess dielectric 42 can be removed to obtain the corresponding structure in which the isolation region 40 includes a high-dielectric-constant material film 43 located on the sidewalls and bottom wall of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40.

[0129] like Figure 11D As shown, for a lateral single-photon avalanche diode, it is only necessary to simultaneously form a third doped region 70 during the ion implantation step, and then form a first electrode 61 electrically connected to the third doped region 70 on the third doped region 70.

[0130] like Figures 17D to 17I As shown, for a vertically oriented single-photon avalanche diode, after obtaining... Figure 17E After the corresponding structure is formed, the structure outside the isolation region 40 needs to be removed. Then, after bonding the wafer containing the single-photon avalanche diode to another logic circuit wafer, the substrate is thinned. Then, the fourth doped region 80 and the first electrode 61 are formed on the back side of the substrate by ion implantation, thereby obtaining... Figure 17I The single-photon avalanche diode structure in the image.

[0131] This application also provides a photoelectric detection device, which includes the aforementioned single-photon avalanche diode, and is configured to obtain relevant information by sensing the electrical signal generated by the optical signal received by the single-photon avalanche diode.

[0132] Specifically, this photoelectric detection device emits sensing light pulses to an external object and receives sensing light pulses returned by the external object, converting the sensing light pulses into corresponding electrical signals. These electrical signals are used to obtain corresponding sensing information. For example, but not limited to, the electrical signals are used to obtain one or more of the following: proximity information, depth information, or distance information of the external object. Depth information is used, for example, in fields such as 3D modeling, face recognition, autonomous driving, and SLAM, and this application does not limit its use. Proximity information is used, for example, to determine whether an object is approaching.

[0133] Specifically, the photoelectric detection device includes a transmitting module, a receiving module, and a processing circuit. The transmitting module transmits sensing light pulses to the space of an external object. At least a portion of the transmitted sensing light pulses return from the external object to form sensing light pulses, and at least a portion of these sensing light pulses is received by the receiving module. The returned sensing light pulses may carry, for example, depth information of the external object.

[0134] The emitting module may include a light-emitting component and an emitting optical component. The light-emitting component is used to emit sensing light pulses. The emitting optical component is used to modulate the sensing light pulses emitted by the light-emitting component to form the sensing light pulses required for sensing, and to project the sensing light pulses into the detection space.

[0135] The photoelectric sensor includes a pixel array composed of multiple pixel units. Each pixel unit may include one or more photoelectric conversion devices to sense the sensed light signal reflected back from an external object and output a corresponding electrical signal to determine the flight time of the light pulse in space, thereby determining the distance information of the external object. This photoelectric conversion device is the aforementioned single-photon avalanche photodiode, that is, the photoelectric sensor is a SPAD array chip.

[0136] The receiving module may also include a readout circuit composed of one or more of the following devices connected to the photoelectric sensor: a signal amplifier, a time-to-digital converter (TDC), and an analog-to-digital converter (ADC), to preprocess the electrical signal output by the photoelectric conversion device. The receiving module may also include receiving optical components for receiving sensed light pulses returned from an external object and transmitting the sensed light pulses to the corresponding pixel units.

[0137] The processing circuit determines the distance information of an external object based on the time difference between the emitted sensing light pulse and the received return sensing light pulse, thereby enabling the photoelectric detection device to perform three-dimensional imaging of the external object. In other embodiments, the processing circuit may also obtain relevant sensing information based on the sensing light pulse and other suitable detection principles, and is not limited to determining relevant sensing information based on the time difference between the emitted sensing light pulse and the received return sensing light pulse. The processing circuit can be disposed on the photoelectric detection device or on an electronic device including the photoelectric detection device, such as on the main control circuit of the electronic device; this application embodiment does not impose any limitations.

[0138] This application also provides an electronic device, which includes the photoelectric detection device described above. The electronic device can perform corresponding functions based on the relevant information obtained by the photoelectric detection device from sensing electrical signals.

[0139] Specifically, the electronic device may include an application module configured to perform preset operations or implement corresponding functions based on the detection results of the photoelectric detection device. For example, but not limited to: determining whether an external object is within a preset detection range in front of the electronic device based on proximity information; or controlling the movement of the electronic device to avoid obstacles based on distance information of the external object; or realizing 3D modeling, facial recognition, machine vision, etc., based on depth information of the external object's surface. The electronic device may also include a storage medium to support the storage needs of the photoelectric detection device during operation, and one or more processors to control related components to achieve corresponding functions.

[0140] It is understood that the corresponding functions include, but are not limited to, unlocking after recognizing the user, making payment, launching a preset application, obstacle avoidance, and using deep learning technology to determine the user's emotions and health status after recognizing the user's facial expressions. This electronic device is, for example, but not limited to, suitable types of electronic products such as consumer electronics, home electronics, smart mobile tools, and financial terminal products. Among them, consumer electronics include, but are not limited to, mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include, but are not limited to, smart door locks, televisions, refrigerators, and wearable devices. Smart mobile tools include, but are not limited to, cars, robots, and unmanned delivery vehicles. Financial terminal products include, but are not limited to, ATMs and self-service terminals.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications or equivalent substitutions made within the spirit and principles of this application should be included within the protection scope of this application.

[0142] Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this application is defined by the appended claims.

Claims

1. A single-photon avalanche diode, characterized in that, include: Basal layer (10); A first doped region (20) and a second doped region (30), wherein the first doped region (20) is located above the substrate layer (10), and the second doped region (30) is located above the first doped region (20), and the net doping types of the first doped region (20) and the second doped region (30) are opposite to those of the second doped region (30) to form a PN junction between them and a depletion region is formed on both sides of the PN junction interface. An isolation region (40) is attached to the outer side of the first doped region (20) and the second doped region (30) in the horizontal direction, and is configured to at least cover the region between the upper interface of the second doped region (30) and the lower interface of the first doped region (20) in the height direction. A first electrode (61) and a second electrode (62), the first electrode (61) being electrically connected to the first doped region (20) and the second electrode (62) being electrically connected to the second doped region (30), the first electrode (61) and the second electrode (62) being configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region.

2. The single-photon avalanche diode according to claim 1, characterized in that, The isolation region (40) is constructed to be filled with polycrystalline silicon (41).

3. The single-photon avalanche diode according to claim 2, characterized in that, The single-photon avalanche diode further includes a third electrode (63) electrically connected to the isolation region (40) to apply a voltage to the isolation region (40).

4. The single-photon avalanche diode according to claim 1, characterized in that, The isolation region (40) is constructed to be filled with dielectric (42).

5. The single-photon avalanche diode according to claim 1, characterized in that, The isolation region (40) includes a high dielectric constant material film (43) located on the sidewalls and bottom wall of the isolation region (40) and a dielectric (42) filling the remainder of the isolation region (40).

6. The single-photon avalanche diode according to claim 1, characterized in that, Also includes: An oxide layer (50) is configured to be located at least between the isolation region (40) and the interfaces of the first doped region (20), the second doped region (30), and the substrate layer (10).

7. The single-photon avalanche diode according to claim 1, characterized in that, The first doped region (20) and the second doped region (30) are configured to have equal dimensions extending in the horizontal direction.

8. The single-photon avalanche diode according to claim 1, characterized in that, The second doped region (30) is configured such that its edges extend beyond the horizontal edge of the first doped region (20) to fit into the horizontally outer isolation region (40).

9. The single-photon avalanche diode according to claim 1, characterized in that, The first doped region (20) includes a first central doped region (21) and a first edge doped region (22) located at the horizontal outer edge of the first central doped region (21) near the PN junction interface. The net doping concentration of the first edge doped region (22) is configured to be less than the net doping concentration of the first central doped region (21). And / or, The second doped region (30) includes a second central doped region (31) and a second edge doped region (32) located at the horizontal outer edge of the second central doped region (31) near the PN junction interface. The net doping concentration of the second edge doped region (32) is configured to be less than the net doping concentration of the second central doped region (31).

10. The single-photon avalanche diode according to any one of claims 1 to 9, characterized in that, It also includes a third doped region (70) arranged around the outside of the isolation region (40) in the horizontal direction, wherein the impurity concentration of the third doped region (70) is higher than the impurity concentration of the substrate layer (10), and the net doping type of the third doped region (70) is the same as the net doping type of the first doped region (20). The first electrode (61) is configured to be electrically connected to the third doped region (70).

11. The single-photon avalanche diode according to any one of claims 1 to 9, characterized in that, It also includes a fourth doped region (80) located below the substrate layer (10), the impurity concentration of the fourth doped region (80) being higher than the impurity concentration of the substrate layer (10), and the net doping type of the fourth doped region (80) being the same as the net doping type of the first doped region (20). The first electrode (61) is configured to be electrically connected to the fourth doped region (80).

12. The single-photon avalanche diode according to any one of claims 1 to 9, characterized in that, The first doped region (20) has a net doping type of P, the second doped region (30) has a net doping type of N, and the substrate layer (10) is a P-type substrate (11).

13. The single-photon avalanche diode according to any one of claims 1 to 9, characterized in that, The first doped region (20) has a net doping type of N-type, the second doped region (30) has a net doping type of P-type, and the substrate layer (10) includes an N-type buried layer (12) and a P-type substrate (11) located below the N-type buried layer (12).

14. A method for fabricating a single-photon avalanche diode, characterized in that, include: A substrate is provided, and the corresponding positions of the isolation region (40) on the substrate are etched to obtain a substrate with an annular deep trench (44); At least within the annular deep trench (44), a corresponding material is deposited to form a substrate having the isolation region (40); Ion implantation is performed on the internal region of the isolation region (40) of the substrate to form at least a first doped region (20) and a second doped region (30), wherein the second doped region (30) is located above the first doped region (20), and the net doping types of the first doped region (20) and the second doped region (30) are opposite to those of the second doped region (30) to form a PN junction between them, and depletion regions are formed on both sides of the PN junction interface. The isolation region (40) is attached to the outer side of the first doped region (20) and the second doped region (30) in the horizontal direction, and at least covers the region between the upper interface of the second doped region (30) and the lower interface of the first doped region (20) in the height direction. At least a first electrode (61) and a second electrode (62) are formed, wherein the first electrode (61) is electrically connected to the first doped region (20), and the second electrode (62) is electrically connected to the second doped region (30).

15. A photoelectric detection device, characterized in that, Including a single-photon avalanche diode as described in any one of claims 1 to 13, the photodetector is configured to obtain relevant information by sensing the electrical signal generated corresponding to the optical signal received by the single-photon avalanche diode.

16. An electronic device, characterized in that, Including the photoelectric detection device as described in claim 15, the electronic device is configured to perform a corresponding function based on relevant information obtained by the photoelectric detection device from sensing electrical signals.

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