Heterojunction-based bipolar synaptic transistor and preparation method thereof

Abstract

The invention discloses a heterojunction-based bipolar synapse transistor and a preparation method thereof, and the heterojunction-based bipolar synapse transistor comprises a gate layer, a gate insulating layer located on the surface of the gate layer, a charge storage layer located on the surface of the gate insulating layer, and a semiconductor layer located on the surface of the charge storage layer. The drain electrode and the source electrode are located on the surface of the semiconductor layer. The charge storage layer is prepared from n-type N, N '-dioctyl-3, 4, 9, 10-perylene dicarboximide through vacuum evaporation; and the semiconductor layer is prepared by vacuum evaporation of p-type pentacene. According to the transistor prepared by the invention, a balanced bipolar behavior is combined with an effective charge capture mechanism, the functions of a memory and a photoelectric synapse transistor can be realized at the same time, and the transistor has huge application potential in the aspect of constructing a brain-like computing system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, specifically a bipolar synaptic transistor based on a heterojunction and its fabrication method. Background Technology

[0002] Devices that simultaneously realize the functions of memory and photosynaptic transistors have enormous application potential in building neuromorphic computing systems. However, the realization of photoelectric writing operations and the simulation of photosynaptic functions require certain conditions to be met, such as sufficient photon energy and the device's photon absorption efficiency. An ideal synaptic transistor needs the ability to capture charge carriers at different spatial locations and energy levels, achieving multi-level data storage through the effective capture and release of electrons and holes to meet the need for wide-range modulation of synaptic weights. However, the unipolar charge capture mechanism limits the tunability of the synapse due to the limited number of capture sites. Summary of the Invention

[0003] To address the shortcomings of existing unipolar charge trapping mechanisms, this invention provides a bipolar synaptic transistor based on a heterojunction and its fabrication method. The transistor fabricated by this invention combines balanced bipolar behavior with an effective charge trapping mechanism, enabling it to simultaneously realize the functions of a memory and a photoelectric synaptic transistor, and has great application potential in building neuromorphic computing systems.

[0004] Technical solution: A bipolar synaptic transistor based on a heterojunction, the bipolar synaptic transistor based on a heterojunction comprising:

[0005] Gate layer;

[0006] The gate insulating layer located on the surface of the gate layer;

[0007] The charge storage layer located on the surface of the gate insulating layer is formed by vacuum evaporation of n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide;

[0008] A semiconductor layer located on the surface of the charge storage layer is formed by vacuum evaporation of p-type pentacene.

[0009] The drain electrode and source electrode are located on the surface of the semiconductor layer.

[0010] Furthermore, the gate layer material is an n-type heavily doped silicon wafer, the gate insulating layer material is silicon dioxide, and the drain electrode and source electrode material is metallic copper.

[0011] Furthermore, the gate insulating layer has a thickness of 300 nm; the charge storage layer has a thickness of 40 nm; the semiconductor layer has a thickness of 40 nm; and the source electrode and drain electrode have a thickness of 50 nm.

[0012] A method for fabricating a bipolar synaptic transistor based on a heterojunction includes the following steps:

[0013] S1. Grow a gate insulating layer on the surface of the gate layer;

[0014] S2. An n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide is vacuum-deposited on the surface of the gate insulating layer to form a charge storage layer;

[0015] S3. Vacuum evaporation of p-type pentacene on the surface of the charge storage layer to form a semiconductor layer;

[0016] S4. Source and drain electrodes are deposited on the semiconductor layer to obtain a bipolar synaptic transistor based on a heterojunction.

[0017] Furthermore, in S1, the gate layer is made of n-type heavily doped silicon wafer, the gate insulating layer is made of silicon dioxide, and the thickness of the gate insulating layer is 300 nm.

[0018] The gate layer with the grown gate insulating layer was cut into 1.5 × 1.5 cm pieces. 2 After being ultrasonically cleaned in acetone, ethanol and deionized water for 15 min each, the samples were placed in a 120℃ oven for 30 min to dry for later use.

[0019] Furthermore, the specific operation of S2 is as follows:

[0020] The n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide was placed in a crucible, and the crucible and the device obtained in S1 were placed in the vacuum chamber of a vacuum evaporation apparatus; the pressure in the vacuum chamber was controlled to be below 5 × 10⁻⁶. -4 Pa, evaporation rate maintained at 1 Å / s, charge storage layer thickness of 40 nm, and left to stand for 30 min after evaporation.

[0021] Furthermore, the specific operations of S3 are as follows:

[0022] The p-type pentacene is placed into a crucible, and the crucible and the device obtained in S2 are placed into the vacuum chamber of a vacuum evaporation apparatus; the pressure inside the vacuum chamber is controlled to be below 5 × 10⁻⁶. -4 Pa, evaporation rate maintained at 1 Å / s, semiconductor layer thickness of 40 nm, and left to stand for 30 min after evaporation.

[0023] Furthermore, the specific operation of S4 is as follows:

[0024] The copper block and the device obtained in step S3 are placed into the vacuum chamber of a vacuum evaporation apparatus. The mask channel width for the source and drain electrodes is 1500 μm, and the channel length is 100 μm. The pressure inside the vacuum chamber is controlled to be below 5 × 10⁻⁶. -4Pa, the evaporation rate was maintained at 1 Å / s, the thickness of the source electrode and the drain electrode were both 50 nm, and after the evaporation was completed, the electrode was left to stand for 30 min to obtain a bipolar synaptic transistor based on a heterojunction.

[0025] Beneficial effects:

[0026] 1) This invention uses an n-type PTCDI-C8 charge storage layer and a p-type Pentacene semiconductor layer to form a heterojunction. Compared with single-layer PTCDI-C8 and single-layer Pentacene transistor devices, it can simultaneously capture and release electrons and holes. Specifically, at a source-drain voltage of −30 V, the hole mobility is 0.00482 cm⁻¹. 2 / V -1 s -1 Electron mobility 0.00393 cm⁻¹ 2 / V -1 s -1 It exhibits balanced bipolar behavior.

[0027] 2) The bipolar synaptic transistor provided by this invention obtains a storage window of nearly 20 V under the combined action of a 100 V gate bias and white light for 3 s; in the sustain time test, the effective information storage time can reach 11000 s; at the same time, after 110 write / erase cycles, the source drain current of the device does not show significant degradation.

[0028] 3) The bipolar synaptic transistor provided by this invention can realize the simulation of photoelectric synaptic functions, including inhibitory postsynaptic current (IPSC), double pulse facilitation (PPF), number-dependent plasticity (SNDP), and frequency-dependent plasticity (SRDP), under the stimulation of the maximum absorption peak of the charge storage layer material PTCDI-C8 at a wavelength of 475 nm, without additional voltage modulation (gate voltage is 0 V).

[0029] 4) The bipolar synaptic transistor provided by this invention has a simple fabrication process, low cost, and can be fabricated on a large scale. Its balanced bipolar behavior combined with an effective charge trapping mechanism can simultaneously realize the functions of memory and photoelectric synaptic transistor, and has great application potential in building brain-like computing systems. Attached Figure Description

[0030] Figure 1 This is a device structure diagram of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0031] Figure 2 It has the structural formulas of n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide and p-type pentabenzene;

[0032] Figure 3This is the transfer characteristic curve of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0033] Figure 4 This is the output characteristic curve of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0034] Figure 5 This is the forward storage window characteristic curve of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0035] Figure 6 This is the forward storage read / write erase cycle characteristic curve of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0036] Figure 7 This is the forward storage retention time characteristic curve of the bipolar synaptic transistor based on a heterojunction described in this invention;

[0037] Figure 8 The UV-Vis absorption spectrum of the charge storage layer PTCDI-C8 in the heterojunction-based bipolar synaptic transistor described in this invention is shown.

[0038] Figure 9 This is the pulse number and synaptic plasticity characteristic curve of the bipolar synaptic transistor based on heterojunction described in this invention under 475 nm wavelength light stimulation;

[0039] Figure 10 This is the pulse width synaptic plasticity characteristic curve of the bipolar synaptic transistor based on heterojunction described in this invention under 475 nm wavelength light stimulation;

[0040] Figure 11 This is the pulse frequency synaptic plasticity characteristic curve of the bipolar synaptic transistor based on heterojunction described in this invention under 475 nm wavelength light stimulation;

[0041] Figure 12 This is the pulse intensity synaptic plasticity characteristic curve of the bipolar synaptic transistor based on heterojunction described in this invention under 475 nm wavelength light stimulation.

[0042] Figure 13 The curves show the double-pulse facilitation index of the fabricated bipolar synaptic transistor based on a heterojunction under 475 nm wavelength light stimulation, based on the pulse interval. Detailed Implementation

[0043] The technical solution of the present invention will be described in detail below through embodiments, but the scope of protection of the present invention is not limited to the embodiments described.

[0044] In the following examples, the gate layer with the gate insulating layer was purchased from Suzhou Crystal Silicon Electronics Technology Co., Ltd. Acetone was purchased from Shanghai Lingfeng Chemical Reagent Co., Ltd., and ethanol was purchased from Sinopharm Chemical Reagent Co., Ltd. n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8), p-type pentacene, and metallic copper were all purchased from Sigma-Aldrich Trading Co., Ltd.

[0045] Example 1

[0046] This embodiment provides a bipolar synaptic transistor based on a heterojunction, the structure of which is as follows: Figure 1 As shown, the bipolar synaptic transistor includes: a gate layer 1; a gate insulating layer 2 located on the surface of the gate layer 1; a charge storage layer 3 located on the surface of the gate insulating layer 2; a semiconductor layer 4 located on the surface of the charge storage layer 3; and a drain electrode 5 and a source electrode 6 located on the surface of the semiconductor layer 4. The charge storage layer is formed by vacuum evaporation of n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide; the semiconductor layer is formed by vacuum evaporation of p-type pentacene.

[0047] The structural formulas of n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide and p-type pentabenzene are as follows: Figure 2 As shown in the image.

[0048] The fabrication method of the heterojunction-based bipolar synaptic transistor is as follows:

[0049] S1, the gate layer with the grown gate insulating layer is cut into 1.5 × 1.5 cm pieces. 2 After being ultrasonically cleaned in acetone, ethanol and deionized water for 15 min each, the samples were placed in a 120℃ oven for 30 min to dry for later use.

[0050] The gate layer is made of n-type heavily doped silicon wafer, the gate insulating layer is made of silicon dioxide, and the thickness of the gate insulating layer is 300 nm.

[0051] S2, deposit a charge storage layer on the surface of the gate insulating layer.

[0052] Remove n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide from the vial and place it into a clean crucible. Place the crucible and the device obtained in S1 into a vacuum evaporation apparatus, controlling the pressure inside the vacuum chamber to be below 5 × 10⁻⁶. -4 Pa, the evaporation rate was maintained at 1 Å / s, the charge storage layer thickness was 40 nm, and the layer was left to stand for 30 min after evaporation.

[0053] S3, deposit a semiconductor layer on the surface of the charge storage layer.

[0054] Remove the p-type pentacene from the vial and place it into a clean crucible. Place the crucible and the device obtained in S2 into a vacuum evaporation apparatus, controlling the pressure inside the vacuum chamber to be below 5 × 10⁻⁶. -4 Pa, the evaporation rate was maintained at 1 Å / s, the semiconductor layer thickness was 40 nm, and the layer was left to stand for 30 min after evaporation.

[0055] S4, source electrode and drain electrode are deposited on the semiconductor layer by vapor deposition.

[0056] The copper block and the device obtained in S3 were placed into a vacuum evaporation apparatus. The mask channel width for the source and drain electrodes was 1500 μm, and the channel length was 100 μm. The pressure inside the vacuum chamber was controlled to be below 5 × 10⁻⁶. -4 Pa, the evaporation rate was maintained at 1 Å / s, the thickness of the source electrode and the drain electrode were both 50 nm, and after the evaporation was completed, the electrode was left to stand for 30 min to obtain a bipolar synaptic transistor based on a heterojunction.

[0057] The performance of the fabricated bipolar synaptic transistor device was tested using a Keithley 4200 SCS semiconductor parameter analyzer. The test results are as follows:

[0058] Figure 3 These are the transfer characteristic curves of the fabricated bipolar synaptic transistor based on a heterojunction. The transfer curves were tested at different source-drain voltages of -30 V, -40 V, and -50 V, respectively. It can be seen that the device exhibits balanced bipolar behavior. At a source-drain voltage of -30 V, according to the formula... The hole mobility was found to be 0.00482 cm. 2 / V -1 s -1 Electron mobility 0.00393 cm⁻¹ 2 / V -1 s -1 .

[0059] Figure 4 The output characteristic curves of the fabricated bipolar synaptic transistor based on heterojunction are shown. The output curves were tested at different gate voltages of 0 V, -5 V, -10 V, -15 V, -20 V, and -25 V, respectively. It can be seen that the device has good field effect.

[0060] Figure 5 The curve shows the forward storage window characteristics of the fabricated bipolar synaptic transistor based on a heterojunction. Under a gate bias of 100 V and white light for 3 s, the device achieves a storage window of nearly 20 V.

[0061] Figure 6The curves show the forward storage read / write / erase cycle characteristics of the fabricated bipolar synaptic transistor based on a heterojunction. After 110 write / erase cycles at a gate voltage of -3 V, the source and drain currents of the device did not show significant degradation.

[0062] Figure 7 The curve shows the forward storage sustaining time characteristic of the fabricated bipolar synaptic transistor based on a heterojunction. At a gate voltage of -3V, the device can effectively trap charge and remain stable after 11000 s.

[0063] Figure 8 The image shows the UV-Vis absorption spectrum of the charge storage layer PTCDI-C8 in the fabricated heterojunction-based bipolar synaptic transistor. The specific testing procedure was as follows: the device obtained in S2 was tested using a LAMBDA 650 UV-Vis-NIR spectrophotometer. The results showed that the maximum absorption peak of PTCDI-C8 was 475 nm.

[0064] Figure 9 , Figure 10 , Figure 11 , Figure 12 These are the synaptic plasticity characteristic curves of the fabricated bipolar synaptic transistor based on a heterojunction under 475 nm wavelength light stimulation, including pulse number, pulse width, pulse frequency, and pulse intensity. By changing the pulse number, width, frequency, and intensity, the device can be transformed from short-term plasticity to long-term plasticity.

[0065] Figure 13 The curves show the double-pulse facilitation index of the fabricated bipolar synaptic transistor based on the heterojunction under 475 nm wavelength light stimulation, based on the pulse interval. As the pulse interval increases, the double-pulse facilitation index decreases (the double-pulse facilitation index is defined as the ratio of the amplitude of the second pulse response to the amplitude of the first pulse response, and is presented as a percentage).

[0066] In summary, this invention relates to a bipolar synaptic transistor based on a heterojunction and its fabrication method. Its balanced bipolar behavior combined with an effective charge trapping mechanism enables it to simultaneously realize the functions of a memory and a photoelectric synaptic transistor, and has great application potential in building brain-like computing systems.

[0067] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

1. A bipolar synaptic transistor based on a heterojunction, characterized in that, The heterojunction-based bipolar synaptic transistor includes: Gate layer; The gate insulating layer located on the surface of the gate layer; The charge storage layer located on the surface of the gate insulating layer is formed by vacuum evaporation of n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide; A semiconductor layer located on the surface of the charge storage layer is formed by vacuum evaporation of p-type pentacene. The drain electrode and source electrode are located on the surface of the semiconductor layer.

2. The bipolar synaptic transistor based on a heterojunction according to claim 1, characterized in that, The gate layer material is an n-type heavily doped silicon wafer, the gate insulating layer material is silicon dioxide, and the drain electrode and source electrode material is metallic copper.

3. The bipolar synaptic transistor based on a heterojunction according to claim 1, characterized in that, The gate insulating layer has a thickness of 300 nm; the charge storage layer has a thickness of 40 nm; the semiconductor layer has a thickness of 40 nm; and the source electrode and drain electrode have a thickness of 50 nm.

4. The method for fabricating a bipolar synaptic transistor according to claim 1, characterized in that, Includes the following steps: S1. Grow a gate insulating layer on the surface of the gate layer; S2. An n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide is vacuum-deposited on the surface of the gate insulating layer to form a charge storage layer; S3. Vacuum evaporation of p-type pentacene on the surface of the charge storage layer to form a semiconductor layer; S4. Source and drain electrodes are deposited on the semiconductor layer to obtain a bipolar synaptic transistor based on a heterojunction.

5. The preparation method according to claim 4, characterized in that, In S1, the gate layer is made of n-type heavily doped silicon wafer, the gate insulating layer is made of silicon dioxide, and the thickness of the gate insulating layer is 300 nm. The gate layer with the grown gate insulating layer was cut into 1.5 × 1.5 cm pieces. 2 After being ultrasonically cleaned in acetone, ethanol and deionized water for 15 minutes each, they were placed in a 120℃ oven for 30 minutes to dry for later use.

6. The preparation method according to claim 4, characterized in that, The specific operation of S2 is as follows: The n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide is placed in a crucible, and the crucible and the device obtained in S1 are placed in the vacuum chamber of a vacuum evaporation equipment. Control the pressure inside the vacuum chamber to be below 5×10 -4 Pa, evaporation rate maintained at 1 Å / s, charge storage layer thickness of 40 nm, and left to stand for 30 min after evaporation.

7. The preparation method according to claim 4, characterized in that, The specific operation of S3 is as follows: The p-type pentacene is placed into a crucible, and the crucible and the device obtained in S2 are placed into the vacuum chamber of the vacuum evaporation equipment. Control the pressure inside the vacuum chamber to be below 5×10 -4 Pa, evaporation rate maintained at 1 Å / s, semiconductor layer thickness of 40 nm, and left to stand for 30 min after evaporation.

8. The preparation method according to claim 4, characterized in that, The specific operation of S4 is as follows: The copper block and the device obtained in S3 are placed into the vacuum chamber of the vacuum evaporation equipment. The mask channel width of the source electrode and the drain electrode is 1500 μm and the channel length is 100 μm. Control the pressure inside the vacuum chamber to be below 5×10 -4 Pa, the evaporation rate was maintained at 1 Å / s, the thickness of the source electrode and the drain electrode were both 50 nm, and after evaporation, the electrode was left to stand for 30 min to obtain a bipolar synaptic transistor based on a heterojunction.

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