Capacitor dielectric layer, preparation method thereof and capacitor structure

Abstract

The invention discloses a capacitor dielectric layer and a preparation method thereof and a capacitor structure, the capacitor dielectric layer comprises at least two of a first lamination layer, a second lamination layer and a third lamination layer which are stacked along a first direction, and each lamination layer comprises a first dielectric layer and a second dielectric layer, the main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthogonal structure phase, and the main crystal phase of the second dielectric layer is at least one of the tetragonal structure phase and the orthogonal structure phase. The capacitor dielectric layer has a high dielectric constant and a low leakage current.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a capacitor dielectric layer, its preparation method, and capacitor structure. Background Technology

[0002] As semiconductor chips continue to evolve and their key dimensions shrink, semiconductor chips, such as Dynamic Random Access Memory (DRAM), consist of arrayed memory cells, each containing a transistor and a capacitor. Achieving higher dielectric constants and lower leakage currents in DRAM capacitors has become crucial to DRAM chip development. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a capacitor dielectric layer is provided, the capacitor dielectric layer comprising at least two of a first stack, a second stack, and a third stack stacked along a first direction, wherein the first stack comprises at least one first unit stacked along the first direction, the second stack comprises at least one second unit stacked along the first direction, and the third stack comprises at least one third unit stacked along the first direction; the first unit comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction; the second unit comprises a second dielectric layer and a first dielectric layer stacked along the first direction; and the third unit comprises a first dielectric layer and a second dielectric layer stacked along the first direction; wherein the main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase, and the main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

[0004] In some embodiments, the capacitor dielectric layer further includes a barrier layer located on each of the first stack, the second stack, and the third stack.

[0005] In some embodiments, the capacitor dielectric layer includes the third stack, the barrier layer, the first stack, and the barrier layer stacked along the first direction.

[0006] In some embodiments, the capacitor dielectric layer includes the third stack, the barrier layer, the second stack, and the barrier layer stacked along the first direction.

[0007] In some embodiments, the capacitor dielectric layer includes a first stack, the barrier layer, the first stack, and the barrier layer stacked along the first direction.

[0008] In some embodiments, the capacitor dielectric layer includes any two of the first stack, the second stack, and the third stack stacked along the first direction, wherein the thickness ratio of the two stacks is in the range of (0.4-2.5):1.

[0009] In some embodiments, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where,

[0010] The first stack is Z a H b (Z 2a H b ) c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a Stacked along the first direction, the Z in the sub-stacked structure 2a and the H b The first stacked layers are arranged along the first direction, with a total thickness of 2.4 nm-6 nm, 1 ≤ a / b ≤ 20, where c1 is the number of the first units in the first stacked layers, and the first unit is represented by a Z-shaped stack arranged along the first direction. a H b and Z a The first layered structure is formed, wherein c1 is a positive integer and 1≤c1≤30; and / or

[0011] The second stack is (H) b Z a ) c2 In the second stack, c2 second units are stacked along the first direction, and the second unit is represented by H units stacked along the first direction. b and Z a The second stacked structure is formed, wherein the total thickness of the second stacked layer is 2.4nm-6nm, 1≤a / b≤20, and c2 is a positive integer and 1≤c2≤50; and / or

[0012] The third stack is (Z) a H b ) c3In the third stack, c3 third units are stacked along the first direction, and the third unit is represented by Z units stacked along the first direction. a and H b The third stacked structure is formed, the total thickness of the third stack is 2.4nm-6nm, 1≤a / b≤20, and c3 is a positive integer and 1≤c3≤50.

[0013] In some embodiments, the thickness of the barrier layer is 0.07 nm to 0.4 nm.

[0014] In some embodiments, the total thickness of the capacitor dielectric layer is 5nm-9nm.

[0015] In some embodiments, the material of the first dielectric layer includes zirconium oxide.

[0016] In some embodiments, the material of the second dielectric layer includes at least one selected from hafnium oxide, titanium oxide, niobium oxide, yttrium oxide, lanthanum oxide, and tantalum oxide.

[0017] In some embodiments, the material of the barrier layer includes at least one of aluminum oxide, silicon oxide, niobium oxide, silicon-doped niobium oxide, silicon-doped hafnium oxide, and lanthanum oxide. The band gap of the barrier layer is greater than the band gap of the first dielectric layer, and the band gap of the barrier layer is greater than the band gap of the second dielectric layer.

[0018] According to a second aspect of the present disclosure, a capacitor structure is provided, including a first electrode layer, a second electrode layer, and a capacitor dielectric layer as described in any of the first aspects, wherein the capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

[0019] According to a third aspect of the present disclosure, a method for fabricating a capacitor dielectric layer is provided, the method comprising forming at least two of a first stack, a second stack, and a third stack disposed along a first direction, wherein...

[0020] The first stack includes at least one first unit stacked along the first direction; the second stack includes at least one second unit stacked along the first direction; and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase. The main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

[0021] In some embodiments, the preparation method further includes forming a barrier layer on each of the first stack, the second stack, and the third stack.

[0022] In some embodiments, the fabrication method includes: forming the third stack, the barrier layer, the first stack, and the barrier layer stacked together along the first direction.

[0023] In some embodiments, the fabrication method includes: forming the third stack, the barrier layer, the second stack, and the barrier layer stacked along the first direction.

[0024] In some embodiments, the preparation method includes: forming a first stacked layer, a barrier layer, the first stacked layer, and the barrier layer along the first direction.

[0025] In some embodiments, forming at least two of the first, second, and third stacks stacked along a first direction includes forming any two of the first, second, and third stacks stacked along the first direction, wherein the thickness ratio of the two stacks is in the range of (0.4-2.5):1.

[0026] In some embodiments, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where,

[0027] Forming the first stack includes:

[0028] (11) The Z-shaped structure is formed using a first atomic layer deposition process. a The Z-shaped layer is formed using the first atomic layer deposition process. a The process includes a1 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a ;

[0029] (12) The Z formed in step (11) is carried out along the first direction using a second atomic layer deposition process. a The H formed above b The H is formed using the second atomic layer deposition process. bThe process includes b1 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. b1 of the second sub-dielectric layers constitute the H. b ;

[0030] (13) The H formed in step (12) is constructed using a third atomic layer deposition process along the first direction. b The Z is formed again above a The Z-layer is formed using the third atomic layer deposition process. a The process includes a1 cycles of growing the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a The Z-shaped stacked arrangement formed along the first direction a The H b and the Z a This constitutes a first unit;

[0031] (14) Repeat steps (11)-(13) c1 times to obtain the first stack, wherein a1, b1, and c1 satisfy: 1≤a1 / b1≤20, c1 is the number of the first units in the first stack, c1 is a positive integer and 1≤c1≤30, 30≤(2a1+b1)*c1≤60, and satisfies: the first stack is Z a H b (Z 2a H b ) c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a Stacked along the first direction, the Z in the sub-stacked structure 2a and the H b Stacked along the first direction, the total thickness of the first stack is 2.4nm-6nm, 1≤a / b≤20; and / or

[0032] Forming the second stack includes:

[0033] (21) The H was formed using a fourth atomic layer deposition process. b The H is formed using the fourth atomic layer deposition process. b The process includes b2 cyclic growth cycles of the second sub-dielectric layer. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b2 second sub-dielectric layers constitute the H.b ;

[0034] (22) The H formed in step (21) is obtained by using a fifth atomic layer deposition process along the first direction. b The Z formed above a The Z-layer is formed using the fifth atomic layer deposition process. a The process includes a2 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a2 first sub-dielectric layers constitute the Z. a The H stacked along the first direction b and the Z a This constitutes a second unit;

[0035] (23) Repeat steps (21)-(22) c2 times to obtain the second stack, wherein a2, b2, and c2 satisfy: 1≤a2 / b2≤20, c2 is the number of the second units in the second stack, c2 is a positive integer and 1≤c2≤50, 30≤(a2+b2)*c2≤60, and satisfies: the second stack is (H b Z a ) c2 In the second stack, c2 second units are stacked along the first direction, and the total thickness of the second stack is 2.4nm-6nm, 1≤a / b≤20; and / or

[0036] Forming the third stack includes:

[0037] (31) The Z-shaped structure was formed using a sixth atomic layer deposition process. a The Z-layer is formed using the sixth atomic layer deposition process. a The process includes a3 cycles of first sub-dielectric layer growth. After each first sub-dielectric layer growth cycle is completed, a first sub-dielectric layer is formed. The a3 first sub-dielectric layers constitute the Z. a ;

[0038] (32) The Z-shaped layer formed in step (31) along the first direction using a seventh atomic layer deposition process. a The H formed above b The H is formed using the seventh atomic layer deposition process. b The process includes b3 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b3 second sub-dielectric layers constitute the H. b The Z-shaped stacked arrangement formed along the first direction a and the H b This constitutes one of the aforementioned third units;

[0039] (33) Repeat steps (31)-(32) c3 times to obtain the third stack, wherein a3, b3, and c3 satisfy: 1≤a3 / b3≤20, c3 is the number of the third units in the third stack, c3 is a positive integer and 1≤c3≤50, 30≤(a3+b3)*c3≤60, and satisfies: the third stack is (Z a H b ) c3 In the third stack, c3 third units are stacked along the first direction, and the total thickness of the third stack is 2.4nm-6nm, 1≤a / b≤20.

[0040] In some embodiments, forming the barrier layer includes: forming the barrier layer using an eighth atomic layer deposition process. The process of forming the barrier layer using the eighth atomic layer deposition process includes d1 sub-barrier layer growth cycles. After the sub-barrier layer growth cycle is completed, a sub-barrier layer is formed. The d1 sub-barrier layers constitute the barrier layer, where d1 is 1-4, and the thickness of the barrier layer is 0.07nm-0.4nm.

[0041] In this embodiment of the disclosure, the capacitor dielectric layer is a stacked structure, including at least two of a first stack, a second stack, and a third stack stacked along a first direction. The first stack includes at least one first unit stacked along the first direction, the second stack includes at least one second unit stacked along the first direction, and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase (mainly a tetragonal structure phase), and the main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase (mainly a tetragonal structure phase). In this stacked structure comprising at least two layers, the second dielectric layer (e.g., hafnium oxide layer) whose main crystalline phase is at least one of a tetragonal structure phase and an orthorhombic structure phase can be a ferroelectric material that has ferroelectric or antiferroelectric properties according to an electric field. By using a second dielectric layer (e.g., hafnium oxide layer) with ferroelectric or antiferroelectric properties, the dielectric constant of the stacked structure can be increased. Such a stacked structure can satisfy higher dielectric constant and lower leakage current, for example, satisfying the requirements of capacitors for high capacitance and low leakage current. Attached Figure Description

[0042] Figure 1 This is a schematic cross-sectional view of a capacitor dielectric layer according to an exemplary embodiment of the present disclosure;

[0043] Figure 2 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure;

[0044] Figure 3 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure;

[0045] Figure 4 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure;

[0046] Figure 5 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure;

[0047] Figure 6 This is a schematic cross-sectional view of the first stacked structure shown in an exemplary embodiment of this disclosure;

[0048] Figure 7 This is a schematic cross-sectional view of the second stacked structure shown in an exemplary embodiment of this disclosure;

[0049] Figure 8 This is a schematic cross-sectional view of the third stacked layer shown in an exemplary embodiment of this disclosure;

[0050] Figure 9 This is in the public disclosure Figure 3 The diagram shows the fabrication process of the capacitor dielectric layer.

[0051] Figure 10 This is in the public disclosure Figure 4 The diagram shows the fabrication process of the capacitor dielectric layer.

[0052] Figure 11 This is in the public disclosure Figure 5 The diagram shows the fabrication process of the capacitor dielectric layer.

[0053] Figure 12 This is in the public disclosure Figure 6 The diagram shows the fabrication process of the first stacked layer;

[0054] Figure 13 This is in the public disclosure Figure 7 The diagram shows the preparation process of the second stack;

[0055] Figure 14 This is in the public disclosure Figure 8 The diagram shows the preparation process of the third layer. Detailed Implementation

[0056] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0057] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0058] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0059] In the embodiments of this disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0060] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0061] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0062] The term "high dielectric constant" refers to a dielectric constant value higher than 3.9, and "high dielectric constant material" refers to a material with a dielectric constant higher than 3.9.

[0063] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0064] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has changed from 8F2 to 6F. 2 Then go to 4F 2 The architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0065] In some embodiments of this disclosure, whether planar transistors or buried transistors, dynamic random access memory includes multiple memory cells. Each memory cell is mainly composed of a transistor and a memory structure (memory capacitor) controlled by the transistor. That is, dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0066] The capacitor dielectric layer involved in the embodiments of this disclosure is at least a portion that will be used in subsequent processes to form the final device structure.

[0067] Here, the final device may include capacitors, memory, etc. The memory includes, but is not limited to, DRAM; the following description uses DRAM as an example only.

[0068] However, it should be noted that the following description of DRAM in the embodiments is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0069] With the development of DRAM technology, the size of memory cells is becoming smaller and smaller. How to achieve higher dielectric constants and lower leakage currents in DRAM capacitors has become the key to the success or failure of DRAM chip development. Developing capacitor dielectric layers with higher dielectric constants and lower leakage currents has become an urgent problem to be solved.

[0070] Silicon has a dielectric constant (K) of approximately 11.5. Currently, the dielectric layer of capacitors is mainly obtained by crystallizing zirconium oxide (ZrO) into a tetragonal structure to achieve a high dielectric constant (approximately 47). Therefore, zirconium oxide is widely used in dynamic random access capacitors (DRAMs). Zirconia can crystallize at 260℃-350℃ to form monoclinic, cubic, or tetragonal structures at a certain thickness. However, hafnium oxide (HfO) usually does not crystallize or forms a monoclinic phase when deposited as a thin film at 300℃. The application of pure hafnium oxide in High K films cannot achieve a high dielectric constant (the K value is relatively low, generally around 25), and may even result in thin film materials with high leakage current. Hafnium oxide with a tetragonal structure can achieve a dielectric constant (K) of up to 70. Therefore, the key lies in how to form hafnium oxide layers with tetragonal or even orthorhombic structures. Therefore, it is crucial to form a capacitor dielectric layer with a stacked structure including a first dielectric layer (such as zirconium oxide) and a second dielectric layer (such as hafnium oxide), such that the first dielectric layer (such as zirconium oxide) and the second dielectric layer (such as hafnium oxide) can crystallize simultaneously and that the main crystal phases of the first dielectric layer (such as zirconium oxide) and the second dielectric layer (such as hafnium oxide) are both tetragonal or even orthorhombic phases, so as to obtain high K materials with high dielectric constant and low leakage current.

[0071] This disclosure provides a capacitor dielectric layer, its preparation method, and a capacitor structure.

[0072] In this context and below, the first direction refers to the direction parallel to the thickness of each process layer, which can also be understood as the stacking direction of the formed process layers. Specifically, it can be a direction parallel to the thickness of each process layer, pointing from the second electrode layer below the first electrode layer in the capacitor structure to the first electrode layer above the first electrode layer. The second and third directions are two orthogonal directions perpendicular to the direction of each process layer thickness. For example, the first direction is represented by the Z direction in the attached figure; the second direction is represented by the X direction in the attached figure; and the third direction is represented by the Y direction in the attached figure.

[0073] Figure 1 This is a schematic cross-sectional view of a capacitor dielectric layer according to an exemplary embodiment of the present disclosure; Figure 2 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure; Figure 3 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure; Figure 4 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure; Figure 5 This is a schematic cross-sectional view of a capacitor dielectric layer shown in another exemplary embodiment of this disclosure; Figure 6 This is a schematic cross-sectional view of the first stacked structure shown in an exemplary embodiment of this disclosure; Figure 7 A schematic cross-sectional view of the second stacked structure is shown in an exemplary embodiment of this disclosure; Figure 8 This disclosure presents an exemplary embodiment illustrating a cross-sectional structural diagram of a third stack; the following will be combined with... Figures 1 to 8 The structure of the capacitor's dielectric layer is explained.

[0074] According to a first aspect of the embodiments of this disclosure, such as Figures 1-8 As shown, a capacitor dielectric layer is provided, comprising at least two of a first stack, a second stack, and a third stack stacked along a first direction. The first stack includes at least one first unit stacked along the first direction; the second stack includes at least one second unit stacked along the first direction; and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase, and the main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

[0075] In the embodiments described herein and below, for ease of description, the capacitor dielectric layer is a stacked structure. The term "stacked structure" needs to be understood adaptively in conjunction with specific embodiments or application scenarios, and unless otherwise specified, it is not intended to limit the embodiments of this disclosure. Exemplarily, in the embodiments of this disclosure, the capacitor dielectric layer includes at least two of any two of a first stack, a second stack, and a third stack stacked along a first direction (e.g., ...). Figure 1 As shown, the capacitor dielectric layer 4000 includes a third stacked layer 300 and a first stacked layer 100 stacked along the first direction Z; as Figure 2 As shown, the capacitor dielectric layer 5000 includes a third stack 300, a first stack 100, and a second stack 200 stacked along the first direction Z; at least two stacks can be arbitrarily selected from the first, second, and third stacks (not all stacks are shown here); however, in some embodiments, the capacitor dielectric layer includes at least two of the first, second, and third stacks stacked along the first direction, and a barrier layer located on each of the first, second, and third stacks (e.g., ...). Figures 3-5 As shown, a barrier layer 400 is provided on each stack, and at least two stacks can be arbitrarily selected from the first stack, the second stack, and the third stack (not all stacks are shown here).

[0076] In some embodiments, such as Figure 6As shown, the first stack 100 includes at least one first unit 10 stacked along the first direction Z, and the first unit 10 includes a first dielectric layer 1, a second dielectric layer 2 and a first dielectric layer 1 stacked along the first direction Z.

[0077] In some embodiments, such as Figure 7 As shown, the second stack 200 includes at least one second unit 20 stacked along the first direction Z, and the second unit 20 includes a second dielectric layer 2 and a first dielectric layer 1 stacked along the first direction Z.

[0078] In some embodiments, such as Figure 8 As shown, the third stack 300 includes at least one third unit 30 stacked along the first direction Z, and the third unit 30 includes the first dielectric layer 1 and the second dielectric layer 2 stacked along the first direction Z.

[0079] In the embodiments of this disclosure, the main crystalline phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase, and the main crystalline phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase. This can be understood as follows: the main crystalline phases of the first and second dielectric layers are each independently one or both of a tetragonal structure phase and an orthorhombic structure phase. For example, in a specific embodiment, the main crystalline phase of the first dielectric layer is a tetragonal structure phase, and the main crystalline phase of the second dielectric layer is a tetragonal structure phase and / or an orthorhombic structure phase (when both tetragonal and orthorhombic structure phases are included, the crystalline phase is still predominantly tetragonal). Specifically, the main crystalline phase of the first dielectric layer being a tetragonal structure phase can be understood as follows: based on the cross-section of the capacitor dielectric layer, 80%, 85%, or 95% or more of the crystalline phase of the capacitor dielectric layer is a tetragonal structure phase. The dominant crystalline phase of the second dielectric layer is a tetragonal and / or orthorhombic phase. Specifically, this can be understood as follows: based on the cross-section of the capacitor dielectric layer, 80%, 85%, or 95% or more of the capacitor dielectric layer has a tetragonal and / or orthorhombic phase (when both tetragonal and orthorhombic phases are included, the tetragonal phase is still dominant). Other types of dominant crystalline phases can be understood similarly and will not be elaborated here.

[0080] The dielectric layer of a capacitor is a multilayer structure, which can be a ferroelectric material that exhibits ferroelectric or antiferroelectric properties depending on the electric field. The dielectric constant of ferroelectric materials can be significantly increased within the switching voltage range, which is the voltage range from which ferroelectric properties can transition to antiferroelectric properties or vice versa. Therefore, the capacitor can possess a high dielectric constant within its operating voltage range.

[0081] The second dielectric layer (e.g., a hafnium oxide layer with a tetragonal main crystal phase) can be a ferroelectric material that exhibits ferroelectric or antiferroelectric properties depending on the electric field. The dielectric constant of the stacked structure can be increased by using a second dielectric layer with ferroelectric or antiferroelectric properties (e.g., a hafnium oxide layer with a tetragonal main crystal phase). (The dielectric constant of a hafnium oxide layer with a tetragonal main crystal phase can reach 70 or higher, while a hafnium oxide layer with a monoclinic phase or an amorphous hafnium oxide layer does not exhibit ferroelectric properties and has a lower dielectric constant K value, typically around 25.) Such a stacked structure can satisfy the requirement for a high dielectric constant, for example, meeting the high capacitance requirements of capacitors.

[0082] Therefore, the dielectric constant of the capacitor's dielectric layer can be increased by using a second dielectric layer with ferroelectric properties (e.g., a hafnium oxide layer with a tetragonal main crystal phase).

[0083] In embodiments of this disclosure, the capacitor dielectric layer further includes a barrier layer located on each of the first stack, the second stack, and the third stack.

[0084] In the embodiments of this disclosure, a barrier layer is provided on each of the first, second, and third stacks, which can further block the leakage path of the capacitor dielectric layer, thereby improving the capacitance value of the capacitor dielectric layer and reducing the leakage current. Therefore, the capacitor dielectric layer including the barrier layer can meet the requirements of high dielectric constant and low leakage current, for example, meeting the requirements of capacitors for high capacitance value and low leakage current.

[0085] In the embodiments of this disclosure, the thickness of the barrier layer is 0.07nm-0.4nm. The barrier layer's effectiveness in blocking leakage current is not highly correlated with its thickness. In order to control the dielectric constant K value through the first and second dielectric layers and avoid the barrier layer's excessive thickness from having a significant impact on the dielectric constant K value, the thickness of the barrier layer needs to be controlled to be 0.07nm-0.4nm.

[0086] In one embodiment of this disclosure, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where,

[0087] The first stack is Z a H b (Z 2a H b )c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a The sub-stacked structure is stacked along the first direction Z, wherein the Z... 2a and the H b The first stack is arranged in a Z-direction, with a total thickness of 2.4 nm to 6 nm, where 1 ≤ a / b ≤ 20. c1 represents the number of first units in the first stack, and each first unit is represented by a Z-shaped stack arranged in the first direction. a H b and Z a The first stacked structure is formed, where c1 is a positive integer and 1≤c1≤30. In this first stack, the bottom first dielectric layer (such as a zirconium oxide layer) acts as the nucleating phase and crystallizes into a tetragonal structure. The second dielectric layer (such as a hafnium oxide layer) will continue to nucleate on the basis of the nucleation of the bottom first dielectric layer. After reaching a certain thickness, it can crystallize. If the first dielectric layer continues to be deposited, the surface energy of the first and second dielectric layers can be effectively reduced, thereby reducing the formation of the monoclinic phase (M-phase) and increasing the probability of the second dielectric layer (such as the hafnium oxide layer) forming a tetragonal structure.

[0088] The second stack is (H) b Z a ) c2 In the second stack, c2 second units are stacked along the first direction Z, and the second unit is represented by H units stacked along the first direction Z. b and Z a The second stacked structure has a total thickness of 2.4 nm-6 nm, where 1 ≤ a / b ≤ 20, and c2 is a positive integer with 1 ≤ c2 ≤ 50. In this second stack, the bottom second dielectric layer (such as a hafnium oxide layer) does not crystallize as a substrate. After the first dielectric layer (such as a zirconium oxide layer) is deposited on the second dielectric layer (such as a hafnium oxide layer) to a certain thickness, it will spontaneously crystallize into a tetragonal phase and induce the second dielectric layer (such as a hafnium oxide layer) to nucleate and crystallize into a tetragonal phase. Therefore, the crystallinity of this second stack is also relatively good.

[0089] The third stack is (Z) a H b ) c3 In the third stack, c3 third units are stacked along the first direction Z, and the third unit is represented by Z units stacked along the first direction Z. a and H bThe third stacked structure has a total thickness of 2.4 nm to 6 nm, where 1 ≤ a / b ≤ 20, and c3 is a positive integer where 1 ≤ c3 ≤ 50. In this third stacked structure, the bottom first dielectric layer (such as a zirconium oxide layer) is the nucleating phase and crystallizes into a tetragonal structure. The second dielectric layer (such as a hafnium oxide layer) continues to nucleate based on the nucleation of the bottom first dielectric layer (such as a zirconium oxide layer), and can crystallize into a tetragonal structure after reaching a certain thickness.

[0090] In this disclosure, by controlling the aforementioned specific combination and ratio of the first dielectric layer (such as a zirconium oxide layer) and the second dielectric layer (such as a hafnium oxide layer), the first dielectric layer (such as a zirconium oxide layer) and the second dielectric layer (such as a hafnium oxide layer) have almost the same lattice parameters. By adjusting the thickness ratio of the first dielectric layer (such as a zirconium oxide layer) in the stack, the energy barrier required for the crystallization of the second dielectric layer (such as a hafnium oxide layer) can be effectively reduced, the crystallization state of the second dielectric layer (such as a hafnium oxide layer) can be changed, and a barrier layer can be formed on the stack, which can further effectively block the leakage path of the capacitor dielectric layer.

[0091] The a / b ratio determines the type of structural phase formed (e.g., monoclinic, cubic, tetragonal, or orthorhombic). A higher a / b ratio increases the probability of forming a tetragonal phase and results in a higher dielectric constant for the resulting capacitor dielectric layer. However, the a / b ratio should not be too large, as this can lead to excessively large grains. When the a / b ratio decreases, stress caused by lattice mismatch at the interface between the first dielectric layer (e.g., zirconium oxide layer) and the second dielectric layer (e.g., hafnium oxide layer) is relaxed, making it easier for the second dielectric layer (e.g., hafnium oxide layer) to transform from a tetragonal phase to a monoclinic phase, which is detrimental to improving the dielectric constant K value of the stacked structure. Therefore, it is necessary to control the a / b ratio to control the degree of crystallinity, aiming to form more tetragonal phases without causing excessive grain growth. Therefore, based on the above considerations, 1 ≤ a / b ≤ 20, and preferably, 3 ≤ a / b ≤ 5.

[0092] The total thickness of each of the first, second, and third layers is independently between 2.4 nm and 6 nm. Maintaining the thickness of each layer within the aforementioned range is the key thickness required for the crystallization of the second dielectric layer (such as a hafnium oxide layer). This allows for the presence of stress at the interface between the first and second dielectric layers (such as a hafnium oxide layer) with a tetragonal structure, preventing stress relaxation. This enables the second dielectric layer (such as a hafnium oxide layer) to form a tetragonal structure under stress and avoids the formation of a monoclinic phase, which is beneficial for increasing the dielectric constant K value of the stacked structure.

[0093] Therefore, by controlling the aforementioned a / b ratio, the total thickness of the first, second, and third stacks, and the values ​​of c1, c2, and c3, a certain stress caused by lattice mismatch exists at the interface between the first dielectric layer with a tetragonal crystal phase and the second dielectric layer with a tetragonal crystal phase (such as a hafnium oxide layer). The presence of this stress causes the second dielectric layer (such as a hafnium oxide layer) to be deposited as a tetragonal crystal phase within a certain thickness range, thus minimizing the Gibbs free energy of the entire stacked structure. The second dielectric layer with a tetragonal crystal phase can be a ferroelectric material with ferroelectric or antiferroelectric properties based on the electric field. By using a second dielectric layer with ferroelectric or antiferroelectric properties to increase the dielectric constant of the stacked structure, the dielectric constant K value of the entire stacked structure can be increased, maximizing the K value. The resulting capacitor dielectric layer can satisfy the requirements of high dielectric constant and low leakage current.

[0094] In one embodiment of this disclosure, the total thickness of the capacitor dielectric layer can be 5nm-9nm.

[0095] In one embodiment of this disclosure, the material of the first dielectric layer includes zirconium oxide.

[0096] In one embodiment of this disclosure, the material of the second dielectric layer includes at least one selected from hafnium oxide, titanium oxide, niobium oxide, yttrium oxide, lanthanum oxide, and tantalum oxide.

[0097] In one embodiment of this disclosure, the barrier layer is made of at least one of aluminum oxide, silicon oxide, niobium oxide, silicon-doped niobium oxide, silicon-doped hafnium oxide, and lanthanum oxide. The band gap of the barrier layer is larger than the band gap of the first dielectric layer, and the band gap of the barrier layer is larger than the band gap of the second dielectric layer. In the silicon-doped niobium oxide, the atomic ratio of silicon to niobium is 1:(1-20), and in the silicon-doped hafnium oxide, the atomic ratio of silicon to hafnium is 1:(1-20).

[0098] The total thickness of the first, second, and third layers helps ensure a higher dielectric constant (K) value as DRAM bond sizes continue to decrease. The total thickness of the first, second, and third layers is greater than the thickness of the barrier layer, and these layers primarily determine the overall capacitance of the capacitor. In some specific embodiments, the total thickness of the first, second, and third layers is 2.4 nm to 6 nm, and they utilize materials with high dielectric constants, such as at least one of high-K dielectric materials including zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, yttrium oxide, lanthanum oxide, and tantalum oxide. For example, the first stack, the second stack, and the third stack include a zirconium oxide layer and a hafnium oxide layer stacked sequentially, and the barrier layer includes an aluminum oxide layer. Compared with the barrier layer, the zirconium oxide layer and the hafnium oxide layer have higher dielectric constant K values ​​but also higher leakage rates, while the aluminum oxide layer has a lower dielectric constant K value but a lower leakage rate. Therefore, the capacitor dielectric layer with the stacked structure, including each stack and the barrier layer, can obtain both a high dielectric constant K value and a reduced leakage rate.

[0099] The inventors of this disclosure have creatively discovered in their research that, in the aforementioned capacitor dielectric layer, there are various combinations of first, second, and third stacked layers forming the capacitor dielectric layer. These include, but are not limited to, capacitor dielectric layers formed by two stacked layers of the first, second, and third layers arranged in different ways with a barrier layer, and capacitor dielectric layers formed by three stacked layers of the first, second, and third layers arranged in different ways with a barrier layer. Among these numerous combinations, compared to other forms of capacitor dielectric layers (the tetragonal structure has a maximum phase ratio of only 80% and a maximum dielectric constant of only 35; at a voltage of -0.6V to 0.6V, the leakage current range is -5e),... -5 pA~5e -5 The capacitor dielectric layer formed by the following three arrangements (pA / cell) has a significantly higher dielectric constant and a significantly lower leakage current.

[0100] In one embodiment of this disclosure, the capacitor dielectric layer includes any two of the following stacks: a first stack, a second stack, and a third stack, stacked along the first direction, wherein the thickness ratio of the two stacks is in the range of (0.4-2.5):1. Within this thickness ratio range, the capacitor dielectric layer can achieve a high dielectric constant K value.

[0101] In one embodiment of this disclosure, such as Figure 3 As shown, the capacitor dielectric layer 1000 includes a third stacked layer 300, a barrier layer 400, a first stacked layer 100, and the barrier layer 400 stacked along the first direction Z. Figure 6As shown, the first stack 100 includes at least one first unit 10 stacked along the first direction Z, and the first unit 10 includes a first dielectric layer 1, a second dielectric layer 2, and a first dielectric layer 1 stacked along the first direction Z; as Figure 8 As shown, the third stack 300 includes at least one third unit 30 stacked along the first direction Z. The third unit 30 includes a first dielectric layer 1 and a second dielectric layer 2 stacked along the first direction Z. The thickness of the third stack 300 to the first stack 100 is (0.4-2.5):1. The thickness of each barrier layer is 0.07nm-0.4nm, and the total thickness of the capacitor dielectric layers is 5nm-9nm. The first stack Z... a H b (Z 2a H b C 1-1 Z a and the third stack (Z) a H b ) c3 The range of the corresponding parameters is as described above. The main crystal phase of the first dielectric layer 1 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase), and the main crystal phase of the second dielectric layer 2 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase).

[0102] In this embodiment, the first dielectric layer 1 is zirconia, and the second dielectric layer 2 is hafnium oxide. First, zirconia and hafnium oxide (ZrHf) are grown. Hafnium oxide can be epitaxially grown based on zirconia crystallization, reducing the energy required for hafnium oxide crystallization, thus facilitating the formation of a tetragonal phase structure. High bandgap elements such as barrier layers (e.g., alumina) are formed on the stack, which reduces leakage paths and prevents ZrHf grain growth through doping of the barrier layers (e.g., aluminum). Then, zirconia and hafnium oxide are grown... After the growth of (ZHZ), the incorporation of the first barrier layer (such as aluminum) inhibits the crystallization of ZrHf, promoting the growth of a small amount of metastable orthorhombic phase (O phase). A quasi-isotropic phase boundary (MPB) is formed at the grain boundaries between the orthorhombic phase (O phase) (5%-10%) and the tetragonal phase (T phase) (80%-90%). This phase boundary achieves a dielectric constant higher than that of the orthorhombic phase (O phase) and the tetragonal phase (T phase), specifically 39-41. At voltages of -0.6V to 0.6V, the leakage current range of the capacitor dielectric layer in this embodiment is -2e -5 pA~2e -5 pA / cell.

[0103] In one embodiment of this disclosure, such as Figure 4As shown, the capacitor dielectric layer 2000 includes a third stacked layer 300, a barrier layer 400, a second stacked layer 200, and a barrier layer 400 stacked along the first direction Z. Figure 7 As shown, the second stack 200 includes at least one second unit 20 stacked along the first direction Z, and the second unit 20 includes a second dielectric layer 2 and a first dielectric layer 1 stacked along the first direction Z; as Figure 8 As shown, the third stack 300 includes at least one third unit 30 stacked along the first direction Z. The third unit 30 includes a first dielectric layer 1 and a second dielectric layer 2 stacked along the first direction Z. The thickness of the third stack 300 and the second stack 200 is (0.4-2.5):1. The thickness of each barrier layer is 0.07nm-0.4nm, and the total thickness of the capacitor dielectric layers is 5nm-9nm. The third stack (Z... a H b ) c3 Second stack (H) b Z a ) c2 The range of the corresponding parameters is as described above. The main crystal phase of the first dielectric layer 1 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase), and the main crystal phase of the second dielectric layer 2 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase).

[0104] In this embodiment, the first dielectric layer 1 is zirconia, and the second dielectric layer 2 is hafnium oxide. First, zirconia and hafnium oxide (ZrHf) are grown. Hafnium oxide can be epitaxially grown based on zirconia crystallization, reducing the energy required for hafnium oxide crystallization, thus facilitating the formation of a tetragonal phase structure. High bandgap elements such as barrier layers (e.g., alumina) are formed on the stack. This reduces leakage paths, and the doping of the barrier layer (e.g., aluminum) prevents ZrHf grain growth. In the barrier layer (e.g., alumina)... Hafnium oxide and zirconium oxide (HfZr) continue to grow on the substrate. The HfAlHf interface provides excellent resistance to leakage current because the bandgap is: alumina > hafnium oxide > zirconium oxide. However, hafnium oxide and alumina are more difficult to crystallize than zirconium oxide, so no orthorhombic phase (O phase) forms near the alumina. The main structure is tetragonal (T phase) (90%-95%), with a small amount of cubic (C phase) and monoclinic (M phase). The dielectric constant of the capacitor dielectric layer in this embodiment is 35-37. At a voltage of -0.6V to 0.6V, the leakage current range is -1e. -5 pA~1e -5 pA / cell.

[0105] In one embodiment of this disclosure, such as Figure 5As shown, the capacitor dielectric layer 3000 includes a first stack 100, a barrier layer 400, and the first stack 100 and barrier layer 400 stacked along the first direction Z. Figure 6 As shown, the first stack 100 includes at least one first unit 10 stacked along the first direction Z. The first unit 10 includes a first dielectric layer 1, a second dielectric layer 2, and a first dielectric layer 1 stacked along the first direction Z. The thickness ratio of the two first stacks 100 is (0.4-2.5):1, the thickness of each barrier layer is 0.07nm-0.4nm, and the total thickness of the capacitor dielectric layer is 5nm-9nm. The first stack Z a H b (Z 2a H b )c 1-1 Z a The range of the corresponding parameters is as described above. The main crystal phase of the first dielectric layer 1 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase), and the main crystal phase of the second dielectric layer 2 is at least one of a tetragonal structure phase and an orthorhombic structure phase (specifically a tetragonal structure phase).

[0106] In this embodiment, the first dielectric layer 1 is zirconia, and the second dielectric layer 2 is hafnium oxide. The combination of zirconia and hafnium oxide (ZHZ) allows hafnium oxide to grow epitaxially on zirconia. On the other hand, hafnium oxide also hinders the subsequent crystallization of zirconia, increasing the surface energy of zirconia crystallization. When the zirconia reaches a certain thickness, a tetragonal structure phase of zirconia hafnium oxide (ZrHfO) can be obtained. Elements with high bandgap, such as barrier layers (e.g., alumina), are formed on the stack. On the one hand, this can reduce leakage paths, and on the other hand, the doping of the barrier layer (e.g., aluminum) can prevent ZrHf grain growth. However, the surface energy that needs to be overcome for the crystallization of the combination of zirconia and hafnium oxide (ZHZ) is relatively large, and there are relatively many interfaces, which is not conducive to leakage performance. The dielectric layer is predominantly composed of a tetragonal structure (T-phase) (90%-95%), with a small amount of cubic structure (C-phase) and monoclinic phase (M-phase). The dielectric constant of the capacitor dielectric layer in this embodiment is 37-39. At a voltage of -0.6V to 0.6V, the leakage current range is -2e. -5 pA~2e -5 pA / cell.

[0107] In related technologies, the capacitor dielectric layer comprises a stacked first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer, as well as an aluminum oxide layer and a third zirconium oxide layer. The first zirconium oxide layer, hafnium oxide layer, and second zirconium oxide layer all have a tetragonal phase structure. The aluminum oxide and third zirconium oxide layers are amorphous. The first and second zirconium oxide layers each have a thickness of 0.5 nm to 3 nm, the hafnium oxide layer has a thickness of 0.5 nm to 1.8 nm, the aluminum oxide layer has a thickness of 0.2 nm, and the third zirconium oxide layer has a thickness of 0.3 nm to 1 nm. The overall capacitor dielectric layer has a thickness of 2 nm to 6 nm. The tetragonal phase accounts for a maximum of only 75% of this dielectric layer, and the dielectric constant is only 33. At a voltage range of -0.6V to 0.6V, the leakage current range is -5e. -5 pA~5e -5 pA / cell.

[0108] According to a second aspect of the present disclosure, a capacitor structure is provided, including a first electrode layer, a second electrode layer, and a capacitor dielectric layer as described in any of the above embodiments, wherein the capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

[0109] In some embodiments, the capacitor includes a plate-type, cup-type, cylindrical-type, or pillar-type capacitor.

[0110] In some embodiments, each of the first electrode layer and the second electrode layer may include a metal, a metal carbide, a metal nitride, or a conductive oxide. In some embodiments, each of the first electrode layer and the second electrode layer may include, for example, polycrystalline silicon, and may also include, but is not limited to, metallic materials such as titanium (Ti), cobalt (Co), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium tungsten (TiW), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), and combinations thereof. In some embodiments, the materials of the first electrode layer and the second electrode layer may be the same or different from each other.

[0111] In the dielectric layer of a capacitor, the second dielectric layer (e.g., a hafnium oxide layer) whose main crystalline phase is at least one of a tetragonal structure phase and an orthorhombic structure phase can be a ferroelectric material that has ferroelectric or antiferroelectric properties according to the electric field. The dielectric constant of the stacked structure is increased by using a second dielectric layer (e.g., a hafnium oxide layer) with ferroelectric or antiferroelectric properties. Such a stacked structure can meet the requirements of high dielectric constant and low leakage current (especially when it is used as a barrier layer), for example, to meet the requirements of capacitors for high capacitance and low leakage current.

[0112] Figure 9 This is in the public disclosure Figure 3 The diagram shows the fabrication process of the capacitor dielectric layer. Figure 10 This is in the public disclosure Figure 4The diagram shows the fabrication process of the capacitor dielectric layer. Figure 11 This is in the public disclosure Figure 5 The diagram shows the fabrication process of the capacitor dielectric layer. Figure 12 This is in the public disclosure Figure 6 The diagram shows the fabrication process of the first stacked layer; Figure 13 This is in the public disclosure Figure 7 The diagram shows the preparation process of the second stack; Figure 14 This is in the public disclosure Figure 8 The diagram shows the fabrication process of the third stack. The following will combine... Figures 9 to 14 The fabrication process of the capacitor dielectric layer is explained.

[0113] According to a third aspect of the embodiments of this disclosure, such as Figures 9-14 As shown, a method for fabricating a capacitor dielectric layer is provided. The method includes forming at least two of a first stack, a second stack, and a third stack stacked along a first direction, wherein...

[0114] The first stack includes at least one first unit stacked along the first direction; the second stack includes at least one second unit stacked along the first direction; and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase. The main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

[0115] In the preparation method of this disclosure, the explanation of relevant terms or words, the structure and thickness of each layer, the material selection of each film layer, the relevant functions and mechanisms, etc., can be found in the relevant description in the capacitor dielectric layer of the first aspect of this disclosure, and will not be repeated here.

[0116] In embodiments of this disclosure, the preparation method further includes forming a barrier layer, the barrier layer being formed on each of the first stack, the second stack, and the third stack.

[0117] The following describes the preparation process of three capacitor dielectric layers with significantly higher dielectric constants and significantly lower leakage currents according to the first aspect of the present disclosure, to specifically illustrate the preparation method of the capacitor dielectric layer of the third aspect of the present disclosure.

[0118] In one embodiment of this disclosure, such as Figure 9As shown, the fabrication method includes: forming the third stacked layer, the barrier layer, the first stacked layer, and the barrier layer along the first direction. Specifically, it includes:

[0119] S91: Formation of the third layer;

[0120] S92: A barrier layer is formed in the third stack along the first direction;

[0121] S93: A first stack is formed in the barrier layer along the first direction;

[0122] S94: A barrier layer is formed in the first stack along the first direction.

[0123] In another embodiment of this disclosure, such as Figure 10 As shown, the fabrication method includes: forming the third stacked layer, the barrier layer, the second stacked layer, and the barrier layer along the first direction. Specifically, it includes:

[0124] S101: Formation of the third layer;

[0125] S102: A barrier layer is formed in the third stack along the first direction;

[0126] S103: A second stack is formed in the barrier layer along the first direction;

[0127] S104: A barrier layer is formed in the second stack along the first direction.

[0128] In another embodiment of this disclosure, such as Figure 11 As shown, the fabrication method includes: forming a first stacked layer, a barrier layer, the first stacked layer, and the barrier layer along the first direction. Specifically, it includes:

[0129] S111: Formation of the first stack;

[0130] S112: A barrier layer is formed in the first stack along the first direction;

[0131] S113: A first stack is formed in the barrier layer along the first direction;

[0132] S114: Form a barrier layer again on the first stack located on the barrier layer along the first direction.

[0133] In embodiments of this disclosure, forming at least two of the first, second, and third stacked layers stacked along a first direction includes forming any two of the first, second, and third stacked layers stacked along the first direction, wherein the thickness ratio of the two stacked layers is in the range of (0.4-2.5):1.

[0134] In embodiments of this disclosure, forming the first stack includes forming at least one first unit stacked along the first direction. Forming the first unit includes forming a first dielectric layer, a second dielectric layer, and a first dielectric layer stacked along the first direction.

[0135] In embodiments of this disclosure, forming the second stack includes forming at least one second unit stacked along the first direction. Forming the second unit includes forming a second dielectric layer and a first dielectric layer stacked along the first direction.

[0136] In embodiments of this disclosure, forming the third stack includes forming at least one third unit stacked along the first direction. Forming the third unit includes forming a first dielectric layer and a second dielectric layer stacked along the first direction.

[0137] In the embodiments of this disclosure, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where,

[0138] like Figure 12 As shown, forming the first stack includes:

[0139] (11) The Z-shaped structure is formed using a first atomic layer deposition process. a The Z-shaped layer is formed using the first atomic layer deposition process. a The process includes a1 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a ;

[0140] (12) The Z formed in step (11) is carried out along the first direction using a second atomic layer deposition process. a The H formed above b The H is formed using the second atomic layer deposition process. b The process includes b1 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. b1 of the second sub-dielectric layers constitute the H. b ;

[0141] (13) The H formed in step (12) is constructed using a third atomic layer deposition process along the first direction.b The Z is formed again above a The Z-layer is formed using the third atomic layer deposition process. a The process includes a1 cycles of growing the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a The Z-shaped stacked arrangement formed along the first direction a The H b and the Z a This constitutes a first unit;

[0142] (14) Repeat steps (11)-(13) c1 times to obtain the first stack, wherein a1, b1, and c1 satisfy: 1≤a1 / b1≤20, c1 is the number of the first units in the first stack, c1 is a positive integer and 1≤c1≤30, 30≤(2a1+b1)*c1≤60, and satisfies: the first stack is Z a H b (Z 2a H b ) c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a Stacked along the first direction, the Z in the sub-stacked structure 2a and the H b The layers are stacked along the first direction, and the total thickness of the first stack is 2.4nm-6nm, where 1≤a / b≤20.

[0143] For example, forming the first stack includes:

[0144] Using TiN as the lower electrode layer, ozone is used to treat the TiN surface to ensure uniform atomic layer deposition of the high dielectric constant capacitance dielectric layer. Taking a first dielectric layer composed of zirconium oxide and a second dielectric layer composed of hafnium oxide as an example, both the zirconium oxide and hafnium oxide layers are formed using atomic layer deposition (ALD) technology. Source gases containing Zr and Hf are chemically and physically adsorbed onto the TiN lower electrode layer. Excess source gases that cannot be adsorbed are blown away using Ar inert gas. Ozone is used as a reactant gas to break the chemical bonds of the source gases to form oxides. Unreacted gases are then blown away using Ar. This process constitutes one growth cycle. First, zirconium oxide ALD is deposited for a1 growth cycles, then hafnium oxide ALD is deposited on the zirconium oxide for b1 growth cycles.a H b Based on this, continue depositing a1 growth cycles using the same zirconium oxide atomic layers. a H b Z a As a cycle, this cycle can be repeated c1 times as a whole. The bottom zirconium oxide acts as the nucleating phase. Hafnium oxide continues to nucleate on the basis of the nucleated bottom zirconium oxide, and can crystallize after reaching a certain thickness. Continuing to deposit zirconium oxide can effectively reduce the ZH surface energy, thereby reducing the formation of the monoclinic phase (M-phase) and increasing the probability of the tetragonal phase (T-phase) formation, thus improving the dielectric constant. (Definitions: 1≤a1 / b1≤20, 1≤c1≤30, 30≤(2a1+b1)*c1≤60, used for ZH...) a H b Z a Hafnium oxide is fully crystallized, thus obtaining a larger dielectric constant.

[0145] like Figure 13 As shown, forming the second stack includes:

[0146] (21) The H was formed using a fourth atomic layer deposition process. b The H is formed using the fourth atomic layer deposition process. b The process includes b2 cyclic growth cycles of the second sub-dielectric layer. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b2 second sub-dielectric layers constitute the H. b ;

[0147] (22) The H formed in step (21) is obtained by using a fifth atomic layer deposition process along the first direction. b The Z formed above a The Z-layer is formed using the fifth atomic layer deposition process. a The process includes a2 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a2 first sub-dielectric layers constitute the Z. a The H stacked along the first direction b and the Z a This constitutes a second unit;

[0148] (23) Repeat steps (21)-(22) c2 times to obtain the second stack, wherein a2, b2, and c2 satisfy: 1≤a2 / b2≤20, c2 is the number of the second units in the second stack, c2 is a positive integer and 1≤c2≤50, 30≤(a2+b2)*c2≤60, and satisfies: the second stack is (H b Za ) c2 In the second stack, c2 second units are stacked along the first direction, and the total thickness of the second stack is 2.4nm-6nm, 1≤a / b≤20.

[0149] For example, forming the second stack includes:

[0150] Using TiN as the lower electrode layer, ozone is used to treat the TiN surface to ensure uniform atomic layer deposition of the high-dielectric-constant capacitance dielectric layer. Taking a first dielectric layer composed of zirconium oxide and a second dielectric layer composed of hafnium oxide as an example, both the zirconium oxide and hafnium oxide layers are formed using atomic layer deposition (ALD) technology. Source gases containing Zr and Hf are chemically and physically adsorbed onto the TiN lower electrode layer. Excess source gases that cannot be adsorbed are blown away using Ar inert gas. Ozone is used as a reactant gas to break the chemical bonds of the source gases to form oxides. Unreacted gases are then blown away using Ar. This process constitutes one growth cycle. Hafnium oxide ALD is deposited for b2 growth cycles, followed by zirconium oxide ALD for a2 growth cycles. b Z a As a cycle, this cycle can be repeated c2 times as a whole. The underlying hafnium oxide substrate does not crystallize; zirconium oxide, after being deposited on the hafnium oxide to a certain thickness, will spontaneously crystallize and induce nucleation and crystallization of the hafnium oxide. Therefore, (H... b Z a ) c2 The crystallization consistency is relatively good. (By defining 1≤a² / b²≤20, 1≤c²≤50, and 30≤(a²+b²)*c²≤60, the degree of crystallinity of hafnium oxide can be well controlled, thereby obtaining a larger dielectric constant).

[0151] like Figure 14 As shown, forming the third stack includes:

[0152] (31) The Z-shaped structure was formed using a sixth atomic layer deposition process. a The Z-layer is formed using the sixth atomic layer deposition process. a The process includes a3 cycles of first sub-dielectric layer growth. After each first sub-dielectric layer growth cycle is completed, a first sub-dielectric layer is formed. The a3 first sub-dielectric layers constitute the Z. a ;

[0153] (32) The Z-shaped layer formed in step (31) along the first direction using a seventh atomic layer deposition process. a The H formed above b The H is formed using the seventh atomic layer deposition process. bThe process includes b3 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b3 second sub-dielectric layers constitute the H. b The Z-shaped stacked arrangement formed along the first direction a and the H b This constitutes one of the aforementioned third units;

[0154] (33) Repeat steps (31)-(32) c3 times to obtain the third stack, wherein a3, b3, and c3 satisfy: 1≤a3 / b3≤20, c3 is the number of the third units in the third stack, c3 is a positive integer and 1≤c3≤50, 30≤(a3+b3)*c3≤60, and satisfies: the third stack is (Z a H b ) c3 In the third stack, c3 third units are stacked along the first direction, and the total thickness of the third stack is 2.4nm-6nm, 1≤a / b≤20.

[0155] For example, forming the third stack includes:

[0156] Using TiN as the lower electrode layer, ozone is used to treat the TiN surface to ensure uniform atomic layer deposition of the high-dielectric-constant capacitance dielectric layer. Taking a first dielectric layer composed of zirconium oxide and a second dielectric layer composed of hafnium oxide as an example, both the zirconium oxide and hafnium oxide layers are formed using atomic layer deposition (ALD) technology. Source gases containing Zr and Hf are chemically and physically adsorbed onto the TiN lower electrode layer. Excess source gases that cannot be adsorbed are blown away using Ar inert gas. Ozone is used as the reactant gas to break the chemical bonds of the source gases to form oxides. Unreacted gases are then blown away using Ar. This process constitutes one growth cycle. Zirconia ALD is deposited for three growth cycles (a), followed by hafnium oxide ALD for three more growth cycles (b). a H b As a loop, this loop can be repeated c3 times as a whole. (By defining 1≤a3 / b3≤20, 1≤c3≤50, and 30≤(a3+b3)*c3≤60, the degree of crystallinity of hafnium oxide can be well controlled, thereby obtaining a larger dielectric constant).

[0157] In the embodiments of this disclosure, the process temperature for forming the first sub-dielectric layer is 260℃-350℃, and the pressure range used is 0.5 torr to 2.5 torr; the process temperature for forming the second sub-dielectric layer is 260℃-350℃, and the pressure range used is 0.5 torr to 2.5 torr in both cases. That is, in the embodiments of this disclosure, the process steps for forming the first and second dielectric layers can both be performed under low-temperature conditions, thereby helping to ensure the stable growth and good performance of the first and second dielectric layers.

[0158] In some embodiments, the material of the first dielectric layer includes zirconium oxide, and the material of the second dielectric layer includes hafnium oxide; the gas source used to form the first dielectric layer includes (cyclopentadienyl)tris(dimethylamide)zirconium (CpZr(NMe2)3) and ozone, and the gas source used to form the second dielectric layer includes (cyclopentadienyl)tris(dimethylamide)hafnium (also known as cyclopentadienyltris(dimethylamino)hafnium, tris(dimethylamino)cyclopentadienylhafnium, or (cyclopentadienyl)tris(dimethylamide)hafnium, CpHf(NMe2)3) and ozone.

[0159] Since zirconium oxide and hafnium oxide are oxides of the same group of elements and have similar structures, the zirconium oxide layer acts as a "seed" during the crystallization process of the hafnium oxide layer, which accelerates the crystallization process of the hafnium oxide layer and increases the phase transition rate.

[0160] Meanwhile, the lattice constants of zirconium oxide and hafnium oxide differ. When a hafnium oxide layer is formed on the zirconium oxide layer via epitaxial growth, a transition region with a mismatched lattice constant is created at the interface between the two layers. This transition region introduces strain, effectively applying stress to each other through the transition zone. This stress causes the hafnium oxide layer to deposit as a tetragonal hafnium oxide phase within a certain thickness range, thereby increasing the dielectric constant K value of the resulting capacitor dielectric layer.

[0161] In the embodiments of this disclosure, forming the barrier layer includes: forming the barrier layer using an eighth atomic layer deposition process. The process of forming the barrier layer using the eighth atomic layer deposition process includes d1 sub-barrier layer growth cycles. After the sub-barrier layer growth cycle is completed, a sub-barrier layer is formed. The d1 sub-barrier layers constitute the barrier layer, where d1 is 1-4, and the thickness of the barrier layer is 0.07nm-0.4nm.

[0162] In the embodiments of this disclosure, the process temperature for forming the sub-barrier layer is 250°C-400°C, and the pressure range used is 0.5 torr to 2.5 torr.

[0163] Here, we will use alumina as an example to illustrate the process. The gas source used to form the barrier layer includes trimethylaluminum (TMA) and ozone; the temperature range used for forming the barrier layer is 250℃-400℃, and the pressure range is 0.5 torr to 2.5 torr. Forming the alumina layer under the aforementioned conditions helps to ensure its uniform and stable growth. The alumina layer plays a major role in reducing the leakage current of the capacitor dielectric layer.

[0164] In this embodiment of the disclosure, the total thickness of the capacitor dielectric layer can be 5nm-9nm.

[0165] The capacitor dielectric layer manufactured by the method for preparing the capacitor dielectric layer provided in the third aspect of this disclosure has the same structure as the capacitor dielectric layer provided in the first aspect of this disclosure. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding, and they will not be repeated here.

[0166] The capacitor structure provided in the second aspect of this disclosure can be prepared by various conventional methods for preparing capacitor structures in the art, based on the capacitor dielectric layer provided in the first aspect of this disclosure. Further details will not be provided here.

[0167] The capacitor dielectric layer and capacitor structure provided in this disclosure can be used to fabricate a memory. That is, this disclosure can also provide a memory including the capacitor structure as described in any of the above embodiments.

[0168] In some embodiments, the memory provided in this disclosure includes various types of memory. For example, NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), phase-change memory (PCM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0169] In some embodiments, the memory provided in this disclosure can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, tablet computer, or smart bracelet, or it can be a personal computer (PC), server, workstation, etc. The storage function in the electronic device can be implemented through the aforementioned corresponding memory.

[0170] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0171] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0172] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0173] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A capacitor dielectric layer, characterized in that, The capacitor dielectric layer includes at least two of a first stack, a second stack, and a third stack stacked along a first direction. The first stack includes at least one first unit stacked along the first direction, the second stack includes at least one second unit stacked along the first direction, and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase, and the main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

2. The capacitor dielectric layer according to claim 1, characterized in that, The capacitor dielectric layer further includes a barrier layer located on each of the first stack, the second stack, and the third stack.

3. The capacitor dielectric layer according to claim 2, characterized in that, The capacitor dielectric layer includes the third stacked layer, the barrier layer, the first stacked layer, and the barrier layer stacked along the first direction; or The capacitor dielectric layer includes the third stacked layer, the barrier layer, the second stacked layer, and the barrier layer stacked along the first direction; or The capacitor dielectric layer includes a first stack, a barrier layer, the first stack, and the barrier layer stacked along the first direction.

4. The capacitor dielectric layer according to any one of claims 1-3, characterized in that, The capacitor dielectric layer includes any two of the first stack, the second stack, and the third stack stacked along the first direction, and the thickness ratio of the two stacks is in the range of (0.4-2.5):

1.

5. The capacitor dielectric layer according to any one of claims 1-3, characterized in that, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where, The first stack is Z a H b (Z 2a H b ) c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a Stacked along the first direction, the Z in the sub-stacked structure 2a and the H b The first stacked layers are arranged along the first direction, with a total thickness of 2.4 nm-6 nm, 1 ≤ a / b ≤ 20, where c1 is the number of the first units in the first stacked layers, and the first unit is represented by a Z-shaped stack arranged along the first direction. a H b and Z a The first layered structure is formed, wherein c1 is a positive integer and 1≤c1≤30; and / or The second stack is (H) b Z a ) c2 In the second stack, c2 second units are stacked along the first direction, and the second unit is represented by H units stacked along the first direction. b and Z a The second stacked structure is formed, wherein the total thickness of the second stacked layer is 2.4nm-6nm, 1≤a / b≤20, and c2 is a positive integer and 1≤c2≤50; and / or The third stack is (Z) a H b ) c3 In the third stack, c3 third units are stacked along the first direction, and the third unit is represented by Z units stacked along the first direction. a and H b The third stacked structure is formed, the total thickness of the third stack is 2.4nm-6nm, 1≤a / b≤20, and c3 is a positive integer and 1≤c3≤50.

6. The capacitor dielectric layer according to claim 2 or 3, characterized in that, The thickness of the barrier layer is 0.07nm-0.4nm.

7. The capacitor dielectric layer according to any one of claims 1-3, characterized in that, The total thickness of the capacitor dielectric layer is 5nm-9nm.

8. The capacitor dielectric layer according to claim 2 or 3, characterized in that, The material of the first dielectric layer includes zirconium oxide; and / or The material of the second dielectric layer includes at least one of hafnium oxide, titanium oxide, niobium oxide, yttrium oxide, lanthanum oxide, and tantalum oxide; and / or The material of the barrier layer includes at least one of aluminum oxide, silicon oxide, niobium oxide, silicon-doped niobium oxide, silicon-doped hafnium oxide, and lanthanum oxide. The band gap of the barrier layer is greater than the band gap of the first dielectric layer, and the band gap of the barrier layer is greater than the band gap of the second dielectric layer.

9. A capacitor structure, characterized in that, It includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer as described in any one of claims 1-8, wherein the capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

10. A method for preparing a capacitor dielectric layer, characterized in that, The preparation method includes forming at least two of a first stack, a second stack, and a third stack stacked along a first direction, wherein, The first stack includes at least one first unit stacked along the first direction; the second stack includes at least one second unit stacked along the first direction; and the third stack includes at least one third unit stacked along the first direction. The first unit includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked along the first direction. The second unit includes a second dielectric layer and a first dielectric layer stacked along the first direction. The third unit includes a first dielectric layer and a second dielectric layer stacked along the first direction. The main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase. The main crystal phase of the second dielectric layer is at least one of a tetragonal structure phase and an orthorhombic structure phase.

11. The preparation method according to claim 10, characterized in that, The preparation method further includes forming a barrier layer, which is formed on each of the first stack, the second stack, and the third stack.

12. The preparation method according to claim 11, characterized in that, The preparation method includes: The third stack, the barrier layer, the first stack, and the barrier layer are formed in a stacked manner along the first direction; or The third stack, the barrier layer, the second stack, and the barrier layer are formed in a stacked manner along the first direction; or The first stack, the barrier layer, the first stack, and the barrier layer are formed in a stacked manner along the first direction.

13. The preparation method according to any one of claims 10-12, characterized in that, The formation of at least two of the first, second, and third stacked layers arranged along the first direction includes: forming any two of the first, second, and third stacked layers arranged along the first direction, wherein the thickness ratio of the two stacked layers is in the range of (0.4-2.5):

1.

14. The preparation method according to any one of claims 10-12, characterized in that, Z a Let Z be a first dielectric layer with a first thickness a. 2a It is represented as a first dielectric layer having a second thickness of 2a and the Z 2a This refers to two Z-shaped structures stacked along the first direction. a , will H b This is represented as a second dielectric layer with a third thickness b, where, Forming the first stack includes: (11) The Z-shaped structure is formed using a first atomic layer deposition process. a The Z-shaped layer is formed using the first atomic layer deposition process. a The process includes a1 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a ; (12) The Z formed in step (11) is carried out along the first direction using a second atomic layer deposition process. a The H formed above b The H is formed using the second atomic layer deposition process. b The process includes b1 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. b1 of the second sub-dielectric layers constitute the H. b ; (13) The H formed in step (12) is constructed using a third atomic layer deposition process along the first direction. b The Z is formed again above a The Z-layer is formed using the third atomic layer deposition process. a The process includes a1 cycles of growing the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a1 first sub-dielectric layers constitute the Z. a The Z-shaped stacked arrangement formed along the first direction a The H b and the Z a This constitutes a first unit; (14) Repeat steps (11)-(13) c1 times to obtain the first stack, wherein a1, b1, and c1 satisfy: 1≤a1 / b1≤20, c1 is the number of the first units in the first stack, c1 is a positive integer and 1≤c1≤30, 30≤(2a1+b1)*c1≤60, and satisfies: the first stack is Z a H b (Z 2a H b ) c1-1 Z a The Z in the first stack a The H b (c1-1) of the Z 2a and the H b The sub-layered structure formed, the Z a Stacked along the first direction, the Z in the sub-stacked structure 2a and the H b Stacked along the first direction, the total thickness of the first stack is 2.4nm-6nm, 1≤a / b≤20; and / or Forming the second stack includes: (21) The H was formed using a fourth atomic layer deposition process. b The H is formed using the fourth atomic layer deposition process. b The process includes b2 cyclic growth cycles of the second sub-dielectric layer. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b2 second sub-dielectric layers constitute the H. b ; (22) The H formed in step (21) is obtained by using a fifth atomic layer deposition process along the first direction. b The Z formed above a The Z-layer is formed using the fifth atomic layer deposition process. a The process includes a2 cyclic growth cycles of the first sub-dielectric layer. After the first sub-dielectric layer growth cycle is completed, the first sub-dielectric layer is formed. The a2 first sub-dielectric layers constitute the Z. a The H stacked along the first direction b and the Z a This constitutes a second unit; (23) Repeat steps (21)-(22) c2 times to obtain the second stack, wherein a2, b2, and c2 satisfy: 1≤a2 / b2≤20, c2 is the number of the second units in the second stack, c2 is a positive integer and 1≤c2≤50, 30≤(a2+b2)*c2≤60, and satisfies: the second stack is (H b Z a ) c2 In the second stack, c2 second units are stacked along the first direction, and the total thickness of the second stack is 2.4nm-6nm, 1≤a / b≤20; and / or Forming the third stack includes: (31) The Z-shaped structure was formed using a sixth atomic layer deposition process. a The Z-layer is formed using the sixth atomic layer deposition process. a The process includes a3 cycles of first sub-dielectric layer growth. After each first sub-dielectric layer growth cycle is completed, a first sub-dielectric layer is formed. The a3 first sub-dielectric layers constitute the Z. a ; (32) The Z-shaped layer formed in step (31) along the first direction using a seventh atomic layer deposition process. a The H formed above b The H is formed using the seventh atomic layer deposition process. b The process includes b3 cycles of second sub-dielectric layer growth. After the second sub-dielectric layer growth cycle is completed, a second sub-dielectric layer is formed. The b3 second sub-dielectric layers constitute the H. b The Z-shaped stacked arrangement formed along the first direction a and the H b This constitutes one of the aforementioned third units; (33) Repeat steps (31)-(32) c3 times to obtain the third stack, wherein a3, b3, and c3 satisfy: 1≤a3 / b3≤20, c3 is the number of the third units in the third stack, c3 is a positive integer and 1≤c3≤50, 30≤(a3+b3)*c3≤60, and satisfies: the third stack is (Z a H b ) c3 In the third stack, c3 third units are stacked along the first direction, and the total thickness of the third stack is 2.4nm-6nm, 1≤a / b≤20.

15. The preparation method according to claim 11, characterized in that, The formation of the barrier layer includes: forming the barrier layer using an eighth atomic layer deposition process. The process of forming the barrier layer using the eighth atomic layer deposition process includes d1 sub-barrier layer growth cycles. After the sub-barrier layer growth cycle is completed, a sub-barrier layer is formed. The d1 sub-barrier layers constitute the barrier layer, where d1 is 1-4, and the thickness of the barrier layer is 0.07nm-0.4nm.

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