Physical interface configuration buffer in flash memory system

Abstract

The present disclosure provides systems, methods, and devices for supporting a memory system that updates a configuration of a physical layer interface (PHY) using information stored in a buffer of a connected memory system. In a first aspect, a method of accessing data in a flash memory system includes initializing, by a memory controller of a host device, a PHY for connecting the host device to a memory system to operate at a first speed; receiving PHY configuration information for configuring the PHY to operate from a first buffer of the memory system at a second speed greater than the first speed; and adjusting, by the memory controller, a configuration of the PHY to operate at the second speed according to the PHY configuration information. Other aspects and features are also claimed and described.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 187,259, filed on March 21, 2023, entitled “PHYSICAL INTERFACECONFIGURATION BUFFER IN A FLASH MEMORY SYSTEM”, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] In general, aspects of this disclosure relate to apparatus and methods for controlling memory devices. More specifically, some aspects may relate to an apparatus and method for controlling operations for updating physical interface (PHY) configuration using information from a PHY configuration buffer. Background Technology

[0004] As the value and use of information continue to increase, individuals and businesses are seeking additional ways to process and store information. Furthermore, the use of information in various locations and the expectation of information portability continue to grow. Therefore, users are increasingly turning to portable electronic devices such as mobile phones, digital cameras, and laptops. Portable electronic devices typically employ memory systems that use storage devices to store data. These memory systems can serve as either main memory or secondary memory in portable electronic devices.

[0005] Memory devices in a memory system can include combinations of one or more types of storage. For example, magnetic-based memory systems (such as hard disk drives (HDDs)) store data by encoding data as combinations of small magnets. As another example, optical-based memory systems (such as DVDs and Blu-ray discs) store data by encoding data as physical bits that cause different reflections when illuminated by a light source. As yet another example, electronic memory devices store data as the collection of electrons that can be detected by voltage and / or current measurements.

[0006] Electronic storage devices can be advantageous in certain systems because they offer fast data access and consume minimal power. Examples of electronic storage devices with these advantages include Universal Serial Bus (USB) memory devices (sometimes called "Memory Sticks"), memory cards (such as those used in some camera and gaming systems), and solid-state drives (SSDs) (such as those used in laptops). NAND flash memory is one type of storage device that can be used in electronic storage devices. NAND flash memory is manufactured as memory cards or flash disks. Example memory cards include Compact Flash (CF) cards, eMMC cards, Smart Media (SM) cards, and Secure Digital (SD) cards.

[0007] In some cases, memory systems can be integrated with or otherwise connected to electronic systems. For example, a flash memory system, which may be a universal flash storage (UFS) system, can be integrated into electronic systems such as access points (APs), stations (STAs), user equipment (UEs), base stations, modems, cameras, or other systems. Summary of the Invention

[0008] The following outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This overview is not a comprehensive summary of all anticipated features of this disclosure, and is neither intended to identify key or essential elements of all aspects of this disclosure, nor to depict the scope of any or all aspects of this disclosure. Its sole purpose is to introduce some concepts of one or more aspects of this disclosure in the form of an inventive summary, as a prelude to the more detailed description that follows.

[0009] A buffer located on the flash memory can be used to store configuration information for patching the PHY to operate at enhanced speed. For example, a PHY that connects a memory system (such as a memory system including flash memory) to a host device can be configured to operate at a lower speed during host device initialization, which may include the initialization of the PHY and the memory system. The configuration information stored on the PHY can be accessed during host device initialization (e.g., before the flash memory initialization is complete). The host device can read the PHY configuration information from the flash memory and adjust the PHY configuration to operate at a higher speed based on the PHY configuration information. Therefore, the host device's memory controller can access the configuration information early in the initialization process to patch the PHY to operate at enhanced speed. This enhanced speed allows for faster initialization of the host device. Furthermore, the buffer can allow the storage of other PHY configuration information to facilitate post-silicon patching of errors and enhance the efficiency of PHY operation early in the boot process.

[0010] In one aspect of this disclosure, a memory device includes a memory controller coupled to a memory module via a first channel and configured to access data stored in the memory module via the first channel; and coupled to a host device via a first physical interface (PHY) and configured to communicate with the host device via the first interface. The memory controller of the memory device may be configured to perform operations including: after the PHY is initialized to operate at a first speed, receiving from the host device a request for PHY configuration information for configuring the PHY to operate from a first buffer of the memory module at a second speed greater than the first speed; and sending the PHY configuration information to the host device. In another aspect of this disclosure, a method for a processor to perform these operations by executing instructions stored in memory coupled to the processor is also disclosed. In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform these operations.

[0011] In an additional aspect of this disclosure, an apparatus includes a memory controller for a host device configured to couple the host device to a memory system via a first physical interface (PHY). The memory controller is configured to perform operations including: initializing the PHY to operate at a first speed; receiving PHY configuration information for configuring the PHY to operate from a first buffer of the memory system at a second speed greater than the first speed; and adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information. In another aspect of this disclosure, a method for a processor to perform these operations by executing instructions stored in memory coupled to the processor is also disclosed. In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform these operations.

[0012] The features and technical advantages of examples according to this disclosure have been summarized quite extensively above to facilitate a better understanding of the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose as this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The features (both their organization and manner of operation) of the concepts disclosed herein, as well as their associated advantages, will be better understood when considered in conjunction with the accompanying drawings, based on the following description. Each drawing in the accompanying drawings is provided for illustrative and descriptive purposes and is not intended to define a limitation of the claims.

[0013] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or uses may arise via integrated chip implementations and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial installations, retail / purchasing devices, medical devices, devices implementing artificial intelligence (AI), etc.). While some examples may or may not be specific to a particular use case or application, a wide variety of applicability to the described innovations is possible. The range of implementations can extend from die-level or modular components to non-modular, non-die-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessary include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily include multiple components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / converters, etc.). The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0014] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, components of the same type can be distinguished by adding a dash after the reference numerals and a second reference numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, without regard to the second reference numeral.

[0015] Figure 1 This is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present invention.

[0016] Figure 2 This is a block diagram illustrating an example electronic device including a memory system according to one or more aspects of this disclosure.

[0017] Figure 3 This is a block diagram illustrating components for facilitating access to a flash memory device from a host device, according to some embodiments of the present disclosure.

[0018] Figure 4A This is a timing flowchart illustrating the initialization process for a host device according to some embodiments of the present disclosure.

[0019] Figure 4B This is a timing flowchart illustrating the initialization process for a host device according to some embodiments of the present disclosure.

[0020] Figure 5 This is a flowchart illustrating a method for initializing a host device according to some embodiments of the present disclosure.

[0021] Figure 6 This is a flowchart illustrating a method for initializing a host device using PHY configuration information stored in a flash buffer, according to some embodiments of the present disclosure.

[0022] Figure 7 This is a flowchart illustrating a method for initializing a host device by a host controller using PHY configuration information stored in a flash buffer, according to some embodiments of the present disclosure.

[0023] Figure 8 This is a flowchart illustrating a method for initializing a host device by a flash memory device using PHY configuration information stored in a flash buffer, according to some embodiments of the present disclosure.

[0024] Figure 9 It is a block diagram illustrating details of an example wireless communication system according to one or more aspects.

[0025] Similar reference numerals and naming conventions in the various figures indicate similar elements. Detailed Implementation

[0026] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations and are not intended to limit the scope of this disclosure. Rather, "specific embodiments" includes specific details for providing a full understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every case, and in some instances, well-known structures and components are shown in block diagram form for clarity.

[0027] This disclosure provides systems, apparatus, methods, and computer-readable media that support data processing, including techniques for storing, retrieving, and organizing data in a memory system. Various aspects of this disclosure provide operations and data structures used in those operations for patching a PHY that connects a host device to a memory system to operate at higher speeds using PHY configuration information stored in a buffer in the memory of the memory subsystem.

[0028] Specific implementations of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides techniques for improved performance of memory systems, such as enhanced speed and reduced boot time during the boot process of a host device. Enhanced speed during boot and reduced boot time may be particularly advantageous in the context of automotive computer systems, where boot time of less than 50 ms may be desired.

[0029] Memory can be used in, for example Figure 1 The organized computing system shown. Figure 1 A data processing system 100 (such as that which may be included in a mobile computing device) according to one or more aspects of this disclosure is illustrated. A memory system 110 may be coupled to a host device 102 via one or more channels. For example, the host device 102 and the memory system 110 may be coupled via a serial interface comprising a single channel for transmitting data or a parallel interface comprising two or more channels for transmitting data. In some aspects, control data may be transmitted via the same channel as the data, or control data may be transmitted via additional channels. The host device 102 may be, for example, a portable electronic device (such as a mobile phone, MP3 player, or laptop computer) or a non-portable electronic device (such as a desktop computer, game player, television (TV), media player, or projector). As another example, the host device 102 may be an automotive computer system. Reference Figure 6 Additional example host devices are shown and described.

[0030] The memory system 110 can perform operations in response to commands (e.g., requests) from the host device 102. For example, the memory system 110 can store data provided by the host device 102, and the memory system 110 can also provide the stored data to the host device 102. The memory system 110 can be used by the host device 102 as main memory, short-term memory, or long-term memory. As an example of main memory, the host device 102 can use the memory system 110 to supplement or replace system memory by storing temporary data (such as data related to the operating system and / or threads executing within the operating system). As an example of short-term memory, the host device 102 can use the memory system 110 to store page files for the operating system. As an example of long-term memory, the host device 102 can use the memory system 110 to store user files (e.g., documents, videos, pictures) and / or application files (e.g., word processing executables, game applications).

[0031] According to the host interface protocol used to couple the memory system 110 to one or more channels of the host device 102, the memory system 110 can be implemented using any of a variety of storage devices. The memory system 110 can be implemented using any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash (CF) cards, smart media (SM) cards, or memory sticks.

[0032] Memory system 110 may include memory module 150 and controller 130 coupled to memory module 150 via one or more channels. Memory module 150 can store and retrieve data in memory blocks 152, 154, and 156 under the control of controller 130, which can execute commands received from host device 102. Controller 130 is configured to control data exchange between memory module 150 and host device 102. Storage components in memory module 150 (such as blocks 152, 154, and 156) may be implemented as volatile memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory devices (such as read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (SCRAM), or NAND flash memory).

[0033] The controller 130 and memory module 150 can be formed as integrated circuits on one or more semiconductor dies (or other substrates). In some aspects, the controller 130 and memory module 150 can be integrated into a single chip. In some aspects, the memory module 150 may include one or more chips coupled in series or parallel to each other and coupled to the controller 130, which is on a separate chip. In some aspects, the memory module 150 and controller 130 chips are integrated into a single package, such as in a package-on-a-package (PoP) system. In some aspects, the memory system 110 and one or more of the components of the host device 102 (e.g., application processor, system memory, digital signal processor, modem, graphics processing unit, memory interface, input / output interface, network adapter) are integrated onto a single chip, such as in a system-on-a-chip (SoC). The controller 130 and the memory module 150 can be integrated into a single semiconductor device to form a memory card (such as, for example, PCMCIA card, Compact Flash (CF) card, Smart Media Card (SMC), Memory Stick, Multimedia Card (MMC), RS-MMC, Micro MMC, Secure Digital (SD) card, Mini SD, Micro SD, SDHC, and Universal Flash (UFS) device).

[0034] The controller 130 of the memory system 110 can control the memory module 150 in response to commands from the host device 102. The controller 130 can execute read commands to provide data from the memory module 150 to the host device 102. The controller 130 can execute write commands to store data provided from the host device 102 into the memory module 150. The controller 130 can execute other commands to manage data in the memory module 150 (such as programming and erasing commands). The controller 130 can also execute other commands to manage control of the memory system 110 (such as setting the configuration registers of the memory system 110). By executing commands according to the configuration specified in the configuration registers, the controller 130 can control the operation of the memory module 150 (such as read, write, programming, and erase operations).

[0035] Controller 130 may include several components configured to execute received commands. For example, controller 130 may include host interface (I / F) unit 132, processor 134, error correction code (ECC) unit 138, power management unit (PMU) 140, NAND flash memory controller (NFC) 142, and / or memory 144. Power management unit (PMU) 140 may provide and manage power for components within controller 130 and / or memory module 150.

[0036] The host interface unit 132 can process commands and data provided by the host device 102 and can communicate with the host device 102 through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Fast (PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronic Device (IDE)). For example, the host interface 132 can be a parallel interface (such as an MMC interface) or a serial interface (such as Ultra-High Speed ​​Category 1 (UHS-I) / UHS Category 2 (UHS-II) or Universal Flash Storage (UFS) interface).

[0037] ECC unit 138 can detect and correct errors in data read from memory module 150 during a read operation. When the number of error bits exceeds a threshold number of correctable error bits, ECC unit 138 may not correct the error bits, which may cause ECC unit 138 to output an error correction failure signal indicating that the error correction has failed. In some aspects, ECC unit 138 may not be provided, or ECC unit 138 may be configured to be active for some or all of the memory modules 150. ECC unit 138 may perform error correction operations using coded modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM)).

[0038] NFC 142 provides an interface between controller 130 and memory module 150, allowing controller 130 to control memory module 150 in response to commands received from host device 102. NFC 142 can generate control signals for memory module 150 (such as signals for row lines and bit lines) and process data under the control of processor 134. Although NFC 142 is described as a NAND flash memory controller, other controllers can perform similar functions for other memory types used as memory module 150.

[0039] Memory 144 can be used as working memory for memory system 110 and controller 130. Memory 144 can store data used to drive memory system 110 and controller 130. When controller 130 controls the operation of memory module 150 (such as, for example, read, write, program, or erase operations), memory 144 can store data used by controller 130 and memory module 150 for operation. Memory 144 can be implemented using volatile memory (such as, for example, static random access memory (SRAM) or dynamic random access memory (DRAM)). In some aspects, memory 144 can store address maps, program memory, data memory, write buffers, read buffers, mapping buffers, etc.

[0040] In response to write or read requests received from host device 102, processor 134 can control the general operation of memory system 110 and write or read operations on memory module 150. For example, processor 134 can execute firmware, which may be referred to as a flash translation layer (FTL), to control the general operation of memory system 110. Processor 134 may be implemented, for example, using a microprocessor, central processing unit (CPU), or application-specific integrated circuit (ASIC).

[0041] Figure 2 This is a block diagram illustrating an example electronic device including a memory system 200 according to one or more aspects of this disclosure. The electronic device 200 may include a user interface 210, memory 220, application processor 230, network adapter 240, and storage system 250 (which may be...). Figure 1 (An embodiment of the memory system 100). The application processor 230 can be coupled to other components via a bus (such as a peripheral component interface (PCI) bus, including a PCI fast (PCIe) bus).

[0042] Application processor 230 can execute computer program code, including applications, drivers, and operating systems, to coordinate tasks performed by components included in electronic device 200. For example, application processor 230 can execute a memory driver for accessing storage system 250. Application processor 230 may be part of a system-on-a-chip (SoC) that includes one or more other components shown in electronic device 200.

[0043] Memory 220 can operate as main memory, working memory, buffer memory, or cache memory of electronic device 200. Memory 220 may include volatile random access memory (such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM) or non-volatile random access memory (such as phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM)). In some aspects, application processor 230 and memory 220 may be combined using a stacked package (POP).

[0044] Network adapter 240 can communicate with external devices. For example, network adapter 240 can support wired communication and / or various wireless communications (such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), Bluetooth, Wireless Display (Wi-Di), etc.), and can thereby communicate with wired and / or wireless home appliances (e.g., mobile home appliances).

[0045] Storage system 250 can store data, such as data received from application processor 230, and send the data stored therein to application processor 230. Storage system 250 can be a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash memory, NOR flash memory, or 3-dimensional (3-D) NAND flash memory. Storage system 250 can be a removable storage medium, such as a memory card or external drive. For example, storage system 250 can correspond to the above reference. Figure 1 The memory system 110 described can be an SSD, eMMC, UFS or other flash memory system.

[0046] User interface 210 provides one or more graphical user interfaces (GUIs) for inputting data or commands to application processor 230 or for outputting data to external devices. For example, user interface 210 may include user input interfaces (such as a virtual keyboard, touch screen, camera, microphone, gyroscope sensor or vibration sensor) and user output interfaces (such as a liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, light-emitting diode (LED), speaker or haptic motor).

[0047] Figure 3 This is a block diagram illustrating components for facilitating access to a flash memory system from a host device, according to some embodiments of this disclosure. Host device 102 accesses memory system 110 via a first interface 310. The first interface may be, for example, a physical interface (PHY). Host device 102 may include a physical layer access block 312 configured to generate signals for output to the first interface 310 and process signals received through the first interface 310. Memory system 110 includes a similarly configured physical layer access block 322 for communication over the first interface 310. An example physical layer specification for communication over the first interface 310 is MIPI M-PHY. TM Physical layer specifications.

[0048] Host device 102 also includes a data link layer block 314 configured to format frames for data transmission on the first interface 310. Frames can be provided to physical layer access block 312 for transmission. Data link layer block 314 can receive frames from physical layer access block 312 and decode frames of data received on the first interface 310. Memory system 110 includes a similarly configured data link layer block 324 for processing frames sent or received by physical layer access block 322 on the first interface 310. This is for use in MIPI M-PHY. TM An example data link protocol for communication over a physical link is MIPIUNIPRO. TM specification.

[0049] Memory system 110 includes N logical units 350a-n, which comprise logical memory blocks for storing information including user data (e.g., user documents, application data) and configuration data (e.g., information about the operation of memory system 110). Logical units 350a-n may be mapped to portions of physical memory blocks 152, 154, and 156. Some or portions of logical units 350a-n may be configured to have write protection, boot capability, be a specific memory type (e.g., default, system code, non-persistent, enhanced), have priority access, or have replay protection as a replay protected memory block (RPMB). Physical layer access block 322 and data link layer block 324 perform operations of the memory controller of memory system 110 for storing and retrieving data in logical units 350a-n. As a specific example, one or more logical units of logic units 350a-n can be configured as buffers for storing PHY configuration information as described herein, such as one or more patches for configuring interface 310 to operate at different speeds. The logical units of the buffer can be configured to be accessible before the memory system 110 is fully initialized (e.g., before the fDeviceInit operation for the memory system completes), to allow for increased speed of communication across interface 310 early in the boot process of host device 102. The fDeviceInit operation can be an initialization operation for the memory system. In some embodiments, the fDeviceInit flag can be set at the beginning of the initialization operation for the UFS memory system and can be reset when the memory system initialization is complete. In some embodiments, the logical units of the buffer can be locked or configured to be read-only to prevent changes to the PHY configuration information.

[0050] The memory system 110 also includes a configuration structure 352. Configuration structure 352 may include information such as configuration descriptors for boot enable (bBotEnable), initial power mode (bInitPowerMode), RPMB activity (bRPMBRegionEnable), and / or RPMB region sizes (bRPMBRegion1Size, bRPMBRegion2Size, bRPMBRegion3Size). Such a configuration structure may be specified, for example, by the UFS standard.

[0051] Host device 102 can be configured to execute one or more applications 334, such as user applications executed by the operating system under user control to receive user input and provide information stored in memory system 110 to the user. Host device 102 may include several components for connecting application 334 to memory system 110 via first interface 310. For example, SCSI drive 332 and UFS drive 330 can connect application 334 to a host memory controller including data link layer block 314 and physical layer access block 312. SCSI drive 332 can execute at the application layer to handle transactions requested by application 334 with memory system 110. UFS drive 330 can execute at the transport layer and manage the operation of data link layer block 314, such as operating first interface 310 in one of a plurality of operating modes. Operating modes may include two or more gear settings, such as one or more PWM-GEAR settings and four or more HS-GEAR settings, specifying a bit rate from 182MBps, 364MBps, 728MBps, and 1457MBps.

[0052] The first interface 310 may include one or more lines, including a reset RST line, a reference clock REF_CLK line, a data input DIN line (for data transfer from host device 102 to memory system 110), and a data output DOUT line (for data transfer from memory system 110 to host device 102). The DIN and DOUT lines may be two separate conductors, or they may include multiple conductors. In some embodiments, the DIN and DOUT lines may be asymmetrical, where the DIN line includes N conductors and the DOUT line includes M conductors, where N>M or M>N.

[0053] UFS drive 330 can generate and decode packets to execute transactions requested by application 334. Packets are sent via first interface 310. Packets can be formatted as UFS Protocol Information Units (UPIUs). In a transaction with storage system 110, host device 102 is the initiator, and storage system 110 is the target. Based on the transaction type, UFS drive 330 can form one of several types of UPIUs for processing SCSI commands, data operations, task management operations, and / or query operations. Each transaction may include a command UPIU, zero or more DATAIN or DATA OUT UPIUs, and a response UPIU. Each UPIU may include a header, followed by optional fields depending on the type of UPIU.

[0054] An example transaction is a read operation. A read transaction may include an initiator (e.g., host device 102) sending a command UPIU to cause a target (e.g., memory system 110) to perform a read operation requested by application 334. The target responds to the command UPIU by providing one or more DATAIN UPIUs, where the DATAIN UPIU includes the requested data. The read transaction is completed by the target that sent the response UPIU.

[0055] Another example transaction is a write operation. A write operation may include an initiator (e.g., host device 102) sending a command UPIU to cause a target (e.g., memory system 110) to perform a write operation requested by application 334. The target provides a Ready to Transfer UPIU signaling the initiator to begin the transfer of write data. The initiator then sends one or more DATAOUT UPIUs, followed by a Ready to Transfer UPIU signaling the initiator to continue transferring the write data. The sequence of DATA OUT UPIUs and Ready to Transfer UPIUs continues until all write data has been provided to the target, after which the target provides a response UPIU to the initiator.

[0056] Another example transaction is a query operation. A query operation may include an initiator (e.g., host device 102) requesting information about a target (e.g., memory system 110). The initiator may send a query request UPIU to request information such as the target's configuration, enumeration, device descriptors, flags, and / or attributes. Example query operations include reading descriptors, writing descriptors, reading attributes, writing attributes, reading flags, setting flags, clearing flags, and / or toggling flags. Example descriptors include device, configuration, cell, interconnect, string, geometry, power, and / or device health. Example flags include fDeviceInit, fPermanenteWPEn, fPowerOnWPEn, fBackgroundOpsEn, fDeviceLifanModeEn, fPurgeEnable, fRefreshEnable, fPhyResourceRemoval, fBusyRTC, and / or fPermanentlyDisableFwUpdate. Example properties include bBootLunEn, bCurrentPowerMode, bActiveICLevel, bOutOfOerDataEn, bBackgroundOpStatus, bPurgeStatus, bMaxDataInSize, bMaxDataOutSize, dDynCapNeeded, and bRefClkFreq. Such flags can be, for example, flags specified by the UFS standard.

[0057] The aforementioned operations and capabilities can be used to support adjusting the PHY configuration based on PHY configuration information stored in the memory of a memory system connected to the host device via the PHY to achieve enhanced communication speeds via the PHY. Using a buffer in the memory system's memory to store the PHY configuration information allows the PHY configuration to be updated before the host device's initialization process is complete (e.g., before the memory on which the buffer is located is initialized), and the PHY configuration information to be retrieved from memory before the memory is fully initialized.

[0058] As described herein, a host device can connect to a memory system, such as a UFS flash memory system, via a PHY. In some cases, the host device, memory system, and PHY can be integrated into a single SoC. During the initialization or boot of the host device, the PHY can be configured to operate at different speeds during different parts of the initialization process. In some systems, such as those where the host device is connected to a UFS or NVMe memory system, initialization can take a significant amount of time, such as 34 to 150 ms, due to the initialization of the PHY connecting the host device to the memory system, link startup requirements (e.g., link initialization and negotiation between the host device and the memory system), and firmware initialization (e.g., preparation of logical-to-physical (L2P) tables and other background activities for the host device and / or the memory system). Initialization time can vary based on vendor and device type. Specifically, different devices manufactured by different vendors may require different amounts of time for different initialization phases and operations, such as link startup, no-op message transmission (NOP), fDeviceInit, and other operations. Initialization time can be affected by PHY initialization time, link startup time, slow PHY operation speed when reading from the boot ROM, and multiple UFS initialization processes executed during the initialization process. In some use cases, such as automotive use cases, reduced initialization time, such as less than 50ms, may be desirable.

[0059] During the initialization of the host device, the PHY connecting the host device to the memory system can operate at different times and at different link speeds. Such initialization may include initialization of the PHY connecting the host device to the memory system, initialization of the host device, and initialization of the memory system. Increasing the speed at which the PHY is configured to operate during one or more periods of the initialization process can reduce the amount of time required for the initialization process. Example initialization process 400 may include the initialization of the PHY, memory system, and other systems and / or devices. Initialization process 400 (also referred to as the boot process) can be divided into multiple phases, such as... Figure 4AAs shown. At the first stage 402, which may be a pre-bootloader (PBL) stage, the PBL can configure the PHY to operate at a lower speed (such as high-speed gear one (HS-G1) speed). For example, the PHY can be configured by the PBL at HS-G1 speed in the first stage 402 to minimize post-silicon changes to the PHY, which may require PBL patching. At the beginning of the first stage 402, the PHY can be configured to operate at a pulse width modulation 1 (PWM-1) speed, which may be slower than HS-G1 speed. At operation 418, the host device, PHY, and memory system can be powered on and initialized to operate at a low speed (such as PWR-1). Such operations may include power-on reset, hardware reset, and end-of-life reset. After performing such a reset, there may be no active task in the device UFS descriptor, and attributes and flags can be set to their default values. In addition, UniPro attributes can be reset. The memory system can be minimally initialized to allow the memory system to begin communicating with the host device via the PHY, and a link startup procedure can be performed. Such a link initiation process can initialize the earliest link between the host device and the memory system via the PHY. When operation 418 is complete, the PHY speed can be increased to HS-G1 speed. At operation 420, the host device can read from one or more boot lookup numbers (LUNs). In the second stage 404, a complete reinitialization of the memory system can be performed, and the PHY operating speed can be increased to high-speed gear 4 (HS-G4) speed. For example, at operation 422, the memory system, which may be a UFS memory system and the PHY, can be reset, and the link initiation process can be performed. After the reset, the PHY speed can be reduced to PWM-1 speed until at operation 424, when the UFS is reinitialized, NOP OUT is sent by the host device, NOP IN is received by the host device, and the memory system initialization phase (such as fDeviceInit) is completed. After operation 424 is complete, the PHY can be configured to operate at HS-G4 speed, where the PHY can read from all LUNs of the memory system at operation 426. The speeds of devices such as PWM-1, HS-G1, HS-G2, HS-G3, and HS-G4 can be, for example, the speeds specified by the UFS standard.

[0060] During initialization process 400, multiple resets and initializations of the memory system can be performed. For example, a first reset and initialization during first phase 402 and a second reset and initialization during second phase 404. Such resets and associated initializations and link startup operations can substantially contribute to the initialization time. For example, a link startup associated with a reset may contribute to and exceed 80 ms of the initialization time, with each link startup adding 20-30 ms to the initialization time. Furthermore, during a later startup phase, a complete re-initialization of the PHY and memory system can be performed, including configuring the PHY to operate at HS-G4 speed, the link startup process, the fDeviceInit process, and other startup operations. The link startup performed at operation 422 can invalidate and / or reset any initializations performed by the memory system prior to operation 422.

[0061] To reduce initialization time, such as boot time, the host device can perform a single initialization of the memory system and PHY during the initialization process. However, to allow the PHY to be initialized for higher-speed operation during PBL phase 402, PHY configuration information stored in the memory of the memory system (such as flash memory) can be used to patch the PHY for higher-speed operation (such as HS-G4 speed). For example, one or more of the link startup and initialization processes of the memory system can be eliminated, where the PHY and link startup processes are performed only once during the entire initialization process. In some cases, two link startups and one device initialization process can be eliminated. Eliminating one or more re-initialization processes of the PHY and / or memory system can reduce initialization time by up to or more than 70ms. Furthermore, the memory system can be configured to complete background initialization during second phase 404 and subsequent phases, which can allow skipping one or more NOP and fDeviceInit operations performed during second initialization phase 404. The PHY can also be initialized for higher-speed operation, such as HS-G4 instead of HS-G1, during the PBL phase, further reducing initialization time. For example, as... Figure 4B As shown in process 450, the PHY speed can be increased from the PW-1 speed at the beginning of the first stage 402 of the initialization process to the HS-G4 speed. The host device can then read from the boot LUN at HS-G4 speed instead of HS-G1 at 420, as... Figure 4A As shown in the diagram. Furthermore, operation 422 can be bypassed, and operation 452 can include a complete initialization of the memory system, including the fDeviceInit operation, while the PHY remains configured to operate at HS-G4 speed through the second stage 404 and subsequent stages.

[0062] Configuring a PHY to operate at high speeds (such as speeds greater than HS-G1) early in the boot process may include updating the PHY configuration. Such updates can be challenging due to limitations in post-silicon updates to PHY firmware and PBL ROM patching. Configuring the PHY to operate at high speeds early in the boot process (such as during PBL stage 402) increases the risk of PBL patching requirements due to post-silicon PHY characteristics, and also increases the risk of post-silicon PHY changes due to customer board-specific adjustments. Updating the PHY configuration during PBL stage 402 to facilitate PHY operation at speeds greater than HS-G1 may include using additional PBL patching space allocation to support such patching and to support UFS PHY updates that may occur after post-silicon characteristics. Such additional PBL patching space can increase the cost of the SoC, including the host device, PHY, and memory system. However, this can be mitigated by using buffers on memory (such as flash memory) of the memory system used to store PHY configuration information (such as one or more PHY patches for updating the PHY to operate at higher speeds). For example, the PHY configuration information stored in a buffer in the memory of the memory system can be patched, such as after the minimum initialization of the memory system is performed at operation 418 and before the initialization of the memory system is complete, such as before the fDeviceInit operation at 452 is completed. Updating the PHY configuration to operate at an enhanced speed early in the initialization process can reduce the amount of time required to complete the initialization process. For example, in Figure 4A In process 400, the PHY can be configured to operate at HS-G1 speed during PBL phase 402, while Figure 4B During process 450, the PHY can be configured to operate at HS-G4 or other higher speeds during PBL phase 402. The PHY can be reconfigured so that the operating speed is limited by the version of the UFS specification supported by the PHY. For example, if the PHY supports UFS 2.x, it can support the maximum speed of High Speed ​​Gear 3 (HS-G3), Rate B, 2L; if the PHY supports UFS 3.1, it can support the speed of HS-G4, Rate B, 2L; and if the PHY supports UFS 4.0, it can support the speed of High Speed ​​Gear 5 (HS-G5), Rate B, 2L.

[0063] As a specific instance, Figure 5 This is a flowchart illustrating an example initialization process, which can be similar to... Figure 4AThe initialization process 400. In some embodiments, the steps of method 500 may be performed by a host device connected to the memory system via a PHY. In some embodiments, one or more steps may be performed by the PHY and / or the memory system. Method 500 may include: at block 502, configuring the PHY connected to the host device to operate at a first speed (such as a high-reliability speed mode). Such a speed mode may be, for example, HS-G1 speed. Such configuration may be performed by the PBL of the host device.

[0064] At box 504, a first link startup can be performed. For example, the link between the host device and the memory system can be initialized. During this phase, the PHY can operate at PW-1 speed. Such a link startup may include sending a NOPOUT message to the memory system's controller and receiving a NOP IN message from the memory system's controller.

[0065] At box 506, gear shifting can be performed on the PHY to operate at HS-G1 speed. Such gear shifting can be performed, for example, based on the configuration of box 502.

[0066] At box 508, a device query can be sent from the host device and received by the memory system, and the host device can receive a response from the memory system. The response may include, for example, information about the memory system, such as the type of memory system, the boot process configuration of the memory system, one or more LUNs of the memory system storing boot information, the boot sequence ID, and other information for the initialization of the host device, PHY, and memory system.

[0067] At box 510, the host device may read information from one or more boot LUNs. Such information may include, for example, boot code for initializing the host device, PHY, and / or memory system. Specifically, the host device may send one or more Small Computer System Interface (SCSI) READ requests to the memory system to read boot code from a boot known logical unit.

[0068] At box 512, a UFS reset can be performed on the memory system. For example, the host device can completely reset the memory system to facilitate the configuration of the PHY for higher-speed operation.

[0069] At box 514, the PHY can be configured to operate at an increased speed, such as in a high-speed mode. For example, the PHY can be configured to operate in a maximum speed mode (such as HS-G4 speed). Such configuration can be performed, for example, by software.

[0070] At box 516, the link startup procedure can be executed. The link startup procedure in box 516 can be, for example, a second or third link startup procedure within the initialization process.

[0071] At box 518, the fDeviceInit operation can be performed to complete the initialization of the memory system.

[0072] At block 520, gear switching for the PHY to operate in a high-speed mode (such as HS-G4 speed mode) can be performed. In some embodiments, such a configuration may include a configuration to operate in the highest speed mode supported by the memory system. For example, the operating speed of the PHY can be increased from PWM-1 to HS-G4.

[0073] At box 522, a device query can be sent from the host device and received by the memory system, and the host device can receive a response from the memory system. This operation can be similar to that described at box 508.

[0074] At box 524, the host device can read information from one or more boot LUNs.

[0075] However, using PHY configuration information from a memory buffer in the memory system can allow for faster boot times by enabling the PHY configuration to operate at higher speeds earlier in the boot process and by allowing one or more reset, initialization, and link start operations to be bypassed. For example, operations at blocks 512-516 of method 500 can be bypassed by using such configuration information. Figure 6 The diagram illustrates an example method 600 that includes using PHY configuration information stored in a buffer of the memory system connected to the host device by the PHY to increase the speed of the PHY early in the boot process. Method 600 may include, at block 602, configuring the PHY that connects the host device to the memory system to operate at a first speed, such as operating in a reliable low-speed mode. The first speed may be, for example, an HS-G1 or PWM-1 speed. Such configuration may be performed by the host device's PBL to allow the host device to read from a buffer storing the PHY configuration information (e.g., from a SoC buffer).

[0076] At block 604, link initiation can be performed. For example, the link between the host device and the memory system can be initialized. During such a phase, the PHY can operate at PW-1 speed. The link initiation at block 604 can be, for example, the only link initiation process performed during method 600, where multiple link initiation processes can be performed in method 500.

[0077] At block 606, the host device can read PHY configuration information from a buffer (e.g., a buffer in the memory system). As described herein, the PHY configuration information may include one or more patches for patching the PHY. The PHY configuration information may, for example, include instructions for patching the PHY to operate at a higher speed. In some embodiments, the PHY configuration information may include information identifying the timing of applying patches to the PHY, the clock speed of the PHY, and other information for configuring the PHY. The PHY configuration information may be transferred from the memory system to the host device by the PHY, for example, when the PHY is operating at a PWM-1 or HS-G1 speed. In some embodiments, the buffer may be a SoC buffer. In some embodiments, the buffer may be located in an original equipment manufacturer (OEM) customized data area of ​​the memory. For example, the buffer may be located in a data area of ​​a configuration descriptor field to allow the host device to program and / or lock any host-specific data. Therefore, the buffer may be located in the read-only memory of the host device. The host device may be able to access such data with minimal latency early in the initialization of the memory device (e.g., early in the PBL initialization phase). For example, in some embodiments, such data may be accessible within 5ms at the start of the initialization process. For example, such data is accessible to the host device before it begins reading from one or more boot LUNs in the memory system. However, such data can be protected against modification after the device leaves the factory, and therefore such areas can be marked as read-only. However, storing PHY configuration data in the host device's read-only memory buffer may require an increased amount of read-only memory, which could increase device cost.

[0078] As another example, the buffer can reside in the non-volatile memory (e.g., flash memory) of the memory system. The buffer can be labeled SoC_BUFFER. Data stored in the buffer can be accessed at any time after the RST_n function is executed early in the boot process. The buffer can be used to write PHY configuration information, such as writing one or more PHY patches, during the device provisioning phase using the WRITE BUFFER command. The buffer can then be locked using the bConfigDescrLock command, which can render buffer reads only. Such a buffer can provide low-latency access to PHY configuration information. In some embodiments, the latency of such a buffer can be less than that of a buffer stored in NAND memory. As a specific example, when the MODE variable is set to 02h and the buffer ID is set to F0h, the host can determine that a PHY configuration buffer in the memory of the memory system is supported. The PHY configuration information can be read from the buffer by the host device during initialization using the READ BUFFER command. In some embodiments, the PHY configuration information can be read from the buffer by the host device before the initialization of the memory system (such as the initialization of the flash memory where the buffer resides) is complete. The PHY configuration information stored in the buffer may include information for adjusting the PHY configuration to operate at a higher speed. For example, the PHY configuration information may include information for patching the PHY to operate at the highest speed supported by the UFS version of the memory system. In some embodiments, the buffer may include a library of PHY patches for different maximum PHY speeds, and the PHY patches may be selected based on the UFS version of the memory system. In some embodiments, buffer labels, commands, and functions may be labels, functions, and commands identified by the UFS standard.

[0079] At box 608, the PHY can be configured to operate at a second higher speed based on PHY configuration information. For example, the PHY configuration can be updated based on PHY configuration information stored in a buffer (such as a SoC buffer). For example, the PHY configuration can be updated to adjust the PHY speed from a first slower speed (such as PWM-1 or HS-G1) to a higher speed (such as high-speed gear 2 (HS-G2), HS-G3, HS-G4, HS-G5, or another higher speed). This adjustment can, for example, involve applying a patch to the PHY.

[0080] At box 610, a second link startup procedure can be performed. For example, the link between the host device and the memory system via the PHY can be re-established.

[0081] At box 612, gear shifting can be performed on the PHY, and the PHY can begin operating at a higher speed supported by adjustments to the PHY configuration. For example, the PHY can begin operating at speeds HS-G2, HS-G3, HS-G4, and HS-G5.

[0082] At box 614, a device query can be sent from the host device and received by the memory system, and the host device can receive a response from the memory system. This operation can be similar to that described at box 508.

[0083] At box 616, the host device can read from one or more boot LUNs of the memory system at a higher speed (such as HS-G4) supported by the PHY.

[0084] At box 618, the fDeviceInit operation can be executed, and the memory system initialization can be completed. Therefore, PHY configuration information can be read from the memory of the memory system, and the PHY can be configured to operate at a higher speed based on the PHY configuration information before the memory system initialization is complete. For example, regarding... Figure 5 In the described method, without a buffer containing PHY configuration information, the PHY may not operate at maximum speed until after the fDeviceInit operation is complete, but instead use the buffer containing PHY configuration information to update, for example, regarding... Figure 6 The described PHY configuration allows the PHY to operate at high speeds (such as HS-G4) even before the memory, including the buffer, is initialized.

[0085] At box 620, a device query can be sent from the host device and received by the memory system, and the host device can receive a response from the memory system. This operation can be similar to that described at box 508.

[0086] At box 622, the host device can continue reading from all LUNs. For example, data can be read from all LUNs of the memory system at the highest supported speed. Therefore, using the PHY configuration information stored in the buffer to patch the PHY to operate at a higher speed early in the boot process can reduce the boot process time.

[0087] Figure 7This is a flowchart illustrating a method for updating the configuration of a PHY to operate at a high speed earlier during the initialization process of a host controller, according to some embodiments of the present disclosure. Method 700 includes, at block 702, initializing the PHY by the host controller of a host device to operate at a first speed, the PHY connecting the host device's memory controller to a memory system. For example, the host device, PHY, and memory system may be included in a SoC. The initialization process of the host device may include the initialization of the PHY and the memory system. The memory system may, for example, be a UFS memory system including one or more flash memories. The initialization process may also be referred to as a boot process. The PHY may be initialized, for example, upon completion of power-on and when the memory system is minimally initialized to operate at the first speed. The first speed may, for example, be a low speed, such as PWM-1 speed or HS-G1 speed. The initialization process may, for example, include a link initiation process, also referred to as a link initialization process, for initializing the link between the host device's memory controller and the memory system via the PHY. Such initialization may, for example, be performed by the host device's PBL during the PBL phase of the host device's initialization.

[0088] At block 704, the host device's memory controller may send a request for PHY configuration information for configuring the PHY to operate at a second speed. For example, the memory controller may send a request via the PHY to the memory system for PHY configuration information to configure the PHY to operate at a second speed from a first buffer in the memory system. The PHY configuration information may, for example, include PHY patches associated with a second speed greater than the first speed. For example, the PHY configuration information may include higher gear parameters for PHY reconfiguration. As another example, the PHY configuration information may include one or more post-silicon updates to the PHY configuration, such as updates for increasing the PHY speed, patching one or more PHY errors, optimizing the PHY for operation with a particular host device and / or memory system, or otherwise tuning PHY operation. For example, the PHY configuration information may include one or more PHY tuning parameters. The first buffer may, for example, be a SoC buffer stored on flash memory in the memory system. The buffer may, for example, be a portion of memory in the memory system, such as flash memory allocated for storage by the host device for storing PHY configuration information and, in some embodiments, other information. Other information stored in the buffer may include, for example, additional information for the configuration of the host device and / or SoC, such as information used by the host device before memory system initialization is complete. For example, other information stored in the buffer may include SoC or host configuration information for enabling or disabling hardware or software interfaces and / or adjusting other hardware or software configuration parameters. For example, the buffer may include PHY configuration information for configuring the PHY to operate at one or more speeds greater than a first speed (such as HS-G2, HS-G3, HS-G4, HS-G5, or another higher speed). In some embodiments, the request may include, for example, a READ BUFFER command. Such a command can be used to access information stored in the buffer before and after the host device is fully initialized. The size of the buffer may be, for example, 4kB. In some embodiments, the buffer may store one or more PHY patches for patching the PHY to operate at one or more higher speeds. In some embodiments, the request may specify a particular PHY patch to retrieve from the buffer. For example, the request may specify a PHY patch for configuring the PHY to operate at the highest speed supported by the UFS version of the memory system. Such a request can be sent, for example, by the host device's PBL during the host device's initialization PBL phase. In some embodiments, the buffer can be configured to be read-only to prevent revisions to the PHY configuration information. In some embodiments, the request can be sent after receiving the first NOP IN from the memory system and before sending the first device query to the memory system.

[0089] In some embodiments, the WRITE BUFFER command can be used to update the buffer after the host device has been fully initialized. For example, if the bConfigDescrLock variable is set to 00h, the memory system can process a WRITE BUFFER command targeting the buffer. However, in some embodiments, the buffer can be locked and can be read-only. In such embodiments, the bConfigDescrLock variable can be set to a value of 01h, and the memory system (such as the memory controller of the memory system) can terminate the received WRITE BUFFER command that causes the buffer to have a target with its SENSE KEY variable set to DATA PROTECT's CHECK CONDITION STATUS. In some embodiments, the buffer variables and commands can be variables and commands identified by the UFS standard.

[0090] At block 706, the host device's memory controller can receive PHY configuration information from the memory system. For example, the requested PHY configuration information can be received by the memory controller via the PHY that connects the host device's memory controller to the memory system. The requested PHY configuration information can be received, for example, by the host device's PBL during the host device's initialization PBL phase.

[0091] At block 708, the host device's memory controller can adjust the PHY configuration to operate at a second speed based on the PHY configuration information. For example, the memory controller can apply a patch of configuration information to the PHY to adjust its configuration so that the PHY begins operating at a second higher speed. The memory controller can then continue communicating with the memory system via the PHY at the second higher speed. The PHY configuration can be adjusted, for example, by the host device's PBL during the PBL phase of the host device's initialization. In some embodiments, the host device's memory controller can be configured to complete the initialization of the memory system after the PHY configuration is adjusted to operate at the second speed, such as the initialization of a flash memory including a buffer storing the PHY configuration information. For example, part or all of the fDeviceInit operation can be performed and completed after the PHY configuration is updated for operating the PHY at the second speed. Therefore, the PHY configuration can be updated to increase the PHY speed during the PBL phase of the initialization process, and the PHY can continue to facilitate communication between the host device and the memory system at a higher speed during the PBL phase of the initialization process and in subsequent phases of the initialization process. Using such a buffer allows for post-silicon updates to facilitate enhanced PHY speed without requiring additional boot ROM for the host device. Such a buffer thus allows for optimized boot processes, reduced initialization time, storage of higher gear parameters, and reconfiguration of the PHY to operate at higher speeds during the PBL and bootloader initialization phases. Including a buffer on the memory of the memory system allows for optimization of the host device's boot ROM. For example, when an ROM error or inefficiency is found in the host device's ROM, the buffer can store a patch in the ROM code to correct the error and / or improve performance, rather than requiring a new die spinner. Furthermore, such a buffer can be used to store one or more custom operations for one or more initialization phases of the host device.

[0092] Figure 8 This is a flowchart illustrating a method 800 for updating the configuration of a PHY to operate at high speed early in the initialization process of a flash memory system, according to some embodiments of this disclosure. The memory system may be connected to the memory controller of a host device, for example, via the PHY. Method 800 may be performed by the memory controller of the flash memory system. Method 800 includes: at block 802, after the PHY, to which the memory controller is connected to the host device, is initialized to operate at a first speed, the memory controller of the memory system receives from the host device a request for PHY configuration information for configuring the PHY to operate at a second speed greater than the first speed. The request may, for example, be about... Figure 7The request described in box 704, and the buffer may be a buffer that stores PHY configuration information (such as one or more PHY patches), as per the description. Figure 7 As described.

[0093] At box 804, the memory controller can send PHY configuration information to the host device. For example, the memory controller of the memory system can send requested PHY configuration information for updating the PHY to the memory controller of the host device, such as regarding... Figure 7 As described in box 706. Therefore, the memory controller can receive requests and can send PHY configuration information before the memory system is fully initialized (such as before the fDeviceInit operation for the memory system is completed). The host device can then adjust the PHY configuration according to the PHY configuration information, such that the PHY is configured to operate at a second speed. The host device can then continue to communicate with the memory controller of the memory system via the PHY at the second speed.

[0094] The operation of method 500, method 600, method 700, or method 800 can be performed by the UE (such as reference). Figure 9 The UE described herein is used to perform this action. For example, example operations (also referred to as “boxes”) of method 500, method 600, method 700, or method 800 can enable UE 915 to support greater user data confidentiality. Figure 9 This is a block diagram illustrating details of an example wireless communication system according to one or more aspects. The wireless communication system may include a wireless network 900. The wireless network 900 may, for example, include a 5G wireless network. As those skilled in the art will understand, in Figure 9 The components appearing in this network likely have corresponding counterparts in other network arrangements, including, for example, cellular and non-cellular network arrangements (e.g., device-to-device, peer-to-peer, or self-organizing network arrangements).

[0095] exist Figure 9The wireless network 900 shown includes multiple base stations 905 and other network entities. A base station can be a station communicating with a UE and can also be referred to as an evolved Node B (eNB), a next-generation eNB (gNB), an access point, etc. Each base station 905 can provide communication coverage for a specific geographic area. In 3GPP, the term "cell" can refer to the specific geographic coverage area of ​​a base station or a base station subsystem serving that coverage area, depending on the context in which the term is used. In the implementation of the wireless network 900 described herein, base stations 905 can be associated with the same operator or different operators (e.g., the wireless network 900 can include multiple operator wireless networks). Additionally, in the implementation of the wireless network 900 described herein, base stations 905 can use one or more frequencies of the same frequency (e.g., one or more bands of licensed spectrum, unlicensed spectrum, or combinations thereof) as neighboring cells to provide wireless communication. In some examples, a single base station 905 or UE 915 can be operated by more than one network operating entity. In some other examples, each base station 905 and UE 915 can be operated by a single network operating entity.

[0096] Base stations can provide communication coverage for macro cells, small cells (e.g., pico cells or femto cells), or other types of cells. Macro cells typically cover a relatively large geographic area (e.g., a radius of several kilometers) and allow unrestricted access by UEs with service subscriptions to a network provider. Small cells (such as pico cells) typically cover a relatively small geographic area and allow unrestricted access by UEs with service subscriptions to a network provider. Small cells (such as femto cells) also typically cover a relatively small geographic area (e.g., residential areas) and, in addition to unrestricted access, provide restricted access by UEs associated with that femto cell (e.g., UEs in a Closed Subscriber Group (CSG), UEs for users in a residence, etc.). A base station used for a macro cell can be referred to as a macro base station. A base station for a small cell can be referred to as a small cell base station, pico base station, femto base station, or home base station. Figure 9 In the examples shown, base stations 905d and 905e are conventional macro base stations, while base stations 905a-905c are macro base stations implemented using one of 3D MIMO, full-dimensional (FD) MIMO, or massive MIMO. Base stations 905a-905c utilize their higher-dimensional MIMO capabilities to increase coverage and capacity using 3D beamforming in both elevation and azimuth beamforming. Base station 905f is a small cell base station, which can be a home node or a portable access point. A base station can support one or more (e.g., two, three, four, etc.) cells.

[0097] The Wireless Network 900 can support synchronous or asynchronous operation. For synchronous operation, base stations can have similar frame timings, and transmissions from different base stations can be roughly aligned in time. For asynchronous operation, base stations may have different frame timings, and transmissions from different base stations may not be aligned in time. In some cases, the network can be enabled or configured to handle dynamic switching between synchronous and asynchronous operation.

[0098] UE 915 can be distributed throughout the entire wireless network 900, and each UE can be stationary or mobile. It should be understood that although mobile devices are generally referred to as UEs in standards and specifications issued by 3GPP, such devices can be otherwise referred to by those skilled in the art as mobile station (MS), subscriber station, mobile unit, subscriber unit, radio unit, remote unit, mobile device, radio device, wireless communication device, remote device, mobile subscriber station, access terminal (AT), mobile terminal, radio terminal, remote terminal, handheld device, terminal, user agent, mobile client, client, gaming device, augmented reality device, vehicle component, vehicle equipment or vehicle module, or some other suitable term. Within this document, a “mobile” device or UE does not necessarily need to be mobile and can be stationary. Some non-limiting examples of mobile devices (such as implementations that may include one or more of those in UE915) include mobile stations, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, laptop computers, personal computers (PCs), notebook computers, netbooks, smartbooks, tablet devices, and personal digital assistants (PDAs). Mobile devices can also be IoT or “Internet of Everything” (IoE) devices, such as automobiles or other vehicles, satellite radio units, Global Positioning System (GPS) devices, Global Navigation Satellite System (GNSS) devices, logistics controllers, flight equipment, smart energy or security devices, solar panels or solar arrays, municipal lighting, water or other infrastructure; industrial automation and enterprise equipment; consumer and wearable devices, such as glasses, wearable cameras, smartwatches, health or fitness trackers, mammalian implantable devices, posture tracking devices, medical devices, digital audio players (e.g., MP3 players), cameras, game consoles, etc.; and digital home or smart home devices, such as home audio, video and multimedia equipment, appliances, sensors, vending machines, smart lighting, home security systems, smart meters, etc. In one aspect, the UE can be a device that includes a Universal Integrated Circuit Card (UICC). In another aspect, the UE can be a device that does not include a UICC. In some aspects, a UE that does not include a UICC can also be referred to as an IoE device. Figure 9The UEs 915a-915d shown in the implementation are examples of mobile smartphone-type devices accessing the wireless network 900. The UE can also be a machine specifically configured for connected communications, including machine-type communication (MTC), enhanced MTC (eMTC), narrowband IoT (NB-IoT), etc. Figure 9 The UE915e-915k shown is an example of various machines configured for communication to access the wireless network 900.

[0099] Mobile devices (such as UE 915) can communicate with any type of base station (whether macro base station, pico base station, femto base station, repeater, etc.). Figure 9 In this context, a communication link (represented by a lightning bolt shape) indicates a radio transmission between the UE and a serving base station (which is designated to serve the UE on the downlink or uplink), or a desired transmission between base stations, and a backhaul transmission between base stations. In some scenarios, the UE may operate as a base station or other network node. Backhaul communication between base stations of the wireless network 900 can be performed using wired or wireless communication links.

[0100] In operation at wireless network 900, base stations 905a-905c use 3D beamforming and cooperative spatial technologies (e.g., Cooperative Multipoint (CoMP) or Multi-Connection) to serve UEs 915a and 915b. Macro base station 905d performs backhaul communication with base stations 905a-905c and the small cell (base station 905f). Macro base station 905d also transmits multicast services customized and received by UEs 915c and 915d. Such multicast services may include mobile TV or streaming video, or may include other services for providing community information, such as weather emergencies or alerts (e.g., Amber Alerts or Grey Alerts).

[0101] The wireless network 900 supports mission-critical communication for mission-critical equipment (such as UE 915e, which is an aircraft) using highly reliable and redundant links. Redundant communication links with UE 915e include links from macro base stations 905d and 905e, and small cell base station 905f. Other machine-type devices (such as UE 915f (thermometer), UE 915g (smart meter), and UE 915h (wearable device)) can communicate directly with base stations (such as small cell base station 905f and macro base station 905e) via the wireless network 900, or in a multi-hop configuration by communicating with another user device that relays its information to the network (e.g., UE 915f transmits temperature measurement information to the smart meter (UE 915g), and the temperature measurement information is subsequently reported to the network via small cell base station 905f). The wireless network 900 can also provide additional network efficiency through dynamic, low-latency TDD or low-latency FDD communication (such as in vehicle-to-vehicle (V2V) mesh networks between UE915i-915k communicating with macro base station 905e).

[0102] In various implementations, the technologies and apparatus described can be used in wireless communication networks such as Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, Single Carrier FDMA (SC-FDMA) networks, LTE networks, GSM networks, 5th Generation (5G) or New Radio (NR) networks (sometimes referred to as "5G NR" networks, systems, or devices), and other communication networks. As described herein, the terms "network" and "system" are used interchangeably. For example, a CDMA network can implement radio technologies such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc. UTRA includes Wideband CDMA (W-CDMA) and Low Chip Rate (LCR). CDMA2000 encompasses the IS-2000, IS-95, and IS-856 standards. For example, a TDMA network can implement radio technologies such as Global System for Mobile Communications (GSM). The 3rd Generation Partnership Project (3GPP) defines standards for GSM EDGE (GSM Evolution Enhanced Data Rate) Radio Access Networks (RANs) (also known as GERAN). OFDMA networks can implement radio technologies such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, and flash-OFDM. UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunications System (UMTS). In particular, Long Term Evolution (LTE) is a UMTS version that uses E-UTRA. Different network types can use different Radio Access Technologies (RATs) and RANs.

[0103] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, various implementations or uses may arise via integrated chip implementations or other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail or purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not be specific to a particular use case or application, a wide variety of applicability to the described innovations is possible. The range of implementations can extend from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more described aspects. In some practical settings, devices incorporating described aspects and features may also necessary include additional components and features for implementing and practicing the claimed and described aspects. The innovations described herein are intended to be implemented in a variety of ways, including large or small devices with different sizes, shapes and constructions, chip-level components, multi-component systems (e.g., radio frequency (RF) chains, communication interfaces, processors), distributed layouts, end-user devices, etc.

[0104] In one or more aspects, the technology for supporting data storage and / or data transfer may include additional aspects, such as any single aspect or any combination of aspects described below or in conjunction with one or more other processes or devices described elsewhere herein. In one aspect, an electronic device (such as a UE) may be an apparatus such as a host device, the host device including a memory controller configured to be coupled to a memory system via a physical interface (PHY), wherein the memory system may be integrated with or externally coupled to the host device. The memory system may include a memory controller coupled to the memory system via a first channel and configured to access data stored in the memory system via the first channel, coupled to the host device via a first interface (such as a PHY), and configured to communicate with the host device via the first interface. Operations may be performed as part of an initialization operation, a read operation, or a write operation.

[0105] In a first aspect, the memory controller of the memory system can be configured to perform operations including: after the PHY is initialized to operate at a first speed, receiving from the host device a request for PHY configuration information, the PHY configuration information being used to configure the PHY to operate from a first buffer of the memory module at a second speed greater than the first speed; and sending the PHY configuration information to the host device.

[0106] In a second aspect, in conjunction with the first aspect, the first buffer is located in the flash memory of the memory module.

[0107] In a third aspect, in conjunction with one or more of the first or second aspects, the transmission of the PHY configuration information is performed before the initialization of the flash memory is completed.

[0108] In a fourth aspect, in conjunction with one or more of the first to third aspects, the PHY is initialized to operate at the first speed during the link initialization phase of the host device's initialization.

[0109] In a fifth aspect, in conjunction with one or more of the first to fourth aspects, the PHY configuration information includes a PHY patch associated with the second speed.

[0110] In a sixth aspect, in conjunction with one or more of the first to fifth aspects, the buffer stores multiple PHY patches associated with multiple speeds.

[0111] In the seventh aspect, in conjunction with one or more of the first to sixth aspects, the first buffer is configured to be read-only.

[0112] In an eighth aspect, the memory controller of the host device can be configured to perform operations including: initializing the PHY to operate at a first speed; receiving PHY configuration information for configuring the PHY to operate from a first buffer of the memory system at a second speed greater than the first speed; and adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information.

[0113] In the ninth aspect, in conjunction with the eighth aspect, the first buffer is located in the flash memory of the memory system.

[0114] In a tenth aspect, in conjunction with one or more of the eighth to ninth aspects, the memory controller is further configured to complete the initialization of the flash memory after adjusting the configuration of the PHY.

[0115] In the eleventh aspect, in conjunction with one or more of the eighth to tenth aspects, the PHY is initialized to operate at a first speed including a link initialization phase that completes the initialization of the host device.

[0116] In a twelfth aspect, in conjunction with one or more of aspects eight through eleven, the memory controller of the memory system may also be configured to perform operations including: sending a request for PHY configuration information to the memory system after initializing the PHY to operate at the first speed.

[0117] In the thirteenth aspect, in conjunction with one or more of the eighth to twelfth aspects, the PHY configuration information includes a PHY patch associated with the second speed, and wherein adjusting the configuration of the PHY includes applying the PHY patch.

[0118] In the fourteenth aspect, in conjunction with one or more of aspects eight through thirteen, the buffer stores multiple PHY patches associated with multiple speeds.

[0119] In the fifteenth aspect, in conjunction with one or more of the eighth to fourteenth aspects, the first buffer is configured to be read-only.

[0120] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0121] The article about Figure 1-8 The components, functional blocks, and modules described include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, and other examples or any combination thereof. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other terms, software should be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable programs, threads of execution, procedures and / or functions, and other examples. Furthermore, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0122] Those skilled in the art believe that, referring to Figure 4A One or more boxes (or operations) described in -E, 5, 6, 7, or 8 may be combined with one or more boxes (or operations) described with reference to another figure. For example, Figure 1One or more boxes (or operations) can be combined with Figure 3 A combination of one or more boxes (or actions). As another example, with... Figure 1 One or more associated boxes can be combined with Figure 4A -E, 5, 6, 7, or 8 are associated with one or more boxes (or operations). Alternatively or alternatively, refer to the above. Figures 1-3 One or more of the operations described can be compared with those shown in Figure 4- Figure 8 The above one or more operations are combined.

[0123] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in relation to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure. It will also be readily apparent to those skilled in the art that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure can be combined or performed in ways different from those shown and described herein.

[0124] The various illustrative logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the implementation methods disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether this functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0125] Hardware and data processing apparatuses for implementing the various illustrative logics, logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a general-purpose single-chip or multi-chip processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some implementations, specific processes and methods may be executed by circuitry specific to a given function.

[0126] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware (including the structures disclosed in this specification and their structural equivalents), or any combination thereof. Implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0127] If implemented in software, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module residing on a computer-readable medium. Computer-readable media include both computer storage media and communication media, wherein the communication medium includes any medium capable of being implemented to transfer a computer program from one place to another. Storage media can be any available medium accessible by a computer. By way of example, and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. Furthermore, any connection may be appropriately referred to as a computer-readable medium. As used herein, "disk" and "optical disc" include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while optical discs utilize lasers to optically copy data. The combinations described above should also be included within the scope of computer-readable media. Furthermore, the operation of a method or algorithm may reside as one or any combination or set of code and instructions on machine-readable and computer-readable media, which may be incorporated into a computer program product.

[0128] Various modifications to the implementations described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are given the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0129] Additionally, those skilled in the art will readily understand that opposing terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” or “forward” and “backward” are sometimes used for the convenience of describing graphics and indicate the relative position of the graphics on a correctly oriented page, and may not reflect the correct orientation of any device.

[0130] Some features described in this specification in the context of different implementations can also be implemented in a combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features are described above as working under a particular combination and even initially claimed in this way, in some cases one or more features in the claimed combination can be separated from the combination, and the claimed combination can be for sub-combinations or variations thereof.

[0131] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or performing all shown operations to achieve the desired result. Furthermore, the drawings may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be incorporated into the schematically shown example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any shown operations. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be construed as requiring such separation in all implementations, but rather should be understood as meaning that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result.

[0132] As used herein (including in the claims), when used in a list of two or more items, the term "or" means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a composition is described as containing components A, B, or C, the composition may contain: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including in the claims), "or" as in a list of items ending in "at least one of" indicates a separate list, such that, for example, a list of "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination thereof. As understood by one of ordinary skill in the art, the term "substantially" is defined as largely but not necessarily fully specified (and includes specified; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any publicly disclosed implementation, the term “substantially” can be replaced with “within the specified [percentage]”, where the percentage includes 0.1, 1, 5, or 10%.

[0133] The foregoing description of this disclosure is provided to enable those skilled in the art to implement or use it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A host device's memory controller, configured to couple the host device to a memory system via a physical layer interface (PHY), the memory controller being configured to perform operations including the following: The PHY is initialized to operate at a first speed; Receive PHY configuration information from the first buffer of the memory system for configuring the PHY to operate at a second speed greater than the first speed; as well as Based on the PHY configuration information, the PHY configuration is adjusted to operate at the second speed.

2. The apparatus according to claim 1, wherein, The first buffer is located in the flash memory of the memory system.

3. The apparatus according to claim 2, wherein, The memory controller is also configured to complete the initialization of the flash memory after adjusting the configuration of the PHY.

4. The apparatus according to claim 3, wherein, The PHY is initialized to operate at the first speed, including a link initialization phase that completes the initialization of the host device.

5. The apparatus according to claim 1, wherein, The memory controller is also configured to perform operations including the following: After initializing the PHY to operate at the first speed, a request for PHY configuration information is sent to the memory system.

6. The apparatus according to claim 1, wherein, The PHY configuration information includes a PHY patch associated with the second speed, and wherein adjusting the PHY configuration includes applying the PHY patch.

7. The apparatus according to claim 6, wherein, The buffer stores multiple PHY patches associated with multiple speeds.

8. The apparatus according to claim 1, wherein, The first buffer is configured to read-only.

9. A method comprising: The host device's memory controller initializes the physical interface (PHY) for connecting the host device to the memory system to operate at a first speed; Receive PHY configuration information from the first buffer of the memory system for configuring the PHY to operate at a second speed greater than the first speed; as well as The memory controller adjusts the PHY configuration to operate at the second speed according to the PHY configuration information.

10. The method according to claim 9, wherein, The first buffer is located in the flash memory of the memory system.

11. The method of claim 10, further comprising: After adjusting the configuration of the PHY, the initialization of the flash memory is completed.

12. The method according to claim 11, wherein, The PHY is initialized to operate at the first speed, including a link initialization phase that completes the initialization of the host device.

13. The method of claim 9, further comprising: After initializing the PHY to operate at the first speed, a request for PHY configuration information is sent to the memory system.

14. The method according to claim 9, wherein, The PHY configuration information includes a PHY patch associated with the second speed, and wherein adjusting the PHY configuration includes applying the PHY patch.

15. The method according to claim 14, wherein, The buffer stores multiple PHY patches associated with multiple speeds.

16. The method according to claim 9, wherein, The first buffer is configured to read-only.

17. An apparatus comprising: Memory controller: Coupled to the memory module via the first channel, and configured to access data stored in the memory module via the first channel; as well as Coupled to the host device via a first physical interface (PHY), and configured to communicate with the host device via the first PHY. The memory controller is configured to perform operations including the following: After the PHY is initialized to operate at a first speed, a request for PHY configuration information is received from the host device. The PHY configuration information is used to configure the PHY to operate from the first buffer of the memory module at a second speed greater than the first speed. as well as Send the PHY configuration information to the host device.

18. The apparatus according to claim 17, wherein, The first buffer is located in the flash memory of the memory module.

19. The apparatus according to claim 18, wherein, The PHY configuration information is sent before the initialization of the flash memory is complete.

20. The apparatus according to claim 19, wherein, The PHY is initialized to operate at the first speed during the link initialization phase of the host device's initialization.

21. The apparatus according to claim 17, wherein, The PHY configuration information includes a PHY patch associated with the second speed.

22. The apparatus according to claim 21, wherein, The buffer stores multiple PHY patches associated with multiple speeds.

23. The apparatus according to claim 17, wherein, The first buffer is configured to read-only.

24. A method comprising: After the physical interface (PHY) connecting the memory controller to the host device is initialized to operate at a first speed, a request for PHY configuration information for configuring the PHY to operate at a second speed greater than the first speed is received from the memory controller of the host device, from a first buffer of the memory module coupled to the memory controller. as well as The memory controller sends the PHY configuration information to the host device.

25. The method according to claim 24, wherein, The first buffer is located in the flash memory of the memory module.

26. The method of claim 25, wherein, The PHY configuration information is sent before the initialization of the flash memory is complete.

27. The method according to claim 26, wherein, The PHY is initialized to operate at the first speed during the link initialization phase of the host device's initialization.

28. The method according to claim 24, wherein, The PHY configuration information includes a PHY patch associated with the second speed.

29. The method according to claim 28, wherein, The buffer stores multiple PHY patches associated with multiple speeds.

30. The method according to claim 24, wherein, The first buffer is configured to read-only.

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