Microelectronic device and related memory device package and electronic system

Abstract

A microelectronic device includes: a controller device; a first die vertically overlying the controller device; a second die vertically overlying the first die; and a lead. The first die includes a first pad horizontally separated by a first distance from a horizontal center of the controller device. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance. The lead contacts the first pad of the first die and the second pad of the second die. A memory device package and an electronic system are also disclosed.

Description

[0001] Priority Claim

[0002] This application claims the filing date benefit of U.S. Provisional Patent Application No. 63 / 489,047, filed March 8, 2023, entitled “Microelectronic Devices, and Relatted Memory Device Packages and Electronic Systems,” and U.S. Patent Application No. 18 / 424,693, filed January 26, 2024, entitled “Microelectronic Devices, and Relatted Memory Device Packages and Electronic Systems,” the full disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design. More specifically, this disclosure relates to microelectronic devices comprising wire-bonded memory dies as memory device system stacks and configured in fan-in assemblies, and to electronic systems comprising stacks and fan-in assemblies containing wire-bonded memory dies. Background Technology

[0004] Microelectronic devices typically require complex external interconnections between memory devices and other devices, such as processors, including logic and graphics processors. Memory devices, which can be assembled using wire bonding technology, are often provided as internal integrated circuits in computers or other electronic devices, and one type of memory device includes, but is not limited to, volatile memory devices. One type of volatile memory device is a NAND-based memory device. A NAND-based memory device may include a three-dimensional (3D) memory array comprising hierarchical strings of memory cells arranged in horizontal rows extending in a first horizontal direction and columns extending in a second horizontal direction, wherein the strings of memory cells are coupled to contact means, such as a stepped contact structure. Another type of volatile memory device is a dynamic random access memory (DRAM) device.

[0005] Wire-bonded memory devices can be assembled onto a package board or motherboard. Unfortunately, wire bonding consumes available substrate surface area on the package board or motherboard. Summary of the Invention

[0006] In some embodiments, a microelectronic device includes: a controller device; a first die vertically overlying the controller device; a second die vertically overlying the first die; and a lead. The first die includes a first pad horizontally separated from the horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance. The lead contacts the first pad of the first die and the second pad of the second die.

[0007] In an additional embodiment, a memory device package includes: a memory controller device vertically overlaid on a package substrate; a first die vertically overlaid on the memory controller device and including a first bonding pad; a second die vertically overlaid on the first die and including a second bonding pad; and a first lead bonded to the first bonding pad of the first die and the second bonding pad of the second die. The horizontal center of the memory controller device is horizontally further away from the second bonding pad of the second die than from the first bonding pad of the first die.

[0008] In another embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device. The memory device includes a controller device, a first die, a second die, and leads. The first die vertically covers and horizontally overlaps the controller device and includes a first bonding pad. The second die vertically covers and horizontally overlaps the first die and includes a second bonding pad. The horizontal center of the controller device is positioned closer to the first bonding pad of the first die than to the second bonding pad of the second die. The leads are bonded to the first bonding pad of the first die and the second bonding pad of the second die. Attached Figure Description

[0009] Figure 1 This illustration shows a simplified vertical cross-sectional view of a microelectronic device with a fan-in lead-bonded interposer flip-chip memory device controller configuration according to some embodiments of the present disclosure.

[0010] Figures 1A to 1F Description of some embodiments according to this disclosure in the formation Figure 1 Simplified vertical cross-sectional view of different processing stages of a microelectronic device method ( Figure 1A , 1B 1C, 1E and 1F) and simplified partial perspective views ( Figure 1D ).

[0011] Figure 2This illustration shows a simplified vertical cross-sectional view of a microelectronic device with a fan-in lead-bonded integrated redistribution layer and a flip-chip memory device controller configuration according to some embodiments of the present disclosure.

[0012] Figure 2A Description of some embodiments according to this disclosure in the formation Figure 2 A simplified perspective view of the processing stage of a method for microelectronic devices.

[0013] Figure 3 This illustration shows a simplified vertical cross-sectional view of a microelectronic device having a fan-in lead-bonded memory device controller and a lead-bonded interposer configuration according to some embodiments of the present disclosure.

[0014] Figure 3A and 3B Description of some embodiments according to this disclosure in the formation Figure 3 A simplified perspective view of the different processing stages of a method for a microelectronic device.

[0015] Figure 4A and 4B A simplified partial vertical cross-sectional view illustrating a microelectronic device with a fan-in lead-bonded interposer flip-chip memory device controller configuration (in an XY symmetrical configuration comprising at least four memory die groups) according to some embodiments of the present disclosure. Figure 4A ) and simplified top view ( Figure 4B ).

[0016] Figure 5 A flowchart illustrating a method for assembling a microelectronic device package according to some embodiments of the present disclosure.

[0017] Figure 6 A flowchart illustrating a method for manufacturing a microelectronic device package according to an additional embodiment of the present disclosure.

[0018] Figure 7 This is a block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The following description provides specific details (e.g., material compositions, shapes, and sizes) to provide an exhaustive description of embodiments of the present disclosure. However, those skilled in the art will understand that embodiments of the present disclosure can be practiced without these specific details. In fact, embodiments of the present disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structures can be performed using conventional manufacturing techniques.

[0020] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings are anticipated due to, for example, manufacturing techniques and / or limitations. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but include, for example, shape deviations arising from manufacturing processes. For example, an area illustrated or described as box-shaped may have rough and / or non-linear features, and an area illustrated or described as circular or curved may include some rough and / or linear features. Furthermore, acute angles illustrated may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the appended claims. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same numerical designation.

[0021] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and only by way of non-limiting example, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory; conventional non-volatile memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0022] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and the device.

[0023] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure having a relatively larger area compared to its other surfaces. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0024] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) mean and include features of the disclosed individuals (or individuals) located closest to each other (e.g., closest to each other). Additional features (e.g., additional areas, additional structures, additional devices) of disclosed individuals (or individuals) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature of an individual different from an individual associated with at least one “adjacent” feature is positioned between “adjacent” features. Accordingly, features described as “vertically adjacent” to each other mean and include features of the disclosed individuals (or individuals) located most vertically adjacent to each other (e.g., closest to each other). Furthermore, features described as “horizontally adjacent” to each other mean and include features of the disclosed individuals (or individuals) located most horizontally adjacent to each other (e.g., closest to each other).

[0025] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “bottom,” “top,” “above,” “upper,” “front,” “back,” “left,” “right,” and the like may be used to describe the relationship of one element or feature to another element(s), as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figures were reversed, an element described as “below other elements or features,” “below other elements or features,” “under other elements or features,” or “on the bottom of other elements or features” would then be oriented as “above other elements or features” or “on the top of other elements or features.” Thus, depending on the context in which the terms are used, the term “below” may cover both orientations of above and below, as will be apparent to one of ordinary skill in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0026] As used herein, the singular forms “a” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0027] As used in this article, “and / or” includes any and all combinations of one or more of the items listed in connection with the document.

[0028] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other (e.g., via direct ohmic connection or via indirect connection (e.g., via another structure) electrically connected).

[0029] As used herein, the term "generally" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with a range of variation (e.g., within acceptable tolerances), as would be understood by one of ordinary skill in the art. For example, depending on the specific parameter, property, or condition that is generally satisfied, it may be satisfied by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0030] As used herein, “about” or “approximate” with respect to a particular parameter includes the value and the degree of variation of the value within an acceptable tolerance range for the particular parameter, as would be understood by one of ordinary skill in the art. For example, “about” or “approximate” with respect to a value may include additional values ​​in the range of 90.0% to 110.0% of the value (e.g., in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%).

[0031] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based) The term "conductive structure" refers to and includes structures formed from and containing conductive materials. This includes alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel. It also includes conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides) and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from and containing conductive materials.

[0032] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon oxide material (e.g., silicon oxycarbonate (SiO) x C y ()), and at least one hydrogenated dielectric carbon oxide material (e.g., hydrogenated silicon carbide (SiC) x O y H z and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y This text contains formulas that include one or more of "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C y SiC x O y H z SiO x C z N y This indicates a material containing, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of any additional element (if any). Because this formula represents relative atomic ratios and is not a strict chemical structure, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes chemical compounds having an elemental composition that cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0033] As used herein, the term "semiconductor material" refers to a material having a conductivity between that of an insulating material and that of a conductive material. For example, at room temperature, a semiconductor material may have a conductivity between approximately 10⁻⁶. -8 Siemens / cm (S / cm) and about 10 4 S / cm(10 6The conductivity between S / m. Examples of semiconductor materials include elements present in column IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials (e.g., binary compound semiconductor materials (e.g., gallium arsenide (GaAs)) and ternary compound semiconductor materials (e.g., Al). X Ga 1-X As) and quaternary compound semiconductor materials (e.g., Ga) X In 1-X As Y P 1-Y Compound semiconductor materials may contain, but are not limited to, combinations of elements from columns III and V of the periodic table (Group III-V semiconductor materials) or from columns II and VI of the periodic table (Group II-VI semiconductor materials). Further examples of semiconductor materials include oxide semiconductor materials, such as zinc tin oxide (ZnO). x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In) x Zn y O, commonly referred to as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly referred to as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In) x W y O, commonly referred to as "IWO"), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zna O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), Zirconia zinc tin (Zr) x Zn y Sn z O) and other similar materials.

[0034] As used herein, the term "homogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) remain constant across different portions of the feature (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term "heterogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) vary across different portions of the feature. If a feature is heterogeneous, then the amounts of one or more elements contained in the feature may vary gradually (e.g., abruptly) or continuously (e.g., gradually (e.g., linearly, parabolically)) across different portions of the feature. For example, the feature may be formed by and contain a stack of at least two different materials.

[0035] As used herein, the terms “integrated circuit” or “integrated circuit device” may refer to “microelectronic device” or “nanoelectronic device,” each of which may be associated with a critical size demonstrated by testing. The term “integrated circuit” includes, but is not limited to, memory devices, and other devices (e.g., semiconductor devices) that may or may not be incorporated into memory. The term “integrated circuit” may include, but is not limited to, logic devices. The term “integrated circuit” may include, but is not limited to, processor devices, such as central processing units (CPUs) or graphics processing units (GPUs). The term “integrated circuit” may include, but is not limited to, radio frequency (RF) devices. Furthermore, an “integrated circuit” device may incorporate memory in addition to other functions (e.g., for example, a so-called “system-on-a-chip” (SoC) containing a processor and memory, or an integrated circuit device containing logic and memory). Furthermore, an “integrated circuit” device may incorporate memory in addition to other functions (e.g., for example, a so-called “depolymerization device”), wherein dissimilar integrated circuit components are associated to produce higher functionality, such as functions performed by a SoC, including processor-only, memory-only, processor and memory, or integrated circuit devices containing logic and memory.

[0036] As used herein, the term "substrate" means and includes materials (e.g., base materials) or structures on which additional materials are formed. A substrate may be a semiconductor substrate. A substrate may be a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. The material on a semiconductor substrate may include, but is not limited to, one or more of semiconductor materials, insulating materials, and conductive materials. A substrate may be a conventional silicon substrate or other bulk substrate including layers of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates. A "bulk substrate" may be an SOI substrate, such as a silicon-on-sapphire ("SOS") substrate. A "bulk substrate" may be an SOI substrate, such as a silicon-on-glass ("SOG") substrate. A "bulk substrate" may include a silicon epitaxial layer on a base semiconductor substrate. A "bulk substrate" may include other semiconductor and / or optoelectronic materials. Semiconductor and / or optoelectronic materials may include, for example, one or more of silicon-germanium materials, germanium-containing materials, silicon carbide-containing materials, gallium arsenide-containing materials, gallium nitride-containing materials, and indium phosphide-containing materials. The substrate may be doped or undoped.

[0037] As used herein, the term "mounting substrate" means and includes a structure configured to receive an integrated circuit device. A mounting substrate may be a silicon bridge configured to connect more than one integrated circuit device. A mounting substrate may be a package board that directly contacts an integrated circuit device (e.g., an exposed die containing a central processing unit). The package board may be mounted on a printed circuit board (PWB). A mounting substrate may be a printed circuit board on which at least one integrated circuit device and / or package board is mounted. A mounting substrate may include depolymerization devices. Unless the context otherwise indicates, the materials described herein may be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by one of ordinary skill in the art. Additionally, unless the context otherwise indicates, the removal of the material described herein can be accomplished by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization (CMP)) or other known methods.

[0038] Figure 1The illustration shows a simplified partial vertical cross-sectional view of a microelectronic device 100 according to some embodiments of the present disclosure. The microelectronic device 100 may be referred to as a fan-in memory device assembly having a flip-chip configuration. The microelectronic device 100 may also be referred to herein as a flip-chip fan-in memory device assembly 100 or a flip-chip fan-in memory device assembly package 100.

[0039] like Figure 1 As shown, the flip-chip fan-in memory device assembly 100 includes a first memory die group 112 and a second memory die group 120 that are vertically stacked (Z-direction) and adjacent to each other. The first memory die group 112 may be referred to as a Level 1 (L1) assembly 112, and the L1 assembly 112 is stacked together with and adjacent to a memory controller device 116. The second memory die group 120 may be referred to as a Level 2 (L2) assembly 120, and the L2 assembly 120 is stacked together with and adjacent to the L1 assembly 112. Figure 1 As depicted, the L2 assembly 120 is spaced apart from the memory controller device 116.

[0040] L1 assembly 112 includes L1 first die 112a and L1 second die 112b vertically stacked (Z direction) and adjacent to each other. L1 first die 112a includes an L1 first die metallization layer 111a and an L1 first die back surface 113a opposite to the L1 first die metallization layer 111a. L1 second die 112b also includes an L1 second die metallization layer 111b and an L1 second die back surface 113b opposite to the L1 second die metallization layer 111b. Memory controller device 116 includes a memory controller device metallization layer 115 and a memory controller device back surface 117 opposite to the memory controller device metallization layer 115. The second die metallization layer 111b of L1 is physically coupled to the memory controller device 116 at the back surface 117 of the memory controller device, such that the L1 assembly 112 is assembled to the memory controller device 116, wherein the L1 assembly 112 is closer to the memory controller device 116 than the L2 assembly 120. In some embodiments, the second die metallization layer 111b of L1 is physically coupled to the memory controller device 116 at the back surface 117 of the memory controller device by an adhesive material (not shown).

[0041] The L2 assembly 120 includes vertically stacked (Z-direction) and adjacent L2 first die 120a and L2 second die 120b. The L2 first die 120a includes an L2 first die metallization layer 119a and an L2 first die back surface 121a opposite to the L2 first die metallization layer 119a. The L2 second die 120b further includes an L2 second die metallization layer 119b and an L2 second die back surface 121b opposite to the L2 second die metallization layer 119b. The L2 first die back surface 121a and L2 second die back surface 121b are... Figure 1 The L2 die back surface 121 is shown together. Additionally, the L2 first die metallization layer 119a and the L2 second die metallization layer 119b are... Figure 1 The L2 die metallization layer 119 is collectively shown. In some embodiments, the memory controller device 116 has control logic that prioritizes memory locations, such that a given memory die closer to the memory controller device 116 may have a lower memory identifier. For example, a memory die in the L1 assembly 112 may receive more memory store and recall commands than a memory die in the L2 assembly 120. In other words, the memory controller device 116 may send more store and recall commands to the L1 first die 112a during operation than the number of store and recall commands sent to the L2 first die 120a. Other control logic circuitry can manage heat generation by temporarily sending, for example, more store and recall commands to the L2 second die 120b than to the L1 first die 112a, even though the L1 first die 112a is physically closer to the memory controller device 116. In some embodiments, the memory controller device 116 has control logic circuitry configured to prioritize store and recall commands via a relatively small number of physical links between a given memory die and the memory controller device 116. The following describes... Figure 1D Further illustrations are provided to illustrate the described embodiments.

[0042] Memory controller device 116 is assembled to a redistribution device, such as interposer device 126, via an array of memory controller electrical connectors 128, close to the memory controller device metallization layer 115. The memory controller electrical connectors 128 may include one or more of solder bumps, electrical pillars, electrical bumps, and interconnect pins electrically insertable into the body of the interposer device 126. The interposer device 126 is assembled to the memory controller device 116 at the “device side” 125 or “assembly side” 125 using the memory controller electrical connectors 128. The interposer device 126 is assembled to a printed circuit board substrate 130 at the “platform side” 127 or “board side” 127 via a platform-side electrical contact array 132. When the printed circuit board substrate 130 is a package substrate 130, the platform-side electrical contact array 132 is used for further assembly to a board, such as a motherboard, via a motherboard electrical contact array 134. The printed circuit board substrate 130 may have a motherboard electrical contact array 134 when it is configured as a package substrate 130 as described.

[0043] Electrical connectivity between the memory controller device 116 and each of the L1 assembly 112 and L2 assembly 120 can be achieved via a series of wire-bonded interconnects coupled from a plurality of metallization layers within the L1 assembly 112 and L2 assembly 120 to the memory controller device 116. For example, via the L1 assembly 112, an L1 first die terminal wire-bonded interconnect 136 extends from the L1 first die metallization layer 111a to the L1 second die metallization layer 111b; and an L1 first die intervening wire-bonded interconnect 140 continues the electrical connectivity from the L1 first die 112a through an interposer device 126 to the memory controller device 116, wherein the L1 first die intervening wire-bonded interconnect 140 contacts the interposer device 126. "Terminal wire-bonded interconnect" means that a direct contact interconnect between given memory dies is an interconnect that interconnects the given memory dies to, for example... Figure 1 The collective redistribution device is one of at least two wire bonding interconnects, wherein the collective device is the interposer device 126. In other words, the interconnection between the L1 first die 112a and the memory controller device 116 includes an L1 first die originating wire bonding interconnect 136 that makes direct contact with the L1 first die 112a, and an L1 first die intervening wire bonding interconnect 140 completes the interconnection between the L1 first die 112a and the interposer device 126. Figure 1D The interconnection between L1 second die 112b and memory controller device 116 is described below (which will be described in further detail below).

[0044] With the aid of the L2 assembly 120 for the L2 first die 120a, the L2 first die terminal wire bonding interconnect 144 extends from the L2 first die metallization layer 119a to the L2 second die metallization layer 119b. Furthermore, the L2 first die intervening wire bonding interconnect 148 continues the electrical communication from the L2 first die 120a to the memory controller device 116. The interconnection between the L2 first die 120a and the memory controller device 116 includes the L2 first die terminal wire bonding interconnect 144, the L2 first die intervening wire bonding interconnect 148, and the interconnection via the intervening layer device 126. Figure 1D The document also describes the interconnection between the L2 second die 120b and the memory controller device 116.

[0045] Encapsulation block 152 covers interposer device 126, memory controller device 116, and L1 assembly 112 and L2 assembly 120. Encapsulation block 152 may extend to cover and protect electrical interconnections between the devices. In some embodiments, encapsulation block 152 comprises a polysiloxane resin material configured to be compatible with the coefficient of thermal expansion of silicon-based materials within the microelectronic devices of L1 assembly 112 and L2 assembly 120.

[0046] Figures 1A to 1F Description of some embodiments according to this disclosure in the formation Figure 1 Simplified vertical cross-sectional view of different processing stages of the method for the microelectronic device 100 ( Figure 1A , 1B 1C, 1E and 1F) and simplified partial perspective views ( Figure 1D ). refer to Figure 1A During processing, the carrier substrate 110 supports the L1 assembly 112 and the L2 assembly 120. The L1 assembly 112 has been provided (e.g., positioned) over the L2 assembly 120. After the L2 assembly 120 has been provided on the carrier substrate 110, the L1 assembly is provided on the L2 assembly.

[0047] Figure 1A The processing during the processing phase includes terminal wire bonding of each of the L1 first die 112a and the L2 first die 120a. After installation, the L1 first die terminal wire bonding interconnect 136 extends from the L1 first die metallization layer 111a to the L1 second die metallization layer 111b. After installation, the L2 first die terminal wire bonding interconnect 144 extends from the L2 first die metallization layer 119a to the L2 second die metallization layer 119b.

[0048] Next reference Figure 1B The explanation is in the reference. Figure 1AThe microelectronic device 100 in the post-processing stage described herein, the memory controller device 116 may be provided (e.g., positioned) over the L1 second die metallization layer 111b on the L1 second die 112b. In some embodiments, the memory controller device 116 is preprocessed to receive an electrical connector 128, wherein the electrical connector 128 may be placed on an array of electrical bump pads (not shown).

[0049] Next reference Figure 1C The explanation is in the reference. Figure 1B In the microelectronic device 100 of the post-processing stage described above, an interposer device 126 may be provided (e.g., positioned) on a plurality of electrical connections 128 at the metallization layer 115 of the memory controller device. An L1 first die-end wire bonding interconnect 136 may be coupled to the memory controller device 116 via a connection on the interposer device 126 to an L1 second die-end wire bonding interconnect 140. Similarly, an L2 first die-end wire bonding interconnect 144 may be coupled to the memory controller device 116 via a connection on the interposer device 126 to an L2 second die-end wire bonding interconnect 148.

[0050] Next reference Figure 1D The explanation is in the reference. Figure 1CIn the post-processing stage of the microelectronic device 100 described above, the L1 first die terminal wire bonding interconnect 136 can be bonded to a terminal bonding pad 138, which is a portion of the L1 first die metallization layer 111a. The L1 first die terminal wire bonding interconnect 136 also contacts an intervention bonding pad 142, which is a placeholder portion of the L1 second die metallization layer 111b, for use by the L1 first die 112a. In some embodiments, the intervention bonding pad 142 is not electrically connected to the circuitry within the L1 second die 112b, but the intervention bonding pad 142 is a placeholder bonding pad to facilitate a continuous interconnection between the L1 first die 112a and the interposer device 126. Electrical communication between the L1 first die 112a and the interposer device 126 is established when the L1 first die intervention wire bonding interconnect 140 contacts each of the intervention bonding pad 142 and the L1 interposer first bonding pad 162L1. The electrical connection from the L1 second die 112b to the memory controller device 116 includes an L1 second die originating lead bonding interconnect 158 ​​mounted between the L1 second die originating bonding pad 160 and the L1 interposer subsequent bonding pad 164L1. Therefore, the L1 first die intervening lead bonding interconnect 140 and the L1 second die single lead bonding interconnect 158 ​​are laterally adjacent to each other (in the Y direction). In some embodiments, the L1 second die originating lead bonding interconnect 158 ​​is the "only" L1 second die lead bonding interconnect 158 ​​because it is the only lead bonding interconnect 158 ​​originating from a given bonding pad 160 of a given L1 second die 112b and terminating at the interposer device 126.

[0051] The L2 first die originating lead interconnect 144 can be bonded to the originating bonding pad 146, which is part of the L2 first die metallization layer 119a. The L2 first die originating lead interconnect 144 can also contact the intervening bonding pad 150, which is a berthing portion of the L2 second die metallization layer 119b, for use by the L2 first die 120a. Electrical communication between the L2 first die 120a and the intervening layer device 126 can be facilitated by the contact between the L2 first die intervening lead interconnect 148 and the L2 intervening layer first bonding pad 162L2. Electrical communication between the L2 second die 120b and the memory controller device 116 includes the L2 second die originating lead interconnect 166 provided between the L2 second die originating bonding pad 168 and the L2 intervening layer subsequent bonding pad 164L2. The L2 first die intercalation interconnect 148 and the L2 second die originating interconnect 166 are laterally adjacent to each other (Y direction). Similar to the L1 second die "unique" interconnect 158, in some embodiments, the L2 second die originating interconnect 166 is considered the L2 second die "unique" interconnect 166. The package board 130 passes through a series of originating interconnects and intercalation interconnects at the corresponding lead bonding pads on the L1 second die 112b and L2 second die 120b via an array of electrical contacts 132. Figure 1 It is coupled to the printed circuit board.

[0052] Still referencing Figure 1D Intermediate interconnect bonding pad array 170 can be positioned on the intermediate platform side 127, ready to receive intermediate electrical contact array, such as intermediate electrical contact array 132. Figure 1 ).

[0053] In some embodiments, the memory controller device 116 includes control logic circuitry configured to allow prioritization of store and recall commands via a relatively low number of physical links between a given memory die and the memory controller device 116. In an example embodiment, store and recall commands can be prioritized by sending a maximum of commands to the L1 second die 112b, as it is physically closest to the memory controller device 116. A single wire bond interconnect 158 ​​may be present between the L1 second die 112b and the interposer device 126. A second set of commands can be sent to the L2 second die 120b, as it is physically next to the memory controller device 116. A single wire bond interconnect 166 may be present between the L2 second die 120b and the interposer device 126.

[0054] Next reference Figure 1E The explanation is in the reference. Figure 1D The microelectronic device 100 in the post-processing stage described above, in Figures 1A to 1DThe flip-chip fan-in memory device assembly 100 formed during the processing stage is reversible (Z direction), and the interposer electrical contact array 132 is coupled to the interposer interconnect pad array 170. Figure 1D This facilitates flip-chip fan-in configuration of the microelectronic device 100. The process may include thermo-pressing the interposer electrical contact array 132 back onto the package substrate 130.

[0055] Next reference Figure 1F The explanation is in the reference. Figure 1E The microelectronic device 100 (also referred to herein as "flip-chip fan-in memory device assembly 100") is a post-processing stage microelectronic device, and the carrier substrate 110 is a carrier substrate. Figure 1E The substrate 110 can be removed, for example, by a peeling process. In some embodiments, the carrier substrate 110 is removed by activating a heat-release adhesive material (not shown) that holds the L2 first die 120a to the carrier substrate 110. After removing the carrier substrate 110, the flip-chip fan-in memory device assembly 100 is ready to receive the encapsulation block 152. Figure 1 For example, resin-based polymer-coated molding materials.

[0056] Refer again Figure 1 The flip-chip fan-in memory device assembly 100 can be treated as one of a wafer-level array of flip-chip fan-in memory device assemblies 100, wherein the illustrated flip-chip fan-in memory device assembly 100 has been monolithized from the wafer-level array of flip-chip fan-in memory device assemblies. In some embodiments, the flip-chip fan-in memory device assembly 100 is monolithized from a wafer-level array of four (4) flip-chip fan-in memory device assemblies molded with a capsule block 152. In some embodiments, the flip-chip fan-in memory device assembly 100 can be monolithized from a wafer-level array of eight (8) flip-chip fan-in memory device assemblies. In some embodiments, the flip-chip fan-in memory device assembly 100 can be monolithized from a wafer-level array of sixteen (16) flip-chip fan-in memory device assemblies. In some embodiments, the flip-chip fan-in memory device assembly 100 is monolithically generated from a wafer-level array of thirty-two (32) flip-chip fan-in memory device assemblies. In some embodiments, the flip-chip fan-in memory device assembly 100 is monolithically generated from a wafer-level array of sixty-four (64) flip-chip fan-in memory device assemblies. In some embodiments, the flip-chip fan-in memory device assembly 100 is monolithically generated from a wafer-level array of one hundred and forty-four (144) flip-chip fan-in memory device assemblies. Figure 6 The 652nd entry further explains this process.

[0057] Figure 2 This illustration shows a simplified partial vertical cross-sectional view of a microelectronic device 200 according to some embodiments of the present disclosure. The microelectronic device 200 includes a group of memory dies wire-bonded fan-in stacked packages. Figure 1 Compared to the flip-chip fan-in memory device assembly 100 described herein, the microelectronic device 200 includes an integrated redistribution layer (iRDL) 226 and serves as a part of the memory controller device 216 (while... Figure 1 The memory controller device 116 described herein is electrically coupled to the interposer device 126. In some embodiments, the iRDL 226 is stacked on the memory controller device metallization layer 215 at different processing operations. In some embodiments, the iRDL 226 and the memory controller device metallization layer 215 are integral units. The memory controller device metallization layer 215 and the iRDL 226 can be assembled in a single processing operation. The microelectronic device 200 may be referred to herein as a flip-chip iRDL memory device assembly 200 or a flip-chip iRDL memory device assembly package 200. Still referring to... Figure 2 Similarly, with Figure 1 Compared to the flip-chip memory device 100 described herein, the wire bonding interconnect is mounted at iRDL 226, which is mounted at the interposer device 126.

[0058] like Figure 2 As shown, wire bonding interconnects can be mounted at iRDL 226. Additionally, the first memory die group 112 and the second memory die group 120 are vertically stacked (Z-direction) and adjacent to each other. The first memory die group 112 may be referred to as Level 1 (L1) assembly 112. The L1 assembly 112 may be stacked together with and adjacent to the memory controller device 216. The second memory die group 120 may be referred to as Level 2 (L2) assembly 120. The L2 assembly 120 may be stacked together with and adjacent to the L1 assembly 112.

[0059] L1 assembly 112 includes L1 first die 112a and L1 second die 112b vertically stacked (Z direction) and adjacent to each other. L1 first die 112a includes an L1 first die metallization layer 111a and an L1 first die back surface 113a opposite to the L1 first die metallization layer 111a. L1 second die 112b further includes an L1 second die metallization layer 111b and an L1 second die back surface 113b opposite to the L1 second die metallization layer 111b. The L1 first die back surface 113a and L1 second die back surface 113b are... Figure 1 The L1 die back surface 113 is shown together. Additionally, the L1 first die metallization layer 111a and the L1 second die metallization layer 111b are... Figure 1 The L1 die metallization layer 111 is shown together with the L2 assembly 120. The memory controller device 216 includes a memory controller device back surface 217 opposite to the memory controller device metallization layer 215. The L1 second die metallization layer 111b can be physically coupled to the memory controller device 216 at the memory controller device back surface 217. The L1 assembly 112 can be assembled to the memory controller device 216 such that the L1 assembly 112 is relatively closer to the memory controller device 216 than the L2 assembly 120.

[0060] The L2 assembly 120 includes L2 first die 120a and L2 second die 120b that are vertically stacked (in the Z direction) and adjacent to each other. The L2 first die 120a includes an L2 first die metallization layer 119a and an L2 first die back surface 121a opposite to the L2 first die metallization layer 119a. The L2 second die 120b also includes an L2 second die metallization layer 119b and an L2 second die back surface 121b opposite to the L2 second die metallization layer 119b.

[0061] The memory controller device 216 is assembled to the package board 230, wherein a plurality of memory controller electrical connectors 232, such as solder bumps, electrical pillars, electrical bumps, and / or electrical pins, in the iRDL 226 contact array can be inserted into the body of the package board 230. The memory controller electrical connectors 232 are assembled to the package board 230 at either the "device side" 225 or the "assembly side" 225 using the memory controller electrical connectors 232. The package board 230 can be assembled to a motherboard (not shown) via a platform-side electrical contact array 234.

[0062] Electrical communication between the memory controller device 216 and each of the L1 assembly 112 and L2 assembly 120 is accomplished by a series of wire-bonded interconnects coupled from a plurality of metallization layers within the L1 assembly 112 and L2 assembly 120 to the memory controller device 216. For example, with the aid of the L1 assembly 112, the L1 first die-end wire-bonded interconnect 136 extends from the L1 first die metallization layer 111a to the L1 second die metallization layer 111b, and the L1 first die-intercept wire-bonded interconnect 240 continues the electrical communication from the L1 first die 112a to the memory controller device 216, wherein the L1 first die-intercept wire-bonded interconnect 240 contacts the memory controller device 216 at the iRDL 226. In other words, the interconnection between the L1 first die 112a and the memory controller device 216 includes the L1 first die originating wire bonding interconnect 136 and the L1 first die intervening wire bonding interconnect 240, as well as the interconnection via iRDL 226. Figure 2A The following describes the interconnection between L1 second die 112b and memory controller device 216.

[0063] With the aid of the L2 assembly 120 for the L2 first die 120a, the L2 first die terminal wire bonding interconnect 144 extends from the L2 first die metallization layer 119a to the L2 second die metallization layer 119b. Furthermore, the L2 first die intervening wire bonding interconnect 248 continues the electrical communication from the L2 first die 120a to the memory controller device 216. The interconnection between the L2 first die 110a and the memory controller device 216 includes the L2 first die terminal wire bonding interconnect 144 and the L2 first die intervening wire bonding interconnect 248, as well as interconnection via iRDL 226. Figure 2A The document also describes the interconnection between the L2 second die 120b and the memory controller device 216.

[0064] Encapsulation block 252 covers iRDL 226, memory controller device 216, L1 assembly 112, and L2 assembly 120. Encapsulation block 252 may extend to cover and protect the electrical interconnections between the devices.

[0065] Figure 2A Description of some embodiments according to this disclosure in the formation Figure 2 A simplified perspective view of the processing stage of the method for the microelectronic device 200. Figure 2A The processing phases can follow the previous references Figure 1B The described process is similar to that of processing, while Figure 2A In the middle, iRDL 226 replaces Figure 1B The redistribution device 126 is present. The microelectronic device 200 is provided (e.g., mounted) on the carrier substrate 210. The L1 first die terminal wire bonding interconnect 136 is bondable to the terminal bonding pad 138, which is part of the L1 first die metallization layer 111a, and the L1 first die terminal wire bonding interconnect 136 also contacts the intervention bonding pad 142, which is the occupant portion of the L1 second die metallization layer 111b. Electrical communication between the L1 first die 112a and the iRDL 226 can be facilitated by the contact between the L1 first die intervention wire bonding interconnect 240 and the L1 iRDL first bonding pad 262L1. Electrical communication between the L1 second die 112b and the memory controller device 216 includes the L1 second die original wire bonding interconnect 258 provided between the L1 second die original bonding pad 160 and the L1 iRDL subsequent bonding pad 264L1. The L1 first die insertion lead bonding interconnect 240 and the L1 second die originating lead bonding interconnect 158 ​​are laterally adjacent to each other (in the Y direction). Similar to the reference... Figure 1DThe L1 second die “unique” lead bonding interconnect 158 ​​described herein, in some embodiments, the L1 second die originating lead bonding interconnect 258 is regarded as the L1 second die “unique” lead bonding interconnect 258.

[0066] The L2 first die originating lead bonding interconnect 144 can be bonded to the originating bonding pad 146, which is part of the L2 first die metallization layer 119a. The L2 first die originating lead bonding interconnect 144 can contact the placeholder intervention bonding pad 150, which is part of the L2 second die metallization layer 119b. Electrical communication between the L2 first die 120a and the iRDL 226 can be facilitated by the contact between the L2 first die intervention bonding interconnect 248 and the L2 iRDL first bonding pad 262L2. Electrical communication between the L2 second die 120b and the memory controller device 216 includes the L2 second die originating lead bonding interconnect 266 provided between the L2 second die originating bonding pad 168 and the L2 iRDL subsequent bonding pad 264L2. The L2 first die intervention bonding interconnect 248 and the L2 second die originating lead bonding interconnect 266 can be laterally adjacent to each other (Y direction).

[0067] iRDL interconnect bonding pad array 270 can be positioned on iRDL platform side 227, ready to receive memory controller electrical connector 232, which, due to iRDL 226, also serves as interposer layer electrical contact array 232. Figure 2 ).

[0068] Refer again Figure 2 The iRDL flip-chip fan-in memory device assembly 200 can be treated as one iRDL flip-chip fan-in memory device assembly 200 in a wafer-level array of iRDL flip-chip fan-in memory device assemblies, wherein the illustrated flip-chip fan-in memory device assembly 200 has been monolithized from the wafer-level array of flip-chip fan-in memory device assemblies. In several embodiments, similar to that for... Figure 1 The memory device assembly 100 described and illustrated allows for the fan-in of several iRDL flip chips from a single wafer-level array into a memory array device.

[0069] Figure 3 This illustration shows a simplified partial vertical cross-sectional view of a microelectronic device 300 according to some embodiments of the present disclosure. The microelectronic device 300 includes a group of memory dies wire-bonded fan-in stacked together. Figure 1 Compared to the flip-chip fan-in memory device assembly 100 described herein, the microelectronic device 300 includes wire bonding interconnects to the memory controller device 316 (while... Figure 1The memory controller device 116 described herein is electrically coupled to the interposer device 126 via an array of electrical contacts 132. The microelectronic device 300 may be referred to herein as a flip-chip lead bonding controller microelectronic device assembly 300 or a flip-chip lead bonding controller microelectronic device assembly package 300.

[0070] The flip-chip fan-in bonding controller memory device assembly 300 includes a first memory die group 112 and a second memory die group 120 that are vertically stacked (in the Z direction) and adjacent to each other. The first memory die group 112 may be referred to as a Level 1 (L1) assembly 112, and the L1 assembly 112 is stacked together with and adjacent to the memory controller device 316. The second memory die group 120 may be referred to as a Level 2 (L2) assembly 120, and the L2 assembly 120 is stacked together with and adjacent to the L1 assembly 112.

[0071] Still referencing Figure 3 The L1 assembly 112 includes vertically stacked (Z-direction) and adjacent L1 first die 112a and L1 second die 112b. The L1 first die 112a includes an L1 first die metallization layer 111a and an L1 first die back surface 113a opposite to the L1 first die metallization layer 111a. The L1 second die 112b also includes an L1 second die metallization layer 111b and an L1 second die back surface 113b opposite to the L1 second die metallization layer 111b. The memory controller device 316 includes a memory controller device metallization layer 315 and a memory controller device back surface 317 opposite to the memory controller device metallization layer 315. The L1 second die metallization layer 111b is physically coupled to a spacer structure 372, which provides a headspace (“headspace”) for the interposer-to-memory controller device lead bonding interconnect 368. Therefore, the L1 second die metallization layer 111b and the memory controller device metallization layer 315 are face-to-face and spaced apart by the spacer structure 372. The L1 assembly 112 is assembled to the memory controller device 316, wherein the L1 assembly 112 is closer to the memory controller device 316 than the L2 assembly 120.

[0072] The L2 assembly 120 includes L2 first die 120a and L2 second die 120b that are vertically stacked (in the Z direction) and adjacent to each other. The L2 first die 120a includes an L2 first die metallization layer 119a and an L2 first die back surface 121a opposite to the L2 first die metallization layer 119a. The L2 second die 120b also includes an L2 second die metallization layer 119b and an L2 second die back surface 121b opposite to the L2 second die metallization layer 119b.

[0073] The memory controller device 316 is assembled against a relay device (e.g., interposer device 326) on the side opposite to the memory controller device metallization layer 315. The interposer device 326 can be assembled to the memory controller device 316 at a "device side" 325 or an "assembly side" 325 using an adhesive material. The interposer device 326 is assembled to the printed circuit board substrate 330 at a "platform side" 327 or a "board side" 327 via a platform-side electrical contact array 332. When the printed circuit board substrate 330 is a package substrate 330, the platform-side electrical contact array 332 is used for further assembly to a board, such as a motherboard, via a motherboard electrical contact array 334. The printed circuit board substrate 330 may have a motherboard electrical contact array 334 when configured as a package substrate 330 as described.

[0074] In some embodiments, several devices and structures up to the platform-side electrical contact array 332, but excluding the package plate 330, are assembled onto a motherboard positioned at the berth sites described by the package plate 330. For example, in forming with a carrier substrate (e.g., Figure 3B After the encapsulated blocks are in contact with the carrier substrate 310, the pre-placed array of electrical contact array 332 may be uncovered by grinding some encapsulated blocks, monolithizing a given assembly and mounting it onto a motherboard.

[0075] Electrical connectivity between the memory controller device 316 and each of the L1 assembly 112 and L2 assembly 120 can be achieved via a series of wire bonding interconnects coupled from a plurality of metallization layers within the L1 assembly 112 and L2 assembly 120 to the memory controller device 316. For example, with the aid of the L1 assembly 112, the L1 first die terminal wire bonding interconnect 136 extends from the L1 first die metallization layer 111a to the L1 second die metallization layer 111b; and the L1 first die intervening wire bonding interconnect 340 continues the electrical connectivity from the L1 first die 112a to the memory controller device 316, wherein the L1 first die intervening wire bonding interconnect 340 is similar to the L1 first die intervening wire bonding interconnect 140 ( Figure 1 The interposer device 326 continues to be contacted via electrical communication from the L1 first die 112a to the memory controller device 316. In other words, the interconnection between the L1 first die 112a and the memory controller device 316 includes the L1 first die originating wire bonding interconnect 136 and the L1 first die intervening wire bonding interconnect 340, the interconnection through the interposer device 326, and the interconnection from the interposer device 326 to the memory controller device 316 via the interposer-to-memory controller device wire bonding interconnect 368. Figure 3B The interconnection between L1 second die 112b and memory controller device 116 is described here.

[0076] With the aid of the L2 assembly 120 for the L2 first die 120a, the L2 first die terminal wire bonding interconnect 144 extends from the L2 first die metallization layer 119a to the L2 second die metallization layer 119b. Furthermore, the L2 first die intervening wire bonding interconnect 348 continues the electrical communication from the L2 first die 120a to the memory controller device 316. The interconnection between the L2 first die 210a and the memory controller device 316 includes the L2 first die terminal wire bonding interconnect 144, the L2 first die intervening wire bonding interconnect 348, and the interconnection via the intervening layer device 326. Figure 3B The document also describes the interconnection between the L2 second die 120b and the memory controller device 316.

[0077] Encapsulation block 352 covers interposer device 326, memory controller device 316, and L1 assembly 112 and L2 assembly 120. Encapsulation block 352 may extend to cover and protect electrical interconnections between the devices.

[0078] Figure 3A and 3B Description of some embodiments according to this disclosure in the formation Figure 3 A simplified perspective view of the different processing stages of the method for the microelectronic device 300. (Reference) Figure 3A An interposer has been installed to the memory controller device lead bonding interconnect 368 to interconnect the memory controller device 316 with the interposer device 326. Furthermore, a spacer structure 372 has been physically mounted above the metallization layer 315 of the memory controller device (Z direction).

[0079] Next reference Figure 3B The explanation is in the reference. Figure 3A The microelectronic device 300 in the post-processing stage, as described, includes a sub-assembly of a memory controller device 316, an interposer device 326, and a spacer structure 372 that has been reversed and assembled into the L1 assembly 112 (which was previously assembled into the L2 assembly 120). Additionally, further wire bonding interconnects are described. Figure 3 and 3AThe wire bonding interconnect described herein. The L1 first die originating wire bonding interconnect 136 is bondable to an originating bonding pad 138, which is part of the L1 first die metallization layer 111a, and the L1 first die originating wire bonding interconnect 136 is contactable to an intervening bonding pad 142. The intervening bonding pad 142 may be a berthing portion of the L1 second die metallization layer 111b. Contact between the L1 first die intervening wire bonding interconnect 340 and the L1 interposer first bonding pad 362L1 facilitates electrical communication between the L1 first die 112a and the interposer device 326. Electrical communication from the L1 second die 112b to the memory controller device 316 includes providing an L1 second die originating wire bonding interconnect 358 mounted between the L1 second die originating bonding pad 160 and the L1 interposer subsequent bonding pad 364L1. L1 first die intercalation lead bonding interconnect 140 and L1 second die originating lead bonding interconnect 358 are laterally adjacent to each other (Y direction).

[0080] The L2 first die terminal lead bonding interconnect 144 is bondable to a terminal bonding pad 146 that is a portion of the L2 first die metallization layer 119a; and the L2 first die intercalation lead bonding interconnect 348 is contactable to an intercalation bonding pad 150 that is a portion of the L2 second die metallization layer 119b. Electrical connectivity between the L2 first die 120a and the interposer device 326 can be facilitated by the contact between the L2 first die intercalation lead bonding interconnect 348 and the L2 interposer first bonding pad 362L2. Electrical connectivity from the L2 second die 120b to the memory controller device 116 includes the L2 second die terminal lead bonding interconnect 366 provided between the L2 second die terminal lead bonding pad 168 and the L2 interposer subsequent bonding pad 364L2. The L2 first die intercalation lead bonding interconnect 348 and the L2 second die terminal lead bonding interconnect 366 may be laterally adjacent to each other (Y direction). Similar to the previous reference. Figure 1D The described L2 second die “unique” wire bonding interconnect 166, in some embodiments, is considered the L2 second die originating wire bonding interconnect 366 as the L2 second die “unique” wire bonding interconnect 366.

[0081] Intermediate interconnect pad array 370 can be positioned on the intermediate platform side 327, ready to receive intermediate electrical contact array 332. Figure 3 ). In the placement of spacer structure 372 ( Figure 3 and 3A Subsequently, the interposer-to-memory controller device interconnect 368 may have sufficient clearance in the Z direction to provide headspace for the interposer-to-memory controller device interconnect 368 above the second die 112b of L1.

[0082] Refer again Figure 3 The flip-chip lead bonding controller microelectronic device assembly 300 can be processed as one of the flip-chip lead bonding controller microelectronic device assemblies in a wafer-level array of flip-chip lead bonding controller microelectronic device assemblies. The flip-chip lead bonding controller microelectronic device assembly 300 can be monolithized from the wafer-level array of flip-chip fan-in memory device assemblies.

[0083] Figure 4A and 4B A simplified vertical cross-sectional view of a microelectronic device 400 according to some embodiments of the present disclosure is shown. Figure 4A ) and simplified top view ( Figure 4B Microelectronic device 400 is provided (e.g., mounted) on carrier substrate 410. Microelectronic device 400 may have a fan-in lead bonded interposer flip-chip memory device controller configuration (presented as including similar...). Figure 1 The microelectronic device 100 described herein includes at least four memory die groups 112, 120, 472, and 480, as well as those previously referenced. Figures 1A to 1F The microelectronic device 400 may have a wire-bonded fan-in stacked package configuration, assuming an XY-symmetric configuration of the described processing actions. This configuration may include two memory die groups 112 and 120 oriented about a bilateral symmetry line 401 in the X direction, and two memory die groups 472 and 480 oriented about a bilateral symmetry line 402 in the Y direction.

[0084] Common Reference Figure 4A and 4BA first memory die group 112 may be positioned closest to the memory controller device 416. The memory controller device 416 may be coupled to a redistribution device 426, such as an RDL device 426, via an array of memory controller electrical connections 428. The first memory die group 112 may be referred to as a Level 1 (L1) assembly 112, and a second memory die group 120 may be referred to as an L2 assembly 120. The L2 assembly 120 may be stacked together with and adjacent to the L1 assembly 112. The L2 assembly 120 may be spaced apart from the memory controller device 416. A third memory die group 472 may be referred to as an L3 assembly 472, and a fourth memory die group 480 may be referred to as an L4 assembly 480. The L3 assembly 472 may be stacked together with and adjacent to the L4 assembly 480. In some embodiments, the L4 assembly 480 is furthest from the memory controller device 416 compared to each of the L1 assembly 112, L2 assembly 120, and L3 assembly 472. "XY symmetry" can mean, for example, that assembly L1 112 and assembly L2 120 are arranged around symmetry line 401, and assembly L3 472 and assembly L4 480 are arranged around symmetry line 402 which is orthogonal to another symmetry line 401.

[0085] Explanation and Figure 1 and 1D The wire bonding described herein is similar to that described above. A first die-starting wire bonding interconnect 436 extends from L1 first die 112a to L1 second die 112b; and an L1 first die-intervening wire bonding interconnect 440 continues electrical communication from L1 first die 112a through an interposer device 426 at its platform side 427 to a memory controller device 416. The L1 first die-intervening wire bonding interconnect 440 contacts the interposer device 426. Electrical communication from L1 second die 112b to the memory controller device 416 includes providing an L1 second die-starting wire bonding interconnect 458 mounted between an L1 second die-starting bonding pad and an L1 interposer subsequent bonding pad. Additionally, electrical communication from L2 second die 120b to the memory controller device 116 includes an L2 second die-starting wire bonding interconnect 466 provided between an L2 second die-starting bonding pad and an L2 interposer subsequent bonding pad. The L2 first die originating lead-bonded interconnect 444 extends from the L2 first die 420a to the L2 second die 420b. Furthermore, the L2 first die intervening lead-bonded interconnect 448 continues the electrical connection from the L2 first die 120a through the interposer 426 to the memory controller device 416. Figure 4B The diagram illustrates the interconnection between the L2 second die 120b and the memory controller device 416.

[0086] A wire bonding interconnect from L3 assembly 472 to interposer device 426 can be provided via L3 first die originating wire bonding interconnect 474. L3 first die originating wire bonding interconnect 474 directly contacts L3 first die 472a and L3 second die 472b. L3 first die intervening wire bonding interconnect 476 completes the interconnection between L3 first die 472a and interposer device 426. Electrical communication from L3 second die 472b to memory controller device 416 includes L3 second die originating wire bonding interconnect 478 provided between L3 second die 472b and memory controller device 416, through interposer device 426. L3 first die intervening wire bonding interconnect 476 and L3 second die originating wire bonding interconnect 478 are laterally adjacent to each other (X direction).

[0087] refer to Figure 4B A wire bonding interconnect from the L4 assembly 480 to the memory controller device 416 can be provided by an L4 first die terminal wire bonding interconnect 484 that makes direct contact with the L4 first die 480a and the L4 second die 480b. An L4 first die intervening wire bonding interconnect 486 completes the interconnection between the L4 first die 480a and the interposer device 426. An L4 second die terminal wire bonding interconnect 488 provided between the L4 second die 480b and the memory controller device 416, through the interposer device 426, facilitates electrical connectivity between the L4 second die 480b and the memory controller device 416. The L4 first die intervening wire bonding interconnect 486 and the L4 second die terminal wire bonding interconnect 488 can be laterally adjacent to each other (in the X direction).

[0088] The platform side 427 of the interposer 426 may have a connection for use with platform-side electrical bumps (e.g., electrical bump 132). Figure 1 Electrical bump 232, Figure 2 ; and electrical bump 332, Figure 3 Interconnecting intermediate layer interconnect pad array 470. The pad array 470 may have more than sixty-four (64) occurrences, as described.

[0089] In some embodiments, similar to Figure 4A and 4B The microelectronic device 400 described herein, and the flip-chip fan-in memory device assembly 100 ( Figure 1 Combined with L3 and L4 assemblies. In some embodiments, similar to Figure 4A and 4B The microelectronic device 400 described herein, iRDL flip-chip fan-in memory device assembly 200 ( Figure 2 Combined with L3 and L4 assemblies. In some embodiments, similar to Figure 4Aand 4B The microelectronic device 400 described herein, the lead-bonded memory device controller fan-in microelectronic device assembly 300 ( Figure 3 The L3 assembly is combined with the L4 assembly. If the L3 assembly is combined with the L4 assembly, then the control logic circuitry system within the memory controller device (e.g., memory controller device 416) may be similar to the disclosed functions, such as thermal management, memory die usage management depending on the proximity of the memory die to the memory controller device, and other functions useful for operating the disclosed memory device.

[0090] Figure 5 This document includes flowcharts illustrating a method 500 for assembling a microelectronic device package (e.g., microelectronic device packages 100, 200, 300, and 400 described above) according to some embodiments of this disclosure. For the purposes of assembling method 500, the fabrication processes for individual components (e.g., semiconductor dies, microelectronic devices, interposers) are not described in detail herein. The following section discusses... Figure 6 A more detailed description of the manufacturing process.

[0091] At action 510, method 500 includes forming a group of memory dies, such as a first group of memory dies 112 (L1 assembly 112, which includes L1 first die 112a and L1 second die 112b). Forming the group of memory dies may further include forming first die terminal wire bonding interconnects, such as L1 group first die terminal wire bonding interconnect 136 extending from L1 first die 112a to L1 second die 112b. Figure 1 ).

[0092] At action 520, method 500 includes assembling at least two memory die groups together. In a non-limiting example embodiment, L1 assembly 112 and L2 assembly 120 ( Figure 1A ) is assembled onto the carrier substrate 110.

[0093] At action 530, method 500 includes assembling a memory controller device to at least an L1 assembly and an L2 assembly. In a non-limiting example embodiment, the memory controller device 116 ( Figure 1B Assembled into L1 assembly 112 and L2 assembly 120.

[0094] At action 540, method 500 includes using a redistribution device (e.g., intermediary layer device 126). Figure 1 ) or iRDL 226( Figure 2 At least two memory die groups are coupled to a memory controller device. In a non-limiting example embodiment, this is achieved by coupling with... Figure 1C and 1DSimilar to the processing actions described above, the L1 assembly 112 and L2 assembly 120 are coupled to the memory controller device 216 via iRDL 226. Figure 2 The coupling action is contained within the... Figure 1C and 1D Similar to the processing action described above, the intervention lead connection interconnects 240 and 248 are installed at the processing action location. Figure 2 and 2A ).

[0095] At action 542, via an array of electrical bumps (e.g., via electrical connector 128) Figure 1 Coupling is completed. Then, at action 542, coupling is completed via iRDL 226 and connected to intervention and originating leads 240 and 258 respectively, and to intervention and originating leads 248 and 266 respectively. Figure 2A ).

[0096] At action 544, coupling is accomplished by first bonding the memory controller device leads to the redistribution device, and then bonding the redistribution device leads to at least two memory die groups. In a non-limiting example embodiment, interconnect 368 is bonded to the memory controller device leads via an interposer, and then the memory controller device 316 and the redistribution device 326 are assembled into the L1 assembly 112. Figure 3B And complete the lead bonding of interconnects 340 and 358 respectively with the intervention and originating lead, and interconnects 348 and 366 respectively with the intervention and originating lead. Figure 3B This completes the interconnection from the intermediate layer device 326 to the memory controller device 316. Figure 3A ).

[0097] At action 550, method 500 includes assembling at least two groups of memory dies onto a package board. In a non-limiting example embodiment, this is achieved, for example, via electrical connector 128 ( Figure 1 The return flow of L1 assembly 112, L2 assembly 120, memory controller device 116 and interposer device 126 will be transferred. Figure 1 The electrical connector 128 is assembled on the package plate 130. It can be reflowed to the interposer bonding pad array 170. Figure 1 On the individual mating pads.

[0098] Figure 6A flowchart illustrating a method 600 for manufacturing a microelectronic device package (e.g., any of the microelectronic device packages 100, 200, 300, and 400 described above) according to embodiments of this disclosure. One or more components of the resulting microelectronic device package (e.g., each) may be formed individually, and then said one or more components are assembled to form said microelectronic device package. Therefore, different forming processes may operate in parallel and / or may not have any particular order of completion. Once the individual components are formed, they can be assembled as described above. Figure 5 The process described herein assembles the components.

[0099] For memory devices and memory controller devices, each of the components can be formed in an array on a substrate (e.g., a semiconductor wafer) via a stacking process (e.g., deposition, sputtering, etc.), a material removal process (e.g., etching (e.g., wet etching, dry etching, etc.), a photolithography process (e.g., photolithography, optical photolithography, UV photolithography, etc.), and a filling process. Once the component array is formed, the array can be divided into individual components via a separation process (e.g., a dicing process). For redistribution devices, an interposer array can be assembled at the wafer level. For integrated redistribution devices, the memory controller device can be fabricated in a single processing setup comprising an iRDL assembly contained above or integrated with a metallization layer. Alternatively, the iRDL can be fabricated during a subsequent processing setup.

[0100] At action 610, an array of interposer devices may be formed, for example, using a wafer-level assembly action. At action 612, individual interposer devices may be monolithized from the array of interposer devices, for example, by sawing, scoring, and cracking, and combinations thereof.

[0101] At action 620, the memory controller device array can be formed at the wafer level, for example, through semiconductor device processing. As an alternative to the processes at actions 610 and 612, at action 622, an integrated redistribution layer can be formed at the wafer level during the formation of the memory controller device array. At action 624, individual memory controller devices can be monolithized from the memory controller device array, for example, through sawing, scoring, and separation, and combinations thereof.

[0102] At action 630, a memory device array can be formed at the wafer level, for example, by semiconductor device processing. Such memory devices may include 3D NAND memory devices or DRAM memory devices. At action 632, individual memory devices can be monolithized from the memory device array, for example, by sawing, scoring, and separating, and combinations thereof. At action 634, two memory devices can be stacked and interconnected with lead-in bonding. At action 636, at least two memory die groups are assembled onto a carrier substrate, for example, assembling L1 assembly 112 and L2 assembly 120. Figure 1A and 1C The carrier substrate 110 described herein, and the lead bonding intervention and the terminal lead bonding interconnect, for example Figure 1D The L1 first bare die intervention lead bonding interconnect 140 and the starting lead bonding interconnect 158 ​​are located at the L1.

[0103] At action 640, the assembly of at least two memory die groups to the interposer and memory controller devices is completed. This assembly may include an array of electrical interconnects (e.g., electrical connectors 128). Figure 1 )) Reflow, and the leads are connected to the interlayer device.

[0104] At action 650, this can be achieved, for example, by including a platform-side electrical contact array 132 ( Figure 1F The electrical connections of the memory dies are reflowed to assemble at least two groups of memory dies with memory controller devices and redistribution devices onto the package board. In some embodiments, the package board (e.g., package board 130) may initially be in the form of a wafer-level array; and at action 652, individual package boards may be monolithized from the array, for example, by sawing, scoring and cracking, and combinations thereof.

[0105] At operation 660, assembly of at least one fan-in wire-bonded memory device package can be completed for assembly into an electronic system, such as... Figure 7 The electronic system 700 described herein.

[0106] Therefore, according to embodiments of this disclosure, a microelectronic device includes: a controller device; a first die vertically covering the controller device; a second die vertically covering the first die; and a lead. The first die includes a first pad horizontally separated from the horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance. The lead contacts the first pad of the first die and the second pad of the second die.

[0107] Furthermore, according to embodiments of this disclosure, a memory device package includes: a memory controller device vertically overlaid on a package substrate; a first die vertically overlaid on the memory controller device and including a first bonding pad; a second die vertically overlaid on the first die and including a second bonding pad; and a first lead bonded to the first bonding pad of the first die and the second bonding pad of the second die. The horizontal center of the memory controller device is horizontally further away from the second bonding pad of the second die than from the first bonding pad of the first die.

[0108] The microelectronic devices disclosed herein (e.g., flip-chip fan-in memory device assembly 100, iRDL flip-chip fan-in memory device assembly 200, wire-bonded memory device controller fan-in microelectronic device assembly 300, and XY-symmetric microelectronic device 400) can be used in embodiments of the electronic systems disclosed herein. For example, Figure 7 This is a block diagram of an electronic system 700 according to an embodiment of the present disclosure. The electronic system 700 may include, for example, a computer or computer hardware component, a server or other networked hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, Wi-Fi, or a tablet computer with cellular functionality (e.g., for example...). or Tablet computers, e-books, or navigation devices, etc. Electronic system 700 includes at least one memory device 720, such as any of microelectronic device assemblies 100, 200, 300, or 400. Memory device 720 may include one or more of the microelectronic devices disclosed herein (e.g., flip-chip fan-in memory device assembly 100, iRDL flip-chip fan-in memory device assembly 200, wire-bonded memory device controller fan-in microelectronic device assembly 300, or XY-symmetric flip-chip fan-in memory device assembly 400). Electronic system 700 may further include at least one electronic signal processor device 710 (generally referred to as a "microprocessor") as part of an integrated circuit. Although memory device 720 and electronic signal processor device 710 are... Figure 7 The system is depicted as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device with the functionality of a memory device 720 and an electronic signal processor device 710 is included in the electronic system 700. In such embodiments, the memory / processor device may include one or more of the microelectronic devices of this disclosure (e.g., flip-chip fan-in memory device assembly 100, iRDL flip-chip fan-in memory device assembly 200, wire-bonded memory device controller fan-in microelectronic device assembly 300, or XY-symmetric flip-chip fan-in memory device assembly 400). The electronic signal processor device 710 and the memory device 720 may be part of depolymerized die assemblies 710 and 720. The depolymerized die assemblies 710 and 720 may be coupled to the electronic signal processor device 710 and the memory device 720 via a multi-die silicon bridge 712 (bridge die 712).

[0109] The electronic system 700 may further include one or more input devices 730 for users to input information into the electronic system 700, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 700 may further include one or more output devices 740 for outputting information to the user (e.g., visual or audio output), such as, for example, a monitor, display, printer, audio output jack, and / or speaker. In some embodiments, the input device 730 and the output device 740 may include a single touchscreen device that can be used both to input information into the electronic system 700 and to output visual information to the user. The input device 730 and the output device 740 may be in electrical communication with one or more of the memory device 720 and the electronic signal processor device 710.

[0110] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device. The memory device includes a controller device, a first die, a second die, and leads. The first die vertically covers and horizontally overlaps the controller device and includes a first bonding pad. The second die vertically covers and horizontally overlaps the first die and includes a second bonding pad. The horizontal center of the controller device is positioned closer to the first bonding pad of the first die than to the second bonding pad of the second die. The leads are bonded to the first bonding pad of the first die and the second bonding pad of the second die.

[0111] Compared to conventional structures, devices, systems, and methods, this disclosure advantageously facilitates one or more of the following: improved performance of the microelectronic device, reduced cost (e.g., manufacturing cost, material cost), increased component miniaturization, and greater packaging density. Compared to conventional structures, devices, systems, and methods, the structures, devices, systems, and methods of this disclosure also improve scalability, efficiency, and simplicity.

[0112] Additional non-limiting example embodiments of this disclosure are described below.

[0113] Example 1: A microelectronic device comprising: a controller device; a first die vertically covering the controller device and including a first pad horizontally separated from the horizontal center of the controller device by a first distance; a second die vertically covering the first die and including a second pad horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance; and a lead wire contacting the first pad of the first die and the second pad of the second die.

[0114] Example 2: The microelectronic device according to Example 1 further includes an intermediary layer device vertically recessed and coupled to the controller device.

[0115] Example 3: The microelectronic device according to Example 2 further includes additional leads for the first pad contacting the first die and the third pad of the interposer.

[0116] Example 4: The microelectronic device according to any one of Examples 2 and 3 further includes a conductive structure vertically inserted between the interposer and the controller and coupling the interposer and the controller, the conductive structure including one or more of solder bumps, electrical pillars, electrical bumps and interconnect pins.

[0117] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the controller device includes an integrated redistribution layer (iRDL) at its lower end.

[0118] Example 6: The microelectronic device according to Example 5 further includes additional leads for the first pad contacting the first die and the third pad of the iRDL.

[0119] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein: the first pad is positioned on the lower surface of the first die; and the second pad is positioned on the lower surface of the second die.

[0120] Example 8: A microelectronic device according to any one of Examples 1 to 7, further comprising: a third die, which is vertically overlying the second die and includes a third pad that is horizontally separated from the horizontal center of the controller device by a third distance; a fourth die, which is vertically overlying the third die and includes a fourth pad that is horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance; and an additional lead that contacts the third pad of the third die and the fourth pad of the fourth die.

[0121] Example 9: The microelectronic device according to Example 8, wherein the third pad of the third die and the fourth pad of the fourth die are each completely horizontally offset from the first pad of the first die and the second pad of the second die.

[0122] Example 10: A microelectronic device according to any one of Examples 8 and 9, wherein the main portions of the first die and the second die are horizontally inserted between the lead and the additional lead.

[0123] Example 11: A microelectronic device according to any one of Examples 8 to 10, further comprising: a redistribution device, which is vertically positioned below the controller device and includes a fifth pad and a sixth pad, the fifth pad being positioned close to a horizontal end of the redistribution device that is different from the sixth pad; additional leads that contact the first pad of the first die and the fifth pad of the redistribution device; and other leads that contact the third pad of the third die and the sixth pad of the redistribution device.

[0124] Example 12: A memory device package includes: a memory controller device vertically overlaid on a package plate; a first die vertically overlaid on the memory controller device and including a first bonding pad; a second die vertically overlaid on the first die and including a second bonding pad, wherein the horizontal center of the memory controller device is horizontally further away from the second bonding pad of the second die than from the first bonding pad of the first die; and a first lead bonded to the first bonding pad of the first die and the second bonding pad of the second die.

[0125] Example 13: The memory device package according to Example 12, wherein the memory controller device, the first die, and the second die are all horizontally overlapped with each other.

[0126] Example 14: A memory device package according to any one of Examples 12 and 13, further comprising an intermediary layer device coupled to the package board and vertically inserted between the package board and the memory controller device, the intermediary layer device being horizontally overlapped with the memory controller device.

[0127] Example 15: The memory device package according to Example 14 further includes a conductive structure vertically inserted between the interposer and the memory controller and coupled to the interposer and the memory controller.

[0128] Example 16: The memory device package according to Example 14 further includes a second lead of the first bonding pad bonded to the first die and an additional bonding pad of the interposer device.

[0129] Example 17: A memory device package according to any one of Examples 12 to 16, wherein the memory controller device includes: a control logic circuit system; and an integrated redistribution layer (iRDL) vertically inserted between the control logic circuit system and the package board.

[0130] Example 18: The memory device package according to Example 17 further includes a second lead of the first bonding pad bonded to the first die and an additional bonding pad of the iRDL.

[0131] Example 19: A memory device package according to any one of Examples 12 to 18, wherein the first die and the second die each comprise an array of NAND memory cells.

[0132] Example 20: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device, the memory device comprising: a controller device; a first die vertically overlying and horizontally overlapping the controller device, the first die including a first bonding pad; a second die vertically overlying and horizontally overlapping the first die and including a second bonding pad, the horizontal center of the controller device being horizontally positioned closer to the first bonding pad of the first die than to the second bonding pad of the second die; and a lead wire bonded to the first bonding pad of the first die and the second bonding pad of the second die.

[0133] While this disclosure is readily adaptable to various modifications and alternatives, specific embodiments have been illustrated by way of example in the drawings and described in detail herein. However, this disclosure is not limited to the particular forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed in one embodiment of this disclosure may be combined with elements and features disclosed in other embodiments of this disclosure.

Claims

1. A microelectronic device comprising: Controller device; A first bare sheet, which is vertically covered on the controller device and includes a first pad that is horizontally separated from the horizontal center of the controller device by a first distance; The second bare sheet is vertically overlaid on the first bare sheet and includes a second pad that is horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance; and The lead wire contacts the first pad of the first die and the second pad of the second die.

2. The microelectronic device of claim 1, further comprising an intermediary layer device vertically disposed on and coupled to the controller device.

3. The microelectronic device of claim 2, further comprising additional leads of the first pad contacting the first die and the third pad of the interposer.

4. The microelectronic device of claim 2, further comprising a conductive structure vertically inserted between the interposer and the controller and coupling the interposer and the controller, the conductive structure comprising one or more of solder bumps, electrical pillars, electrical bumps and interconnect pins.

5. The microelectronic device of claim 1, wherein the controller device includes an integrated redistribution layer (iRDL) at its lower end.

6. The microelectronic device of claim 5, further comprising additional leads contacting the first pad of the first die and the third pad of the iRDL.

7. The microelectronic device according to any one of claims 1 to 6, wherein: The first pad is positioned on the lower surface of the first bare die; and The second pad is positioned on the lower surface of the second bare sheet.

8. The microelectronic device according to any one of claims 1 to 6, further comprising: The third bare sheet, which is vertically overlaid on the second bare sheet and includes a third pad that is horizontally separated from the horizontal center of the controller device by a third distance; A fourth bare sheet, which vertically covers the third bare sheet and includes a fourth pad that is horizontally separated from the horizontal center of the controller device by a second distance greater than the first distance; and An additional lead contacts the third pad of the third die and the fourth pad of the fourth die.

9. The microelectronic device of claim 8, wherein the third pad of the third die and the fourth pad of the fourth die are each completely horizontally offset from the first pad of the first die and the second pad of the second die.

10. The microelectronic device of claim 8, wherein the main portions of the first die and the second die are horizontally inserted between the lead and the additional lead.

11. The microelectronic device according to claim 8, further comprising: A re-laying device, which is vertically positioned below the controller device and includes a fifth pad and a sixth pad, wherein the fifth pad is positioned close to the horizontal end of the re-laying device that is different from the sixth pad; The other lead wire contacts the first pad of the first bare sheet and the fifth pad of the re-fabrication device; and Other leads, which contact the third pad of the third bare sheet and the sixth pad of the re-laying device.

12. A memory device package comprising: A memory controller device, which is vertically mounted on a package plate; A first die, which is vertically overlaid on the memory controller device and includes a first bonding pad; A second die, which is vertically overlaid on the first die and includes a second bonding pad, wherein the horizontal center of the memory controller device is horizontally further away from the second bonding pad of the second die than from the first bonding pad of the first die; and A first lead is coupled to the first bonding pad of the first die and the second bonding pad of the second die.

13. The memory device package of claim 12, wherein the memory controller device, the first die, and the second die are all horizontally overlapping each other.

14. The memory device package of claim 12, further comprising an intermediary layer device coupled to the package board and vertically inserted between the package board and the memory controller device, the intermediary layer device being horizontally overlapping the memory controller device.

15. The memory device package of claim 14, further comprising a conductive structure vertically inserted between the interposer and the memory controller and coupled to the interposer and the memory controller.

16. The memory device package of claim 14, further comprising a second lead bonded to the first bonding pad of the first die and an additional bonding pad of the interposer device.

17. The memory device package according to any one of claims 12 to 16, wherein the memory controller device comprises: Control logic circuit system; and Integrated Redistribution Layer (iRDL) It is vertically inserted between the control logic circuit system and the package board.

18. The memory device package of claim 17, further comprising a second lead bonded to the first bonding pad of the first die and an additional bonding pad of the iRDL.

19. The memory device package according to any one of claims 12 to 16, wherein the first die and the second die each comprise an array of NAND memory cells.

20. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device, the memory device comprising: Controller device; A first bare sheet is vertically overlaid on the controller device and horizontally overlaps the controller device, the first bare sheet including a first bonding pad; A second die, vertically overlying and horizontally overlapping the first die and including a second bonding pad, wherein the horizontal center of the controller device is horizontally positioned closer to the first bonding pad of the first die than to the second bonding pad of the second die; and Lead wires are attached to the first bonding pad of the first die and the second bonding pad of the second die.

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