Decoding metadata encoded in error correction codes

Abstract

Embodiments of the present disclosure include techniques for encoding and decoding metadata in an error correction code. During the read operation, the decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state. When one of the first output and the second output has a zero value, the decoder sets a value of the at least one metadata bit to a first state or a second state corresponding to the first output or the second output having the zero value. When both the first output and the second output are non-zero, the decoder decodes the codeword assuming that the metadata bits have the first state and assuming that the metadata bits have the second state to determine whether the codeword can be corrected with at least one metadata bit.

Description

Background Technology

[0001] This disclosure generally relates to error correction coding and decoding, and specifically to decoding metadata encoded in error correction codes.

[0002] When transmitting digital data in the form of 0s and 1s (bits) between devices on a computer, it is common practice to use error-correcting codes to ensure data integrity. For example, error-correcting codes can analyze a data segment and generate a code from the data value. After the data is transmitted between devices, the code can be checked to determine if any bit has changed. However, error-correcting codes themselves consume bits, thus consuming storage space and bandwidth. Attached Figure Description

[0003] Figure 1 A system for decoding metadata encoded in error-correcting codes, according to an embodiment, is shown.

[0004] Figure 2 A method for decoding metadata encoded in error-correcting codes according to an embodiment is shown.

[0005] Figure 3 An example process for decoding a first codeword according to an embodiment is shown.

[0006] Figure 4 An example process for decoding a second codeword according to an embodiment is shown.

[0007] Figure 5 An example process for decoding a third codeword according to an embodiment is shown.

[0008] Figure 6 An example process for decoding a fourth codeword according to an embodiment is shown.

[0009] Figure 7 An example of voting according to an embodiment is shown.

[0010] Figure 8 An example hardware architecture for decoding metadata encoded in error-correcting codes, according to an embodiment, is shown.

[0011] Figure 9 An example timing diagram for decoding metadata encoded in error-correcting codes, according to an embodiment, is shown. Detailed Implementation

[0012] This document describes techniques for decoding metadata encoded in error-correcting codes. In the following description, numerous examples and specific details are set forth for illustrative purposes to provide a thorough understanding of some embodiments. Various embodiments as defined by the claims may include some or all of these features, individually or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

[0013] Features and advantages of this disclosure include encoding and decoding metadata bits in error-correcting codes (ECC). Typically, ECC is implemented by taking cache lines and constructing them into multiple codewords (CWs), which are formed by a set of bits (sometimes called symbols) of a specified number. Reed-Solomon (RS) coding is an example of an error-correcting code. Error-correcting coding is the entire process of storing data and parities together using codewords so that the correctness of the original data can be determined upon readback. Error-correcting code parities are the generated bits, referred to herein as error-correcting codes (ECCs). In a given RSECC architecture, a symbol width is defined. The symbols of the codewords are encoded to generate ECC / parity bits. These parity bits are combined to form an ECC symbol and written to the medium along with the data symbol. Embodiments of this disclosure encode additional metadata along with the data bits (e.g., simultaneously with the generation of the ECC). In this case, for example, metadata information can be encoded within the parity symbol rather than directly occupying bits from the parity. For example, metadata may include one or more bits. For example, in one embodiment, metadata is a single poison bit indicating that associated data contains an error. Encoding additional metadata onto ECC symbols allows additional information to be stored on the medium without sacrificing medium read / write bandwidth, since the metadata is encoded and may not be physically stored separately on the medium. However, this encoding may affect the corrective capabilities of RS codes, an effect that can be minimized. To achieve this, some embodiments may use codeword dependency in cache lines, for example, using the same metadata for all codewords. Additional decoding is required when reading back from the medium to determine the correct value of the encoded metadata. This method of encoding metadata symbols (MS) along with ECC can provide additional capability to store metadata on the medium without compromising medium read / write bandwidth, when the overall error detection and correction probability is acceptable.

[0014] This disclosure includes example architectures and implementations of cache-line decoding algorithms (e.g., improved concurrent dual decoding algorithms), where the optimal number of decoding operations for a single bit of metadata encoded along with the data can be known deterministically. By invoking parallel decoders when necessary and suppressing unnecessary decoding when not necessary, some embodiments achieve minimal latency and low power consumption while requiring the full decoding pipeline to be activated.

[0015] Figure 1 A system for decoding metadata encoded in error-correcting codes, according to an embodiment, is illustrated. In this example, processor 101 can be coupled to memory 104 via memory controller 102 and error corrector 103. For example, processor 101 can be any of a variety of processors, such as an x86 or ARM-based microprocessor, an artificial intelligence processor, a graphics processor, or other processor that manipulates digital data and sends and receives data with other devices. Memory controller 102 manages the interface between processor 101 and memory 104. Memory 104 stores digital information and can be random access memory (e.g., DRAM or dual in-line memory module). In some embodiments, processor 101, memory controller 102, and error corrector 103 are on the same semiconductor integrated circuit communicating with one or more DIMMs.

[0016] Data written to memory may have one or more metadata bits encoded in error correction codes. For example, data may be processed in 512-bit words, which can be further subdivided into 128-bit "beats". Error corrector 103 may include encoder 105 for generating ECC parities for the data as it is written to memory 104. Parities are associated with the data used to generate them. As described herein, one or more metadata bits are encoded in the ECC for future use. The combination of data and associated ECC parities (and metadata) is sometimes referred to as a codeword. The codeword is stored in memory 104.

[0017] During a read operation, a codeword is retrieved from memory 104. Error corrector 103 includes an encoder for encoding the ECC associated with the data and a decoder 106 for decoding the ECC and metadata. For example, error corrector 103 may include a Reed-Solomon encoder and a decoder. Decoder 106 receives a codeword (CW) 107 comprising data and the associated ECC. The ECC includes encoded bits containing at least one metadata bit. Decoder 110 may include a first decoding stage 110 for generating multiple outputs (e.g., syndrome values). One output may correspond to data that matches the ECC code (valid data without the error to be corrected). However, other outputs may be used to determine the value of the metadata. For example, one output (labeled MS0, i.e., metadata symbol equals 0) may correspond to a metadata bit with a first state (e.g., 0), and a second output (labeled MS1, i.e., metadata symbol equals 1) may correspond to a metadata bit with a second state (e.g., 1). For example, MS0 can correspond to decoding ECC assuming the metadata bits have a value of "0" (first state), and MS1 can correspond to decoding ECC assuming the metadata bits have a value of "1" (second state). If multiple metadata bits are encoded in the ECC, additional outputs can be used to determine additional metadata values ​​(e.g., two metadata bits 00, 01, 10, 11). MS0 and MS1 are coupled to the second decoding stage 112.

[0018] The MS0 and MS1 outputs, as well as the CW, are processed as follows. The outputs of the first decoding stage 110 can all be multiple bits indicating whether the ECC has detected any errors in the associated data. If all bits of the output are 0, there is no error in the output. However, in this example, if the output is non-zero, there is an error in the data. Accordingly, when one of the first or second outputs has a zero value, the decoder 106 can set the value of the metadata bit to a first state or a second state corresponding to the first or second output with a zero value. For example, if the first output MS0 has a zero value (i.e., assuming the metadata bit is "0" is correct and no error has occurred), the metadata bit can be set to "0", while if MS1 has a zero value (i.e., assuming the metadata bit is "1" is correct and no error has occurred), the metadata bit can be set to "1". On the other hand, when both the first output MS0 and the second output MS1 are non-zero (i.e., indicating that the data has some errors under both metadata assumptions and needs to be fully decoded to determine whether it can be corrected), the codeword is decoded under both assumptions to determine the value of at least one metadata bit.

[0019] In some embodiments, the first decoding stage 110 is a syndrome checker that generates multi-bit symbols for output (e.g., MS0, MS1, etc.). Accordingly, in some embodiments, for example, MS0 and MS1 can be generated by using a syndrome checker hardware decoder component to decode the data and associated error correction code. The multi-bit symbols are then used to guide the stream of data and ECC to the second decoder stage 112. When both MS0 and MS1 are non-zero, the decoding stage 112 can decode the CW to obtain metadata. For example, in some embodiments described in more detail below, parallel decoder hardware can be used to reduce latency.

[0020] During a read operation, decoder 106 continuously receives multiple codewords comprising data and associated ECCs, each codeword including at least one metadata bit. For example, a block of memory (e.g., a cache line) may comprise 512 bits divided into four (4) 128-bit “beats”. Each beat of the 128-bit data may have an associated ECC, and each of the four (4) ECCs associated with each beat of the cache line may be encoded using the same(multiple) metadata bits. This allows for the recovery of the(multiple) metadata bits, as described in more detail below. For example, in one embodiment, when one of the outputs (e.g., MS0, MS1) has a zero value for the first codeword, the decoder may set a flag indicating that at least one metadata bit value has been set for the first error correction code. Accordingly, when both the first and second outputs are non-zero for subsequent codewords (as described below) Figure 3 As shown at point 303, the decoder can decode assuming the metadata value is the same as the previous result. If the result does not match, the data may have uncorrectable errors. When the previous codeword is not determined without further decoding, subsequent codewords are further decoded, as described above and further below. Finally, when determining the value of at least one metadata bit for each codeword, the system can vote to specify the determined value of at least one metadata bit. When each vote matches (e.g., each codeword produces the same value for metadata), the codeword is decoded. However, if any codeword produces a different metadata value, the data may have uncorrectable errors.

[0021] Figure 2A method for decoding metadata encoded in an error-correcting code according to an embodiment is illustrated. At 201, a first codeword is received in a decoder. The first codeword includes first data and an associated first error-correcting code. The first error-correcting code includes a first encoded plurality of bits, which includes at least one metadata bit. At 202, the decoder generates a first output corresponding to a first state for the at least one metadata bit. At 203, the decoder generates a second output corresponding to a second state for the at least one metadata bit. At 205, the system determines whether either output is all zeros. When one of the first and second outputs has a zero value, at 205, the decoder sets the value of the at least one metadata bit to either the first or second state corresponding to the first or second output having a zero value. When both the first and second outputs are non-zero, at 206, the decoder decodes the first codeword corresponding to the at least one metadata bit having a first state and decodes the first codeword corresponding to the at least one metadata bit having a second state to determine the value of the at least one metadata bit.

[0022] Figure 3 An example process for decoding a first codeword according to an embodiment is shown. Figures 3-7 In the example shown below, a 512-bit cache line is divided into four 128-bit ticks, with a single metadata bit encoded in the ECC of each tick. Four codewords (CWs) are read from memory. Each codeword has an associated ECC, which includes ECC bits and encoded metadata bits (hereinafter referred to as metadata symbols MS). At 301, CW0 is read. At 302, a checksum check produces two outputs, including symbols S00 and S01, which correspond to the data and ECC decoded for CW0 under the assumption that the metadata symbol values ​​(MS) are 0 (S00) and 1 (S01). The output symbols S00 and S01 are multi-bit values. If the output is all zeros, there is no error. Therefore, if either output is 0, the corresponding assumption is correct, and the MS value is the assumed value.

[0023] At 303, the system determines whether S00 or S01 is all zeros. If so, at 304, a flag indicating that metadata bits have been decoded (e.g., MS_decoded = True) is set. Additionally, at 305, an estimate of the MS value is set to an appropriate value (e.g., MSest = 0 or 1). At 306, a vote is taken on the value of MS. At 307, CW0 decoding is complete. However, if neither S00 nor S01 is all zeros, CW0 is decoded at 308 assuming MS is 0 (MS0), and at 309 assuming MS is 1 (MS1). If the output of the second decoding supports this result, a vote is taken on each output at 310 and 311.

[0024] Figure 4 An example process for decoding a second codeword according to an embodiment is shown. Figure 4 The processing of the second codeword (CW1) to be read is shown. At 401, CW1 is read. At 402, the checksum verification produces two outputs, including symbols S10 and S11, which correspond to the decoding of the data for CW1 and ECC under the assumption that the metadata symbol values ​​(MS) are 0 (S10) and 1 (S11). As mentioned above, the output symbols S10 and S11 are multi-bit values. If the output is all zeros, there is no error. Therefore, if either output is 0, the corresponding assumption is correct, and the MS value is the assumed value.

[0025] At 403, the system determines whether S10 or S11 is all zeros. If so, at 420, the estimated value of MS is set to the corresponding value (e.g., MS_est1 = 0 or 1). At 421, a vote is taken on the value of MS. At 422, the MS_decoded flag is checked. If so, the estimated values ​​are compared at 423. If they match, CW1 decoding is complete. However, if they do not match, an uncorrectable error flag is triggered. If MS_decoded is not, MS_decoded is set at 425, MS_est is set to be equal to MS_est1 at 426, and CW1 decoding is complete at 427.

[0026] Referring again to 403, if neither S10 nor S11 is all zero, then MS_decoded is checked at 404. If so, then at 405, CW1 can be decoded using the MS_est value from CW0. This result is used to exercise voting at 406. If it is decodable at 407 (decoding 405 produces all zeros based on the assumption that MS = MS_est), then CW1 decoding is complete. If it is not decodable at 407, then an uncorrectable error is recorded at 408. If MS_decoded is not set at 404, then CW1 is decoded at 409 with the assumption that MS is 0 (MS0), and at 410 with the assumption that MS is 1 (MS1). If the output of the second decoding supports this result, then each output is used to exercise voting at 411 and 412.

[0027] Figure 5 An example process for decoding a third codeword according to an embodiment is shown. The third codeword (CW2) is used with... Figure 4 The process is essentially similar to that shown in CW1. This process is shown in steps 501-527, where S20 and S21 are the symbols of the output, and MS_est2 is, for example, the MS value when S20 or S21 is all zero. Figure 6 An example process for decoding a fourth codeword according to an embodiment is shown. The fourth codeword (CW3) is obtained using... Figure 4 and Figure 5 The process is essentially similar to that shown for CW1 and CW2. This process is shown in steps 601-627, where S30 and S31 are the symbols of the output, and MS_est3 is, for example, the MS value when S30 or S31 is all zero.

[0028] Figure 7 An example of voting according to an embodiment is shown. As described above, embodiments of this disclosure may include a decoder that exercises voting on metadata values ​​stored in multiple ECCs across multiple codewords. Referring to the above... Figures 4-6 In step 701, the system determines whether there is exactly one vote for MS=0 or MS=1 (e.g., every vote for every CW matches). If not, the system triggers an uncorrectable error. If yes, cache line decoding is complete.

[0029] Figure 8 An example hardware architecture for decoding metadata encoded in error-correcting codes is shown, and Figure 9 An example timing diagram for decoding metadata encoded in error-correcting codes is shown. (Reference) Figure 8, receive data and ECC from a medium (e.g., RAM) in the RS syndrome check hardware decoder component 801. If any of the output symbols (assuming MS = 0 or 1) is all zeros, store the data and ECC in a first-in-first-out (FIFO) 802. According to the algorithm shown above, each CW can be further decoded assuming MS = 0 (path MS0) or MS = 1 (path MS1). In this example, the decoder can include a first hardware decoder component 803 and a second hardware decoder component 805 for decoding the CWs in parallel based on the first output and the second output. For example, each decoder 803 / 805 can be substantially the same and include a key equation solver error locator polynomial (KES-ELP) section 810 / 813, a Chien error locator search (EPS) section 811 / 814, an error magnitude calculation (EMG) section 812 / 815, and an error correction (ECN) section 805. Figure 9 The timing diagram in shows how the codewords flow through the system. The syndrome check for CW0 is performed at time 1, and the syndrome check for each subsequent CW is performed at each subsequent cycle. CW0 is processed by KES1 and KES2 (two cycles per KES stage) at cycles 2 and 3, and CW0 is processed by CHIEN1 and CHIEN2 (two cycles per CHIEN stage) at cycles 4 and 5. Finally, for example, CW0 is processed by EMG and ECN at cycle 6 and is provided to the output data path (DP). Subsequent CWs are processed in a pipelined manner, as Figure 9 shown.

[0030] In various example embodiments, the underlying Reed - Solomon decoder can be a fully pipelined multi - stage <n - cycle> decoder. In the first clock cycle, determine the validity of the syndrome (under two metadata assumptions when there is only one bit of metadata), and based on this, decide whether to call the full decoder. If the CW syndrome is valid under any of the metadata assumptions (MS0 or MS1), it will be invalid under the other assumption and does not need to go through the remaining (n - 1) stages of the full decoder.

[0031] If the syndrome is invalid under any of the MS assumptions, it means the CW has an error and can go through the full decoder to determine whether it can be corrected. To minimize latency, for example, by calling two instances of the full Reed - Solomon decoder, decode the CW in parallel using the two MS options. However, once the MS value has been established for a given CW, it is not necessary to, as Figures 4-6The algorithm shown utilizes two MS options to decode subsequent ticks of the same cache line, as illustrated. In these scenarios, suppressing activation of the full decoder advantageously saves power. Once an error-free CW is found, and the MS value for that particular codeword and subsequently for the cache line is known, embodiments of this disclosure utilize this information to minimize the number of decoding operations for subsequent CWs within the same cache line.

[0032] If all CWs in the cache line are faulty, the system can perform 8 full decodes for 4 codewords in the cache line. For any other combination of clean and faulty CWs, using the above method will minimize the required number of decodes, ideally when the first CW is clean. In this case, subsequent CWs only need to be decoded using the known correct MS assumption, thus reducing the required number of full decodes to exactly three, as described above.

[0033] Physically storing (multiple) metadata bits on the medium is an advantageous solution, but it can reduce medium bandwidth and storage capacity. However, in some embodiments, multiple codewords can be used to carry one bit of metadata. This means that decoding can be performed using the correlation between codewords, thus preventing most error patterns. Another advantage of some embodiments is the granularity of the number of metadata bits it can handle. For example, various embodiments can use exactly the same number of bits required for the metadata and maintain ECC correction capabilities at their optimal level without consuming ECC bits. Further examples

[0034] Each of the following non-limiting features in the examples below may exist independently or may be combined with one or more other features in the embodiments below in various permutations or combinations. In various embodiments, this disclosure may be implemented as a processor or method.

[0035] Embodiments of this disclosure include systems, computer-readable media, and / or methods for decoding. In one embodiment, this disclosure includes a system comprising: a processor; a memory controller; and a decoder, wherein the decoder receives a first codeword including first data and an associated first error correction code, the first error correction code including a first encoded plurality of bits, the first encoded plurality of bits including at least one metadata bit, and the decoder generates a first output corresponding to a first state having at least one metadata bit and a second output corresponding to a second state having at least one metadata bit, wherein when one of the first output or the second output has a zero value, the decoder sets the value of at least one metadata bit to the first state or the second state corresponding to the first output or the second output having a zero value, and when both the first output and the second output are non-zero, the first codeword is decoded corresponding to the first state having at least one metadata bit, and the first codeword is decoded corresponding to the second state having at least one metadata bit to determine the value of at least one metadata bit.

[0036] In one embodiment, the decoder is a Reed-Solomon decoder.

[0037] In one embodiment, the first output corresponds to decoding the first error correction code assuming at least one metadata bit has a first state, and the second output corresponds to decoding the first error correction code assuming at least one metadata bit has a second state.

[0038] In one embodiment, the decoder successively receives a plurality of second codewords including second data and a plurality of associated second error correction codes, the second error correction codes including a plurality of second encoded bits, the plurality of second encoded bits including at least one metadata bit.

[0039] In one embodiment, when one of the first outputs or the second output has a zero value for the first codeword, the decoder sets a flag indicating that the codeword can be corrected using at least one metadata bit value already set for the first error correction code, and wherein when both the first and second outputs are non-zero for a plurality of second codewords, when the flag is in a first state, the plurality of second codewords are decoded based on the first and second outputs to determine the value of at least one metadata bit, and when the flag is in a second state, the plurality of second codewords are decoded based on the flag, based on one of the first and second outputs, to determine the value of at least one metadata bit.

[0040] In one embodiment, when determining the value of at least one metadata bit for each codeword, a vote is exercised to specify the determined value of at least one metadata bit, and wherein when each vote matches, the first codeword and a plurality of second codewords are decoded.

[0041] In one embodiment, the first output and the second output are generated by decoding the first data and the first error correction code using a checksum hardware decoder component.

[0042] In one embodiment, the decoder includes a first hardware decoder component and a second hardware decoder component for decoding in parallel based on a first output and a second output.

[0043] In one embodiment, at least one metadata bit is a single bit.

[0044] In one embodiment, a single bit is a poison bit that indicates that the associated data contains a erroneous value.

[0045] In one embodiment, the decoder receives first data and a first error correction code from a random access memory.

[0046] The foregoing description illustrates various embodiments and examples of aspects of how some embodiments can be implemented. The foregoing examples and embodiments should not be considered as the only embodiments, and are presented to demonstrate the flexibility and advantages of some embodiments as defined by the following claims. Based on the foregoing disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be employed without departing from the scope defined by the claims.

Claims

1. A system comprising: Processor (101); Memory controller (102); as well as A decoder (106) receives a first codeword including first data and an associated first error correction (103) code, the first error correction (103) code including a first encoded plurality of bits, the first encoded plurality of bits including at least one metadata bit, and the decoder (106) generates a first output corresponding to a first state of the at least one metadata bit and a second output corresponding to a second state of the at least one metadata bit. When either the first output or the second output has a zero value, the decoder (106) sets the value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having a zero value, and When both the first output and the second output are non-zero, the first codeword is decoded corresponding to the first state of the at least one metadata bit, and the first codeword is decoded corresponding to the second state of the at least one metadata bit, to determine the value of the at least one metadata bit.

2. The system of claim 1, wherein the decoder is a Reed-Solomon decoder.

3. The system of claim 1, wherein the first output corresponds to decoding the first error correction code assuming the at least one metadata bit has the first state, and the second output corresponds to decoding the first error correction code assuming the at least one metadata bit has the second state.

4. The system of claim 1, wherein the decoder successively receives a plurality of second codewords including second data and a plurality of associated second error correction codes, the second error correction codes including a plurality of second encoded bits, the plurality of second encoded bits including the at least one metadata bit.

5. The system of claim 4, wherein when either the first output or the second output for the first codeword has a zero value, a flag is set by the decoder indicating that the codeword is correctable given that at least one metadata bit value has been set for the first error correction code, and Where both the first output and the second output for the plurality of second codewords are nonzero, When the flag is in the first state, for the plurality of second codewords, decoding is performed based on the first output and the second output to determine the value of the at least one metadata bit; and when the flag is in the second state, for the plurality of second codewords, decoding is performed based on the flag based on either the first output or the second output to determine the value of the at least one metadata bit.

6. The system of claim 5, wherein when determining the value of the at least one metadata bit for each codeword, a vote is cast specifying the determined value of the at least one metadata bit, and wherein the first codeword and the plurality of second codewords are decoded upon each vote match.

7. The system of claim 1, wherein the first output and the second output are generated by decoding the first data and the first error correction code using a checksum hardware decoder component.

8. The system of claim 1, wherein the decoder comprises a first hardware decoder component and a second hardware decoder component for performing decoding in parallel based on the first output and the second output.

9. The system of claim 8, wherein the at least one metadata bit is a single bit.

10. The system of claim 9, wherein the single bit is a poison bit indicating that the associated data contains an error.

11. The system of claim 1, wherein the decoder receives the first data and the first error correction code from the random access memory in the same position.

12. A decoding method, comprising: The decoder receives a first codeword including first data and an associated first error correction code, the first error correction code including a first encoded plurality of bits, the first encoded plurality of bits including at least one metadata bit; The decoder generates a first output corresponding to a first state of the at least one metadata bit; The decoder generates a second output that corresponds to the second state of the at least one metadata bit; as well as When either the first output or the second output has a zero value, the decoder sets the value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having a zero value, and When both the first output and the second output are non-zero, the first codeword is decoded corresponding to the first state of the at least one metadata bit, and the first codeword is decoded corresponding to the second state of the at least one metadata bit, to determine the value of the at least one metadata bit.

13. The method of claim 12, wherein the decoder is a Reed-Solomon decoder.

14. The method of claim 12, wherein the first output corresponds to decoding the first error correction code assuming the at least one metadata bit has the first state, and the second output corresponds to decoding the first error correction code assuming the at least one metadata bit has the second state.

15. The method of claim 12, wherein the decoder successively receives a plurality of second codewords comprising second data and a plurality of associated second error correction codes, the second error correction codes comprising a plurality of second encoded bits, the plurality of second encoded bits comprising the at least one metadata bit.

16. The method of claim 15, wherein when either the first output or the second output for the first codeword has a zero value, a flag is set by the decoder, the flag indicating that the at least one metadata bit value has been set for the first error correction code, and Where both the first output and the second output for the plurality of second codewords are nonzero, When the flag is in the first state, for the plurality of second codewords, the first output and the second output are decoded to determine the value of the at least one metadata bit; and when the flag is in the second state, for the plurality of second codewords, one of the first output or the second output is decoded based on the flag to determine the value of the at least one metadata bit.

17. The method of claim 16, wherein when determining the value of the at least one metadata bit for each codeword, a vote is cast specifying the determined value of the at least one metadata bit, and wherein the first codeword and the plurality of second codewords are decoded upon each vote match.

18. The method of claim 12, wherein the first output and the second output are generated by decoding the first data and the first error correction code using a checksum hardware decoder component.

19. The method of claim 12, wherein the decoder comprises a first hardware decoder component and a second hardware decoder component for performing decoding in parallel based on the first output and the second output.

20. The method of claim 19, wherein the at least one metadata bit is a single bit.

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