Methods, systems, and apparatus for channel related error correction coding

Abstract

An encoded bit block is obtained by encoding an input bit, and the encoded bit block is output for transmission, etc. Each of the coded bit blocks has a respective associated coding rate and a respective associated capacity. The blocks of coded bits comprise nested blocks, each nested block comprising a subcode of another block of coded bits, the other block of coded bits having a corresponding associated coding rate higher than the nested block. The nesting block comprises coupling blocks which are coupled with each other. The coupled block may provide or support any one or more of: a flexible output order based on block-level coding rate and capacity, a flexible decoding order based on block-level coding rate and capacity, or a variable block-level coding rate.

Description

[0001] Cross-references to related applications

[0002] This application relates to and claims priority to U.S. Provisional Patent Application No. 63 / 454,070, filed March 23, 2023, entitled “Methods, Systems, and Apparatus for Channel-dependent Error Correction Coding”.

[0003] This application relates to the following Patent Cooperation Treaty (PCT) applications filed by the same applicant:

[0004] PCT application filed on March 23, 2023, with application number PCT / CN2023 / 083350 and invention title "Methods, Systems, and Apparatus for Non-Sequential Decoding of Polar Codes";

[0005] PCT application filed on March 23, 2023, with application number PCT / CN2023 / 083348 and invention title "Methods, Systems, and Apparatus for Bit Value Placement in Polar Coding";

[0006] PCT application filed on March 23, 2023, with application number PCT / CN2023 / 083345 and invention title "Methods, Systems, and Apparatus for EncodedBit Reduction in Polar Coding";

[0007] PCT application filed on May 31, 2023, with application number PCT / CN2023 / 097662 and invention title "Methods, Systems, and Apparatus for Protograph-based Low Density Parity Check Coding";

[0008] PCT application filed on May 6, 2023, with application number PCT / CN2023 / 092465 and invention title "Methods, Systems, and Apparatus for Partial Code Rate Reduction in Polar Coding";

[0009] PCT application filed on June 27, 2023, with application number PCT / CN2023 / 102653 and invention title "Methods, Systems, and Apparatus for Rateless Polar Coding";

[0010] PCT application No. PCT / CN2023 / 103893, filed on June 29, 2023, entitled "Methods, Systems, and Apparatus for Rateless Polar Coding and Low-complexity Decoding," is also applicable to the following U.S. provisional patent applications:

[0011] U.S. Provisional Patent Application No. 63 / 454,066, filed on March 23, 2023, entitled “Methods, Systems, and Apparatus for Partial Code Rate Reduction in Polar Coding”;

[0012] U.S. Provisional Patent Application No. 63 / 454,067, filed on March 23, 2023, entitled “Methods, Systems, and Apparatus for Rateless Polar Coding”;

[0013] U.S. Provisional Patent Application No. 63 / 454,068, filed on March 23, 2023, entitled “Methods, Systems, and Apparatus for RatelessPolar Coding and Low-complexity Decoding”;

[0014] U.S. Provisional Patent Application No. 63 / 454,069, filed on March 23, 2023, entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Incremental Redundancy”.

[0015] The full disclosure of the above application is incorporated herein by reference. Technical Field

[0016] This application relates to coding, and more particularly to channel-related error correction coding. Background Technology

[0017] In wireless communication, channel conditions continuously change on both fast and slow scales due to factors such as fading effects. Therefore, traditionally, channel coding design has always aimed to adapt to these channel conditions. Adaptive modulation and coding schemes (MCS) are an effective method for dealing with constantly changing channel conditions, where the modulation sequence, code length, and coding rate can be changed in real time.

[0018] To adapt to channel conditions, channel coding needs to be able to flexibly change code length and coding rate in a fine-grained manner while maintaining good error correction performance under all possible configurations. However, achieving this fine-grained flexibility in channel coding remains a challenge.

[0019] Low-density parity-check (LDPC) codes and other probabilistic codes resemble random codes more closely and may be inherently suited for flexibility. Algebraic codes, such as Reed-Muller (RM) codes and Bose-Chaudhuri-Hocquenghem (BCH) codes, are less flexible than probabilistic codes. This is because their inherent coding structure can be affected by changes in code length or coding rate. Polar codes combine characteristics of both probabilistic and algebraic codes. Therefore, the flexibility of polar codes lies between that of probabilistic and algebraic codes.

[0020] Rate matching techniques (including puncturing and shortening) can be used to design rate-compatible polar codes, such as those used in fifth-generation (5G) new radio (NR). However, this level of flexibility is insufficient to support more advanced features, such as fine-grained incremental-redundancy hybrid automatic repeat request (IR-HARQ).

[0021] Therefore, a more flexible channel coding method is needed. Summary of the Invention

[0022] This invention relates to embodiments related to the implementation or promotion of what is referred to herein primarily as channel-dependent error correction coding, and may relate to a novel coding structure that, after code construction and encoding, can provide multiple decoding schemes for different channel conditions.

[0023] According to one aspect of the present invention, a method is provided for encoding input bits to obtain encoded bit blocks and outputting the encoded bit blocks. Each encoded bit block has a corresponding associated coding rate and a corresponding associated capacity. The encoded bit blocks include nested blocks. Each nested block includes a subcode of another encoded bit block, the other encoded bit block having a higher corresponding associated coding rate than the nested block. The nested blocks include coupled blocks.

[0024] In addition, another method is provided for receiving a block of encoded bits obtained by encoding input bits, and decoding the encoded bits to obtain decoded input bits. Each block of encoded bits has a corresponding associated coding rate and a corresponding associated capacity. The block of encoded bits includes nested blocks, each nested block including a subcode of another block of encoded bits, the other block having a higher associated coding rate than the nested block. The nested blocks include coupled blocks that are mutually coupled.

[0025] An apparatus according to one embodiment includes an encoder and an interface coupled to the encoder. The encoder is used to encode input bits to obtain a block of encoded bits, while the interface is used to output the block of encoded bits.

[0026] An apparatus according to another embodiment includes an interface and a decoder coupled to the interface. The interface is used to receive or receive a block of encoded bits obtained by encoding input bits, and the decoder is used to decode the encoded bits to obtain decoded input bits.

[0027] In the device embodiments and other device embodiments, each of the coded bit blocks has a corresponding associated coding rate and a corresponding associated capacity. The coded bit blocks include nested blocks, each nested block including a subcode of another coded bit block. The other coded bit block has a higher corresponding associated coding rate than the nested block. The nested blocks include mutually coupled coupling blocks.

[0028] In other device embodiments, the device may include a processor for causing the device to perform any of the methods disclosed herein.

[0029] The apparatus may include: a processor; and a non-transitory computer-readable storage medium coupled to the processor and storing a program for execution by the processor.

[0030] Storage media need not necessarily be, or only need to be, implemented in or in conjunction with such a device. A computer program product may, for example, be or include a non-transitory computer-readable medium storing a program for execution by a processor.

[0031] A program stored in a computer-readable storage medium may include instructions for or for causing a processor to execute, implement, support or enable any of the methods disclosed herein.

[0032] A system is also disclosed, which may include a first communication device and a second communication device. The first communication device is used to transmit an encoded bit block obtained by encoding input bits. The second communication device is used to receive the encoded bit block and decode the encoded bits to obtain decoded input bits. In other embodiments, each encoded bit block has a corresponding associated coding rate and a corresponding associated capacity, the encoded bit block includes nested blocks, each nested block includes a sub-code of another encoded bit block, the other encoded bit block having a higher corresponding associated coding rate than the nested block, and the nested blocks include mutually coupled coupling blocks.

[0033] This invention covers these and other aspects or embodiments. Attached Figure Description

[0034] To gain a more comprehensive understanding of the embodiments of the present invention and their advantages, the following description is provided with reference to examples and the accompanying drawings, in which:

[0035] Figure 1 This is a simplified diagram of a communication system;

[0036] Figure 2 yes Figure 1 A block diagram of an exemplary communication system;

[0037] Figure 3 Examples of exemplary electronic devices and base stations are shown;

[0038] Figure 4 This shows the units or modules in the device;

[0039] Figure 5 An exemplary original model diagram matrix is ​​shown;

[0040] Figure 6 This is a lattice diagram of a polar code example;

[0041] Figure 7 It is a lattice diagram of the distribution of the log-likelihood ratio (LLR) in polar code decoding;

[0042] Figure 8 This is a diagram illustrating the decoding of a block with sufficient capacity before decoding a block with insufficient capacity.

[0043] Figure 8 This is a diagram illustrating the decoding of a block with sufficient capacity before decoding a block with insufficient capacity.

[0044] Figure 9 It is a block diagram comparison of channel-independent codes and channel-dependent codes;

[0045] Figure 10 An exemplary factor graph of the code is shown;

[0046] Figure 11 An example of a nested code structure is shown;

[0047] Figure 12 An example of information bit mapping according to an embodiment is shown;

[0048] Figure 13 Another exemplary factor graph is shown;

[0049] Figure 14 An example of check node coupling between blocks with variable coding rates is shown;

[0050] Figure 15A This is a schematic diagram illustrating the placement of bit values ​​on bit indices according to an embodiment;

[0051] Figure 15B This is a schematic diagram illustrating an example of a bit index to a tag mapping;

[0052] Figure 15C This is a schematic diagram illustrating the placement of bit values ​​on bit indices using bit tags according to an embodiment;

[0053] Figure 16 This is a block diagram of the f function used in polar code decoding;

[0054] Figure 17 This is a block diagram of the g function used in polar code decoding;

[0055] Figure 18 This is a schematic diagram of the "butterfly" structure processing in polar code decoding;

[0056] Figure 19 This is a schematic diagram of the binary tree representation of continuous elimination decoding;

[0057] Figure 20 This is a block diagram of the binary tree representation of the SC decoding of a polar code of length N=4;

[0058] Figure 21 g is used in an embodiment of non-sequential polar code decoding. r A flowchart of a function;

[0059] Figure 22 f is used in an embodiment of non-sequential polar code decoding. r A flowchart of a function;

[0060] Figure 23 This is a schematic diagram of the processing of the "butterfly" structure in an embodiment of non-sequential polar code decoding;

[0061] Figure 24 This is a schematic diagram of a binary tree representation of a decoding scheduling example;

[0062] Figure 25 This is a schematic diagram of the binary tree representation of the non-sequential SC decoding of a polar code of length N=4;

[0063] Figure 26 Includes tables and lattice diagrams illustrating the differences between non-sequential and sequential decoding;

[0064] Figure 27 It is a lattice diagram of a decoding example involving non-sequential polar code decoding;

[0065] Figure 28 This is a lattice diagram of another decoding example involving non-sequential polar code decoding;

[0066] Figure 29 This is a lattice diagram representing yet another example of decoding involving non-sequential polar codes;

[0067] Figure 30 This is a lattice diagram representing another example of decoding non-sequential polar codes;

[0068] Figure 31 It is a lattice diagram of a bidirectional decoding example;

[0069] Figure 32 This is a lattice diagram of another example of bidirectional decoding;

[0070] Figure 33An example of block-coupled coding is shown;

[0071] Figure 34 An encoding with block coupling according to another embodiment is shown;

[0072] Figure 35 This is a flowchart of a more general exemplary method according to an embodiment;

[0073] Figure 36 This is a block diagram of an apparatus according to an embodiment. Detailed Implementation

[0074] For illustrative purposes, specific exemplary embodiments will be explained in more detail below with reference to the accompanying drawings.

[0075] The embodiments described herein illustrate information sufficient to practice the claimed subject matter and explain methods for practicing such subject matter. Upon reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the claimed subject matter and recognize the application of these concepts not specifically mentioned herein. It should be understood that these concepts and applications are within the scope of this invention and the appended claims.

[0076] refer to Figure 1 The diagram provided is a simplified schematic of a communication system, intended as an illustrative example and not as limiting. Communication system 100 includes a radio access network 120. Radio access network 120 can be a next-generation (e.g., sixth-generation, 6G, or later) radio access network or a traditional (e.g., 5G, 4G, 3G, or 2G) radio access network. One or more communication electrical devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (collectively referred to as 110) can be interconnected with each other or connected to one or more network nodes (170a, 170b, collectively referred to as 170) within radio access network 120. Core network 130 can be part of the communication system and can depend on or be independent of the radio access technology used in communication system 100. In addition, the communication system 100 includes a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160.

[0077] Figure 2This is an exemplary communication system 100. Typically, communication system 100 enables multiple wireless or wired components to transmit data and other content. The purpose of communication system 100 may be to provide information such as voice, data, video, signaling, and / or text via broadcast, multicast, and unicast. Communication system 100 can operate by sharing resources such as carrier spectrum bandwidth among its constituent components. Communication system 100 may include terrestrial communication systems and / or non-terrestrial communication systems. Communication system 100 can provide a wide range of communication services and applications (e.g., earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, automated delivery and mobility, etc.). Communication system 100 can provide high availability and robustness through the joint operation of terrestrial and non-terrestrial communication systems. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can create a heterogeneous network that can be considered as comprising multiple layers. Compared to traditional communication networks, heterogeneous networks can achieve better overall performance through efficient multi-link joint operation, more flexible function sharing, and faster physical layer link switching between terrestrial and non-terrestrial networks.

[0078] Terrestrial communication systems and non-terrestrial communication systems can be considered subsystems of a communication system. Figure 2 In the example, communication system 100 includes electronic devices (EDs) 110a, 110b, 110c, and 110d (collectively referred to as ED 110), radioaccess networks (RANs) 120a and 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. RANs 120a and RAN 120b include corresponding base stations (BSs) 170a and 170b, commonly referred to as terrestrial transmit and receive points (T-TRPs) 170a and 170b. The non-terrestrial communication network 120c includes access nodes 172, commonly referred to as non-terrestrial transmit and receive points (NT-TRPs) 172.

[0079] Any ED 110 can be used alternatively or additionally to connect, access, or communicate with any T-TRP 170a, 170b, and NT-TRP 172, Internet 150, core network 130, PSTN 140, other network 160, or any combination of the aforementioned networks. In some examples, ED 110a can perform uplink and / or downlink transmission with T-TRP 170a via terrestrial air interface 190a. In some examples, ED 110a, ED 110b, ED 110c, and ED 110d can also communicate directly with each other via one or more side-channel air interfaces 190b. In some examples, ED 110d can perform uplink and / or downlink transmission with NT-TRP 172 via non-terrestrial air interface 190c.

[0080] Air interfaces 190a and 190b can use similar communication technologies, such as any applicable wireless access technology. For example, communication system 100 can implement one or more channel access methods in air interfaces 190a and 190b, such as code division multiple access (CDMA), space division multiple access (SDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), direct Fourier transform spread OFDMA (DFT-OFDMA), or single-carrier FDMA (SC-FDMA). Air interfaces 190a and 190b can utilize other higher-dimensional signal spaces, which may include combinations of orthogonal and / or non-orthogonal dimensions.

[0081] The non-terrestrial air interface 190c enables communication between the ED 110d and one or more NT-TRP 172s via a wireless link or link. In some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection between a group of ED 110s and one or more NT-TRP 172s for multicast transmission.

[0082] RAN 120a and RAN 120b communicate with core network 130 to provide various services, such as voice, data, and other services, to ED 110a, ED 110b, and ED 110c. RAN 120a and RAN 120b and / or core network 130 can communicate directly or indirectly with one or more other RANs (not shown), which may or may not be directly served by core network 130, and may or may not use the same radio access technology as RAN 120a, RAN 120b, or both. Core network 130 can also serve as a gateway access between (i) RAN 120a and RAN 120b or ED 110a, ED 110b, ED 110c, or both, and (ii) other networks (e.g., PSTN 140, Internet 150, and other networks 160). Additionally, some or all of the EDs in ED 110a, ED 110b, and ED 110c may include the ability to communicate with different wireless networks via different wireless links using different wireless technologies and / or protocols. ED 110a, ED 110b, and ED 110c may communicate with a service provider or exchange (not shown) via a wired communication channel and with the Internet 150, rather than wirelessly (or otherwise wirelessly). PSTN 140 may include a circuit-switched telephone network for providing plain old telephone service (POTS). The Internet 150 may include a computer network and / or subnet (internal network) and include protocols such as Internet Protocol (IP), Transmission Control Protocol (TCP), and User Datagram Protocol (UDP). ED 110a, ED 110b, and ED 110c may be multimode devices capable of operating according to multiple wireless access technologies and may include multiple transceivers required to support these technologies.

[0083] Figure 3Another example of an ED 110 and base stations 170a, 170b, and / or 170c is shown. The ED 110 is used to connect people, objects, machines, etc. The ED 110 can be widely used in various scenarios, such as cellular communication, device-to-device (D2D), vehicle-to-everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), machine-type communications (MTC), Internet of Things (IoT), virtual reality (VR), augmented reality (AR), mixed reality (MR), metaverse, digital twins, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearable devices, smart transportation, smart cities, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, automated delivery and mobility, etc.

[0084] Each ED 110 represents any suitable end-user equipment used for wireless operation and may include devices such as (or may be referred to as) user equipment / device (UE), wireless transmit / receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular phone, station (STA), machine type communication (MTC) device, personal digital assistant (PDA), smartphone, laptop, computer, tablet, wireless sensor, consumer electronics device, smart book, vehicle, car, truck, bus, train, or IoT device, wearable device (e.g., watch, head-mounted device, and a pair of glasses), industrial equipment, or devices within the aforementioned equipment (e.g., communication module, modem, or chip), etc. Future generations of ED 110 may be referred to using other terms. Base stations 170a and 170b are T-TRPs and will be referred to as T-TRP 170 below. Also... Figure 3As shown, NT-TRP is referred to as NT-TRP 172 below. Each ED 110 connected to T-TRP 170 and / or NT-TRP 172 can be configured to be dynamically or semi-statically turned on (i.e., established, activated, or enabled), turned off (i.e., released, deactivated, or disabled), and / or in response to one or more of connection availability and connection necessity.

[0085] ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is shown in the figure. Alternatively, one, some, or all of the antennas 204 may be panels. The transmitter 201 and receiver 203 may, for example, be integrated as a transceiver. The transceiver is used to modulate data or other content for transmission over at least one antenna 204 or a network interface controller (NIC). The transceiver may also be used to demodulate data or other content received over at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and / or for processing signals received wirelessly or wiredly. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals.

[0086] ED 110 includes at least one memory 208. Memory 208 stores instructions and data used, generated, or acquired by ED 110. For example, memory 208 may store software instructions or modules for implementing some or all of the functions and / or embodiments described herein, and executed by one or more processing units (e.g., processor 210). Each memory 208 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, on-processor cache, etc.

[0087] ED 110 may also include one or more input / output devices (not shown) or interfaces (e.g. Figure 1(A wired interface connecting to the Internet 150). Input / output devices support interaction with the user or other devices on the network. Each input / output device includes any suitable structure for providing or receiving information from the user, such as operation via a speaker, microphone, keypad, keyboard, display, or touchscreen, including network interface communication.

[0088] ED 110 includes a processor 210 for performing operations including: operations related to preparing uplink transmissions to NT-TRP 172 and / or T-TRP 170; operations related to processing downlink transmissions received from NT-TRP 172 and / or T-TRP 170; and operations related to processing sidelink transmissions to and from another ED 110. Processing operations related to preparing uplink transmissions may include operations such as encoding, modulation, transmit beamforming, and generating symbols for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulation, and decoding of received symbols. According to an embodiment, the downlink transmission may be received by receiver 203 using receive beamforming, and processor 210 may extract signaling from the downlink transmission (e.g., by detecting and / or decoding signaling). For example, the signaling may be a reference signal transmitted by NT-TRP 172 and / or T-TRP 170. In some embodiments, processor 210 performs transmit beamforming and / or receive beamforming based on beam direction indications received from T-TRP 170, such as beam angle information (BAI). In some embodiments, processor 210 may perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as operations related to detecting synchronization sequences, decoding, and acquiring system information. In some embodiments, processor 210 may perform channel estimation, for example, using reference signals received from NT-TRP 172 and / or T-TRP 170.

[0089] Although not shown, processor 210 may be part of transmitter 201 and / or receiver 203. Although not shown, memory 208 may be part of processor 210.

[0090] Processor 210, the processing components of transmitter 201, and the processing components of receiver 203 can all be implemented by the same or different processors for executing instructions stored in memory (e.g., memory 208). Alternatively, some or all of the processor 210 and the processing components of transmitter 201 and receiver 203 can be implemented using dedicated circuitry, such as a programmable field-programmable gate array (FPGA), a graphics processing unit (GPU), a central processing unit (CPU), or an application-specific integrated circuit (ASIC).

[0091] In some implementations, T-TRP 170 can be referred to by other names, such as base station, basetransceiver station (BTS), wireless base station, network node, network device, network-side device, transmit / receive node, NodeB, evolved NodeB (eNodeB or eNB), home eNodeB, next-generation NodeB (gNB), transmission point (TP), site controller, access point (AP), wireless router, relay station, ground node, ground network device or ground base station, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc. T-TRP 170 can be a macro base station, pico base station, relay node, host node, or a combination thereof. T-TRP 170 may refer to the aforementioned equipment or a device within the aforementioned equipment (e.g., a communication module, modem, or chip).

[0092] In some embodiments, the various parts of T-TRP 170 may be distributed. For example, some modules of T-TRP 170 may be located at a remote end of the device housing the antenna 256 of T-TRP 170, and may be coupled to the device housing the antenna 256 via a communication link (not shown) sometimes referred to as a fronthaul (e.g., a common public radio interface (CPRI)). Therefore, in some embodiments, the term "T-TRP 170" may also refer to network-side modules that perform processing operations such as ED 110 location determination, resource allocation (scheduling), message generation, and encoding / decoding, which are not necessarily part of the device housing the antenna 256 of T-TRP 170. These modules may also be coupled to other T-TRPs. In some embodiments, T-TRP 170 may actually be multiple T-TRPs operating together to serve ED 110, for example, through cooperative multicast transmission.

[0093] T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is shown in the figure. Alternatively, one, some, or all of the antennas 256 may be a panel. The transmitter 252 and receiver 254 may be integrated as a transceiver. T-TRP 170 also includes a processor 260 for performing operations including preparing transmissions for downlink transmission to ED 110, processing uplink transmissions received from ED 110, preparing transmissions for backhaul transmission to NT-TRP 172, and processing transmissions received from NT-TRP 172 via backhaul. Processing operations related to preparing transmissions for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., multiple-input multiple-output (MIMO) precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to transmissions received in the uplink or via backhaul may include receive beamforming, demodulating received symbols, and decoding received symbols. Processor 260 may also perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as generating the contents of a synchronization signal block (SSB), generating system information, etc. In some embodiments, processor 260 also generates a beam direction indication (e.g., BAI), which scheduler 253 may schedule for transmission. Processor 260 performs other network-side processing operations described herein, such as determining the location of ED 110, determining the deployment location of NT-TRP 172, etc. In some embodiments, processor 260 may generate signaling to configure one or more parameters of ED 110 and / or one or more parameters of NT-TRP 172, etc. Any signaling generated by processor 260 is transmitted by transmitter 252. It should be noted that "signaling" as used herein may also be referred to as control signaling. Dynamic signaling can be transmitted in control channels such as the physical downlink control channel (PDCCH), while static or semi-static higher-layer signaling can be included in data packets transmitted in data channels such as the physical downlink shared channel (PDSCH).

[0094] Scheduler 253 may be coupled to processor 260. Scheduler 253 may be included in T-TRP 170 or operate separately from T-TRP 170. Scheduler 253 may schedule uplink, downlink, and / or backlink transmissions, including issuing scheduling authorizations and / or configuring schedule-free (“configuration authorization”) resources. T-TRP 170 also includes memory 258 for storing information and data. Memory 258 stores instructions and data used, generated, or acquired by T-TRP 170. For example, memory 258 may store software instructions or modules for implementing some or all of the functions and / or embodiments described herein and executed by processor 260.

[0095] Although not shown, processor 260 may be part of transmitter 252 and / or receiver 254. Furthermore, although not shown, processor 260 may implement scheduler 253. Although not shown, memory 258 may be part of processor 260.

[0096] The processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can each be implemented by the same or different processors for executing instructions stored in memory (e.g., memory 258). Alternatively, some or all of the processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 can be implemented using dedicated circuitry such as FPGA, GPU, or ASIC.

[0097] It should be noted that the NT-TRP 172 is shown as an example of a drone only. The NT-TRP 172 can be implemented in any suitable non-terrestrial form, such as an aerial platform, a satellite, an aerial platform as an international mobile telecommunications base station, and an unmanned aerial vehicle, which will be discussed below. Furthermore, in some implementations, the NT-TRP 172 may have other names, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is shown in the figure. Alternatively, one, some, or all of the antennas may be panels. The transmitter 272 and receiver 274 may be integrated as a transceiver. NT-TRP 172 also includes a processor 276 for performing operations, including operations related to: preparing a transmission for downlink transmission to ED 110, processing an uplink transmission received from ED 110, preparing a transmission for backhaul transmission to T-TRP 170, and processing a transmission received from T-TRP 170 via backhaul. Processing operations related to preparing a transmission for downlink or backhaul transmission may include operations such as encoding, modulation, precoding (e.g., MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing transmissions received in the uplink or via backhaul may include operations such as receive beamforming, demodulating the received signal, and decoding the received symbols. In some embodiments, processor 276 performs transmit beamforming and / or receive beamforming based on beam direction information (e.g., BAI) received from T-TRP 170. In some embodiments, processor 276 may generate signaling, such as configuring one or more parameters of ED 110. In some embodiments, the NT-TRP 172 implements physical layer processing but not higher-level functions such as medium access control (MAC) or radio link control (RLC) layer functions. Since this is only an example, in general, the NT-TRP 172 can implement higher-level functions in addition to physical layer processing.

[0098] The NT-TRP 172 also includes a memory 278 for storing information and data. Although not shown, a processor 276 may be part of the transmitter 272 and / or the receiver 274. Although not shown, the memory 278 may be part of the processor 276.

[0099] The processing components of processor 276, transmitter 272, and receiver 274 can all be implemented by the same or different processors for executing instructions stored in memory (e.g., memory 278). Alternatively, some or all of the processing components of processor 276, transmitter 272, and receiver 274 can be implemented using dedicated circuitry such as a programmable FPGA, GPU, CPU, or ASIC. In some embodiments, NT-TRP 172 can actually be multiple NT-TRPs operating together, for example, via cooperative multicast service ED 110.

[0100] T-TRP 170, NT-TRP 172 and / or ED 110 may include other components, but these components have been omitted for clarity.

[0101] according to Figure 4 One or more steps of the methods in the embodiments provided herein may be performed by the corresponding units or modules. Figure 4 The diagram illustrates units or modules within a device (e.g., ED 110, T-TRP 170, or NT-TRP 172). For example, signals may be transmitted by a transmitting unit or transmitting module. Signals may be received by a receiving unit or receiving module. Signals may be processed by a processing unit or processing module. Other steps may be performed by an artificial intelligence (AI) module or a machine learning (ML) module. The corresponding units or modules may be implemented using hardware, one or more components or devices executing software, or a combination thereof. For example, one or more of these units or modules may be integrated circuits, such as a programmable FPGA, GPU, CPU, or ASIC. It should be understood that if these modules are implemented using software executed by a processor, etc., then these modules may be retrieved by the processor, wholly or partially, individually or collectively, for processing, in single or multiple instances, and these modules themselves may include instructions for further deployment and instantiation.

[0102] Further details regarding ED 110, T-TRP 170, and NT-TRP 172 are known to those skilled in the art. Therefore, these details are omitted herein.

[0103] After a broad discussion of communication above, the following text will turn its attention to specific exemplary embodiments.

[0104] Channel coding aims to address the uncertainties that arise when a signal passes through a noisy channel. The channel conditions used in this paper can refer to any of the following: channel gain / fading, additive noise, and interference. Channel-independent coding design means that code construction, encoding, and decoding are independent of specific channel conditions. Channel-dependent coding design means that any (or more) of the code construction, encoding, or decoding scheme is designed or implemented based on specific channel conditions.

[0105] LDPC codes are defined by their parity check matrix (usually denoted by H). Each row of H represents a parity check function, where the position of the value "1" corresponds to the code bit participating in that parity check function. For example, the row [1,0,0,1,0,1] means that the exclusive OR (XOR) result of the 1st, 4th, and 6th code bits must be 0 to pass the parity check function.

[0106] The generation of codeword c requires passing all parity checks defined in the row definition of H, or H·c = 0.

[0107] The parity check matrix contains far more 0s than 1s, hence its "low density." In 5G, a quasi-cyclic LDPC code design based on the original model graph is used, where the generation of the parity check matrix involves two steps:

[0108] 1. Read the predefined original model matrix ( Figure 5 An exemplary original model matrix is ​​shown.

[0109] 2. Replace each "1" in the original model matrix with a cyclic shift identity matrix (or simply a cyclic matrix), and apply a predefined shift value to the position of each "1". This step is called "lifting". The matrix obtained after lifting is the final parity check matrix of the LDPC code.

[0110] Currently, this type of LDPC is simple in design and suitable for various coding rates and code lengths. For example:

[0111] For higher coding rates, fewer primitive lines can be used; for lower coding rates, more primitive lines can be used (i.e., more parity checks).

[0112] For longer codes, a larger cyclic matrix can be used to improve the protograph; for shorter codes, a smaller cyclic matrix is ​​used to improve the protograph.

[0113] Therefore, LDPC codes are highly flexible and well-suited for wireless communication applications. Through MCS adaptation, LDPC codes can adapt to dynamic wireless channel conditions between data packets. However, as mentioned above, current LDPC designs are still channel-independent, meaning they cannot adapt to any dynamic channel changes within the data packet (codeword).

[0114] The basic decoding algorithm of polar codes is successive cancellation (SC), and all frozen bits and information bits are decoded bit by bit in sequence according to this algorithm. Before decoding the current bit, the previous bits are always decoded first.

[0115] Successive cancellation list (SCL) is an enhanced polar code decoding algorithm, in which multiple (L) SC decoding instances are executed. Each instance is called a "decoding path". When decoding each binary bit, two branches of "0" and "1" are extended to each path, creating 2L paths. Then all 2L paths are compared, and the most likely L paths are retained, and the least likely L paths are discarded (or pruned). When decoding each information bit, path extension and pruning operations are performed until all information bits are decoded. Finally, the most likely path is selected as the decoding output.

[0116] The working principle of CRC-aided successive cancellation list (CA-SCL) decoding is similar to that of SCL, except that in the last step, the most likely path passing the CRC check is selected as the decoding output.

[0117] The working principle of parity-check successive cancellation list (PC-SCL) decoding is also similar to that of SCL, except that when decoding the parity-check (PC) bits, the parity-check value of the associated previous bits is used as the bit decision result. PC bits are the bits other than the frozen bits and information bits.

[0118] Polar codes are linear block codes. For a polar code with length N, its generating matrix is G N , and its encoding process is where is the binary input vector, is the binary code vector. The N×N binary generating matrix where is the polarization kernel matrix, is the Kronecker product, and n = log2N.

[0119] When K information bits are encoded into N code bits and K < N, the coding rate R = K / N < 1. This means that only A part of it is used to carry information bits. The remaining bits are called frozen bits. Among them, the information bit set (or information set) can be represented by I, the frozen bit set (or frozen set) can be represented by F, and sometimes there is also an additional set of parity-check (PC) bits, represented by P. The frozen bits are known and are usually set to all zeros before decoding, so they do not carry any information. The PC bits are the parity-check bits of a subset of information bits. Therefore, once the relevant information bits are decoded, they are known. The decoding objective of a polar code is to recover all the information bits.

[0120] The code length M may or may not always be a power of 2. In this case, M < N. In practical applications, the number of transmitted code bits is reduced from N to M by puncturing or shortening. For convenience, in this article, N is referred to as the mother code length, and M is referred to as the code length. Specifically, the punctured bits are the non-transmitted bits unknown to the decoder (i.e., the non-transmitted bits in the mother code length), and the shortened bits are the non-transmitted bits known to the decoder (usually set to all zeros).

[0121] Figure 6 is the trellis diagram of a polar code example with N = 8 and K = 4. Each "butterfly" structure in the figure is a polarization. An example of a butterfly structure is shown on the right side of Figure 6 where, In the example shown, the non-shaded circles on the left represent the information set I = {u4, u6, u7, u8}, and the shaded circles represent the frozen set F = {u1, u2, u3, u5}.

[0122] Figure 6 the input vector u on the left in Figure 6 and the code vector x on the right in

[0123] both include multiple bit positions. The bit positions in the input vector are indexed by the corresponding bit indices, and the bit values are placed on these bit indices or bit positions or at these bit indices or bit positions for encoding. These bit indices or bit positions are sometimes also referred to as bit channels or sub-channels. The placement of bit values on bit indices described in this article can also be expressed in other ways. For example: placing a bit or bit value on a bit index, bit position, bit channel or sub-channel or at a bit index, bit position, bit channel or sub-channel; or assigning a bit value or bit to a bit index, bit position, bit channel or sub-channel. Other terms can be used to represent how to provide bit values or bits as the input for encoding. This invention mainly uses the expression "placing a bit value on a bit index", but other equivalent terms can also be used to convey the same concept.

[0123] Thus, polar codes can be considered to provide or include bit indices, bit positions, bit channels, or sub-channels for bit values. These bit indices, bit positions, bit channels, or sub-channels are not necessarily only used for the bits to be encoded. For example, during decoding, u vector elements u1…u are also referenced. N Therefore, the decoded bit values ​​can also be associated with bit index, bit position, bit channel, or sub-channel.

[0124] exist Figure 6 To the right of the code vector x, the code vector x also includes multiple elements located at bit positions or bit indices. The bit value at the i-th bit index in the input vector u will have some influence on multiple code bits in the code vector x, but the bit value at the i-th bit index in the input vector u is the main influencing factor on the corresponding code bit value at the i-th bit index in the code vector x. In this sense, for polar codes, the bit index or bit position of the input vector can be considered to correspond to, be associated with, or be related to the bit index or bit position of the code vector. This is a characteristic of polar codes, while for other types of codes, the correspondence, association, or correlation between input bits and code bits may be different.

[0125] Regarding encoding, the encoding process can be represented in various ways. For example, encoding can be described as: encoding bits to obtain encoded bits or generating encoded bits. The above encoding process... For example, it can be described as: generating or otherwise acquiring an encoded input (input vector u in this example) to acquire or generate multiple encoded bits (code vector x in this example), wherein the encoded input includes bits or bit values ​​for encoding.

[0126] From an encoding perspective, the bit values ​​of each element in the input vector u can be referred to, for example, as the values ​​to be encoded or bits, or as the values ​​or bits used for encoding. A block of bits or bit values ​​used for encoding is sometimes also called a coding block. The bit values ​​of each element in the code vector x can be referred to as coded bits, encoded bits, or code bits, and a block of such bits can be referred to, for example, as a codeword.

[0127] From a decoding perspective, decoding can be described as: decoding encoded bits, codewords, or codes; or decoding, obtaining, or recovering (encoded) bits or bit values ​​from encoded bits, codewords, or codes. In the context of decoding, the bit values ​​of each element in vector u can be referred to as decoded or recovered bits or bit values.

[0128] Polar codes are typically decoded using successive cancellation (SC) and its variants. Currently, SC-based polar decoders follow a sequential operation when performing successive cancellation. If the positions of the information bits, frozen bits, and parity check (PC) bits are determined by… If this is the case, then the decoding order is u1, u2, ..., u N .

[0129] Figure 7 This is a lattice diagram showing the distribution of the log-likelihood ratio (LLR) in polar code decoding. Under sequential SC decoding, the LLR distribution (u1, u2, ..., u...) is... N ()( Figure 7 The leftmost column of the grid chart can be based on the distribution of LLR (x1, x2, ..., x). N ()( Figure 7 The rightmost column of the grid diagram is derived from this.

[0130] Therefore, polar codes are channel-dependent codes. Arikan Erdal, in his paper "Channel Polarization: A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels" published in IEEE Transactions on Information Theory, Vol. 55, No. 7 (2009): 3051-3073, explicitly states: "Polar codes are channel-specific designs: a polar code designed for one channel may not be suitable for another." However, this channel-dependent polar code design is static. This means that once a polar code is constructed, a specific, fixed channel implementation is assumed. The receiver cannot adapt to any constantly changing channel conditions.

[0131] Channel-independent channel coding design has two main drawbacks:

[0132] When channel conditions are constantly changing and channel estimation is inaccurate, channel-independent channel coding design makes the transceiver unable to adapt to real channel conditions.

[0133] Channel-independent channel coding has a finite coding structure.

[0134] The technical problem considered in this paper involves how to construct, encode, and decode channel-dependent error-correcting codes. Obtaining channel-dependent codes may require a new coding structure that allows the codes to provide multiple decoding schemes for different channel conditions, even after code construction and encoding.

[0135] One observation about channel coding is the relationship between coding rate and capacity. As code length approaches infinity, if the coding rate exceeds the capacity, error-free communication becomes virtually impossible. In finite-length coding, even if the coding rate exceeds the capacity, correct decoding is still possible, but the bit error rate will increase significantly.

[0136] Codewords can be divided into multiple shorter (sub)blocks, each with the following attributes:

[0137] The corresponding block capacity: the total bit channel capacity of the corresponding code bits in the block, which depends on the channel and the code length;

[0138] The corresponding block coding rate: the ratio of the unknown number of bits to the block length.

[0139] In some embodiments, the corresponding block coding rate (also known as the block-level coding rate) is not fixed. The block coding rate or block-level coding rate of a block may depend on the decoding order, etc. There may be a maximum coding rate and / or a minimum coding rate, but apart from that, the block coding rate or block-level coding rate does not need to be fixed.

[0140] A block is called a "sufficient block" when its size is greater than its block coding rate; a block is called a "insufficient block" when its size is less than its block coding rate. To achieve good error correction performance, the rule of thumb or default decoding order is to decode sufficient blocks first, then decode insufficient blocks.

[0141] Figure 8 This is a diagram illustrating the decoding of a block with sufficient capacity before decoding a block with insufficient capacity. Figure 8 The arrows marked "help" are intended to describe how decoding one block of a codeword can help in decoding another block of the codeword, as detailed in this article.

[0142] Figure 9 The block diagrams compare channel-independent codes and channel-dependent codes, outlining the proposed channel-dependent coding structure consistent with this invention.

[0143] Figure 9 Several features of the mid-channel correlation code are noteworthy, as they represent key points in some embodiments of the present invention. These features include:

[0144] Flexible decoding order Decoders have multiple approaches to determining which block to decode first and the subsequent decoding order. Decoding can be performed block-by-block or by switching between different blocks ("jumping"). Flexible decoding orders can also be called, or alternatively, configurable decoding orders, such as... Figure 9 As shown, in Figure 9 The inner arrows between blocks are shown in the diagram.

[0145] Variable coding rate blocks Each block can have a variable coding rate when observed in different subspaces, depending on the decoding of other blocks (as detailed elsewhere in this paper). The length of any variable coding rate block remains constant, but the coding rate will change as other blocks are decoded.

[0146] Block coupling Multiple blocks, or even all blocks (e.g.) Figure 9 (As indicated by the arrow in the middle outer layer) is coupled to another block. In the example shown, Figure 9 Each block on the right is coupled to another block, but other embodiments may also include one or more blocks that are not coupled to any other blocks. Block coupling is used to enable the flow of mutual information between blocks during decoding. There are various ways to couple blocks together, and illustrative examples are provided elsewhere in this document.

[0147] Transmission or output order In the case of variable-length blocks, code bits can be transmitted in a specific order or otherwise output to provide balanced performance across different lengths. For example, when multiple blocks exist, code bits corresponding to the block with the most available capacity can be transmitted or output preferentially. The transmission or output order of the encoder or encoding device can be known to the decoder or decoding device, and under static channel conditions used to determine the transmission or output order, the decoding order can be the same as the transmission or output order. However, in some embodiments, decoding can still take advantage of dynamic channel conditions by decoding blocks in a different decoding order, or otherwise relate to dynamic channel conditions, wherein the decoding order differs from the order in which the block is transmitted or otherwise output (and received or otherwise acquired or provided for decoding).

[0148] These features are not necessarily associated with any particular code or code type (e.g., LDPC codes or polar codes), but can be applied to or alternatively applied to a variety of codes, including any of the following examples: algebraic codes, convolutional codes, polar codes, and probabilistic codes (e.g., Turbo codes and LDPC codes).

[0149] Regarding the flexible decoding order, in the embodiments disclosed herein, the decoding order of multiple blocks and the code bits within each block is not predetermined, but can be adapted to changing channel conditions.

[0150] For example, the decoding order can be determined based on the block-level coding rate to capacity ratio. In this context, the coding rate can be defined as the ratio of the number of unknown bits to the block length, and can be considered as a form of coding rate. This coding rate changes during the decoding process as more and more code bits in a block are decoded. In this context, capacity can be the total capacity of the corresponding code bits in the block (e.g., bit channel capacity). As other blocks are decoded, mutual information about that block flows in, and therefore the block-level capacity increases accordingly.

[0151] For example, in some embodiments, based on the block-level coding rate and capacity ratio defined above, the decoding order is as follows:

[0152] Decode the block with the smallest coding rate to capacity ratio;

[0153] During decoding, the coding rate and capacity ratio of each block are updated (because they change at least in the case of coupled blocks).

[0154] The decoding order can be represented in any of a variety of ways, including the following four exemplary ways of representing the decoding order:

[0155] A sequence including or consisting of indices of variable nodes;

[0156] A sequence including or consisting of the indices of the check nodes;

[0157] A sequence consisting of or composed of the indices of blocks;

[0158] A sequence of indices, including or consisting of the indices of switching points or "jumps" between two blocks, where decoding operations switch between blocks.

[0159] Check nodes and variable nodes can be defined in the factor graph representation of the code. Figure 10 This is an example factor graph, which includes two check nodes on the left and three variable nodes on the right.

[0160] Regarding variable coding rate blocks, in some embodiments, the coding rate of these blocks is variable to adapt to changing channel conditions. Specifically, although codeword blocks are constructed and encoded with a fixed length, different subspaces of the codespace can have different coding rates. By definition, a subcode is a subset of codewords in a parent code.

[0161] Figure 11 An example of a nested code structure is shown. In a nested structure of codeword blocks, a low-rate code is a sub-code of a high-rate code of the same length. In practical applications, BCH codes, polar codes, and LDPC codes can all be constructed as variable-rate blocks using nested blocks.

[0162] To construct variable coding rate (VCR) codes, specific information bit mapping methods can be designed and used for encoding and decoding. For example, to facilitate the flow of mutual information between different blocks, some information bits can be shared among multiple blocks. In a VCR code, there may be high, medium, and low coding rate subcodes, each corresponding to a set of information bits. The information bits of the low coding rate subcode are a subset of those of the high coding rate subcode. The information bits of the low coding rate subcode can be unique to that block because it is more likely to be correctly decoded without relying on mutual information generated by decoding other blocks, while the additional information bits of the higher coding rate subcode can be shared by multiple blocks. This example illustrates a possible general rule: as the coding rate of a subcode (block) increases, newly added information bits in that block (i.e., bits not in lower coding rate blocks) will be shared by more blocks.

[0163] Figure 12 An example of mapping information bits according to this mapping method is shown.

[0164] The above-described exemplary information bit mapping method can be applied to a variety of different channel code types, such as BCH codes, polar codes, and LDPC codes.

[0165] There are multiple ways to implement block coupling. Some implementations may have the same result or essence, but they may manifest differently.

[0166] In a general case, any code can be represented by a factor graph, which consists of variable nodes and check nodes.

[0167] Variable nodes can be divided into three types:

[0168] Information variable nodes represent bits used for encoding; they can also be called information bits, system bits, or payload bits.

[0169] Transmit or output variable nodes, representing code bits. Note that some codes include system bits that are both information bits and bits that are transmitted or output.

[0170] Hidden variable nodes represent intermediate or auxiliary bits in the encoding / decoding process. These bits are not transmitted or output, nor are they information bits.

[0171] Figure 13 This is another exemplary factor graph, which includes nodes for all three types of variables.

[0172] In some embodiments, coupling can occur between two variable nodes v i v j Or two variable node sets {v i1 ,v i2,…} and {v j1 ,v j2 Between , ...}. Examples of coupling include the following two categories:

[0173] Coupling of the same value: v i =v j or {v i1 ,v i2 ,…}={v j1 ,v j2 ,…};

[0174] Mapping function coupling: v i =f(v j ) or (v i1 ,v i2 ,…)=f(v j1 ,v j2 ,…), where the function f() is predefined and both the encoder and decoder are known.

[0175] Using variable nodes as a coupling method, examples of coupling include the following methods and combinations thereof:

[0176] Couple information variable nodes with information variable nodes;

[0177] Couple the information variable node with the sent or output variable node;

[0178] Couple information variable nodes with hidden variable nodes;

[0179] Couple the sent or output variable node to the sent or output variable node;

[0180] Couple the sent or output variable nodes with the hidden variable nodes;

[0181] Couple hidden variable nodes with hidden variable nodes.

[0182] Using verification nodes as a coupling method, examples of coupling include the following methods and combinations thereof:

[0183] degree d c A check node with a value of 2 connects two blocks where the two connected variable nodes have the same value.

[0184] degree d c A check node with a value of >2 connects two blocks;

[0185] degree d c A check node with a value of >2 has more than two blocks connected.

[0186] Figure 14 An example of check node coupling between blocks with variable coding rates is shown. Figure 14Check node 1402 is an example of a check node connecting two blocks 1412 and 1414 (block 1412 has one variable node, and block 1414 has two variable nodes). Check node 1404 is an example of a check node connecting multiple blocks (e.g., 1412, 1414, and 1416) (each block has one variable node). Check node 1406 is an example of a check node connecting two blocks 1412 and 1416 (each block has one variable node), and may be the degree d. c =2 is a special check node that connects two blocks where the two connected variable nodes have the same value.

[0187] These coupling examples are not mutually exclusive and can be used in combination in some embodiments.

[0188] Regarding the order of transmission or output, it can be represented by an ordered sequence in a variety of ways, including the following examples:

[0189] Use bits (or variable nodes) to index sequences;

[0190] Use block index sequences;

[0191] A sequence of block indexes is used, where a block index may appear multiple times (hinting or indicating switching or jumping between blocks), and combined with a subset or multiple bit indices to indicate where to jump out of one block and where to enter another.

[0192] Ordered sequences can be designed to minimize the difference between overall block-level coding rate and capacity, while still maintaining local decodeability.

[0193] Based on the general features and processes illustrated in this article, there are a large number of code types that can be decoded in a channel-dependent manner.

[0194] The embodiments disclosed herein may integrate one or more aspects mentioned in the aforementioned related applications. For example, some embodiments may integrate features related to non-sequential decoding of polar codes (to provide or support one or more of features such as flexible decoding order, variable coding rate blocks, or transmission / output order in the case of polar codes), or involve methods for placing input bit values ​​on multiple bit indices (to support features such as variable coding rate blocks and / or block coupling).

[0195] In this invention, embodiments are described primarily using the method of transmitting encoded bits as an example. Output encoded bits may include transmitted encoded bits, or output encoded bits may also be transmitted; however, it should be understood that not all embodiments necessarily involve transmitting encoded bits. Features disclosed herein in the context of transmitting encoded bits (e.g., from a transmitter) can also be more broadly applied to output encoded bits (e.g., from a logical-to-physical interface).

[0196] Similarly, this article discusses examples of polar codes in detail, but the embodiments are not limited to polar codes or any other type of code. The extended BCH (eBCH) code will be described in detail below.

[0197] When considering polar codes, bit index selection and bit value placement may involve techniques called tagging. Bit index selection and bit value placement may depend on the number of input bits, also known as the information length K. Bit value placement (including tagging in some embodiments) is described in more detail herein, at least as follows.

[0198] Encoding can be used to generate codewords. For example, in some embodiments, the values ​​of K information bits are placed on information bit indices, each using K tags. The bit value of any input bit can be placed on multiple information bit indices by assigning the same tag to multiple bit indices. Therefore, an input bit can actually be placed on multiple bit indices. In tag-based embodiments, multiple bit indices are associated with the same tag. This can be viewed as implicitly establishing a check function, where the bit value at a first bit index can be checked by the same bit value that is also placed on one or more other bit indices. This method of placing the same input bit value on two or more bit indices makes it possible that once a bit value is decoded at any bit index, the decoded input bit value is known from all of these bit indices.

[0199] For example, assuming the code length N = 32, the number of information bits K = 16, and the bit indices of the information set are selected based on reliability, the K most reliable bit indices in {1…N} are {8,12,14,15,16,20,22,23,24,26,27,28,29,30,31,32}. Then the information set is:

[0200] I={8,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32}.

[0201] For bit value placement, in one embodiment, the label used for the 32-bit index is as follows:

[0202] l=[0,0,0,0,0,0,0,5,0,0,0,4,0,3,2,1,1,2,3,6,4,7,8,12,5,9,10,13,11,14,15,16].

[0203] Before encoding, K = 16 input bits [a1, a2…a2] 16In this example, the values ​​of [a1, a2, a3, a4, a5] are assigned to tags 1, 2, ..., 16, respectively. Specifically, according to the tags mentioned above, the values ​​of the bits [a1, a2, a3, a4, a5] corresponding to tags 1, 2, 3, 4, and 5 are placed on two bit indices respectively. The frozen bit index (marked as 0 in the example above) is assigned a value known to the decoder, such as 0. Using tags to place bit values ​​is just one exemplary method of how bit values ​​are placed on bit indices. The invention is not limited to this bit tagging method.

[0204] The information vector after placing the information bits and frozen bit values ​​at the bit index is shown below:

[0205] u=[0,0,0,0,0,0,0,a5,0,0,0,a4,0,a3,a2,a1,a1,a2,a3,a6,a4,a7,a8,a 12 a5, a9, a 10 ,a 13 ,a 11 ,a 14 ,a 15 ,a 16 ].

[0206] In this example, the information vector u is multiplied by the polarization matrix G. 32 To perform encoding, thereby obtaining the code vector x = u·G 32 .

[0207] There are various ways to implement or support placing bit values ​​on bit indices, which may or may not involve bit tags. Figure 15A This is a schematic diagram illustrating the placement of bit values ​​on bit indices according to one embodiment. The placement of bit values ​​may involve or be based on a mapping from bit indices (or bit positions) to bit values, which may also be referred to as a mapping from bit values ​​to bit indices or bit positions, or a mapping between bit indices and bit values. Such a mapping can be a one-to-one mapping or a many-to-one mapping.

[0208] A one-to-one mapping can be defined or represented by i→p, where i is the bit index of the bit position in the input vector (e.g., ...). Figure 15A (as shown); p is a sequence of bit values ​​(e.g.) Figure 15A The bit value index in the input sequence shown. For example, if bit u in the input vector iBy mapping a bit value to a one-to-one value, that bit could be a frozen bit (when there is only one frozen bit) or an information bit (for input bit values ​​that do not need to be placed on any other bit indices). In this sense, the information bit in a one-to-one mapping is an information bit that is not checked against any other information bits in the input vector. This type of mapping can be called a direct mapping between bit values ​​and bit indices because it does not use labels. Figure 15A The mapping N→K in the example is a one-to-one direct mapping.

[0209] A many-to-one mapping can be defined or represented by {i1,i2,i3…}→p, where i1,i2,i3… are bit indices of bit positions; and p is the index of the bit value to which these bit indices are mapped. For example, the mapping {i,j,k}→p can be related to a function or relation u of the check type. i =u j =u k Consistent. In {i,j,k}, if bit u j First decode, then the other bits u i and u k will use u j The decoded value, in this sense, u i and u k These are information bits, but can also be considered as a form of check bit. A many-to-one mapping from bit index to bit value (or a one-to-many mapping from bit value to bit index) is a direct mapping, meaning there is a direct relationship between a bit value and multiple bit indices, and vice versa. Figure 15A The mapping of input bit values ​​a1 and a2 in the example is an example of such a one-to-many or many-to-one direct mapping.

[0210] exist Figure 15A In the input sequence, the bit values ​​include the input bit value (a i This input bit sequence represents the input block used for channel coding, and the bit values ​​in this bit sequence are represented by a1, a2, ..., a K This is represented as K, where K is the number of bits to be encoded. The bit values ​​in the input bit sequence and the predetermined bit values ​​for freezing bits (0 in the illustrated example) will be placed in the binary input vector u1, u2, ..., u N The bit index is used, and polar coding is applied based on it, according to... Figure 15A The bit index / value mapping is shown on the right. The arrows between the input sequence bit values ​​and the input vector bit values ​​indicate how the bit values ​​are placed, i.e., the input vector bit values ​​are set to the input sequence bit values. Figure 15A The image also shows the placement of the predetermined bit value 0 for the frozen bits to ensure integrity.

[0211] Figure 15AThe example illustrates the pre-frozen bit value 0 and the input bit values ​​a1, a2, ..., a K How to place them in the binary input vector u1, u2, ..., u N On the bit index. Using the notation introduced above: u i =a p The premise is that i→p is suitable for one-to-one mapping; or {…i…}→p is suitable for many-to-one mapping.

[0212] The placement of the predetermined value 0 for all frozen bits and the input bit values ​​of the input bit sequence {1,2…K} can be described by a mapping sequence. Let i∈{1,2…N} represent the bit position index used for encoding; l∈{0,1…K} represent the predetermined value 0 for frozen bits and the input bit values ​​a1,a2,…,a… K The bit index; then: a one-to-one mapping i→p can be represented as l(u i The many-to-one mapping {i,j,k}→p can be represented as l(u) = p; i )=l(u j )=l(u k ) = p; the mapping sequence can be represented as l(u1), l(u2), ..., l(u N ), where N is the mother code length or the total number of bit indices. Figure 15A In the example, the mapping sequence can be described as {0,0,0,...,1,2,...,1,2,3,...,K}.

[0213] In some embodiments, bit value placement may also involve tags. Similar to bit index / bit value mapping, the mapping from bit index (or bit position) to tag (also referred to as the mapping from tag to bit index or bit position, or the mapping between bit index or bit position and tag) can also be a one-to-one mapping or a many-to-one mapping.

[0214] A one-to-one mapping using labels can be defined or represented by i→p, where i is the index of the bit position and p is the index of the label. For example, bit u in the input vector i By mapping a bit to a tag in a one-to-one manner, the bit may be a frozen bit (when there is only one frozen bit), or an information bit that does not share a tag and is not verified by other information bits in some sense.

[0215] A many-to-one mapping using tags can be defined or represented by {i1,i2,i3…}→p, where i1,i2,i3… are indices of the bit positions mentioned above; and p is the index of the tag to which these bit indices are mapped. For example, the mapping {i,j,k}→p can be related to a function or relation u of the check type. i =u j =uk Consistent. In {i,j,k}, if bit u j First decode, then the other bits u i and u k will use u j The decoded value, in this sense, u i and u k It is an information bit, but it can also be regarded as a kind of check bit.

[0216] In some embodiments, many-to-one mapping (including direct mapping or mapping using labels) can be used for block coupling, that is, placing the same bit value on multiple bit indices that are associated with code bits in different blocks of codewords.

[0217] Figure 15B This is a block diagram illustrating an exemplary bit index to tag mapping. Figure 15B In this diagram, the mapping from bit index to label is represented with the bit index on the left and the label index on the right. The top mapping is a one-to-one mapping, while the bottom mapping is a many-to-one mapping. Label mapping is optional; bit indices can also be directly mapped to bit values ​​or their indices without using labels. In some embodiments, using label mapping instead of direct mapping may be a preferred approach. For example, in the textual description of a communication standard or specification, the bit values ​​of input bits are often unknown, and labels can be used to represent these input bit values. Therefore, by using labels as a reference form for bit values, bit mapping and bit value placement may be easier to describe.

[0218] Figure 15C This is a block diagram illustrating the placement of bit values ​​on bit indices using bit tags, according to an embodiment. Figure 15C In the input sequence, the bit values ​​include the input data bit values ​​(a i It also indicates the predetermined bit value of 0 to ensure integrity. Figure 15CThe diagram also illustrates the bit values ​​of a tag sequence, where each element in the sequence is a tag placed at a bit position or a tag assigned to a bit in the input vector for encoding. Arrows between bit values ​​and tag sequence bit values ​​indicate the assignment of tags and the setting or allocation of tags by bit values. Tags include tags that are uniquely assigned and thus associated with bit positions in the input sequence, as well as tags for frozen bits included in the example shown. These tags are set to the bit values ​​of the input bits when encoding the sequence of input bits. This can also be equivalently described as tags being assigned to input bits or input sequence bits (or their values), or input bits or input sequence bits (or their values) being assigned tags. There is a unique relationship between each of the K input bits and its assigned tag; that is, each input bit has only one uniquely assigned tag, and no tag is assigned to any other input bit. This can be viewed as another form of one-to-one mapping, namely a one-to-one mapping between input bit positions (or bits) in the input bit sequence and their corresponding tags.

[0219] Figure 15C The input bit sequence in the code represents the input block used for channel coding, and the bit values ​​in this bit sequence are denoted by a1, a2, ..., a K The tag sequence is represented as l0, l1, l2, ..., l, where K is the number of bits to be encoded. K This indicates that each label l1, l2, ..., l K This is associated with the position of the input bit to be encoded and the input bit itself, or, in the case of being labeled l0, with a predefined frozen bit value. The predetermined bit value and the bit values ​​in the input bit sequence are placed in the binary input vector u1, u2, ..., u... N The bit index is used, and polar coding is applied based on it, according to... Figure 15C The right side shows the tags and bit index / tag mapping. The arrows between the tag sequence bit values ​​and the input vector bit values ​​indicate the process of assigning tags to the bit positions of the input vector, and setting the input vector bit values ​​to predetermined bit values ​​or input sequence bit values ​​according to the placement of the bit values ​​on the bit index.

[0220] exist Figure 15A and Figure 15C The bit placement examples shown (with and without labels, respectively) pre-freeze bit value 0 and input bit values ​​a1, a2, ..., a K All are placed at bit indices. When tags are used, the bit values ​​are assigned as the tag sequence I0, l1, l2, ..., l K The value of , where I0 = 0 (or any predefined frozen bit value), and l p =a p(Suitable for p = 1, 2…K). Then, these bit values ​​0, a1, a2, …, a K (Optionally, the bit values ​​already assigned as labels) are placed in the binary input vector u1, u2, ..., u N On the bit index. Using the notation introduced above, u i =a p (or l in examples where labels are used) p The premise is that i→p is suitable for one-to-one mapping; or {…i…}→p is suitable for many-to-one mapping.

[0221] The mapping sequence describing the placement of bit values ​​can include bit value indices as described above, and may also include labels in embodiments using labels. A one-to-one mapping i→p can be represented as l(u i A many-to-one mapping {i,j,k}→p can be represented as l(u) = p. i )=l(u j )=l(u k ) = p, and the mapping sequence can be represented as l(u1), l(u2), ..., l(u N ), where N is the mother code length or the total number of bit indices. Figure 15C In the example, the mapping sequence can be described as {l0,l0,l0,...,l1,l2,...,l1,l2,l3,...,l K}

[0222] Whether the mapping sequence is represented or defined in the form of bit value indexes or tags, it can be defined in a communication standard or specification, or generated according to a process specified in such a standard or specification. Generating such mapping sequences online is one possible approach.

[0223] Figure 15A , Figure 15B and Figure 15C The above description provides examples of how bit values ​​can be placed at one or more bit indices. The embodiments disclosed herein do not depend on any particular bit value placement method. For example, embodiments may, but do not necessarily, involve bit tags.

[0224] The invention also includes embodiments that support non-sequential decoding.

[0225] Polar codes are typically decoded using SC and its variants. Traditionally, all SC-based polar decoders follow the bit order when performing successive elimination. Let... Given an input vector that includes information bits, frozen bits, and possible PC bit indices, the sequential decoding order is u1, u2, ..., u N .

[0226] Before making a hard decision (i.e., 0 or 1) on each information bit and frozen bit (including the PC bit if necessary), the received signals corresponding to the code bits are processed in a "butterfly" structure using the f and g functions. These received signals are often referred to as soft information and are typically expressed in the form of log-likelihood ratio (LLR). Soft information is a non-binary value representing the receiver's confidence or probability that a given bit value is 0 or 1. Figure 16 This is a block diagram of the f function used in polar code decoding. Figure 17 This is a block diagram of the g function used in polar code decoding.

[0227] like Figure 16 As shown, the f function receives two LLR inputs L in1 and L in2 and output LLR L out In the simplified LLR-based algorithm, the function f is defined as follows:

[0228]

[0229] like Figure 17 As shown, the g function receives three inputs, including two LLRs. in1 L in2 And the binary variable b, and output LLR L out In the simplified LLR-based algorithm, the g function is defined as follows:

[0230]

[0231] In the context of SC decoding, it is helpful to consider processing it as a single "butterfly" structure. Figure 18 The block diagram illustrates this process.

[0232] exist Figure 18 In the first step shown on the left, the function f is executed to calculate the LLR of u1, using the two LLRs on the right side of the butterfly structure, represented in the diagram as L'1 = f(L1, L2). If u1 is an information bit, its value is obtained through hard decision: a positive LLR corresponds to 0, and a negative LLR corresponds to 1, which can be equivalently represented as u1 = (1 – sign(L'1)) / 2, where sign(L) is the sign function. Otherwise, if u1 is a frozen bit or a PC bit, its value is known (for frozen bits) or calculated from the previous information bit value (for PC bits). This process applies from u1 to u N All bits.

[0233] exist Figure 18In the second step, as shown in the middle section, the g function is executed to calculate the LLR of u2, using the two LLRs on the right side of the butterfly structure and u1 after hard decision, which is represented in the diagram as L'2 = g(L1, L2, u1). Then, hard decision is performed based on the calculated LLRs to obtain u2. Figure 18 In this context, the hard decision is represented as u2 = (1 – sign(L'2)) / 2. As shown in the figure, the first bit u1 is always decoded before the second bit u2. More generally, each bit is decoded sequentially from u1 to u2. N Decoded sequentially.

[0234] exist Figure 18 In the third step shown on the right, after hard decisions are made on both u1 and u2, bits x1 and x2 can be further recovered, as shown in the figure. And x2 = u2. This step is called the "recoding" step.

[0235] For convenience, binary trees are typically used to simplify the representation of SC decoders or the SC decoding process. Figure 19 The block diagram illustrates this binary tree representation. In a binary tree, Figure 19 In each view, the root node at the top represents the node to the right of the butterfly structure (or lattice), and the leaf nodes at the bottom represent the node to the left of the butterfly structure (or lattice). It can be seen that SC decoding becomes a depth-first binary tree traversal process.

[0236] For illustrative purposes, an example with code length N=4 is provided below. It is believed that this example will enable you to understand the decoding process for all code lengths. Figure 20 This is a block diagram of the binary tree representation of the SC decoding of a polar code of length N=4.

[0237] exist Figure 20 In this context, the "butterfly" structure is represented by "branches" in a binary tree. Each edge represents either a set of functions f or g. The execution order of the f / g functions corresponds precisely to the traversal order of the edges in the binary tree. Figure 20 The dashed arrow indicates this. After all bits on the left side of the butterfly structure have been decoded (hard decision), as shown... Figure 20 As shown by the dotted-line arrow, the bits on the right side of the butterfly structure will be recovered immediately. Based on these rules, SC decoding for any master code length N = 8, 16, 32, 64… can be derived.

[0238] This type of sequential SC decoding order has been used since the introduction of polar codes, and all SC-based decoders (such as SCL, CA-SCL, and PC-SCL) follow this decoding order. SC-based sequential decoding is considered to be the most common decoding type among polar codes.

[0239] However, error propagation can be a problem in SC decoding. When the bit decoding order is fixed, a highly unreliable information bit can become the bottleneck for the entire code block. For example, if the decision on the i-th bit is incorrect, then all subsequent information bits with index j>i have a high probability of also being incorrect. In this case, if it is possible to avoid decoding the i-th bit first, the probability of correctly decoding the j-th bit will be greatly improved; however, traditional sequential SC decoding cannot improve the probability of correctly decoding the j-th bit by skipping the decoding of the i-th bit.

[0240] SC decoding is also inflexible in terms of dynamic channel changes. In some polar code implementations (such as the NR standard), the probability of successful decoding of each bit (sometimes called "reliability") is pre-estimated and specified in the communication standard. In the NR standard, the reliability order is derived by assuming an Additive White Gaussian Noise (AWGN) channel and is represented as an ordered sequence, where bit indices are ordered according to their respective reliability. The K most reliable bit indices are selected as information bit indices to carry the payload data (also referred to as input bits in this paper). However, as discussed in this paper, channel conditions are constantly changing in wireless communication. Therefore, the actual reliability of each bit index may differ from the fixed reliability specified and estimated in the standard. When the actual reliability order of a given bit index (based on actual channel conditions) differs from the reliability order specified in the standard, a standardized polar code implementation may not place all information bits at the bit index with the highest actual reliability. Optimal performance may not be achieved if the same decoding order as in traditional sequential SC decoding is always used.

[0241] Reliability can be viewed as a measure or indication of the probability that a given bit value can be correctly decoded or is decodeable at the decoder. Other related terms or descriptions include capacity, error probability or likelihood, probability or likelihood of error-free decoding, etc. Although this paper primarily uses the term "reliability," the characteristics of reliability described herein can also be applied, or alternatively, to capacity, error probability or likelihood, probability or likelihood of error-free decoding, or other measures or indicators used for ordering or prioritizing bit indices, especially when deciding how to place input bit values ​​for encoding.

[0242] Traditional sequential SC decoding also does not support parallel decoding. This is logical because sequential decoding is inherently serial; the decoding of the current bit can only proceed after all its preceding bits have been decoded.

[0243] Some embodiments disclosed herein relate to a type of SC decoding, but the bit decoding order is arbitrary. For non-sequential decoding, the above traditional bit decision and LLR update rules no longer apply. New rules and new decoding methods for non-sequential decoding orders are disclosed herein.

[0244] The decoding order may have a significant impact on the actual reliability of each bit index. For example, the polarization or reliability defined in current communication standards is fixed and based on and only applicable to traditional sequential decoding. The construction of polarization codes applicable to any bit decoding order can be based on an estimation of the actual reliability of each bit index under the new decoding order. According to the estimation of the actual reliability under the non-sequential decoding order, the selected K most reliable bit indices may be different from the most reliable bit indices selected by traditional polarization codes (including 5G polarization codes) according to the estimated fixed reliability under traditional sequential SC decoding.

[0245] Some embodiments of this document relate to decoding and its decoder. There are multiple possible decoding orders, which are also referred to as decoding schedules. Different rules and operations corresponding to different decoding orders are illustrated herein.

[0246] In the case of having an arbitrary or other flexible decoding order, the decoding order or schedule can be determined based on specific channel conditions.

[0247] Non-sequential decoding can be implemented or deployed in combination with other features disclosed herein.

[0248] Considering the general concept of decoding schedule, the bit value of any bit u1, u2, …, u N in (for ease of reference, denoted as u j ) can be decoded when one or more of its previous bits u i |i < j have not been decoded.

[0249] For a specific bit u j or a continuous set of bits, if a hard decision is not performed due to insufficient capacity of the bit or the continuous set of bits, then the bit or the continuous set of bits can be skipped. In the context of polarization codes, this operation of skipping one or more bits means not processing the butterfly structure associated with the bit or the continuous set of bits. This means that all relevant f functions, g functions, LLR updates, and recoding steps are not performed; or equivalently, in a binary tree structure, if all bits in a subtree are skipped, then the subtree will not be accessed temporarily. The skipped bits can be decoded again when the conditions are suitable for decoding, such as when the capacity is sufficient.

[0250] The general guideline for determining the decoding order is to decode the bits corresponding to higher capacity (or lower bit error probability) bit indices first. For example, there may be many bits or consecutive sets of bits (also referred to as bit blocks) located at zero-capacity or very low-capacity bit indices. In this case, it is preferable to decode these bits later in the decoding process. Suppose there are two blocks b1 and b2, each with a block-level coding rate R. b1 and R b2 And the corresponding finite-length channel capacity C b1 and C b2 If R b1 >C b1 And R b2 <C b2 In this case, it is preferable to decode block b2 first, and then decode b1. The definition of capacity may differ from that in existing polar codes, which will be described in further detail below.

[0251] To describe the code construction and corresponding decoding process, in addition to the existing frozen bits and information bits, some embodiments define and use a new bit type. This new bit type can be represented by various names, such as empty bit, blank bit, zero-capacity bit, low-capacity bit, useless bit, irrelevant bit, non-decision bit, invalid bit, etc. For convenience, the name "empty bit" is used herein. However, it should be understood that any of these example names or other names can be used to refer to bits that do not need to be decoded due to their low capacity.

[0252] Table 1 below compares existing bit types (including information bits and frozen bits) with the new bit type—empty bits.

[0253] Table 1: Comparison of Bit Types

[0254]

[0255] While empty bits may have zero capacity, in some embodiments, bits with very low reliability or capacity can also be considered empty bits. In the context of bit indexing, the set of bit indices for empty bits is a set other than the information set (the set of bit indices corresponding to the values ​​of the input bits) and the freeze set (the set of bit indices corresponding to predetermined bit values).

[0256] Before performing a hard decision, the received signal corresponding to the code bits needs to be processed. Traditional sequential decoding uses two functions, including the f function and g function mentioned above. This paper also discloses other functions or operations besides the f function and g function mentioned above, and refers to them as f. r Functions and g r Functions. These functions are shown in block diagram form. Figure 21 and Figure 22 middle. Figure 21 The g used in the embodiment of non-sequential polar code decoding r A flowchart of a function. Figure 22 f is used in the implementation of non-sequential polar code decoding r A flowchart of the function.

[0257] like Figure 21 As shown, example g r The function receives input LLR L in2 and output LLR L out In some embodiments, g r The function is defined as follows:

[0258]

[0259] like Figure 22 As shown in the example f r The function accepts two inputs, including LLR L in1 And binary variable b, and output LLR L out In some embodiments, f r The function is defined as follows:

[0260]

[0261] Figure 21 and Figure 22 The examples in the text are specific functions in the LLR domain and are only used to describe functions that may be used in some embodiments. In practice, such functions can be implemented in other domains, such as the probability domain or the likelihood domain. Non-sequential decoding is not limited to the LLR examples in the LLR domain.

[0262] More generally, f r The function has two inputs. The first input is soft information, such as a probability value, likelihood value, or LLR; the second input is a binary value. The first input value is associated with the first bit (the top-right bit in the butterfly structure), while the binary value is associated with the second bit (the bottom-right bit in the butterfly structure). r The function has one input, which can be soft information such as a probability value, likelihood value, or LLR, and is associated with a second bit (the bottom right bit in the butterfly structure). These functions differ from traditional functions because the traditional f function has two inputs and the traditional g function has three inputs.

[0263] Based on the following function g r and f r When decoding encoded bits in a non-sequential decoding sequence, g r function and f r Functions can be represented in a more general form:

[0264] Fn out,g_r =g r (Fn in2 )

[0265] Fn out,f_r =f r (Fn in1 b)

[0266] in

[0267] Fn out,g_r and Fn out,f_r Each represents the output associated with each function;

[0268] Fn in1 and Fn in2 The function input represents the corresponding position (upper right and lower right of the butterfly structure) in the lattice diagram of the polar code;

[0269] b represents the binary variable associated with the second bit (the bottom right bit in the butterfly structure).

[0270] In g r function and f r In this general form of the function, the input and output of the "Fn" function can be probability values, likelihood values, or LLR values, etc. The examples above describe the specific forms of each function in the LLR domain.

[0271] Choose to execute function f and function g, or a new f r Functions and g r The function depends on the decoding order. (See reference.) Figure 23 This describes the processing of the "butterfly" structure in an embodiment of non-sequential polar code decoding. If the lower left bit (u2 in the example shown) in the butterfly structure is decoded first, then a new f is used. r Functions and g r Functions, not the traditional f and g functions. Functions in the LLR domain are used for illustrative purposes in this example and other examples herein, but functions from other domains may also be used in these and other examples and embodiments.

[0272] In the first step ( Figure 23 Step 1) in the process, execute the new g r The function uses the LLR on the right side of the butterfly structure to calculate the LLR of u2, expressed as L'2 = g r (L2) = L2 (as shown in the figure). If u2 is an information bit, its value is obtained through hard decision: 0 if LLR is positive, and 1 if LLR is negative. If u2 is a frozen bit, its bit value is known. As shown in the figure, x2 equals u2, so x2 can be immediately set to x2 = u2.

[0273] Figure 23 Step 2 in the text describes the second step, in which the new f is executed. r The function uses the LLR on the right side of the butterfly structure and the hard decision of u2 to calculate the LLR of u1, expressed as L'1 = f r (L1, u2) (as shown in the figure), and then perform a hard decision based on the LLR of u1 to obtain u1 (provided that u1 is an information bit). It should be noted that the decoding order has been changed here: the second bit u2 is decoded before the first bit u1, which is different from the traditional method of decoding u1 first and then u2 in sequence.

[0274] In the third step (step 3), after decoding both u1 and u2, it is easy to further recover the code bits x1, that is... It should be noted that in this example, "recoding" refers to steps 1 (x2 = u2) and 2 (x2 = u2). This is done simultaneously, which is also the difference from sequential decoding.

[0275] It should be understood that LLR-based calculations or procedures (or similar decoding calculations or procedures) apply not only to information bits but also to frozen bits. Although LLR may not be used in the bit decision of frozen bits, the LLR received at the received code bit index corresponding to the frozen bit can still be used for decoding the input bit at the information set bit index.

[0276] Figure 24 This is a schematic diagram of an exemplary binary tree representation of the decoding schedule, and is consistent with the above reference. Figure 23 The examples are consistent.

[0277] Although some bits or blocks of bits may be decoded in reverse order or in other non-sequential ways, the remaining bits or blocks of bits may still follow the traditional sequential decoding order. This hybrid approach, which combines sequential and non-sequential decoding, may exhibit the best decoding performance.

[0278] For example, suppose the decoding order of a polar code of length 8 is as follows: u5, u6, u7, u3, u4, u1, u2, u8. In this example, blocks u5, u6, u7, u3, u4, and u1, u2 are decoded sequentially within themselves; these blocks can be called sequentially decoded blocks. However, in the initial stage and between blocks, the decoding order is non-sequential because u5 is decoded before u1; between the first and second blocks, u5, u6, u7 are decoded before u3, u4; between the last two blocks, u3, u4 are decoded before u1, u2. In this example, the decoding of u8 is non-sequential because u8 is not decoded immediately after u7, but from the f / g function and fr / g r From the function's perspective, since the previous bit u7 has already been decoded, u8 can be decoded using the traditional f and g functions.

[0279] Within any block, decoding can be sequential or include both sequential and non-sequential encoding. For example, in the first block, decoding u5 first is non-sequential decoding because u4 was not decoded before u5. In this case, a new f will be used. r Functions and g r The function is used to perform out-of-order decoding of u5. However, in the first block, once u5 is decoded, u6 and u7 can be decoded sequentially (using the f and g functions) because u5 has been decoded before u6. Decoding then switches or "jumps" from u7 to the discontinuous or out-of-order bit u3, which is decoded out-of-order. Decoding u4 after u3 is sequential, then switches to out-of-order decoding after switching to u1, and finally switches back to sequential decoding to decode u2 after u1. In this example, there are three out-of-order switches, including the initial switch to u5 and two switches at the end of the first two blocks. Generally, if there are multiple decoding scheduling schemes with the same or similar performance but different numbers of switches, the scheme with fewer switches should be preferred.

[0280] In embodiments involving PC bits, the value of the PC bit may be copied from another information bit or determined by XORing other sets of information bits. In the case of out-of-order decoding, the definitions of the PC bit and information bits may depend on the decoding order. Typically, if PC bits are used, then in the PC function, the last bit decoded according to the decoding order should be the PC bit. Once all other bits in the PC function have been decoded, and assuming all other bits have been correctly decoded, the last bit can be determined.

[0281] For example, for the PC function u i +u j =0, if u j Decoding has been performed, then u i It immediately becomes known, because u i =u j In this case, u i (instead of u) j ) is the PC bit. For example, for the PC function u... i +u j +u k =0, if u j and u k Decoding has been performed, then u i It immediately becomes known, because ui =u j +u k In this case, u i (instead of u) k ) is a PC bit. This is an example of placing a bit value on multiple bit indices.

[0282] Within the context of PC bits, soft combination can also be applied to PC bits. For example, if there are only two undecided bits in the PC function, these two bits can be decided simultaneously through joint decision-making, such as by combining their soft information (e.g., LLR). For example, for u i +u j =0 (or u) i +u j Parallel decoding of (=1), and simultaneous acquisition of soft information L′ i and L′ j The following equation can be used:

[0283] u i =u j =(1-sign(L′) i +L′ j )) / 2

[0284] or

[0285] u i =~u j =(1-sign(L′) i -L′ j )) / 2

[0286] This makes u i and u j The decisions can be made simultaneously. This can be called joint decision-making or parallel decoding.

[0287] In serial decoding, the same PC function example as in the parallel decoding described above is used, the difference being the soft information L′. i It was obtained first, and L′ j That is, it is obtained at a later point in time. In this case, u i The hard decision can be postponed until L′ is obtained. j After that. However, it is also possible to do so by adjusting u. i A soft decision is made to continue the decoding process. Once L′ is obtained... j This allows us to perform u-based decoding as described in the parallel decoding example above. i and u j A firm verdict.

[0288] The decoding order can be determined or obtained based on a variety of criteria, such as code length and / or channel.

[0289] For example, when the code length M is a power of 2 (M = N = 2) n When the code length is (1+a)N / 2, where a∈{1 / 8,1 / 4,3 / 8,1 / 2,5 / 8,3 / 4,7 / 8}, sequential decoding can also be used.

[0290] However, when the code length M exceeds (1+a)N / 2, where N is the mother code length (a power of 2) and a∈{0,1 / 8,1 / 4,3 / 8,1 / 2,5 / 8,3 / 4,7 / 8}, the bit index can be divided into two sets. These two sets include the first (1+a)N / 2 bit positions, which can be decoded sequentially; and another M–(1+a)N / 2 bit positions, which are decoded non-sequentially.

[0291] Of course, other standards and / or decoding schedules can also be used in other embodiments, and specific examples will be further described below.

[0292] In some embodiments, a scheduling sequence can be used to indicate or specify the decoding order of all bit indices. The decoding order can be uniquely defined by a scheduling sequence, also known as a decoding scheduling sequence (DS). For example, in DS = [i1, i2, i3…i…] M In the sequence, index i represents the bit position to be decoded, and its order in the sequence is the decoding order. Furthermore, the decoding order can be defined using multiple start and / or end points. Assume the scheduling sequence DS = [i1, ..., i...]. t i t+1 …i M This includes multiple consecutive sets of indices, denoted by "...". Such a scheduling sequence can also be simplified to DS. s =[i1,i t i t+1 i M [This only includes the start and end points of each consecutive index set.]

[0293] A scheduling sequence can be used to indicate or specify the decoding order of bit indices. For example, if sequential decoding is good enough in terms of encoding performance, the decoding sequence can indicate the order of bit indices in ascending order. In other cases, the decoding scheduling sequence may not be in ascending order of bit indices, such as in non-sequential decoding.

[0294] Scheduling sequences can be determined or designed based on various conditions or rules.

[0295] For example, information bits and their previously consecutive frozen bits can be bundled into information bit blocks or clusters. For example, consecutive bit indices [i, i+1…k–1, k] can be bundled into an information bit cluster if and only if the k-th bit index is an information bit index and all previous bit indices [i, i+1…k–1] are frozen bit indices. For simplicity of representation, the information bit cluster including bit indices [i, i+1…k–1, k] can be represented as {k}.

[0296] In some embodiments, decoding of bit indices in an information bit cluster is performed sequentially. In other words, within an information bit cluster, the decoding order is in ascending order of bit indices, and thus no further specification in the scheduling sequence is required. For convenience, referring to decoding the information bit cluster {k} is equivalent to sequentially decoding bit indices [i, i+1…k–1, k]. With this simplification of the description, the decoding sequence can include only or otherwise indicate the information bit indices.

[0297] Non-sequential decoding enables a cluster to be decoded only when the corresponding information bit positions at the information bit indices of the information bit cluster reach sufficient reliability. During the decoding process, as more and more information bits are decoded, the decoding of the bit values of the remaining bit indices generally becomes more reliable. This phenomenon can be observed in both sequential and non-sequential decoding. Sequential decoding is well-known. In non-sequential decoding, the decoding of a bit index (which may involve making a hard decision on the information bit value) can also improve the decoding reliability of previous or smaller information bit indices i (i < j). For example, assume there is an information bit cluster where the bit value of the last bit index of the cluster has been decoded from another bit index. In this example, the bit value of the last bit index is known, making the previous bit indices in the cluster more reliable.

[0298] If the input bit value is placed on multiple bit indices (e.g., using the same label), then decoding the bit value on any one of the bit indices will immediately determine the bit values on the other bit indices. Therefore, after the information bit cluster corresponding to the bit index of the first decoding, the information bit clusters corresponding to the other bit indices can also be decoded immediately. For example, assume there are three information bit clusters {k1}, {k2}, and {k3}, whose corresponding information bit indices satisfy k1 < k2 < k3, and the same input bit value is placed on k1, k2, and k3 (e.g., using the same label). If the information bit cluster {k3} is decoded first, then {k1} and {k2} can be decoded immediately after {k3} is decoded.

[0299] The above information bit clusters are only exemplary descriptions. The encoded bit blocks do not necessarily correspond only to information bit clusters including one information bit and one or more frozen bits. More than one information bit may be decoded from the encoded bit block.

[0300] Figure 25 A non-restrictive example of non-sequential SC decoding is provided, showing a binary tree representation of non-sequential SC decoding of a polar code of length 4. In this example, the decoding order of the polar code of length 4 is u3, u4, u2, u1.

[0301] exist Figure 25 In the diagram, each edge represents the set of functions f, the set of functions g, or f r Function set, g r Function set. Execute f / g / f r / g r The order of the functions is defined by the decoding order (or schedule) u3, u4, u2, u1. It should be noted that the left-to-right hard bit propagation of u3 in step 3, u4 in step 4, u2 in step 6, and u1 in step 7 occurs after the lower left bit of the butterfly structure has been decoded. In other words, it is not necessary to wait until the two bits on the left side of the butterfly structure have been decoded (hard decision) before the bits on the right side of the butterfly structure can be recovered. Based on these rules, given a specific decoding schedule, any SC decoding with a mother code length of N = 8, 16, 32, 64… can be derived.

[0302] Extended to SCL decoding, including CA-SCL and PC-SCL:

[0303] Each path [u i1 ,u i2 ,…,u iN ]∈{0,1} N This represents the result of non-sequential SC decoding, where i1, i2, ..., i N ∈{1,2,…,N} is the bit index;

[0304] Path metric is the likelihood (or probability) of a path given the channel output, and can be expressed as Pr(u i1 ,u i2 ,…,u i |L1,L2,…,L N In practice, this is usually implemented using a logarithmic field and approximated as the sum of the selected LLRs: in It is a binary pointer, L′ j is u j LLR.

[0305] The remaining decoding process may be the same as sequential SCL decoding.

[0306] Figure 26This includes a table and a trellis diagram illustrating the difference between non-sequential and sequential decoding. A characteristic of non-sequential decoding is that decoding can begin at any point on the right side of the trellis diagram. To this end, a novel left-right propagation property is proposed to support arbitrary start and end bit positions.

[0307] Given a bit index i, satisfying 0 ≤ i ≤ N–1 (note that the index starts from 0, not 1), the following auxiliary parameters are referenced in subsequent examples and are listed below. Figure 26 In the table on the left:

[0308] Binary expansion of index i: Represented in the table by the "index" column label, denoted as bin(i);

[0309] Left propagation depth: Represented by the "←" column label in the table, and calculated as sum(xor(bin(i),bin(i–1)));

[0310] The f / g function sequence is represented in the table using the "f / g" column label, denoted as {f,g}. n Where n = log2(N), this sequence is obtained by replacing each 0 in bin(i) with the f function and each 1 with the g function. Note that f / g here generally refers to the f function or the g function, depending on the decoding order and the currently decoded bits. It could be the traditional f function or the f function disclosed in this paper. r Functions, traditional g functions, or the g functions disclosed in this paper r function;

[0311] Right propagation depth: Represented by the "→" column label in the table, and calculated as #(ending 1), which is the number of multiple trailing 1s in bin(i).

[0312] To decode the bit at index i, there are two cases or scenarios:

[0313] If the previous bit at index i–1 has already been decoded, then the bit at index i can be decoded as in sequential decoding, since its predecessor has already been decoded. In this case, the left propagation depth (i.e., the number of stages in which the f / g function is executed) is the second auxiliary parameter mentioned above, and the right propagation depth (i.e., the number of stages in which recoding is performed) is the fourth auxiliary parameter mentioned above.

[0314] If the previous bit at index i–1 has not yet been decoded, non-sequential decoding is used. In this case, left propagation begins from the rightmost stage, i.e., the left propagation depth is n, and the entire f / g function sequence is executed. The right propagation depth depends on the decoding state of subsequent bits. Greedy right propagation recoding is performed as long as there is no XOR operation with the lower bit (in the “butterfly” structure), or the lower bit has been decoded or recoded. For example, suppose decoding starts from index 2 (010), as... Figure 26As shown in label 2602. In sequential decoding, the function f at row 2604 of the lattice with S=2 has already been executed when decoding index 0 bit, but in this example of non-sequential decoding, since decoding starts from index 2 bit, this function f has not yet been executed. Therefore, the sequence of f / g functions for non-sequential decoding starting from index 2 is... f gf, such as Figure 26 As shown in the table on the left, the first f in the f / g function sequence is marked with bold and underline, indicating that in the non-sequential decoding starting from index 2 bits, the f function involved should have been executed in the sequential decoding of index 2 bits (after indices 0 and 1 bits), and does not need to be repeated. Figure 26 The grid on the right also provides another example of non-sequential decoding, starting from index 5 (101), in Figure 26 The Chinese character is marked as 2606.

[0315] In summary, taking the LLR field as an example, the process of jumping into non-sequential decoded bits may include: from deeper stages ( Figure 26 The right side of the grid (from right to left) propagates LLR; hard decisions are propagated to deeper stages (from left to right); f is executed as needed. r Functions and g r function.

[0316] In some embodiments, the information / frozen / PC bits are still decoded one by one, but the decoding order of these bits does not follow the order of the bit indices [1,2,3…N]. Instead, the decoding order is determined by the decoding schedule sequence DS = [i1,i2,i3…i...N]. M The specified value is the information / freeze / PC bit index to be decoded. It should be noted that M can be an integer less than N, as some zero-capacity or near-zero-capacity bit indices can be skipped. This example is referred to as "scheduled serial" decoding.

[0317] Figure 27 It is a lattice diagram of a decoding example involving non-sequential polar code decoding. Figure 27 The example in the example is an 8-bit code where the first 3 bits are punctured, and the decoded schedule sequence is DS = [5, 6, 4, 7, 8]. Figure 27 In the example, bit values ​​for bit indices 4 and 5 are the same. Figure 27 The return arrow on the left, from position 5 to position 4, indicates that after the bit value at bit index 5 is decoded, the bit value at bit index 4 is known.

[0318] To reduce the complexity of the description, the decoding schedule sequence can be shortened to represent only the non-sequential parts. For example, if there exists a continuous sequential subsequence [i, i+1…j], it can be simplified to [i, j]. The complete decoding schedule sequence DS = [i1, i2, i3…i...j ... M] can be represented as DS = [i1, ..., i t i t+1 …i M ], where “…” indicates a consecutive index, which can be simplified to DS s =[i1,i t i t+1 i M For example, DS = [5,6,7,2,3,4,8] can be simplified to DS. s =[5,7,2,4,8].

[0319] Figure 28 This is a lattice diagram of another decoding example involving non-sequential polar code decoding. In this example of an 8-bit code, the first two code bits are punctured, and the decoding schedule sequence is DS = [4,5,6,3,7,8], or simplified to DS. s =[4,6,3,7,8]. In Figure 28 In the example, bit values ​​at bit indices 4 and 5 are the same, and bit values ​​at bit indices 3 and 6 are also the same. Figure 28 The arrows on the left, from position 4 to position 5 and from position 6 to position 3, indicate this. Regarding indices 4 and 5, Figure 28 and Figure 17 The difference is: in Figure 27 In the process, the bit value of bit index 5 is decoded first, and then... Figure 28 In this process, the bit value of bit index 4 is decoded first.

[0320] Information / freeze / PC bits are no longer decoded in serial order, but a parallel decoding order is also possible. When multiple bits have the same value (e.g., according to the PC function), these bits can be hard-determined in parallel after combining their soft information (e.g., LLR). The decoding order within each parallel decoding block can be sequential or non-sequential.

[0321] The parallel decoding order can be represented by a set of decoding schedule sequences, not just a single sequence. If there are p blocks that need to be decoded in parallel, then there can be p decoding schedule sequences, one for each block. For example, this can be represented as follows:

[0322] DS1=[i1,i2…],DS2=[j1,j2…],…,DS p =[k1,k2…].

[0323] Any bits that require simultaneous hard decision can be represented by an index tuple: if two bits require simultaneous hard decision, use a pair; if three bits require simultaneous hard decision, use a triplet, as shown in the following example; and so on.

[0324] (ir =j s =k t ),(i r+4 =j s+2 =k t+1 ),...

[0325] The above example illustrates that bits requiring simultaneous hard decision-making do not necessarily have corresponding positions in the decoding scheduling order of parallel decoding blocks. These bits also do not necessarily reside in the same positions within their respective blocks. In the first example above, the r-th index in DS1, the s-th index in DS2, and the t-th index in DS3 are to be hard decided simultaneously. In this example, r, s, and t, or any two of them, can be the same or all different.

[0326] Figure 29 This is a trellis diagram of another decoding example involving non-sequential polar code decoding. In the example shown, the upper and lower halves of the trellis are decoded in parallel. The decoding schedule sequence is DS1 = [3,4], DS2 = [5,6,7,8], and (4 = 5). It can be seen that the bit values ​​of the 4th and 5th indices are the same, so in this example, their soft information (e.g., LLR) L'4 and L'5 are first combined, and then a joint hard decision is made: u4 = u5 = (1 - sign(L'4 + L'5)) / 2.

[0327] Figure 30 This is a lattice diagram illustrating another decoding example involving non-sequential polar code decoding. In the example shown, similar to the above... Figure 29 Similar to the example, the two blocks to be decoded in parallel have different sizes. More generally, the blocks to be decoded in parallel can be the same size or different sizes.

[0328] Figure 30 The decoding schedule sequence in the example is DS1 = [2], DS2 = [3,4,5,6,7,8] and (2 = 3). It can be seen that the bit values ​​of the second and third indices are the same, so in this example, their soft information (e.g., LLR) L'2 and L'3 are first combined and then a joint hard decision is made: u2 = u3 = (1 - sign(L'2 + L'3)) / 2.

[0329] In these two examples, the split point between the two blocks (denoted as o for ease of explanation) is different, at 4 and 2 respectively. In practical applications, the split point can be set as an integer that is a power of 2 of the mother code length N, such as o = N / 2, N / 4, N / 8, N / 16, etc., or it can be a combination of split points summed up, such as o = N / 2 + N / 4, o = N / 2 + N / 8, o = N / 2 + N / 4 + N / 16, etc.

[0330] In an embodiment that can be called bidirectional decoding, the decoding directions for different blocks can be different. For example, one block can be decoded sequentially, while another block is decoded in reverse order.

[0331] Figure 31 This is a lattice diagram illustrating a bidirectional decoding example according to an embodiment. In the example shown, the upper and lower halves of the lattice are decoded in parallel, but in different directions. Although Figure 31 The example in the example is for parallel decoding blocks, but bidirectional decoding can also be applied to serial decoding blocks.

[0332] Figure 31 The decoding schedule sequence is DS1 = [4,3], DS2 = [5,6,7,8] and (4 = 5). It can be seen that the bit values ​​of the 4th and 5th indices are the first decoded bits in each block, and their values ​​are the same. Therefore, in this example, their soft information (e.g., LLR) L'4 and L'5 are first combined, and then a joint hard decision is made: u4 = u5 = (1 - sign(L'4 + L'5)) / 2.

[0333] Figure 32 Here is a lattice diagram of another example of bidirectional decoding. In this example, the two parallel decoding blocks have different sizes. The decoding schedule sequence is DS1 = [3,2], DS2 = [4,5,6,7,8] and (3 = 4). It can be seen that the bit values ​​of the 2nd and 3rd indices are the first decoded bits in each block, and their values ​​are the same. Therefore, in this example, their soft information (e.g., LLR) L'3 and L'4 are first combined, and then a joint hard decision is made: u3 = u4 = (1 - sign(L'3 + L'4)) / 2.

[0334] Bit tagging, non-sequential decoding, or a combination of both, may be used in conjunction with other features disclosed herein, such as those described below through various exemplary embodiments.

[0335] The following embodiments, as well as other embodiments herein, are merely examples illustrating how to put these features and processes into practice.

[0336] Figure 33A block-coupled coding scheme according to an embodiment is illustrated. The example shown relates to a union code. In this example, the union code consists of three blocks, each of which is an eBCH code. The first (eBCH 1) code and the third (eBCH 3) code have lower block-level coding rates, which may be the same or different; while the second (eBCH 2) code has a higher coding rate. Low and high coding rates can be defined or distinguished by various thresholds or restrictions, or a coding rate can be determined based on relative coding rates. For example, the highest block-level coding rate (or multiple highest block-level coding rates) in a block can be considered a high coding rate, while the remaining block-level coding rates below that rate are considered low coding rates.

[0337] exist Figure 33 In this example, the high-rate block of the second eBCH code is coupled with the low-rate blocks of the first and third eBCH codes. This block-level coupling is achieved by combining one or more code bits from the second eBCH code block with one or more code bits from the first and third eBCH code blocks (via the XOR operation shown in the example) to generate the final output code bits. The code bits of the second eBCH code are then directly output. In the example shown, these final output code bits are transmitted.

[0338] Figure 34 An encoding with block coupling according to another embodiment is shown. Figure 33 As shown, the high-rate block of the second eBCH code is coupled with the low-rate blocks of the first and third eBCH codes, but the implementation differs. In this example, block coupling is achieved by combining one or more payload bits or input bits used for encoding the second eBCH code with one or more payload bits or input bits used for encoding the first and third eBCH codes (via the XOR operation shown in the example) to generate the output code bits. All eBCH code code bits are output and used for transmission in this example.

[0339] The second eBCH code and the code bits obtained by encoding it have the highest coding rate R. b1 Its capacity C b1 It may also be the highest. However, the first and third eBCH codes, and the code bit blocks obtained through their encoding, have lower coding rates and may also have lower capacity. The block-level code rate-capacity ratio can be expressed as: R b1 / C b1 R b2 / C b2 R b3 / C b3

[0340] Suppose we have an example where three eBCH codes have the same length and pass through the same channel, where R... b1 =R b3 <R b2 And C b1 =C b3 <C b2 In this example, the decoding order in some embodiments may be determined by the decoder or decoding device based on the following conditions:

[0341] If R b2 / C b2 <R b1 / C b1 If so, first decode the second eBCH code, then decode the other two eBCH codes;

[0342] If R b2 / C b2 >R b1 / C b1 First, decode the first and third eBCH codes, then decode the second eBCH code.

[0343] The aforementioned conditions or criteria may also be used by the encoder or encoding device to determine the transmission or output order. At least the block-level coding rate is known at the encoder or encoding device, and the capacity can also be estimated using channel condition measurements or estimations.

[0344] In another example, suppose three eBCH codes have the same length but pass through different channels, and suppose R b1 <R b3 <R b2 And C b3 <C b1 <C b2 In some embodiments, the decoding order can be determined by the decoder or decoding device according to the following steps:

[0345] If R b1 / C b1 <R b3 / C b3 Then first decode the third eBCH code;

[0346] Then recalculate or determine the block-level coding rate-capacity ratio of the other two eBCH codes:

[0347] If R' b1 / C' b1 <R’ b2 / C' b2 R' and C' represent the block-level coding rate and capacity after decoding the third eBCH code, followed by decoding the first eBCH code, and finally decoding the second eBCH code;

[0348] If R' b1 / C' b1 >R' b2 / C' b2 Then, decode the second eBCH code, and finally decode the first eBCH code.

[0349] The aforementioned conditions or criteria can also be used by the encoder or encoding device to determine the transmission or output order. As mentioned above, at least the block-level coding rate is known at the encoder or encoding device, and the capacity can also be estimated using channel condition measurements or estimations. Furthermore, when determining the transmission or output order, the variable coding rate and / or capacity can also be estimated based on the expected decoding order.

[0350] These examples use eBCH codes because they naturally support variable coding rates and are excellent candidate codes. For an eBCH code of length 64, its coding rate is equivalent to the following number of information bits (K), where the lower coding rate code is a subcode of the higher coding rate code.

[0351] N <![CDATA[K1]]> <![CDATA[K2]]> <![CDATA[K3]]> <![CDATA[K4]]> <![CDATA[K5]]> <![CDATA[K6]]> <![CDATA[K7]]> <![CDATA[K8]]> <![CDATA[K9]]> <![CDATA[K 10 ]]> <![CDATA[K 11 ]]> <![CDATA[K 12 ]]> 64 2 8 11 17 19 25 31 37 40 46 52 58

[0352] Compared with the embodiments disclosed herein and Figure 33 and Figure 34 Consistent with the example in, up to three different information bits or bit values ​​can be assigned to the payload bits or input bits of an eBCH code, up to K=25; then, up to one eBCH code, the same information bits can be assigned to more than one eBCH code, up to K=37.

[0353] Figure 33 and Figure 34 This is just an example.

[0354] The embodiments are not limited to eBCH codes, polar codes whose various features are detailed elsewhere in this document, or other specific codes.

[0355] The number of codes or code bits can be more or less than three.

[0356] Performing an XOR operation on code bits or input bits of different blocks is just one example of inter-block coupling. Code bits or input bits can also be combined or associated in other ways, such as through check nodes or functions. Furthermore, bit value placement can also be used, or alternatively, for block coupling, for example, placing the same bit value on multiple polarized code bit indices in different input blocks to achieve coupling between code bit blocks corresponding to input bit blocks.

[0357] Block coupling does not necessarily include all blocks, as illustrated in the example. There may be one or more blocks that are not coupled to any other blocks. The coupling examples above are not mutually exclusive. For example, blocks can be coupled in different ways (e.g., a block pair using...). Figure 33 The output coupling shown is such that another block pair adopts as follows: Figure 34 (Input coupling as shown). Alternatively, multiple coupling methods can be used simultaneously or alternatively between blocks (e.g., using both... Figure 33 The output coupling shown is further coupled using, as... Figure 34 (Input coupling shown).

[0358] More generally, the transmission or output order and / or decoding order or decoding schedule can be determined based on various conditions or rules, such as one or more of the following:

[0359] Always output or decode code bits with sufficient capacity (e.g., based on block-level coding rate, block-level capacity, or block-level coding rate-capacity ratio);

[0360] For input-coupled blocks (such as...) Figure 34 As shown in the example, or by placing the same bit value on multiple input bit indices in different code bit blocks, when the information bit is decoded, one or more of its associated bit values ​​will be known or can be determined and can be used as a known bit or frozen bit for decoding another block;

[0361] When the bit value of more information bits of another block is decoded from other code bit blocks or other bit indices, the block may become large enough that decoding can be switched to that block.

[0362] For output-coupled blocks (such as...) Figure 33 As shown in the example, the code bits of a successfully decoded block can be used to determine the coupled code bits in any coupled code block, thereby aiding in the decoding of these coupled code blocks;

[0363] Output coupling of code bit blocks also affects the capacity of coupled code bit blocks. When code bit values ​​from other code blocks are successfully decoded, these coupled code bit blocks may become sufficiently large. At this point, decoding can be switched based on whether the block capacity is sufficient.

[0364] Overview

[0365] Various aspects of the invention have been described above and illustrated by way of example in the accompanying drawings. Figure 35 This is a flowchart of a more general exemplary method according to an embodiment. Figure 35 In the diagram, 3500 on the left illustrates operations or features that the encoder or transmitting-side device can provide or support, while 3550 on the right illustrates operations or features that the decoder or receiving-side device can provide or support. For ease of reference, the following description... Figure 35In the description, a device that can implement or support encoding and / or transmission features is referred to as a first communication device, while a device that can implement or support decoding and / or reception features is referred to as a second communication device. An embodiment may involve one or both of these devices.

[0366] Referring first to 3500, from the perspective of the transmitting device, outputting coded bit blocks (at 3508) may involve transmitting these coded bit blocks. The coded bit blocks can be output or transmitted through various types of interfaces, including communication interfaces (when transmitting these coded bit blocks). The embodiments are not limited in any way to a particular type of interface. For example, in a wireless communication network, the coded bit blocks can be transmitted at 3508 from a first communication device to a second communication device.

[0367] These coded bit blocks are obtained by encoding the input bits (at 3506), and can also be referred to as coded bits obtained by encoding the input bits with a code. The encoding process (at 3506) can be implemented or executed by an encoder or processor, and outputting coded bit blocks at 3508 does not necessarily mean that these coded bit blocks must be transmitted. These coded bit blocks can be output at 3508 for storage in memory and / or for transmission.

[0368] The encoding process at 3506 may include encoding the input bits using polar codes. The polar codes include or provide multiple bit indices for placing bit values ​​before encoding. These bit indices include a first set of bit indices for placing the values ​​of the input bits; and a second set of bit indices for placing predetermined bit values.

[0369] In the context of the coded bit blocks disclosed herein, each coded bit block obtained by encoding the input bits at position 3506 has a corresponding associated coding rate and a corresponding associated capacity. These coded bit blocks include nested blocks, each nested block being a subcode of another coded bit block having a higher associated coding rate than the nested block. As described elsewhere in this document, a subcode is defined as a subset of the codewords of a parent code, and in the nested structure of codeword blocks, a low coding rate code is a subcode of a high coding rate code of the same length. BCH codes, polar codes, and LDPC codes are identified as examples of codes that can be constructed as variable coding rate blocks using nested blocks. Further, in this context of coded bit blocks, nested blocks are or include blocks coupled to each other.

[0370] Not all coded bit blocks are necessarily nested blocks. That is, at least some (but not all) of these blocks are nested blocks. In other words, coded bit blocks include nested blocks, but are not necessarily composed only of nested blocks. Similarly, not all nested blocks are necessarily coupled blocks. At least some, but not all, of the nested blocks are coupled blocks, or in other words, nested blocks include coupled blocks, but are not necessarily composed only of coupled blocks.

[0371] In embodiments of polar codes, an information set including bit indices for placing input bit values ​​is an example of the first set described above, while a frozen set including bit indices for placing predetermined frozen bit values ​​is an example of the second set described above. The first set of bit indices may include a first subset of bit indices associated with a first coupled block in a coupled block, and a second subset of bit indices associated with a second coupled block coupled to the first coupled block.

[0372] The value of the input bit can include the input bit value (or the same input bit value) placed at the first bit index of the first subset and the second bit index of the second subset. Figure 35 In this document, the placement of bit values ​​at bit indices is shown as an optional step or operation (at 3504), but in some embodiments, this may be part of the encoding process at 3506. Although it is mentioned here that the input bit values ​​are placed simultaneously at the first bit index of the first subset and the second bit index of the second subset, embodiments may also include placing a bit value at multiple bit indices, or placing each of more than one bit value at multiple bit indices.

[0373] The coupling method between these coupled blocks is not limited to polar codes. More generally, coupled blocks can be coupled through the same bit values ​​obtained or provided by the input bits associated with these coupled blocks. In this example, the input bits are encoded to obtain the encoded bits in the coupled block, so the input bits are associated with the coupled block at least in this sense.

[0374] Another example of block coupling is that coupled blocks are coupled to each other through coupling between variable nodes associated with these coupled blocks. In some embodiments, variable nodes can be coupled through check nodes. Variable nodes and check nodes are illustrated elsewhere in this document. Figure 14 An example of coupling between variable coding rate blocks via a check node is shown.

[0375] Coupled blocks can also be coupled to each other by combining the coded bits associated with these coupled blocks, such as... Figure 33 The XOR operation example shown implements a combination; and / or couples with each other by combining the input bits associated with these coupled blocks, such as Figure 34The example shown combines the implementations of the XOR operation.

[0376] Some embodiments may include ordering the coded bit blocks based on their respective associated coding rate and associated capacity. This ordering is useful for decoding because the coded bit blocks can be transmitted in the expected decoding order or otherwise output. In some embodiments, the decoding order may be the same as the transmission or output order, but the decoding order may also be determined by the decoder, decoding device, or receiving device based on factors such as channel conditions, and therefore may be the same as or different from the transmission or output order determined by the encoder, encoding device, or transmitting device.

[0377] The sorting of encoded bit blocks can be performed or supported by an encoder or other components or devices. For example, an encoder can be used to encode input bits and sort the encoded bit blocks for output. This is an example of sorting before the encoded bit blocks are output. In some embodiments, the encoder may output encoded bit blocks sequentially in the order in which encoded bits are generated or acquired in the encoded bit stream, while a transmitter or other component or device can be used to sort the encoded bit blocks output by the encoder according to the coding rate and capacity. This is an example of sorting after the encoder outputs the encoded bit blocks.

[0378] Sort coded bit blocks based on coding rate and capacity, which may involve arranging these blocks in ascending order of the ratio of their respective associated coding rate to their respective associated capacity. This can also be referred to as sorting by block-level coding rate to capacity ratio in ascending order.

[0379] Encoded bits can be sent sequentially in the order of the encoded bits in the encoded bit stream or output in other ways, or they can be sent or output in a different order. Regardless of whether the encoded bits are sent sequentially or output in other ways, in some embodiments, the values ​​of the input bits can be decoded from the encoded bit blocks according to a non-sequential decoding order based on the corresponding associated coding rate and the corresponding associated capacity for each encoded bit block. This is also known as a flexible decoding order.

[0380] In some embodiments, an coded bit block comprises a block whose associated coding rate, associated capacity, or both associated coding rate and associated capacity are variable and change as another coded bit block is decoded. For example, in the case of block coupling, the decoding of one block affects the coding rate and / or capacity of any other blocks coupled to the block being decoded. In the example above, the decoding order based on the block-level coding rate to capacity ratio involves decoding the block with the minimum coding rate to capacity ratio and updating the coding rate to capacity ratio of each block during decoding (because they change at least in the case of coupled blocks).

[0381] For the sake of completeness, Figure 35Another operation that may be involved at 3502 according to some embodiments is illustrated. Acquiring the input bits for encoding may include, for example, collecting or otherwise receiving data output from one or more devices and services, or accessing data in memory.

[0382] Implementations may include any or all of the operations shown at 3500. For example, in some implementations, the method may include encoding as shown at 3506 and transmitting or otherwise outputting the encoded bit block at 3508. Other implementations may involve transmitting or otherwise outputting the encoded bit block that has been acquired by encoding the input bits at 3508. Other methods may also include acquiring, placing, and encoding (3502, 3504, 3506), and outputting the encoded bits as shown at 3508.

[0383] These features can be implemented in various ways, and / or may alternatively provide or support other features.

[0384] In some embodiments, the output at 3508 may involve transmission; in others, these features may be implemented separately by the encoder and the transmitter. Encoding at 3506 generates coded bits, which can be output at 3508.

[0385] Some implementations may involve rate matching, such as through punching or shortening, so certain bit indices may have zero or very low reliability or capacity. At least as mentioned above, in addition to frozen bits and information bits, bits that should not be decoded due to insufficient capacity can also be defined as null bits; similarly, null bit indices can be defined as bit indices used to place input bit values.

[0386] The null bit index may be related to reducing the number of coded bits generated by encoding at position 3506. Generally, if there are P puncture positions for coded bits, there will be exactly P null bit indices. For example, in a polar code codeword, if the first P bit positions are punctured at the first P indices, the first P bit indices in the input vector will suffer the most severe negative performance impact; these first P bit indices can be marked or otherwise indicated as or treated as null bit indices. Similarly, for many other puncturing patterns, the null bit pattern is usually the same as the puncturing pattern, such that the null bit index is consistent with the punctured bit index (where the coded bit is punctured). However, there are exceptions, especially when puncturing occurs from the end of the codeword, in which case the null bit pattern differs from the puncturing pattern. In such cases, the communication standard may define or specify the null bit pattern and its relationship with the puncturing pattern.

[0387] Generally, there is a correspondence between the indexes of bits in the encoded bits that are punctured or otherwise reduced in rate matching and the indexes of empty bits in the input vector that are most affected by the reduction in the number of encoded bits. The correspondence between the number of punctured bits and the number of empty bit positions, as well as the correspondence between the punctured bit index and the empty bit index, are examples of relatively simple deterministic relationships.

[0388] For example, the null bit index can be determined by a decoder, receiver, or decoding device based on a known puncturing pattern. In other embodiments, signaling or configuration can also be used to indicate the null bit index, or alternatively.

[0389] Encoding and decoding implementations may be affected by null bits. For example, if a null bit index is also part of the information set, the input bit value that would normally be placed at that index might be placed at another index that is part of the information set in order to correctly decode the input bit value. The input bit value remains at the null bit index and is encoded, but the corresponding encoded bits are not sent or otherwise provided to the decoder, so the input bit value is not decoded at that null bit index.

[0390] This differs from the decoding method of traditional rate-matched codes. For example, although both decoding methods (traditional and empty-bit embodiments) may involve setting the soft information (e.g., LLR) of the punctured bits to 0, the empty-bit index is completely skipped during decoding. In contrast, traditional decoding does not skip any bit positions during decoding, but still attempts to decode the bit value corresponding to the index of the punctured bit.

[0391] In some embodiments, when the input bit values ​​are placed on empty bit indices, these input bit values ​​are preferably also placed on one or more other bit indices so that they can be decoded.

[0392] The bit indices or positions (subchannels in the case of polar codes) of the unencoded bit values ​​can be assigned and thus associated with tags; this is one possible way to place bit values ​​on bit indices. These bit indices include at least an information bit index (also referred to herein as an information bit) for the value of the input bit to be encoded, and may also include a frozen bit index for frozen bits (which is set to a predetermined known bit value), and / or an empty bit index for empty bits. For information bits and frozen bits, the frozen bit position can be marked as "0" or other values ​​not used for information bits, while the information bit positions (K in total) can be marked as l∈{1,2…K}. More generally, the information bit index is used to place the input bit value, the frozen bit index is used to place the predetermined value, and the empty bit index (if provided) is also used to place the input bit value, reducing the number of encoded bits. Code construction and encoding operations can be performed based on how the bit values ​​are placed.

[0393] For multiple bit indices assigned the same tag or containing the same bit value, once the bit value at any one of these bit indices is decoded, the bits at the remaining bit indices with the same bit value or tag can be immediately determined. This is because they establish some kind of relationship or check function through commonly shared bit values ​​or tags. For the input bit of the first bit index among the bit indices with the same bit value or tag, decoding can be based on polar codes; while for the other bit indices associated with that bit value or tag, decoding can be simplified to setting the bit value to the same value as the first decoded input bit, since the same tag or bit value has already been placed at these bit indices. In this sense, the first decoded bit is considered an information bit during encoding and decoding. The other information bits at the bit indices associated with the same bit value or tag do not need to undergo the full decoding process typically applied to information bits; in this sense, they can be considered as check bits.

[0394] Figure 35 At position 3550, various decoding and / or receiving features corresponding to the feature shown at position 3500 are illustrated. From the perspective of the receiving device, the receiving operation at position 3552 represents receiving a block of encoded bits obtained by encoding the input bits using a code. For example, receiving at position 3552 could be a second communication device receiving these blocks of encoded bits from a first communication device in a wireless communication network. The encoded bits can be received through various types of interfaces, and the embodiments are not limited to any particular type of interface.

[0395] As in other embodiments herein, each coded bit block has a corresponding associated coding rate and a corresponding associated capacity, the coded bit block includes nested blocks, each nested block includes a subcode of another coded bit block, the other coded bit block has a higher corresponding associated coding rate than the nested block, and the nested blocks include mutually coupled coupled blocks.

[0396] Decoding at 3554 is intended to describe the decoding of received encoded bits to obtain the input bits for decoding. For example, decoding at 3554 can be implemented or performed by a decoder or processor, etc.

[0397] In some embodiments, the decoder may not be a standalone device, but rather a logic module within a silicon chip, or part of a system-on-a-chip, used to decode and utilize the decoded input bits. In other embodiments, the decoded input bits are output as shown at 3556 for processing and / or storage.

[0398] Any or all features described in this document in the context of encoding-side or transmitting-side methods (e.g., references) Figure 35 (as described in point 3500), and may also be applicable to or have corresponding features in the decoding-side or receiving-side methods. Other features may also be provided or supported alternatively. For example, any one or more of the following features may be provided or supported individually or in various combinations in the decoding-side or receiving-side methods:

[0399] Coupled blocks are coupled to each other through the coupling between the variable nodes associated with the coupled blocks;

[0400] Variable nodes can be coupled through validation nodes;

[0401] Coupled blocks are coupled to each other by combining the coded bits associated with the coupled blocks;

[0402] Coupled blocks are coupled to each other by combining the input bits associated with the coupled blocks;

[0403] Coupled blocks are coupled to each other by the same bit value of the input bit associated with the coupled block;

[0404] The encoded bits may be obtained by polar coding the input bits, which includes multiple bit indices for placing bit values ​​before encoding. These bit indices include: a first set of bit indices for placing the value of the input bit and a second set of bit indices for placing a predetermined bit value. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in the coupled block and a second subset of bit indices associated with a second coupled block in the coupled block coupled to the first coupled block. The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset.

[0405] Reception at 3552 may involve sequentially receiving coded bit blocks based on the corresponding associated coding rate and the corresponding associated capacity for each coded bit block;

[0406] Decoding at 3554 may involve decoding the coded bit blocks in a different order than the order in which they were received;

[0407] Decoding at 3554 may involve decoding the coded bit blocks in ascending order of the ratio of the corresponding associated coding rate to the corresponding associated capacity of each coded bit block;

[0408] Decoding at 3554 may involve decoding the values ​​of the input bits from the coded bit blocks according to a non-sequential decoding order based on the corresponding associated coding rate and associated capacity of each coded bit block;

[0409] The coded bit block received at 3552 may include a block, wherein the corresponding associated coding rate, the corresponding associated capacity, or both the corresponding associated coding rate and the corresponding associated capacity of the block are variable and change as another coded bit block is decoded;

[0410] The method may involve: when decoding other coded bit blocks at 3554, for each block, updating the corresponding associated coding rate to the corresponding updated coding rate, updating the corresponding associated capacity to the corresponding updated capacity, or updating both the corresponding associated coding rate and the corresponding associated capacity to the corresponding updated coding rate and the corresponding updated capacity.

[0411] Decoding at 3554 may involve decoding the block in the order of the corresponding update coding rate, the corresponding update capacity, or both the corresponding update coding rate and the corresponding update capacity.

[0412] Other features related to receiving and / or decoding encoded bits may also be provided or supported, or alternatively. For example, the decoding order may be based on various conditions or criteria, specific examples of which have been described elsewhere in this document. The specific examples listed above are not exhaustive. The order in which encoded bit blocks are transmitted or otherwise output, and / or received may be based on the same or similar conditions or criteria.

[0413] The embodiments may also involve other features or operations. For example, some embodiments may involve communication signaling that indicates one or more of various parameters, such as code length, puncturing pattern, a base sequence for determining the information set and freeze set, etc. Communication signaling may involve an encoder / encoding device or transmitter / transmitting device sending the signaling to a decoder / decoding device or receiver / receiving device. Communication may also, or alternatively, involve a decoder / decoding device or receiver / receiving device receiving signaling from an encoder / encoding device or transmitter / transmitting device. Signaling is not necessarily between, or only between, the communication devices sending or receiving the coded bits. For example, network devices such as gNBs or base stations may send signaling to configure parameters on one or more communication devices. Therefore, the method may involve a network device sending signaling, an encoder / encoding device or transmitter / transmitting device receiving signaling from the network device, and / or a decoder / decoding device or receiver / receiving device receiving signaling from the network device.

[0414] This invention includes various embodiments, not only method embodiments but also other embodiments, such as apparatus embodiments and embodiments related to non-transitory computer-readable storage media. Embodiments may be combined, alone or in combination, with the features disclosed herein.

[0415] The apparatus may include a processor for causing the apparatus to perform the methods or operations disclosed herein, or to provide or support the features disclosed herein, by, for example, executing a program. The apparatus may also include a non-transitory computer-readable storage medium coupled to the processor and storing a program for execution by the processor. Figure 3 For example, processors 210, 260, and 276 may be or include one or more processors, and each memory 208, 258, and 278 is an example of a non-transitory computer-readable storage medium in ED 110 and TRP 170, 172. For example, the non-transitory computer-readable storage medium does not necessarily have to be provided in conjunction with a processor; it may be provided separately in a computer program product.

[0416] As an illustrative example, a program stored or stored in a non-transitory computer-readable storage medium may include instructions for causing a processor to perform operations, or for causing a processor, device, or other component to encode input bits to obtain encoded bit blocks and output those encoded bit blocks. Each encoded bit block has a corresponding associated coding rate and a corresponding associated capacity. These encoded bit blocks include nested blocks, each nested block including a subcode of another encoded bit block, the other encoded bit block having a higher corresponding associated coding rate than the nested block. Nested blocks include coupled blocks that are mutually coupled.

[0417] The apparatus embodiments are not limited to the examples described above, nor are they limited to processor-based or program-based embodiments. For example, the apparatus may also or alternatively include an encoder for encoding input bits to obtain encoded bit blocks, and an interface coupled to the encoder for outputting encoded bit blocks. As in other embodiments, each encoded bit block has a corresponding associated coding rate and a corresponding associated capacity, the encoded bit blocks include nested blocks, each nested block includes a subcode of another encoded bit block, the other encoded bit block has a higher corresponding associated coding rate than the nested block, and the nested blocks include mutually coupled coupling blocks.

[0418] Encoded bits can be output through various types of interfaces, including communication interfaces (when sending encoded bits). Implementations are not in any way limited to a particular type of interface, and their implementation may be at least partly based on how the encoded bits will be output.

[0419] Figure 36 This is a block diagram illustrating an apparatus that can be used to implement or support embodiments of the present invention. Exemplary apparatus 3600 includes an input interface 3602, an encoder 3604 coupled to the input interface, and an output interface 3606 coupled to the encoder. Input bits for encoding are shown as input TBs or payload bits, while encoded bits are shown as the result output from the output interface 3606. Although in Figure 36 The output interface 3606 is shown as a separate component, but the interface for transmitting or otherwise outputting coded bit blocks can also be provided by, integrated into, or coupled to the encoder 3604. Similarly, although in Figure 36 The input interface 3602 is shown as a separate component, but the interface used to provide or obtain input bits to the encoder 3604 for encoding can also be provided by the encoder, integrated into it, or coupled to it.

[0420] Features or functions on the encoding or transmitting side, as well as other features or functions disclosed herein, can be implemented in various ways, such as through hardware, firmware, or one or more components executing software. This invention is not limited to any particular type of implementation; for example, implementation details may differ between different devices.

[0421] In one embodiment, the apparatus includes an encoder 3604 for encoding input bits to obtain encoded bit blocks. Each encoded bit block has a corresponding associated coding rate and a corresponding associated capacity. The encoded bit blocks include nested blocks, each nested block including a subcode of another encoded bit block, the other encoded bit block having a higher corresponding associated coding rate than the nested block. The nested blocks include coupled blocks that are mutually coupled.

[0422] More generally, the device or its components (e.g., encoder 3604 or processor) can be used to encode (or be used for encoding) input bits, or the program can include instructions that instruct the input bits to be encoded (or be used for encoding) or cause the processor to encode the input bits to obtain an encoded bit block. The device or its components (e.g., interface 3606 coupled to encoder 3604) can be used to output (or be configured to output) an encoded bit block, or the program can include instructions that instruct the output (or be used for outputting) an encoded bit block or cause the processor to output an encoded bit block. For example, the output might involve transmitting an encoded bit block from a first communication device to a second communication device in a wireless communication network.

[0423] Embodiments relating to devices or non-transitory computer-readable storage media may include one or more of the following features, which, for example, have been discussed in other parts of this document:

[0424] Coupled blocks are coupled to each other through the coupling between the variable nodes associated with the coupled blocks;

[0425] Variable nodes can be coupled through validation nodes;

[0426] Coupled blocks are coupled to each other by combining the coded bits associated with the coupled blocks;

[0427] Coupled blocks are coupled to each other by combining the input bits associated with the coupled blocks;

[0428] Coupled blocks are coupled to each other by the same bit value of the input bit associated with the coupled block;

[0429] The device or its components (e.g., encoder 3604) may be used to encode (or be used for encoding) input bits using polar codes, or the program may include instructions that instruct the input bits to be encoded (or be used for encoding) or cause the processor to encode the input bits to obtain encoded bits. The polar codes include a plurality of bit indices for placing bit values ​​before encoding. These bit indices include: a first set of bit indices for placing the values ​​of the input bits and a second set of bit indices for placing predetermined bit values. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in a coupled block and a second subset of bit indices associated with a second coupled block in a coupled block coupled to the first coupled block.

[0430] The value of the input bit may include the same bit value placed at the first bit index in the first subset and the second bit index in the second subset;

[0431] The apparatus or its components (e.g., encoder 3604) may be used to sort (or use for sorting) coded bit blocks based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block, or the program may include instructions that instruct the sorting (or use for sorting) of coded bit blocks or cause the processor to sort the coded bit blocks.

[0432] The device or its components (e.g., encoder 3604) may be used to sort (or use for sorting) coded bit blocks based on ascending order of the ratio of the corresponding associated coding rate to the corresponding associated capacity of each coded bit block, or the program may include instructions that instruct the sorting (or use for sorting) of coded bit blocks or cause the processor to sort coded bit blocks.

[0433] The value of the input bit can be decoded from the coded bit block according to the non-sequential decoding order, which is based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block;

[0434] A block of encoded bits may include blocks, wherein the associated coding rate, associated capacity, or both associated coding rate and associated capacity of a block are variable and change as another block of encoded bits is decoded;

[0435] The device or its components (e.g., interface 3606) may be used to transmit (or be configured to transmit) coded bit blocks, or the program may include instructions that instruct the transmission (or are used to transmit) coded bit blocks or cause the processor to transmit coded bit blocks, all three transmission operations transmitting coded bit blocks from a first communication device in a wireless communication network to a second communication device.

[0436] For decoding-side or receiving-side devices or computer program products that include non-transitory computer-readable storage media to support decoding-side or receiving-side operation, the device or its components (e.g., an interface) may be used to receive (or configured to receive) coded bit blocks, or the program may include instructions that instruct the receiving (or for receiving) of coded bit blocks or cause a processor to receive coded bit blocks obtained by encoding input bits. As in other embodiments, each coded bit block has a corresponding associated coding rate and a corresponding associated capacity, and these coded bit blocks include nested blocks, each nested block including a subcode of another coded bit block having a higher corresponding associated coding rate than the nested block. Nested blocks include coupled blocks that are mutually coupled. Such a device or its components (e.g., a decoder coupled to an interface) may be used to decode (or for decoding) coded bits, or the program may include instructions that instruct the decoding (or for decoding) of coded bits or cause a processor to decode coded bits to obtain decoded input bits.

[0437] Embodiments relating to devices or non-transitory computer-readable storage media may include one or more of the following features, which, for example, have been discussed in other parts of this document:

[0438] Coupled blocks are coupled to each other through the coupling between the variable nodes associated with the coupled blocks;

[0439] Variable nodes can be coupled through validation nodes;

[0440] Coupled blocks are coupled to each other by combining the coded bits associated with the coupled blocks;

[0441] Coupled blocks are coupled to each other by combining the input bits associated with the coupled blocks;

[0442] Coupled blocks are coupled to each other by the same bit value of the input bit associated with the coupled block;

[0443] The encoded bit is obtained by encoding the input bit using polar codes. The polar codes include multiple bit indices for placing bit values ​​before encoding. The bit indices include a first set of bit indices for placing the value of the input bit and a second set of bit indices for placing a predetermined bit value. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in the coupled block and a second subset of bit indices associated with a second coupled block in the coupled block, which is coupled to the first coupled block.

[0444] The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset;

[0445] The apparatus or its components (e.g., an interface) may be used to receive (or be used to receive) coded bit blocks in order of their respective associated coding rates and associated capacities, or the program may include instructions that instruct the receiving (or being used to receive) of coded bit blocks or cause the processor to receive coded bit blocks.

[0446] The apparatus or its components (e.g., a decoder) may be used (or configured to) decode coded bit blocks in an order different from the order in which they are received, or the program may include instructions that instruct (or are used to decode) coded bit blocks or cause the processor to decode coded bit blocks.

[0447] The apparatus or its components (e.g., a decoder) may be used to decode (or be used to decode) coded bit blocks in ascending order based on the ratio of the corresponding associated coding rate to the corresponding associated capacity of each coded bit block, or the program may include instructions that instruct the decoder to decode (or be used to decode) the coded bit blocks or cause the processor to decode the coded bit blocks.

[0448] The apparatus or its components (e.g., a decoder) may be used to decode (or for decoding) the values ​​of input bits in a coded bit block according to a non-sequential decoding order based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block, or the program may include instructions that instruct the decoder to decode (or for decoding) the values ​​of input bits in a coded bit block or cause the processor to decode the values ​​of input bits in a coded bit block;

[0449] A block of encoded bits may include blocks, wherein the associated coding rate, associated capacity, or both associated coding rate and associated capacity of a block are variable and change as another block of encoded bits is decoded;

[0450] The apparatus or its components (e.g., a decoder) may be used to: update (or be used to update) a block when decoding other coded bit blocks, or the program may include instructions that instruct (or be used to update) or cause the processor to update the following: update the corresponding associated coding rate to the corresponding updated coding rate, update the corresponding associated capacity to the corresponding updated capacity, or update both the corresponding associated coding rate and the corresponding associated capacity to the corresponding updated coding rate and the corresponding updated capacity.

[0451] The device or its components (e.g., a decoder) may be used to decode (or be used to decode) a block based on the block’s corresponding update coding rate, corresponding update capacity, or both the corresponding update coding rate and corresponding update capacity, or the program may include instructions that instruct the decoder to decode (or be used to decode) a block or cause the processor to decode a block.

[0452] The device or its components (e.g., an interface) may be used to receive (or configured to receive) coded bit blocks, or the program may include instructions that instruct the receiving (or use to receive) of coded bit blocks or cause the processor to receive coded bit blocks, all three of which involve a second communication device receiving coded bit blocks from a first communication device in a wireless communication network.

[0453] The apparatus embodiments are not limited in any way to a single device. For example, the system may include a first communication device and a second communication device. The first communication device may be used to transmit (or be used to transmit) coded bit blocks obtained by encoding input bits, each coded bit block having a corresponding associated coding rate and a corresponding associated capacity, the coded bit blocks including nested blocks, each nested block including a subcode of another coded bit block, the other coded bit block having a higher corresponding associated coding rate than the nested blocks, the nested blocks including mutually coupled coupling blocks. The second communication device is used to receive (or is used to receive) coded bit blocks from the first communication device and decodes (or is used to decode) the coded bit blocks to obtain decoded input bits. The first communication device in the system may also, or alternatively, implement, provide, or support other encoding-side or transmitting-side features disclosed herein, and similarly, the second communication device in the system may, or alternatively, implement, provide, or support other decoding-side or receiving-side features disclosed herein.

[0454] More generally, other features disclosed herein may also be provided in the method, apparatus and / or system embodiments, either by way of alternatives.

[0455] The embodiments disclosed herein cover various aspects of encoding, including encoding and decoding.

[0456] The embodiments disclosed herein can provide a basic upgrade to the code and can make polar codes and / or other codes applicable to a wider range of scenarios.

[0457] For example, the embodiments disclosed herein can be implemented as part of a channel coding scheme and are therefore applicable to any scenario using channel coding. This covers a very wide range of scenarios. The embodiments disclosed herein are highly flexible, making the associated channel coding schemes particularly suitable for wireless communications.

[0458] Possible product deployment scenarios (or scenarios combining with other technologies) include network equipment (e.g., base stations), access equipment (e.g., user equipment), robots, sensors, automobiles, drones, and satellites. Examples of business deployments include enhanced mobile broadband (eMBB), ultra-reliable low-latency communication (URLLC), massive machine-type communication (mMTC) / Internet of Things (IoT), as well as connected vehicles and industrial scenarios. Examples of network deployments include 5G+, 6G, WiFi, non-terrestrial networks (NTN), optical networks, distributed networks, and self-organizing networks. The above examples are for illustrative purposes only and do not constitute limitations; other deployments, implementations, or applications are also feasible.

[0459] The decoding method disclosed in this paper helps to avoid the catastrophic performance degradation that may occur in traditional schemes that rely solely on sequential decoding.

[0460] More generally, the embodiments help to implement channel-dependent coding structures or methods, thereby providing or supporting coding schemes that can better adapt to changes in channel state or conditions.

[0461] Although the invention has been described with reference to illustrative embodiments, this description is not intended to limit the invention. Those skilled in the art will understand, upon referring to this description, various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention.

[0462] Features disclosed herein in the context of any particular embodiment may or alternatively be implemented in other embodiments. For example, method embodiments may or alternatively be implemented in apparatus, system, and / or computer program product embodiments. Additionally, while embodiments are described primarily in the context of methods and apparatus, other implementations are contemplated as instructions stored in one or more non-transitory computer-readable media, etc. Such media may store programs or instructions to perform any of the methods consistent with the present invention.

[0463] While various aspects of the invention have been described with reference to specific features and embodiments thereof, various modifications and combinations may be made to the invention without departing from its scope. The specification and drawings are therefore to be considered merely as illustrations of some embodiments of the invention as defined in the appended claims, and any and all modifications, variations, combinations, or equivalents covering the scope of the invention are contemplated. Thus, while embodiments and possible advantages have been described in detail, various changes, substitutions, and alterations may be made herein without departing from the invention as defined in the appended claims. Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, articles of manufacture, material compositions, modules, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of the invention that existing or soon-to-be-developed processes, machines, articles of manufacture, material compositions, modules, methods, or steps that perform substantially the same functions as the corresponding embodiments described herein, or that can achieve substantially the same results as the embodiments, can be used according to the invention. Therefore, the appended claims are intended to include such processes, machines, articles of manufacture, material compositions, modules, methods, or steps within their scope.

[0464] Furthermore, any module, component, or device executing instructions illustrated herein may include or otherwise access a non-transitory computer-readable or processor-readable storage medium to store information such as computer-readable or processor-readable instructions, data structures, program modules, and / or other data. A non-exhaustive list of examples of non-transitory computer-readable or processor-readable storage media includes magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, compact disc read-only memory (CD-ROM), digital video discs or digital versatile discs (DVDs). Optical discs or other optical storage devices, volatile and non-volatile, removable and non-removable media implemented in any method or technology, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies. Any such non-transitory computer-readable or processor-readable storage medium may be part of a device, or accessible to or connected to said device. Any application or module described herein may be implemented using computer-readable and executable instructions, or a processor may be stored and held by such non-transitory computer-readable or processor-readable storage media.

[0465] U.S. Provisional Patent Application No. 63 / 454,070, filed on March 23, 2023, entitled “Methods, Systems, and Apparatus for Channel-dependent Error Correction Coding,” includes the following as the basis for the embodiments disclosed herein.

[0466] Methods, systems, and apparatus for channel-related error correction coding

[0467] In wireless communication, channel conditions continuously change on both fast and slow timescales due to factors such as fading effects. Therefore, channel coding design always aims to adapt to channel conditions. Adaptive modulation and coding schemes (MCS) are an effective way to cope with changes in channel conditions, with the core being real-time changes in modulation order, code length, and coding rate. Therefore, channel coding schemes need to flexibly adjust code length and coding rate in a fine-grained manner while maintaining good error correction performance under all possible configurations. This fine-grained flexibility of channel codes is one of the most challenging problems faced by engineers in this field. Generally, probabilistic codes (such as LDPC codes) are inherently better suited for this purpose due to their random code-like characteristics. Algebraic codes (such as RM codes and BCH codes) are less flexible than probabilistic codes because their inherent coding structure may be affected by changes in code length or coding rate. Polar codes, however, are unique, possessing characteristics of both probabilistic and algebraic codes, thus offering flexibility between the two. Currently, several rate-matching schemes can be used to design rate-compatible polar codes, such as those used in 5G NR, including puncturing and shortening. However, the current flexibility is insufficient to support more advanced features, such as fine-grained incremental-redundancy hybrid automatic repeat request (IR-HARQ).

[0468] LDPC codes are defined by their parity check matrix (usually denoted by H). Each row of H represents a parity check function, where the position of "1" corresponds to the code bit participating in that parity check function. For example, the row [1,0,0,1,0,1] means that the XOR result of the 1st, 4th, and 6th code bits must be 0 in order to pass the parity check function.

[0469] The generation of codeword c must satisfy all parity check conditions defined by the row definition of H, i.e., H·c = 0.

[0470] The number of 0s in the parity-check matrix is much larger than the number of 1s, so its "density is low". In 5G, the design of quasi-cyclic LDPC codes based on protographs is adopted. The generation of the parity-check matrix is divided into two steps:

[0471] 1. Read the predefined protograph matrix (see below);

[0472] 2. Replace each "1" in the protograph matrix with a circulant shift identity matrix (or simply called a circulant matrix), and use the predefined shift value for the position of each "1". This step is called "lifting". The matrix obtained after lifting is the final parity-check matrix of the LDPC code.

[0473] Currently, the above LDPC design is simple and applicable to a variety of code rates and code length ranges.

[0474] · For higher code rates, fewer protograph rows are used; for lower code rates, more protograph rows are used (i.e., more parity-checks);

[0475] · For longer codes, the protograph can be lifted by using a larger circulant matrix; for shorter codes, a smaller circulant

[0476] matrix is used to lift the protograph.

[0477]

[0478] It can be seen that LDPC codes have high flexibility and are very suitable for wireless communication applications. Through MCS adaptation, LDPC codes can adapt to the dynamic wireless channel conditions between data packets.

[0479] However, the current LDPC designs are still channel-independent, which means they cannot respond to channel variations within a data packet (codeword).

[0480] Polar codes are linear block codes. For a polar code with length N, its generator matrix is G<00> N , and its encoding process is where5] is the binary information vector, is the binary code vector. The N×N binary matrix where is the polarization kernel matrix, n = log2 N, is the Kronecker product. [[ID=]]<00>

[0481] Usually, there are K information bits to be encoded into N code bits. Obviously, we know that K < N, so the obtained code rate is R = K / N < 1. This means that only A part of it is used to carry information bits, and the remaining bits are called frozen bits. Among them, the information bit set (or information set) can be denoted by I, the frozen bit set (or frozen set) can be denoted by F, and sometimes there is also an additional PC bit set, denoted by P. The frozen bits are known and are usually set to all zeros before decoding, so they do not carry any information. The PC bits are the parity check bits of a subset of information bits. Therefore, once the relevant information bits are decoded, they are known. The decoding of a polar code is actually an attempt to recover all the information bits.

[0482] The code length M is not necessarily always a power of 2, that is, M < N. In fact, usually the number of transmitted code bits is reduced from N to M by puncturing or shortening. For convenience, in this article, N is called the mother code length, and M is called the code length. Specifically, the punctured bits are the untransmitted bits unknown to the decoder, and the shortened bits are the untransmitted bits known to the decoder (usually set to all zeros).

[0483] An exemplary polar code (N = 8 and K = 4) is shown in the trellis diagram below. Each "butterfly" structure in the figure is a polarization, that is In this example, the information set is I = {u4, u6, u7, u8}, and the frozen set is F = {u1, u2, u3, u5}.

[0484]

[0485] Polar codes are decoded by successive cancellation (SC) and its variants. Currently, all SC-based polar decoders follow sequential operations when performing successive cancellation. If we use to represent the information subchannels, frozen subchannels, and parity check (PC) subchannels, then the decoding order is u1, u2,..., u N .

[0486] Under sequential SC decoding, the distribution of LLR(u1, u2,..., u N ) (the leftmost column in the figure below) can be derived from the distribution of LLR(x1, x2,..., x N ) (the rightmost column in the figure below).

[0487]

[0488] For this reason, polar codes belong to channel-dependent codes. In Professor Arikan's pioneering paper, "Channel Polarization: A Method for Constructing Capacity Realization Codes for Symmetric Binary Input Memoryless Channels" (IEEE Transactions on Information Theory 55, no. 7 (2009): 3051-3073), he clearly pointed out that "polar codes are channel-specific designs: a polar code designed for one channel may not be suitable for another channel."

[0489] However, this channel-dependent polar code design is static. This means that once the polar code is constructed, a specific and fixed channel implementation is assumed. The receiver cannot adapt to any constantly changing channel conditions.

[0490] Channel-independent channel coding design has two main drawbacks:

[0491] • When channel conditions are constantly changing and channel estimation is inaccurate, channel-independent channel coding design makes the transceiver unable to adapt to real channel conditions.

[0492] Channel-independent channel coding has a finite coding structure.

[0493] To address the challenges of constructing, encoding, and decoding channel-dependent error-correcting codes, we need a new coding structure that allows the error-correcting codes to provide multiple decoding schemes for different channel conditions, even after code construction and encoding.

[0494] An important observation about channel coding is the relationship between coding rate and capacity. Shannon tells us that as code length approaches infinity, if the coding rate exceeds the capacity, error-free communication becomes virtually impossible. However, within a finite length range, even if the coding rate exceeds the capacity, correct decoding is still possible, but the bit error rate will increase significantly.

[0495] Codewords can always be divided into multiple shorter (sub)blocks, each with the following attributes:

[0496] • Block capacity: The total bit channel capacity corresponding to the code bits, which depends on the channel and code length;

[0497] • Block coding rate: The ratio of an unknown number of bits to the block length. In our design, the block-level coding rate is not fixed (there may be a maximum / minimum coding rate), but depends on the decoding order.

[0498] When the block size is greater than the block coding rate, the block is called a "sufficient capacity block";

[0499] When the block size is less than the block coding rate, the block is called an "insufficient block";

[0500] To achieve good error correction performance, a rule of thumb is to decode blocks with sufficient capacity first, and then decode blocks with insufficient capacity.

[0501]

[0502] An overview of the proposed coding structure and a comparison with existing channel-dependent codes are shown below:

[0503]

[0504] Various aspects of the present invention include:

[0505] 1. Flexible decoding order The decoder has several options in determining which blocks to decode first and the subsequent decoding order. Decoding can be performed block by block or by jumping between different blocks.

[0506] 2. Variable coding rate blocks When viewed in different subspaces, each block can have a variable coding rate. However, these variable coding rate codes should have the same length.

[0507] 3. Block coupling Multiple code blocks need to be coupled to allow for the flow of mutual information between blocks during decoding. There are many ways to achieve this coupling.

[0508] 4. Transmission order In the case of variable-length codes, the code bits need to be sent in a carefully designed order to ensure balanced performance across different lengths.

[0509] It should be noted that the above points are not necessarily only related to specific codes (e.g., LDPC codes or polar codes), but are applicable to a wide range of codes, including algebraic codes, convolutional codes, polar codes, and probabilistic codes (Turbo codes or LDPC codes).

[0510] Flexible decoding order

[0511] The decoding order of multiple blocks and their internal bits is not predetermined, but can be adaptively adjusted according to changes in channel conditions.

[0512] The decoding order can be determined by the ratio of block-level coding rate to capacity, where

[0513] The coding rate is the ratio of an unknown number of bits to the block length. This coding rate changes during the decoding process as more and more bits in the block are decoded.

[0514] • Capacity can be the total bit channel capacity of the corresponding code bits in the block. As other blocks are decoded, mutual information about the block will flow in, thus increasing the block-level capacity.

[0515] Based on the definition of block-level coding rate and capacity ratio, the decoding order is as follows:

[0516] Always decode the block with the lowest coding rate to capacity ratio;

[0517] • Update the coding rate and capacity ratio of each block during the decoding process (because they will change).

[0518] There are four ways to represent the decoding order:

[0519] • A sequence consisting of the indices of variable nodes;

[0520] • A sequence consisting of the indices of the check nodes;

[0521] • A sequence of block indices;

[0522] • A sequence consisting of index jump points between two blocks;

[0523] The check nodes and variable nodes are defined in the code's factor graph, as shown below:

[0524]

[0525] Variable coding rate blocks

[0526] To adapt to constantly changing channel conditions, blocks need to have a variable coding rate. Specifically, although (sub)code blocks have been constructed and encoded, and have... Fixed length However, different subspaces of the codespace can have different coding rates. By definition, a subcode is a subset of the codewords in the parent code.

[0527] In a nested code block structure, a low-rate code is a sub-code of a high-rate code of the same length, as shown below. In practical applications, BCH codes, polar codes, and LDPC codes can all be constructed as variable-rate blocks.

[0528]

[0529] To construct variable coding rate codes, we need to design specific information bit mapping methods.

[0530] • To facilitate the flow of mutual information between different blocks, some information bits can be shared among multiple blocks.

[0531] In variable coding rate codes, the high, medium, and low coding rate subcodes have corresponding sets of information bits, among which...

[0532] The information bits of a low-coding-rate subcode are a subset of the information bits of a high-coding-rate subcode.

[0533] • Information bits of low-code-rate subcodes can be exclusively used within a single block, but additional information bits of higher-code-rate subcodes can be shared across multiple blocks. The rule is that as the subcode-rate increases, the additional information bits will be shared by more blocks.

[0534] The mapping method described above is applicable to various channel code types, such as BCH codes, polar codes, and LDPC codes. See the diagram below:

[0535]

[0536] Block coupling

[0537] There are many ways to achieve block coupling. Some methods may have the same essence but manifest differently.

[0538] In the most general case, any code can be represented by a factor graph, consisting of variable nodes and check nodes.

[0539] Variable nodes can be divided into three types:

[0540] • Information variable nodes, i.e., information / system / payload bits;

[0541] • The transmitted variable nodes, i.e., code bits. It should be noted that system bits are information bits, but they can also be transmitted bits;

[0542] • Hidden variable nodes, which are intermediate or auxiliary bits in the encoding and decoding process. These nodes are not sent and are not information bits.

[0543]

[0544] Coupling can occur between two variable nodes v i v j Or two variable node sets {v i1 ,v i2 ,…} and {v j1 ,v j2 Between , ...}. There are two types of coupling:

[0545] • Coupling of the same value: v i =v j or {v i1 ,v i2 ,…}={v j1 ,v j2 ,…};

[0546] • Mapping function coupling: v i =f(v j ) or (v i1 ,v i2 ,…)=f(v j1 ,vj2 ,…), where the function is predefined and both the encoder and decoder are known.

[0547] Using variable nodes as a coupling method, we can obtain the following methods and their combinations.

[0548] Couple information variable nodes with other information variable nodes;

[0549] Couple the information variable node with the sent variable node;

[0550] Couple information variable nodes with hidden variable nodes;

[0551] • Couple the sent variable nodes with the sent variable nodes;

[0552] • Couple the sent variable nodes with the hidden variable nodes;

[0553] Couple hidden variable nodes with hidden variable nodes.

[0554] Using verification nodes as a coupling method, we can obtain the following methods and their combinations.

[0555] ·degrees d c A check node with a value of 2 connects two blocks where the two connected variable nodes have the same value.

[0556] ·degrees d c A check node with a value of >2 connects two blocks;

[0557] ·degrees d c A check node with a value greater than 2 has more than two blocks connected;

[0558]

[0559] In addition to coupling in the binary domain, coupling can also be performed in the symbol domain. The code bits are modulated into QAM symbols and transmitted simultaneously in the air, as shown below.

[0560]

[0561] Transmission order

[0562] The transmission order can be represented in a variety of ways using an ordered sequence.

[0563] • Use bits (or variable nodes) to index sequences;

[0564] • Use block index sequences;

[0565] • Use a sequence of block indexes, where a block index may appear multiple times (implying a jump between blocks), and combine it with a subset of bit indices to indicate where to jump out of one block and where to enter another;

[0566] Ordered sequences can be designed to minimize the difference between overall block-level coding rate and capacity, while still maintaining local decodeability.

[0567] This invention represents a fundamental upgrade to polar codes and makes them applicable to a wider range of scenarios. It is a core component of channel coding schemes, suitable for any scenario using channel coding. This covers a very broad range of scenarios. The flexibility provided by this invention makes the associated channel coding schemes particularly suitable for wireless communication.

[0568] This invention can be applied to products such as BS, UE, robots, sensors, automobiles, drones, and satellites, as well as to services such as eMBB, URLLC, mMTC / IoT, automotive, and industrial scenarios.

[0569] Through the general process described above, there are numerous code types that can be decoded using channel-dependent methods. In practical applications, we will use the following example.

[0570] Example 1 (Point-to-Point Channel)

[0571] We will first describe an example using extended BCH (or eBCH) codes, as shown below.

[0572]

[0573] The combined code consists of three blocks, each of which is an eBCH code.

[0574] The first and third eBCH codes have lower coding rates, while the second eBCH code has a higher coding rate.

[0575] • Perform an XOR operation between the second eBCH code and the first and third eBCH codes to generate the code bits to be transmitted.

[0576] The code bits of the second eBCH code are transmitted directly.

[0577] It can be seen that the second eBCH code has the highest coding rate and the highest capacity. The first and third eBCH codes have the lowest coding rates but lower capacities. Their block-level coding rate-capacity ratios are: R1 / C1, R2 / C2, and R3 / C3.

[0578] Assuming the three eBCH codes have the same length and pass through the same channel, then R1 = R3. <R2、C1=C3<C2。

[0579] · If R2 / C2 < R1 / C1, then first decode the second eBCH code, and then decode the other two eBCH codes;

[0580] · If R2 / C2 > R1 / C1, then first decode the first eBCH code and the third eBCH code, and then decode the second eBCH code;

[0581] Assume that the three eBCH codes have the same length but pass through different channels, then it can be obtained that R1 < R3 < R2, C3 < C1 < C2.

[0582] · If R1 / C1 < R3 / C3, then first decode the third eBCH code;

[0583] · Then, we recalculate the block-level coding rate capacity ratios of the remaining two eBCH codes:

[0584] o If R’1 / C’1 < R’2 / C’2, then next decode the first eBCH code and finally decode the second eBCH code;

[0585] o If R’1 / C’1 > R’2 / C’2, then next decode the second eBCH code and finally decode the first eBCH code;

[0586] eBCH codes are very good candidates because they natively support variable coding rates. For eBCH codes with a length of 64, they have the following coding rates, where the lower coding rate codes are subcodes of the higher coding rate codes.

[0587] N <![CDATA[K1]]> <![CDATA[K2]]> <![CDATA[K3]]> <![CDATA[K4]]> <![CDATA[K5]]> <![CDATA[K6]]> <![CDATA[K7]]> <![CDATA[K8]]> <![CDATA[K9]]> <![CDATA[K 10 ]]> <![CDATA[K 11 ]]> <![CDATA[K 12 ]]> 64 2 8 11 17 19 25 31 37 40 46 52 58

[0588] The above table is prior knowledge, but when we map information bits to eBCH codes, we can use the new method we proposed. According to the above method, we assign different information bits to the three eBCH codes until K = 25, and then assign the same information bits to more than one eBCH code until K = 37.

[0589] Embodiment 2 (multiple access channel)

[0590] We also describe a scenario: each block is encoded and modulated separately by devices separated by geographical locations.

[0591] Similarly, we can use variable coding rate code construction for the blocks and calculate the block-level coding rate and capacity ratios of all blocks. It should be noted that for a multiple access channel, the demodulation order affects the capacity perceived by each block. Therefore, we can compare the block-level coding rate and capacity ratios under all possible demodulation orders, and find the lowest block-level coding rate and capacity ratio corresponding to a specific demodulation order. After demodulating and decoding the block, it is necessary to update and recalculate the remaining block-level coding rate and capacity ratios.

[0592]

[0593] In the example above, the three LDPC codes are coupled not only in the signal domain but also in the binary domain in the following way: the source bits of the three LDPC codes are correlated;

[0594] • Use the above method to couple the source bits of the three LDPC codes.

[0595] • Use the above method to couple the check functions of the three LDPC codes.

[0596] By creating a channel-dependent coding structure, channel codes can better adapt to changes in channel state.

[0597] Abbreviations and key terms

[0598]

[0599]

[0600] Channel coding is designed to address the uncertainties that arise when a signal passes through a noisy channel.

[0601] Channel conditions can include channel gain / fading, additive noise, and interference.

[0602] Channel-independent coding design means that the code construction, encoding, and decoding processes are independent of specific channel conditions.

[0603] Channel-dependent coding design means that any of the code construction, encoding, or decoding schemes is aware of specific channel conditions and is designed or implemented accordingly.

[0604] Cross-references to related applications

[0605] This application relates to the following Patent Cooperation Treaty (PCT) applications filed together by the same applicant on the same date:

[0606] PCT application entitled “Methods, Systems, and Apparatus for Non-Sequential Decoding of Polar Codes”;

[0607] PCT application entitled “Methods, Systems, and Apparatus for Bit Value Placement in Polar Coding”;

[0608] PCT application entitled “Methods, Systems, and Apparatus for Encoded Bit Reduction in Polar Coding”;

[0609] PCT application entitled "Methods, Systems, and Apparatus for Protograph-based Low Density Parity Check Coding" is filed with this application. This application also relates to the following U.S. provisional patent application, also filed on the same date:

[0610] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Partial Code Rate Reduction in Polar Coding”;

[0611] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding”;

[0612] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Low-complexity Decoding”;

[0613] A U.S. provisional patent application entitled “Methods, Systems, and Apparatus for Rateless Polar Coding and Incremental Redundancy”.

Claims

1. A method, characterized in that, include: The input bits are encoded to obtain encoded bit blocks, each of which has a corresponding associated coding rate and a corresponding associated capacity. The coded bit block comprises nested blocks, each nested block comprising a sub-code of another coded bit block, the other coded bit block having a higher corresponding associative coding rate than the nested block. The nested blocks include mutually coupled coupling blocks. The method further includes: Output the encoded bit block.

2. The method according to claim 1, characterized in that, The coupling blocks are coupled to each other through the coupling between the variable nodes associated with the coupling blocks.

3. The method according to claim 2, characterized in that, The variable nodes are coupled through the verification nodes.

4. The method according to claim 1, characterized in that, The coupling blocks are coupled to each other by combining the coded bits associated with the coupling blocks.

5. The method according to claim 1, characterized in that, The coupling blocks are coupled to each other by combining the input bits associated with the coupling blocks.

6. The method according to claim 1, characterized in that, The coupling blocks are coupled to each other by the same bit value as the input bits associated with the coupling block.

7. The method according to claim 6, characterized in that, The encoding includes encoding the input bits using polar codes to obtain the encoded bits. The polar codes include a plurality of bit indices for placing bit values ​​before encoding. The bit indices include: a first set of bit indices for placing the values ​​of the input bits and a second set of bit indices for placing predetermined bit values. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in the coupled block and a second subset of bit indices associated with a second coupled block in the coupled block, the second coupled block being coupled to the first coupled block. The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset.

8. The method according to any one of claims 1 to 7, characterized in that, Also includes: The coded bit blocks are sorted based on their respective associated coding rates and associated capacities.

9. The method according to claim 8, characterized in that, The sorting includes: sorting the coded bit blocks in ascending order according to the ratio of the corresponding associated coding rate of each coded bit block to the corresponding associated capacity of each coded bit block.

10. The method according to any one of claims 1 to 9, characterized in that, The value of the input bit can be decoded from the coded bit block according to a non-sequential decoding order, the non-sequential decoding order being based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block.

11. The method according to any one of claims 1 to 10, characterized in that, The coded bit block comprises a block, wherein the corresponding associated coding rate, the corresponding associated capacity, or both the corresponding associated coding rate and the corresponding associated capacity of the block are variable and change as another coded bit block is decoded.

12. The method according to any one of claims 1 to 11, characterized in that, Also includes: The coded bit block is transmitted from a first communication device to a second communication device in a wireless communication network.

13. A method, characterized in that, include: Receive coded bit blocks obtained by encoding input bits, each coded bit block having a corresponding associated coding rate and a corresponding associated capacity. The coded bit block comprises nested blocks, each nested block comprising a sub-code of another coded bit block, the other coded bit block having a higher corresponding associative coding rate than the nested block. The nested blocks include mutually coupled coupling blocks. The method further includes: The encoded bits are decoded to obtain the decoded input bits.

14. The method according to claim 13, characterized in that, The coupling blocks are coupled to each other through the coupling between the variable nodes associated with the coupling blocks.

15. The method according to claim 14, characterized in that, The variable nodes are coupled through the verification nodes.

16. The method according to claim 13, characterized in that, The coupling blocks are coupled to each other by combining the coded bits associated with the coupling blocks.

17. The method according to claim 13, characterized in that, The coupling blocks are coupled to each other by combining the input bits associated with the coupling blocks.

18. The method according to claim 13, characterized in that, The coupling blocks are coupled to each other by the same bit value as the input bits associated with the coupling block.

19. The method according to claim 18, characterized in that, The encoded bits are obtained by encoding the input bits using polar codes. The polar codes include multiple bit indices for placing bit values ​​before encoding. Each bit indices includes a first set of bit indices for placing the values ​​of the input bits and a second set of bit indices for placing predetermined bit values. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in the coupled block and a second subset of bit indices associated with a second coupled block in the coupled block, the second coupled block being coupled to the first coupled block. The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset.

20. The method according to any one of claims 13 to 19, characterized in that, The receiving includes receiving the coded bit blocks in order based on the corresponding associated coding rate and the corresponding associated capacity for each coded bit block.

21. The method according to claim 20, characterized in that, The decoding includes decoding the encoded bit blocks in an order different from the order in which the encoded bit blocks were received.

22. The method according to any one of claims 13 to 20, characterized in that, The decoding includes decoding the coded bit blocks in ascending order of the ratio of the corresponding associated coding rate to the corresponding associated capacity of each coded bit block.

23. The method according to any one of claims 13 to 20, characterized in that, The decoding includes: decoding the value of the input bit from the coded bit block according to a non-sequential decoding order, the non-sequential decoding order being based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block.

24. The method according to any one of claims 13 to 23, characterized in that, The coded bit block comprises a block, wherein the corresponding associated coding rate, the corresponding associated capacity, or both the corresponding associated coding rate and the corresponding associated capacity of the block are variable and change as another coded bit block is decoded.

25. The method according to claim 24, characterized in that, Also includes: When decoding other coded bit blocks, for the block, the corresponding associated coding rate is updated to the corresponding updated coding rate, and the corresponding associated capacity is updated to the corresponding updated capacity, or both the corresponding associated coding rate and the corresponding associated capacity are updated to the corresponding updated coding rate and the corresponding updated capacity, wherein... The decoding includes decoding the block in an order based on the corresponding update coding rate, the corresponding update capacity, or both the corresponding update coding rate and the corresponding update capacity.

26. The method according to any one of claims 13 to 25, characterized in that, The receiving includes: in a wireless communication network, a second communication device receiving the coded bit block from a first communication device.

27. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 1 to 12.

28. An apparatus, characterized in that, include: An encoder is used to encode input bits to obtain coded bit blocks, each of which has a corresponding associated coding rate and a corresponding associated capacity. The coded bit block comprises nested blocks, each nested block comprising a sub-code of another coded bit block, the other coded bit block having a higher corresponding associative coding rate than the nested block. The nested blocks include mutually coupled coupling blocks. The device further includes: An interface coupled to the encoder is used to output the encoded bit block.

29. The apparatus according to claim 28, characterized in that, The coupling blocks are coupled to each other through the coupling between the variable nodes associated with the coupling blocks.

30. The apparatus according to claim 29, characterized in that, The variable nodes are coupled through the verification nodes.

31. The apparatus according to claim 28, characterized in that, The coupling blocks are coupled to each other by combining the coded bits associated with the coupling blocks.

32. The apparatus according to claim 28, characterized in that, The coupling blocks are coupled to each other by combining the input bits associated with the coupling blocks.

33. The apparatus according to claim 28, characterized in that, The coupling blocks are coupled to each other by the same bit value as the input bits associated with the coupling block.

34. The apparatus according to claim 33, characterized in that, The encoder is used to encode the input bits using polar codes to obtain the encoded bits. The polar codes include a plurality of bit indices for placing bit values ​​before encoding. The bit indices include: a first set of bit indices for placing the values ​​of the input bits and a second set of bit indices for placing predetermined bit values. The first set of bit indices includes a first subset of bit indices associated with a first coupling block in the coupling block and a second subset of bit indices associated with a second coupling block in the coupling block, the second coupling block being coupled to the first coupling block. The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset.

35. The apparatus according to any one of claims 28 to 34, characterized in that, The encoder is used to sort the encoded bit blocks based on the corresponding associated coding rate and the corresponding associated capacity of each encoded bit block.

36. The apparatus according to claim 35, characterized in that, The encoder is used to sort the coded bit blocks in ascending order of the ratio of the corresponding associated coding rate of each coded bit block to the corresponding associated capacity of each coded bit block.

37. The apparatus according to any one of claims 28 to 36, characterized in that, The input bit value can be decoded from the coded bit block according to a non-sequential decoding order, the non-sequential decoding order being based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block.

38. The apparatus according to any one of claims 28 to 37, characterized in that, The coded bit block comprises a block, wherein the corresponding associated coding rate, the corresponding associated capacity, or both the corresponding associated coding rate and the corresponding associated capacity of the block are variable and change as another coded bit block is decoded.

39. The apparatus according to any one of claims 28 to 38, characterized in that, The interface is used to send the coded bit block from a first communication device in a wireless communication network to a second communication device.

40. An apparatus, characterized in that, Includes a processor for causing the device to perform the method according to any one of claims 13 to 26.

41. An apparatus, characterized in that, include: An interface is provided for receiving encoded bit blocks obtained by encoding input bits, each of which has a corresponding associated coding rate and a corresponding associated capacity. The coded bit block comprises nested blocks, each nested block comprising a sub-code of another coded bit block, the other coded bit block having a higher corresponding associative coding rate than the nested block. The nested blocks include mutually coupled coupling blocks. The device further includes: A decoder coupled to the interface is used to decode the encoded bits to obtain the decoded input bits.

42. The apparatus according to claim 41, characterized in that, The coupling blocks are coupled to each other through the coupling between the variable nodes associated with the coupling blocks.

43. The apparatus according to claim 42, characterized in that, The variable nodes are coupled through the verification nodes.

44. The apparatus according to claim 41, characterized in that, The coupling blocks are coupled to each other by combining the coded bits associated with the coupling blocks.

45. The apparatus according to claim 41, characterized in that, The coupling blocks are coupled to each other by combining the input bits associated with the coupling blocks.

46. ​​The apparatus according to claim 41, characterized in that, The coupling blocks are coupled to each other by the same bit value as the input bits associated with the coupling block.

47. The apparatus according to claim 46, characterized in that, The encoded bits are obtained by encoding the input bits using polar codes. The polar codes include multiple bit indices for placing bit values ​​before encoding. The bit indices include: a first set of bit indices for placing the values ​​of the input bits and a second set of bit indices for placing predetermined bit values. The first set of bit indices includes a first subset of bit indices associated with a first coupled block in the coupled block and a second subset of bit indices associated with a second coupled block in the coupled block, which is coupled to the first coupled block. The value of the input bit includes the same bit value placed at the first bit index in the first subset and the second bit index in the second subset.

48. The apparatus according to any one of claims 41 to 47, characterized in that, The interface is used to receive the coded bit blocks in order based on the corresponding associated coding rate and the corresponding associated capacity for each coded bit block.

49. The apparatus according to claim 48, characterized in that, The decoder is used to decode the encoded bit blocks in an order different from the order in which the encoded bit blocks were received.

50. The apparatus according to any one of claims 41 to 48, characterized in that, The decoder is used to decode the coded bit blocks in ascending order of the ratio of the corresponding associated coding rate to the corresponding associated capacity of each coded bit block.

51. The apparatus according to any one of claims 41 to 48, characterized in that, The decoder is used to decode the input bit value from the coded bit block according to a non-sequential decoding order based on the corresponding associated coding rate and the corresponding associated capacity of each coded bit block.

52. The apparatus according to any one of claims 41 to 51, characterized in that, The coded bit block comprises a block, wherein the corresponding associated coding rate, the corresponding associated capacity, or both the corresponding associated coding rate and the corresponding associated capacity of the block are variable and change as another coded bit block is decoded.

53. The apparatus according to claim 52, characterized in that, The decoder is used for: When decoding other coded bit blocks, for the block, the corresponding associated coding rate is updated to the corresponding updated coding rate, and the corresponding associated capacity is updated to the corresponding updated capacity; or both the corresponding associated coding rate and the corresponding associated capacity are updated to the corresponding updated coding rate and the corresponding updated capacity. The block is decoded in the order of the corresponding update coding rate, the corresponding update capacity, or both the corresponding update coding rate and the corresponding update capacity.

54. The apparatus according to any one of claims 41 to 53, characterized in that, The receiving includes: receiving the coded bit block from the first communication device via a second communication device in a wireless communication network.

55. A computer program, characterized in that, Includes a program for execution by a processor, the program including instructions for performing the method according to any one of claims 1 to 26.

56. A non-transitory computer-readable medium, characterized in that, The program is stored for execution by a processor, the program including instructions for performing the method according to any one of claims 1 to 26.

57. A system, characterized in that, include: A first communication device is configured to transmit coded bit blocks obtained by encoding input bits, each coded bit block having a corresponding associated coding rate and a corresponding associated capacity. The coded bit blocks include nested blocks, each nested block including a sub-code of another coded bit block, the other coded bit block having a higher corresponding associated coding rate than the nested block. The nested blocks include coupled blocks that are mutually coupled. A second communication device is configured to receive the encoded bit block from the first communication device and decode the encoded bit block to obtain the decoded input bits.

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