Array substrate, preparation method thereof and display panel
By designing an array substrate with single-layer wiring, the problems of low detection efficiency and high defect rate of FIC panels were solved, achieving more efficient detection and lower-cost production, and improving display effect and product quality.
Patent Information
- Application Number
- CN202410534036.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-11-04
AI Technical Summary
Existing embedded touch panels (FIC panels) have low inspection efficiency and high product defect rate, and the laser cleaning process adds steps and may cause metal residue.
Design an array substrate that uses a single-layer fan-shaped wiring area to avoid crossover of adapter lines and eliminate the need for laser cleaning process. Connect data pins and control pins through adapter lines set on the same layer to improve signal uniformity.
It improved testing efficiency, reduced costs, decreased product defect rates, and enhanced display effects and product quality.
Smart Images
Figure CN120891679A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and its preparation method, and a display panel. Background Technology
[0002] With the continuous advancement of flat panel display technology, liquid crystal displays (LCDs) have been successfully applied to display devices such as notebooks, monitors, and TVs. Each liquid crystal pixel on an LCD is driven by a thin-film transistor integrated behind it. Based on their working principle, touchscreens can be divided into four main categories: resistive, capacitive, infrared, and surface acoustic wave (SAW) touchscreens. Among these, resistive and capacitive touchscreens are widely used, while projected capacitive touchscreens are widely applied due to their ability to achieve multi-touch. However, resistive and capacitive touchscreens suffer from drawbacks such as high cost and bulkiness, making low cost and thinness the new trend in the touchscreen field. In-cell touch is a technology that integrates touch and display functions, combining the touch panel with the LCD display. It offers advantages such as integration, thinness, low cost, low power consumption, high image quality, and the ability to achieve multi-touch. In-cell touch technology includes resistive, capacitive, and optical types.
[0003] Full-in-Cell Touch (FIC) panels are widely used in the field of LCD touch displays. In related technologies, FIC panels require substrate inspection (also called array inspection) and panel inspection (also called cell inspection). Substrate inspection involves checking the continuity of circuits on the array substrate, while panel inspection involves checking the display image on the display panel, including the array substrate, to ensure the yield of the final display device. However, in related technologies, FIC panel inspection efficiency is relatively low, resulting in a relatively high product defect rate. Summary of the Invention
[0004] This disclosure provides an array substrate and its fabrication method, as well as a display panel, to solve or alleviate one or more technical problems in the prior art.
[0005] As a first aspect of the present disclosure, the present disclosure provides an array substrate, including a display area, a bonding area, and a fan-shaped trace area located between the display area and the bonding area, wherein the display area is provided with multiple data lines and multiple touch signal lines;
[0006] The bonding area is provided with multiple data pins and multiple control pins, and the multiple data pins and multiple control pins are spaced apart from each other along a first direction;
[0007] The fan-shaped wiring area is equipped with multiple first adapter wires and multiple second adapter wires. The multiple first adapter wires and multiple second adapter wires are arranged at intervals along the first direction. The multiple first adapter wires and multiple second adapter wires are located on the same layer. The corresponding data lines and data pins are connected through the first adapter wires, and the corresponding touch signal lines and touch pads are connected through the second adapter wires.
[0008] In some embodiments, the array substrate has a first edge located on the side of the bonding area away from the display area. The array substrate also includes multiple data extension lines and multiple touch extension lines. The data extension lines extend from one end of a data pin to the first edge, and the touch extension lines extend from one end of a control pin to the first edge.
[0009] In some embodiments, multiple data lines are arranged along a first direction and extend along a second direction, multiple touch signal lines are arranged along the first direction and extend along the second direction, the multiple data lines and multiple touch signal lines are spaced apart from each other, and the second direction intersects the first direction.
[0010] In some embodiments, the display area is provided with a plurality of sub-pixels arranged in an array, two columns of sub-pixels are provided between two adjacent data lines, and the touch signal line is located between the two columns of sub-pixels between two adjacent data lines.
[0011] In some embodiments, the display area is provided with a plurality of sub-pixels arranged in an array, and two columns of sub-pixels are provided between two adjacent data lines. When sub-pixels are provided on both sides of the data line, the data line is coupled to the thin-film transistors in the sub-pixels on both sides.
[0012] The display area is also provided with multiple pairs of gate lines, which correspond one-to-one with multiple rows of sub-pixels. The two gate lines corresponding to the row sub-pixels are located on both sides of the row sub-pixels. The thin film transistors in a part of the row sub-pixels are coupled to the first gate line of the two gate lines, and the thin film transistors in another part of the sub-pixels are coupled to the second gate line.
[0013] In some embodiments, the display area is further provided with multiple grid lines, and the first adapter line and the second adapter line are both located on the same layer as the grid lines.
[0014] In some embodiments, both the data pins and the control pins are located on the same layer as the first adapter cable and the second adapter cable.
[0015] In some embodiments, the array substrate includes a substrate and a first transparent electrode layer located on one side of the substrate. The first transparent electrode layer includes a plurality of electrode blocks arranged in an array. The plurality of electrode blocks are connected one-to-one with a plurality of touch signal lines. The display area is provided with a plurality of sub-pixels arranged in an array. The electrode blocks are provided with a plurality of sub-pixels in the orthographic projection area on the substrate.
[0016] In some embodiments, a common electrode signal is applied to the electrode block during the display of frames on the display panel, and a touch signal is applied to the electrode block between two frames on the display panel.
[0017] In some embodiments, the array substrate further includes a first metal layer, which is disposed in the same layer as the first transparent electrode layer. The electrode block includes a plurality of sub-electrode blocks. The first metal layer includes a gate line and a first electrode connection line. The first electrode connection line extends along a first direction in the region of the electrode block. The boundary of the sub-electrode block along the first direction overlaps with the first electrode connection line. The plurality of sub-electrode blocks arranged along a second direction in the region of the electrode block are interconnected.
[0018] In some embodiments, the array substrate further includes a first insulating layer, a second metal layer, a second insulating layer, and a second transparent electrode layer sequentially stacked on the side of the first metal layer and the first transparent electrode layer facing away from the substrate.
[0019] The second metal layer includes a touch signal line, the second transparent electrode layer includes a second electrode connection line, and the array substrate also includes a first via. The orthographic projection of the first via on the substrate intersects with the orthographic projection of the touch signal line on the substrate, and the orthographic projection of the first via on the substrate intersects with the orthographic projection of the first electrode connection line on the substrate. The second electrode connection line is connected to the touch signal line and the first electrode connection line through the first via.
[0020] In some embodiments, the second metal layer further includes a third electrode connection line, and the second transparent electrode layer further includes a fourth electrode connection line. The third electrode connection line extends along a second direction within the region of the electrode block and is located between two adjacent columns of sub-pixels. The array substrate further includes a second via. The orthographic projection of the second via on the substrate intersects with the orthographic projection of the third electrode connection line on the substrate. The orthographic projection of the second via on the substrate intersects with the orthographic projection of the first electrode connection line on the substrate. The fourth electrode connection line is connected to the third electrode connection line and the first electrode connection line through the second via.
[0021] As a second aspect of the present disclosure, the present disclosure provides a display panel including an array substrate according to any embodiment of the present disclosure.
[0022] As a third aspect of this disclosure, this disclosure provides a method for fabricating an array substrate, comprising:
[0023] A motherboard is fabricated, comprising a substrate region defined by a first cutting line, a second cutting line, a third cutting line, and a fourth cutting line connected sequentially. The first and third cutting lines extend along a first direction, and the second and fourth cutting lines extend along a second direction, intersecting the first direction. The substrate region includes a display area and a bonding area, with the bonding area located between the display area and the first cutting line. The substrate region also includes a fan-shaped trace area located between the display area and the bonding area. The display area is provided with multiple data lines and multiple touch signal lines. The bonding area is provided with multiple data pins and multiple control pins, which are spaced apart from each other along the first direction. The fan-shaped trace area is provided with multiple first adapter lines and multiple second adapter lines. Corresponding data lines and data pins are connected through the first adapter lines, and corresponding touch signal lines and touch pads are connected through the second adapter lines.
[0024] The motherboard also includes a first metal trace, a second metal trace, and a third metal trace located on the side of the first cutting line away from the substrate region. The first metal trace is connected to a portion of a plurality of data pins, the second metal trace is connected to another portion of a plurality of data pins, and the third metal trace is connected to a plurality of control pins.
[0025] A first detection signal is applied to the first metal trace and the second metal trace, and a second detection signal is applied to the third metal trace to detect the substrate area;
[0026] Cutting is performed along the first cutting line, the second cutting line, the third cutting line and the fourth cutting line to obtain an array substrate located in the substrate region.
[0027] In some embodiments, a first metal trace is connected to an even number of data pins among a plurality of data pins, and a second metal trace is connected to an odd number of data pins among a plurality of data pins.
[0028] In some embodiments, the first metal trace and the second metal trace are located on the same layer as the data line, and the third metal trace is located on the same layer as the gate line in the array substrate.
[0029] The technical solution of this embodiment of the invention involves an array substrate in which multiple first adapter lines and multiple second adapter lines are spaced apart from each other along a first direction, and multiple data pins and multiple control pins are also spaced apart from each other along the first direction. Thus, along the first direction, the first adapter lines, second adapter lines, data pins, and control pins can correspond one-to-one and be connected. The multiple first adapter lines and multiple second adapter lines in the fan-shaped trace area are spaced apart from each other along the first direction, avoiding intersections between the first and second adapter lines. Therefore, the first and second adapter lines can be arranged on the same layer, and the fan-shaped trace area can use a single-layer wiring method, avoiding overlapping capacitance, which is beneficial to the uniformity of data signals and improves the display effect. Furthermore, this array substrate no longer has a laser cleaning area, thus eliminating the need for a laser cleaning process, reducing process steps, lowering costs, and avoiding product defects caused by metal residue, thereby improving product quality.
[0030] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description
[0031] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.
[0032] Figure 1 This is a cross-sectional schematic diagram of a FIC panel;
[0033] Figure 2 for Figure 1 A planar schematic diagram of the array substrate;
[0034] Figure 3 This is a planar schematic diagram of an array substrate motherboard in related technologies;
[0035] Figure 4 for Figure 3 A schematic diagram of the planar connection of the array substrate;
[0036] Figure 5 for Figure 3 A partial schematic diagram;
[0037] Figure 6 This is a planar schematic diagram of an array substrate according to an embodiment of the present disclosure;
[0038] Figure 7A This is a planar schematic diagram of the array substrate in another embodiment of the present disclosure;
[0039] Figure 7B This is a schematic diagram of an electrode block in another embodiment of the present disclosure;
[0040] Figure 8 for Figure 7A A magnified schematic diagram of a portion of M in the image;
[0041] Figure 9 for Figure 8 Schematic diagram of section AA in the diagram;
[0042] Figure 10 for Figure 8 A schematic diagram of the BB or EE cross section in the diagram;
[0043] Figure 11 for Figure 8 Schematic diagram of the CC section in the diagram;
[0044] Figure 12 for Figure 8 Schematic diagram of the DD section in the diagram;
[0045] Figure 13 This is a planar schematic diagram of the array substrate mother plate in one embodiment of the present disclosure;
[0046] Figure 14 for Figure 13 A partial schematic diagram;
[0047] Figure 15 for Figure 14 A schematic diagram of the FF cross-section in one embodiment.
[0048] Explanation of reference numerals in the attached figures:
[0049] 10. Array substrate; 101. First dicing line; 102. Second dicing line; 103. Third dicing line; 11. Substrate; 12. First transparent electrode layer; 121. Electrode block; 13. First metal layer; 14. First insulating layer; 131. Gate line; 132. First electrode connection line; 15. Second metal layer; 153. Third electrode connection line; 16. Second insulating layer; 17. Second transparent electrode layer; 172. Second electrode connection line; 174. Fourth electrode connection line; 175. Auxiliary electrode connection line;
[0050] 20. Color filter substrate; 30. Liquid crystal;
[0051] 31. First metal trace; 32. Second metal trace; 33. Third metal trace; 34. Fourth metal trace; 35. Fifth metal trace;
[0052] 41. First inspection pad; 42. Second inspection pad; 43. Third inspection pad; 44. Fourth inspection pad; 45. Fifth inspection pad; 46. Sixth inspection pad; 47. Seventh inspection pad;
[0053] 51. First adapter cable; 52. Second adapter cable. Detailed Implementation
[0054] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.
[0055] Figure 1 This is a cross-sectional schematic diagram of a FIC panel. Figure 2 for Figure 1 A planar schematic diagram of the array substrate. (See attached diagram.) Figure 1 and Figure 2 As shown, the FIC panel includes an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and liquid crystal located between the array substrate 10 and the color filter substrate 20. The array substrate 10 includes a planar common electrode layer 12, which is divided into multiple electrode blocks 121. The multiple electrode blocks 121 are arranged in an array, and each electrode block 121 serves as a touch sensing electrode. Each electrode block 121 is connected to a separate touch line, i.e., a Tx line, which is connected to a chip-on-film (COF) chip. During the touch phase, the COF provides touch signals to the electrode blocks 121 through the Tx lines and receives capacitance changes to determine the touch position. During the display phase, the COF provides a common signal, i.e., a Vcom signal, to the electrode blocks 121 through the Tx lines for normal display.
[0056] Figure 3 This is a planar schematic diagram of an array substrate motherboard in related technologies. Figure 4 for Figure 3 A schematic diagram of the planar connections of the array substrate. Figure 5 for Figure 3 A partial schematic diagram is shown. It should be noted that... Figure 3 and Figure 4 The same fill pattern is used to indicate the connected traces. That is to say, traces with the same fill pattern are connected to each other. The fill pattern of the trace does not indicate the film layer in which the trace is located. Figure 5 In this context, traces located in the same layer use the same fill pattern; that is, traces with the same fill pattern are located in the same film layer. For example... Figure 3As shown, the array substrate 10 motherboard is provided with a first cutting line 101, a second cutting line 102, a third cutting line (not shown in the figure), and a fourth cutting line 104 connected in sequence. The portion defined by the first cutting line 101, the second cutting line 102, the third cutting line (not shown in the figure), and the fourth cutting line 104 is the array substrate 10. The array substrate 10 includes a display area AA, and below the display area AA is a fan-shaped wiring area (…). Figure 3 The traces of the sector area (not shown) and the bonding area BA are provided. The bonding area BA is equipped with pads, which are used to bond and connect with the corresponding COF.
[0057] like Figure 3 As shown, the bonding area BA has multiple data pins DP and multiple control pins CP. The bonding area BA includes a data area DA, a first control area CA1, and a second control area CA2, located to the left and right of the data area DA, respectively. Multiple data pins DP are arranged sequentially in the data area DA, and multiple control pins CP are distributed in the first control area CA1 and the second control area CA2. The multiple control pins CP located in the first control area CA1 are arranged sequentially, and the multiple control pins CP located in the second control area CA2 are arranged sequentially.
[0058] like Figure 3 As shown, the motherboard also includes a first metal trace 31 and a second metal trace 32 located below the first cutting line 101, i.e., outside the array substrate 10. The data pins DP can be divided into odd-numbered data pins DPO and even-numbered data pins DPE according to their positions. The positions are defined from one side of the data area DA, with data pins located at odd positions being odd-numbered data pins DPO and data pins located at even positions being even-numbered data pins DPE.
[0059] Odd-numbered data pins DPO are all connected to the first metal trace 31, and even-numbered data pins DPE are all connected to the second metal trace 32. Both the first metal trace 31 and the second metal trace 32 extend along the first direction X. The array substrate 10 also includes a laser trimming region TA (i.e., a laser trimming region) located between the first dicing line 101 and the bonding region BA. The laser trimming region TA is provided with a third metal trace 33, a fourth metal trace 34, and a fifth metal trace 35. Odd-numbered data pins DPO are also connected to the fourth metal trace 34, and even-numbered data pins DPE are also connected to the fifth metal trace 35. The control pin CP is connected to the third metal trace 33.
[0060] like Figure 3As shown, the motherboard also includes a first detection pad 41, a second detection pad 42, and a third detection pad 43. The first detection pad 41 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104; the second detection pad 42 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104; and the third detection pad 43 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104. All three detection pads are located outside the array substrate 10. Specifically, the first detection pad 41 is connected to the first metal trace 31, the second detection pad 42 is connected to the second metal trace 32, and the third detection pad 43 is connected to the third metal trace 33.
[0061] The motherboard may also include a fourth detection pad 44, a fifth detection pad 45, and a sixth detection pad 46. The fourth detection pad 44, fifth detection pad 45, and sixth detection pad 46 are located between the display area AA and the first dicing line 101. The fourth detection pad 44, fifth detection pad 45, and sixth detection pad 46 comprise two groups: the first group is located between the second dicing line 102 and the first control area CA1, and the second group is located between the fourth dicing line and the first control area CA2. The fourth detection pad 44 of the array substrate 10 is connected to the fourth metal trace 34, the fifth detection pad 45 is connected to the fifth metal trace 35, and the sixth detection pad 46 is connected to the third metal trace 33.
[0062] For example, such as Figure 3 As shown, the motherboard also includes a gate drive signal area GA and a seventh detection pad 47. The gate drive signal area GA is located in the bonding area B. The seventh detection pad 47 is located to the left of the second cut line 102 and to the right of the fourth cut line 104. The seventh detection pad 47 is connected to the gate drive signal area GA on the corresponding side.
[0063] like Figure 4 As shown, the display area AA is equipped with multiple data lines Data and multiple touch signal lines Tx. The multiple data lines Data are connected one-to-one with multiple data pins DP, and the multiple touch signal lines Tx are connected one-to-one with multiple control pins CP.
[0064] like Figure 5 As shown, in the bonding area BA, the first control area and the second control area are located to the left and right of the data area, respectively, and the gate drive signal area is located to the left of the first control area and to the right of the second control area. Data pins are located in the data area, control pins are located in the first control area and the second control area, and the gate drive signal is located in the gate drive signal area.
[0065] For example, such as Figure 5As shown, the data pin DP and the control pin CP are located on the first metal layer 13, and the first metal trace 31 is also located on the first metal layer 13. The second metal trace 32, the third metal trace 33, the fourth metal trace 34, and the fifth metal trace 35 are all located on the second metal layer 15. An insulating layer is provided between the first metal layer 13 and the second metal layer 15. Figure 5 As can be seen, since the odd-numbered data pins DPO and the first metal trace 31 are located on the same layer, they can be connected on the same layer. The even-numbered data pins DPE are connected to the second metal trace 32 through the first via K1. The control pin CP is coupled to the third metal trace 33 through the second via K2. The odd-numbered data pins DPO are connected to the fourth metal trace 34 through the third via K3, and the even-numbered data pins DPE are connected to the fifth metal trace 35 through the fourth via K4.
[0066] In related technologies, refer to Figure 3 During array detection, corresponding detection signals are applied to the first detection pad 41, the second detection pad 42, and the third detection pad 43, respectively. These signals are then applied to the first metal trace 31, the second metal trace 32, and the third metal trace 33 to detect the internal circuitry of the array substrate 10 and identify any open or short circuits. After the array detection passes, the mother board is cut along the first, second, third, and fourth cutting lines to obtain the array substrate 10.
[0067] In related technologies, refer to Figure 3 During Cell testing, corresponding detection signals are applied to the fourth detection pad 44, the fifth detection pad 45, and the sixth detection pad 46, respectively. These signals are then applied to the fourth metal trace 34, the fifth metal trace 35, and the third metal trace 33 to test the display panel's image. After Cell testing is completed, a laser is used to process the laser removal area (TA) to remove the metal traces in the TA area, preventing short circuits in the signals during normal display.
[0068] It should be noted that when cutting along the first cutting line 101, the second cutting line 102, the third cutting line, and the fourth cutting line 104, the portion outside the array substrate 10 is separated from the array substrate 10, thereby separating the lines connected together during array detection. Therefore, during cell detection, the fourth detection pad 44, the fifth detection pad 45, and the sixth detection pad 46 are used.
[0069] In related technologies, laser processing is required to remove the metal traces in the laser-cleaned area (TA) to prevent short circuits in signals during normal display. However, the use of laser processing increases the number of inspection steps and reduces inspection efficiency. Furthermore, during laser cleaning, fused metal traces can leave metal residue, leading to product defects.
[0070] In addition, such as Figure 4 As shown, the data line Data and the data pin DP are connected via the first adapter cable 51, and the touch signal line Tx and the control pin CP are connected via the second adapter cable 52. The first control area CA1 and the second control area CA2 are located to the left and right of the data area DA, respectively. This causes the first adapter cable 51 and the second adapter cable 52 in the fan-shaped trace area (Fanout area) to overlap. This necessitates a double-layer wiring method for the fan-shaped trace area, resulting in overlapping capacitance between the overlapping first adapter cable 51 and the second adapter cable 52. This affects data uniformity and the display effect.
[0071] To address some problems in the related technologies, this disclosure provides an array substrate 10.
[0072] Figure 6 This is a planar schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 6 As shown, the array substrate 10 includes a display area AA, a bonding area BA, and a fan-shaped trace area located between the display area AA and the bonding area BA. The display area AA has multiple data lines (Data) and multiple touch signal lines (Tx). The bonding area BA has multiple data pins (DP) and multiple control pins (CP), spaced apart from each other along a first direction X. For example, the multiple data pins (DP) are arranged along the first direction, and the control pins (CP) are located between two adjacent data pins (DP). Both the data pins (DP) and the control pins (CP) can be strip-shaped, with the data pins (DP) extending along a second direction Y, and the control pins (CP) extending along the second direction Y. The second direction Y can intersect the first direction X; exemplarily, the second direction Y can be perpendicular to the first direction X.
[0073] like Figure 6 As shown, the fan-shaped wiring area is provided with multiple first adapter lines 51 and multiple second adapter lines 52, which are spaced apart from each other along a first direction. The multiple first adapter lines 51 and multiple second adapter lines 52 are located on the same layer. The corresponding data lines Data and data pins DP are connected through the first adapter lines 51, and the corresponding touch signal lines Tx and touch pins CP are connected through the second adapter lines 52.
[0074] For example, the first adapter line 51, the second adapter line 52, the data pin DP, and the control pin CP are located on the first metal layer. The first metal layer may be disposed on the same layer as the data lines in the array substrate, or the first metal layer may be disposed on the same layer as the gate lines in the array substrate. In the following description, the first metal layer being disposed on the same layer as the gate lines is used as an example.
[0075] In this embodiment of the array substrate 10, multiple first adapter lines 51 and multiple second adapter lines 52 are spaced apart from each other along a first direction. Multiple data pins DP and multiple control pins CP are also spaced apart from each other along the first direction. Thus, along the first direction, the first adapter lines 51 and second adapter lines 52 can correspond one-to-one with and be connected to the data pins DP and control pins CP. The multiple first adapter lines 51 and multiple second adapter lines 52 in the fan-shaped trace area are spaced apart from each other along the first direction, avoiding intersections between the first adapter lines 51 and second adapter lines 52. Therefore, the first adapter lines 51 and second adapter lines 52 can be arranged on the same layer, and the fan-shaped trace area can use a single-layer wiring method, avoiding overlapping capacitance, which is beneficial to the uniformity of data signals and improves the display effect.
[0076] In one embodiment, such as Figure 6 As shown, the array substrate 10 has a first edge 100 located on the side of the bonding region BA away from the display region AA. The array substrate 10 includes multiple data extension lines DY and multiple control extension lines CY. The data extension lines DY extend from one end of the data pin DP to the first edge 100. For example, the data extension line DY is connected to the end of the data pin DP near the first edge 100 and extends to the first edge 100. The control extension lines CY extend from one end of the control pin CP to the first edge 100. For example, the control extension line CY is connected to the end of the control pin CP near the first edge 100 and extends to the first edge 100.
[0077] In one embodiment, multiple data lines (Data) are arranged along a first direction and extend along a second direction. Multiple touch signal lines (Tx) are arranged along the first direction and extend along the second direction. The data lines (Data) and touch signal lines (Tx) are spaced apart from each other. The second direction intersects the first direction; exemplarily, the second direction and the first direction can be perpendicular to each other. In this structure, along the first direction, the multiple data lines (Data) and touch signal lines (Tx) are spaced apart from each other, the multiple first adapter lines 51 and multiple second adapter lines 52 are spaced apart from each other, and the multiple data pins (DP) and multiple control pins (CP) are spaced apart from each other. Thus, along the first direction, the data lines (Data), first adapter lines 51, and data pins (DP) are connected one-to-one, and the touch signal lines (Tx), second adapter lines 52, and control pins (CP) are connected one-to-one. The data signals and touch signals will not cross during transmission, ensuring the stability of signal transmission and improving the display effect.
[0078] For example, the display area AA is provided with multiple sub-pixels P arranged in an array, and the data lines Data can be located between two columns of sub-pixels P. The touch signal line Tx can be located between two adjacent data lines Data. The position of the touch signal line Tx between the two data lines Data can be set as needed. For example, the touch signal line Tx can be made of a transparent conductive material, and the touch signal line Tx can pass through the sub-pixel P area; or, the touch signal line Tx can be located between two adjacent columns of sub-pixels P.
[0079] In one embodiment, such as Figure 6 As shown, the display area AA can be provided with multiple sub-pixels P arranged in an array. Sub-pixels P can include blue sub-pixels B, green sub-pixels G, and red sub-pixels R. Data lines Data can be located between two adjacent columns of sub-pixels P. Two columns of sub-pixels P are arranged between two adjacent data lines Data, meaning one data line Data is set every two columns of sub-pixels P. Touch signal lines Tx are located between two adjacent data lines Data, and also between two columns of sub-pixels P between the two adjacent data lines Data. Thus, with data lines Data and touch signal lines Tx located between two adjacent columns of sub-pixels P, multiple data lines Data and multiple touch signal lines Tx are spaced apart from each other in the first direction. In this structure, with touch signal lines Tx located between two columns of sub-pixels P, the material of touch signal lines Tx is not limited to transparent conductive materials; opaque metal materials can also be used. Metal touch signal lines Tx have lower resistance, which is beneficial for signal transmission on the touch signal lines Tx and improves the performance of the display panel.
[0080] In one embodiment, the display area AA is provided with a plurality of sub-pixels P arranged in an array. Two columns of sub-pixels P are provided between two adjacent data lines Data. When sub-pixels P are provided on both sides of the data line Data, the data line Data is coupled to the thin-film transistors in the sub-pixels P on both sides. For example, Figure 6 In the diagram, sub-pixels P are located on both the left and right sides of the data line Data2. Data line Data2 is coupled to the thin-film transistor in the left sub-pixel P(G) and the thin-film transistor in the right sub-pixel P(R). Thus, data line Data2 can provide data signals to both the left and right sub-pixels P(G).
[0081] The display area AA also has multiple pairs of gate lines, each corresponding to a row of sub-pixels P. The two gate lines corresponding to the row sub-pixels P are located on either side of the row sub-pixel P. The thin-film transistors in a portion of the sub-pixels P are coupled to the first gate line, while the thin-film transistors in the other portion of the sub-pixels P are coupled to the second gate line.
[0082] For example, Figure 6 In the first row of sub-pixels P, the two gate lines are Gate1 and Gate2, located above and below each other. A portion of the thin-film transistors (TFTs) in the first row of sub-pixels P are coupled to Gate1, while the remaining portion are coupled to Gate2. Similarly, the two gate lines corresponding to the second row of sub-pixels P are Gate3 and Gate4, located above and below each other. A portion of the TFTs in the second row of sub-pixels P are coupled to Gate3, while the remaining portion are coupled to Gate4.
[0083] For example, in the same row of sub-pixels P, the thin-film transistors of sub-pixels P located on both sides of the data line Data are coupled to different gate lines. For instance, in the first row of sub-pixels P, the thin-film transistor of the sub-pixel P located to the left of the data line Data2 is coupled to the first gate line Gate1, and the thin-film transistor of the sub-pixel P located to the right of the data line Data2 is coupled to the second gate line Gate2.
[0084] In the second row of sub-pixels P, the thin-film transistor of the sub-pixel P located to the left of data line Data2 is coupled to the first gate line Gate1, and the thin-film transistor of the sub-pixel P located to the right of data line Data2 is coupled to the second gate line Gate2. In other embodiments, in the second row of sub-pixels P, the thin-film transistor of the sub-pixel P located to the left of data line Data2 may be coupled to the second gate line Gate2, and the thin-film transistor of the sub-pixel P located to the right of data line Data2 may be coupled to the first gate line Gate1.
[0085] Within the same column of sub-pixels P, the thin-film transistors in sub-pixels P are coupled to the corresponding identical gate lines. For example, in the second column of sub-pixels P, the thin-film transistors in each sub-pixel P are coupled to the corresponding first gate line; in the third column of sub-pixels P, the thin-film transistors in each sub-pixel P are coupled to the corresponding second gate line.
[0086] In one embodiment, such as Figure 6As shown, in the same row of sub-pixels P, the thin-film transistors of sub-pixels P located on both sides of the touch signal line Tx are coupled to the same gate line. For example, in the first row of sub-pixels P, the thin-film transistor of the sub-pixel P located to the left of the touch signal line Tx2 is coupled to the second gate line Gate2, and the thin-film transistor of the sub-pixel P located to the right of the touch signal line Tx2 is coupled to the second gate line Gate2.
[0087] In one embodiment, the display area AA is further provided with multiple gate lines, and the first adapter line 51 and the second adapter line 52 are both located on the same layer as the gate lines. In other embodiments, the first adapter line 51 and the second adapter line 52 may be located on the same layer as the data line or the touch signal line Tx.
[0088] In one embodiment, both the data pin DP and the control pin CP are located on the same layer as either the first adapter cable 51 or the second adapter cable 52. For example, when the first adapter cable 51 and the second adapter cable 52 are located on the same layer as the gate line, the data pin DP and the control pin CP are also located on the same layer as the gate line; when the first adapter cable 51 and the second adapter cable 52 are located on the same layer as the data line, the data pin DP and the control pin CP are also located on the same layer as the data line.
[0089] Figure 7A This is a planar schematic diagram of the array substrate according to another embodiment of the present disclosure. Figure 7A The diagram illustrates a 3x2 electrode block 121. Taking an example where the area of electrode block 121 contains 3x6 sub-pixels P, it's clear that the size of the electrode block 121 and the number of sub-pixels P within its area can be adjusted as needed in the actual product. Furthermore, for clearer illustration... Figure 7A The gate is not shown; only the sub-electrode block 121, some metal traces, and vias are shown. For example... Figure 7A As shown, the array substrate 10 includes a substrate 11 and a first transparent electrode layer 12 located on one side of the substrate 11. The first transparent electrode layer 12 includes a plurality of electrode blocks 121 arranged in an array, and the plurality of electrode blocks 121 are connected one-to-one with a plurality of touch signal lines Tx. The display area AA is provided with a plurality of sub-pixels P arranged in an array, and the electrode blocks 121 are provided with a plurality of sub-pixels P in the orthographic projection area on the substrate 11. For example, the electrode blocks 121 are provided with a plurality of sub-pixels P arranged in an array in the orthographic projection area on the substrate 11.
[0090] In one embodiment, the first transparent electrode layer 12 is a separate layer in the array substrate 10, that is, the first transparent electrode layer 12 is not disposed on the same layer as other conductive layers in the array substrate 10, and the electrode block 121 can be a continuous block.
[0091] In one embodiment, such as Figure 7A As shown, electrode block 121 may include multiple sub-electrode blocks, which are interconnected to form electrode block 121. For example, each sub-electrode block may correspond one-to-one with a sub-pixel P, with one sub-electrode block disposed within the area of one sub-pixel P. Multiple sub-electrode blocks may be interconnected, for example... Figure 7A In the middle, multiple sub-electrode blocks arranged along the first direction are connected by the first electrode connection line 132.
[0092] Figure 7B This is a schematic diagram of an electrode block according to another embodiment of this disclosure. In another embodiment, as... Figure 7B As shown, the sub-electrode block 1211 can be strip-shaped along the first direction, and multiple sub-pixels P arranged along the first direction can be disposed within the sub-electrode block 1211. Adjacent sub-electrode blocks 1211 can be connected to each other within the region of the electrode block 121. Figure 7B In the process, a first electrode connection line 132 connected to the sub-electrode block 1211 can be provided at the upper and lower edges of the sub-electrode block 1211. The first electrode connection line 132 can reduce the resistance of the electrode block and improve the touch performance.
[0093] In one embodiment, a common electrode signal is applied to the electrode block 121 during the display of a frame on the display panel, and a touch signal is applied to the electrode block 121 between two frames on the display panel.
[0094] It should be noted that the display panel refreshes the image frame by frame during the display process. During the frame display, multiple gate lines are sequentially provided with gate signals from top to bottom. During the frame display, a common electrode signal is applied to electrode block 121 to realize the display of the frame. Between two frames, a touch signal is applied to electrode block 121 to detect the touch position. Thus, electrode block 121 achieves two alternating functions, reducing costs.
[0095] Figure 8 for Figure 7A A magnified diagram of part M in the image. Figure 9 for Figure 8 Schematic diagram of section AA in the diagram. Figure 10 for Figure 8 A schematic diagram of the BB or EE cross section in the diagram. Figure 11 for Figure 8 Schematic diagram of the CC section in the diagram. Figure 12 for Figure 8 A schematic diagram of the DD section. (See diagram below.) Figure 8 and 9As shown, the array substrate 10 may further include a first metal layer 13. The first metal layer 13 and the first transparent electrode layer 12 are disposed in the same layer. In this document, "A and B are disposed in the same layer" means that A and B are located on the same surface. For example, in this embodiment, both the first metal layer 13 and the first transparent electrode layer 12 are located on the upper surface of the substrate 11. In actual implementation, the first transparent electrode layer 12 can be formed on the upper surface of the substrate 11 first, and then the first metal layer 13 can be formed on the upper surface of the substrate 11; or, the first metal layer 13 can be formed on the upper surface of the substrate 11 first, and then the first transparent electrode layer 12 can be formed on the upper surface of the substrate 11.
[0096] like Figures 8-10 As shown, the first transparent electrode layer 12 may include a plurality of sub-electrode blocks, each sub-electrode block corresponding to a sub-pixel P. That is, the sub-electrode block may be located within the sub-pixel P region, or the orthogonal projection of the sub-electrode block on the substrate may coincide with the orthogonal projection of the sub-pixel P on the substrate.
[0097] The first metal layer 13 includes gate lines 131 and first electrode connection lines 132, the first electrode connection lines 132 extending along a first direction within the region of the electrode block 121. In this first direction, the first electrode connection lines 132 in adjacent electrode blocks 121 are disconnected from each other, for example, Figure 7A The first electrode connection line 132a and the first electrode connection line 132b are disconnected from each other.
[0098] Figure 7A The diagram illustrates the region of electrode block 121. It should be noted that when electrode block 121 comprises multiple sub-electrode blocks, although there are gaps between adjacent sub-electrode blocks, the region of electrode block 121 includes the gaps between adjacent sub-electrode blocks within electrode block 121. Within the region of electrode block 121, the boundaries of the sub-electrode blocks along the first direction overlap and connect with the first electrode connection line 132, thereby connecting multiple sub-electrode blocks arranged along the first direction to each other via the first electrode connection line 132. Within the region of electrode block 121, multiple sub-electrode blocks arranged along the second direction are interconnected.
[0099] In another embodiment, within the region of electrode block 121, sub-electrode block 1211 can be a strip extending along a first direction, such as... Figure 7B As shown, that is, multiple sub-electrode blocks 1211 arranged along the first direction can be interconnected to form a strip, and multiple sub-electrode blocks 1211 arranged along the second direction can be interconnected.
[0100] The first metal layer 13 is made of metal material, which has better conductivity. By setting the boundary of the sub-electrode block 1211 along the first direction to overlap with the first electrode connection line 132, the impedance of the electrode block 1211 can be reduced and the conductivity of the electrode block 121 can be improved.
[0101] like Figures 8-10 As shown, the array substrate 10 may further include a first insulating layer 14, a second metal layer 15, a second insulating layer 16, and a second transparent electrode layer 17 sequentially stacked on the side of the first metal layer 13 and the first transparent electrode layer 12 facing away from the substrate 11. The second metal layer 15 includes a data line Data and a touch signal line Tx, with the touch signal line Tx located between two adjacent columns of sub-pixels P.
[0102] The second transparent electrode layer 17 includes a second electrode connection line 172. The array substrate 10 also includes a first via K1, the orthographic projection of the first via K1 on the substrate 11 intersects with the orthographic projection of the touch signal line Tx on the substrate 11, and the orthographic projection of the first via K1 on the substrate 11 intersects with the orthographic projection of the first electrode connection line 132 on the substrate 11. The second electrode connection line 172 is connected to the touch signal line Tx and the first electrode connection line 132 through the first via K1. Thus, the electrode block 121 is connected to the touch signal line Tx through the first electrode connection line 132 and the second electrode connection line 172, realizing the connection between the electrode block 121 and the touch signal line Tx through the second electrode connection line 172.
[0103] like Figure 10 As shown, by way of example, the second electrode connection line 172 can be located between two adjacent rows of sub-pixels P. The second electrode connection lines 172 corresponding to the two first vias K1 located between two adjacent rows of sub-pixels P can be connected to each other.
[0104] In this embodiment, the first electrode connection line 132 extends along a first direction within the region of the electrode block 121. The boundary of the sub-electrode block 1211 along the first direction overlaps with the first electrode connection line 132. Therefore, the first electrode connection line 132 is located between two adjacent rows of sub-pixels P. The touch signal line Tx is located between two adjacent columns of sub-pixels P. The orthographic projection of the first via K1 on the substrate 11 intersects not only the orthographic projection of the touch signal line Tx on the substrate 11 but also the orthographic projection of the first electrode connection line 132 on the substrate 11. Therefore, the first via K1 is located between two adjacent rows and / or two adjacent columns of sub-pixels P. In other words, the first via K1 does not occupy the space of the sub-pixels P, and thus, the first via K1 does not affect the aperture ratio of the display panel. Furthermore, the second electrode connection line 172 is made of a transparent conductive material. Using the second electrode connection line 172 not only enables the connection between the electrode block 121 and the touch signal line Tx, but the transparent second electrode connection line 172 also does not affect the aperture ratio of the display panel.
[0105] In one embodiment, such as Figure 7AAs shown, the second metal layer 15 may further include a third electrode connection line 153. The second transparent electrode layer 17 further includes a fourth electrode connection line 174. The third electrode connection line 153 extends along a second direction within the region of the electrode block 121, and is located between two adjacent columns of sub-pixels P. The array substrate 10 also includes a second via K2, the orthographic projection of the second via K2 on the substrate 11 intersects with the orthographic projection of the third electrode connection line 153 on the substrate 11, and the orthographic projection of the second via K2 on the substrate 11 intersects with the orthographic projection of the first electrode connection line 132 on the substrate 11. The fourth electrode connection line 174 is connected to the third electrode connection line 153 and the first electrode connection line 132 through the second via K2.
[0106] For example, in Figure 7A In the middle, the touch signal line Tx3 corresponding to the electrode block 121 in the third row extends downward and is connected to the control pin CP through the second adapter cable 52. For example... Figure 7A and Figure 10 As shown, a third electrode connection line 153, a fourth electrode connection line 174, and a second via K2 can be provided within the electrode block 121 in the first row. Thus, the sub-electrode block 1211 can be connected to the third electrode connection line 153 via the first electrode connection line 132 and the fourth electrode connection line 174. Multiple sub-electrode blocks 1211 can be interconnected via the third electrode connection line 153. The second metal layer 15 is made of a metallic material, which has better conductivity. Connecting multiple sub-electrode blocks 121 arranged in the second direction to each other via the third electrode connection line 153 can further reduce the impedance of the electrode blocks 121 and improve their conductivity.
[0107] like Figure 10 As shown, by way of example, the fourth electrode connection line 174 can be located between two adjacent rows of sub-pixels P. The fourth electrode connection lines 174 corresponding to the two second vias K2 located between two adjacent rows of sub-pixels P can be interconnected.
[0108] In one embodiment, such as Figure 11 and Figure 12 As shown, the second transparent electrode layer 17 may further include an auxiliary electrode connection line 175, and the array substrate 10 may further include a third via K3. The orthographic projection of the third via K3 on the substrate 11 overlaps with the orthographic projection of the first electrode connection line 132 on the substrate 11. The auxiliary electrode connection line 175 is connected to the first electrode connection line 132 through the third via K3. In this structure, the auxiliary electrode connection line 175 is disconnected from the corresponding touch signal line Tx or the third electrode connection line 153.
[0109] For example, the auxiliary electrode connection line 175 can be located between two adjacent rows of sub-pixels P.
[0110] In this embodiment, when the sub-electrode block 1211 is connected to the touch signal line Tx or the third electrode connection line 153, a second electrode connection line 172 or a fourth electrode connection line 174 is provided. The second electrode connection line 172 or the fourth electrode connection line 174 will form a coupling capacitance with other conductive film layers. By providing an auxiliary electrode connection line 175, a coupling capacitance can be formed between the auxiliary electrode connection line 175 and other conductive film layers, thereby compensating for the capacitance at positions without the second electrode connection line 172 and the fourth electrode connection line 174, balancing the overall capacitance of the array substrate 10, and making the overall performance of the product more balanced.
[0111] For example, such as Figure 9 As shown, the second transparent electrode layer 17 also includes a pixel electrode 171, which is located in the sub-pixel P region.
[0112] Exemplarily, the array substrate 10 may further include a semiconductor layer 18, which is located between the first insulating layer 14 and the second metal layer 15. The second metal layer 15 may include the source and drain of a thin-film transistor, and may also include a data line (Data) and a touch signal line (Tx). The second metal layer 15 may also include a third electrode connection line 153. The semiconductor layer 18 may include a first portion 181 and a second portion, the first portion being located between the source and drain, and the first portion 181 may serve as a channel for the thin-film transistor. The orthographic projection of the second portion onto the substrate 11 coincides with the orthographic projection of the second metal layer 15 onto the substrate 11.
[0113] Figure 13 This is a plan view of the array substrate mother plate in one embodiment of the present disclosure. Figure 14 for Figure 13 A partial schematic diagram is shown. It should be noted that... Figure 13 The same fill pattern is used to indicate the connected traces. That is to say, traces with the same fill pattern are connected to each other. The fill pattern of the trace does not indicate the film layer in which the trace is located. Figure 14 In this context, traces located in the same layer use the same fill pattern, meaning that traces with the same fill pattern are located in the same film layer.
[0114] This disclosure also provides a method for fabricating an array substrate, including the fabrication of a mother plate. For example... Figure 13 and Figure 14 As shown, the motherboard includes a substrate region defined by a first cutting line 101, a second cutting line 102, a third cutting line (not shown), and a fourth cutting line 104 connected in sequence. The first cutting line 101 and the third cutting line extend along a first direction, and the second cutting line 102 and the fourth cutting line 104 extend along a second direction, which intersects with the first direction.
[0115] refer to Figure 6The substrate area includes a display area AA and a bonding area BA, with the bonding area BA located between the display area AA and the first cutting line 101. The substrate area also includes a fan-shaped trace area located between the display area AA and the bonding area BA. Figure 13 (Not shown in the text). The display area AA has multiple data lines (Data) and multiple touch signal lines (Tx). The bonding area BA has multiple data pins (DP) and multiple control pins (CP), with the data pins (DP) and control pins (CP) spaced apart along a first direction. The fan-shaped trace area has multiple first adapter lines 51 and multiple second adapter lines 52. The corresponding data lines (Data) and data pins (DP) are connected via the first adapter lines 51, and the corresponding touch signal lines (Tx) are connected to the touch pads via the second adapter lines 52. The specific structure of the substrate area can be found in the text above. Figure 6 The structure of the array substrate 10 shown.
[0116] like Figure 13 and Figure 14 As shown, the motherboard also includes a first metal trace 31, a second metal trace 32, and a third metal trace 33 located on the side of the first dicing line 101 away from the substrate region. The first metal trace 31 is connected to a portion of the plurality of data pins DP. The second metal trace 32 is connected to another portion of the plurality of data pins DP. The third metal trace 33 is connected to a plurality of control pins CP.
[0117] The fabrication method of the array substrate 10 further includes: applying a first detection signal to the first metal trace 31 and the second metal trace 32, and applying a second detection signal to the third metal trace 33, to detect the substrate area. This detection process can be called array detection, which is used to detect the circuits inside the array substrate 10 and to detect whether there are open circuits or short circuits inside the array substrate 10.
[0118] like Figure 13 and Figure 14As shown, the motherboard also includes a first detection pad 41, a second detection pad 42, and a third detection pad 43. The first detection pad 41 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104; the second detection pad 42 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104; and the third detection pad 43 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104. All three detection pads are located outside the array substrate 10. The first detection pad 41 is connected to the first metal trace 31, the second detection pad 42 is connected to the second metal trace 32, and the third detection pad 43 is connected to the third metal trace 33. A first detection signal can be applied to the first metal trace 31 and the second metal trace 32 through the first detection pad 41 and the second detection pad 42, respectively, and a second detection signal can be applied to the third metal trace 33 through the third detection pad 43.
[0119] In one embodiment, such as Figure 13 and Figure 14 As shown, the first metal trace 31 is connected to the odd-numbered data pins DPO among the multiple data pins DP, and the second metal trace 32 is connected to the even-numbered data pins DPE among the multiple data pins DP.
[0120] Figure 15 for Figure 14 A schematic diagram of the FF cross-section in one embodiment. In one embodiment, the first metal trace 31 and the odd-numbered data pins DPO can be directly connected via vias, or they can be connected via other conductive film layers. For example, Figure 15 In this configuration, the first metal trace 31 is connected to the sixth electrode connection line 176, and the odd-numbered data pins DPO are also connected to the sixth electrode connection line 176. Thus, the first metal trace 31 and the odd-numbered data pins DPO are connected via the sixth electrode connection line 176. The sixth electrode connection line 176 can be located in the second transparent electrode layer 17.
[0121] For example, the second metal trace 32 and the even-numbered data pins DPE can be directly connected via vias, or they can be connected via other conductive film layers. For instance, the second metal trace 32 can be connected to the seventh electrode connection line 177, and the even-numbered data pins DPE can be connected to the seventh electrode connection line 177. Thus, the second metal trace 32 and the even-numbered data pins DPE are connected via the seventh electrode connection line 177. The seventh electrode connection line 177 can be located in the second transparent electrode layer 17.
[0122] like Figure 13 and Figure 14As shown, the first metal trace 31 and the second metal trace 32 are located on the same layer as the data line Data, and the third metal trace 33 is located on the same layer as the gate line Gate in the array substrate 10.
[0123] For example, such as Figure 13 and Figure 14 As shown, the motherboard also includes a gate drive signal area GA and a seventh detection pad 47. The gate drive signal area GA is located in the bonding area B. The seventh detection pad 47 is located to the left of the second dicing line 102 and to the right of the fourth dicing line 104. The seventh detection pad 47 is connected to the gate drive signal area GA on the corresponding side. A portion of the connection line between the seventh detection pad 47 and the gate drive signal area GA is located on the side of the first dicing line 101 away from the substrate region.
[0124] After the array detection passes, the fabrication method further includes cutting along the first cutting line 101, the second cutting line 102, the third cutting line, and the fourth cutting line 104 to obtain the array substrate 10 located in the substrate region. Thus, after cutting, the odd-numbered data pins DPO are separated from the first metal trace 31, the even-numbered data pins DPE are separated from the second metal trace 32, the control pin CP is separated from the third metal trace 33, and the gate drive signal area GA is separated from the corresponding metal trace.
[0125] As mentioned above, the relevant technology requires laser processing to remove the metal traces in the laser-cleaned area (TA) to prevent short circuits in the signals during normal display. The use of laser processing increases the number of inspection steps and reduces inspection efficiency. Furthermore, during laser cleaning, the fused metal traces can leave metal residue, leading to product defects.
[0126] The array substrate of this embodiment no longer has a laser cleaning area, thereby eliminating the need for the laser cleaning process, reducing process steps, lowering costs, and avoiding product defects caused by metal residue, thus improving product quality.
[0127] In an exemplary embodiment, the first insulating layer 14 and the second insulating layer 16 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The metal traces may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The transparent electrode layer may be made of at least one of transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).
[0128] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display panel. The display panel includes an array substrate employing the foregoing embodiments. Exemplarily, the display panel can be a liquid crystal display panel. The display panel can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.
[0129] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.
[0130] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.
[0131] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0132] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0133] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.
[0134] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An array substrate, characterized in that, It includes a display area, a binding area, and a fan-shaped wiring area located between the display area and the binding area. The display area is provided with multiple data lines and multiple touch signal lines. The bonding area is provided with multiple data pins and multiple control pins, and the multiple data pins and multiple control pins are spaced apart from each other along a first direction; The fan-shaped trace area is provided with multiple first adapter wires and multiple second adapter wires. The multiple first adapter wires and multiple second adapter wires are arranged at intervals along the first direction. The multiple first adapter wires and multiple second adapter wires are located on the same layer. The corresponding data lines are connected to the data pins through the first adapter wires, and the corresponding touch signal lines are connected to the touch pads through the second adapter wires.
2. The array substrate according to claim 1, characterized in that, The array substrate has a first edge located on the side of the bonding area away from the display area. The array substrate also includes multiple data extension lines and multiple touch extension lines. The data extension lines extend from one end of the data pin to the first edge, and the touch extension lines extend from one end of the control pin to the first edge.
3. The array substrate according to claim 1, characterized in that, The plurality of data lines are arranged along the first direction and extend along the second direction, the plurality of touch signal lines are arranged along the first direction and extend along the second direction, the plurality of data lines and the plurality of touch signal lines are spaced apart from each other, and the second direction intersects the first direction.
4. The array substrate according to claim 3, characterized in that, The display area is provided with multiple sub-pixels arranged in an array, and two columns of sub-pixels are arranged between two adjacent data lines. The touch signal line is located between the two columns of sub-pixels between two adjacent data lines.
5. The array substrate according to claim 3, characterized in that, The display area is provided with multiple sub-pixels arranged in an array, and two columns of sub-pixels are provided between two adjacent data lines. When sub-pixels are provided on both sides of the data line, the data line is coupled to the thin-film transistors in the sub-pixels on both sides. The display area is also provided with multiple pairs of gate lines, which correspond one-to-one with multiple rows of sub-pixels. The two gate lines corresponding to the row sub-pixels are located on both sides of the row sub-pixels. The thin film transistors in a portion of the sub-pixels are coupled to the first gate line of the two gate lines, and the thin film transistors in another portion of the sub-pixels are coupled to the second gate line.
6. The array substrate according to claim 1, characterized in that, The display area is also provided with multiple grid lines, and the first adapter line and the second adapter line are both located on the same layer as the grid lines.
7. The array substrate according to claim 6, characterized in that, The data pins and the control pins are both located on the same layer as the first adapter cable and the second adapter cable.
8. The array substrate according to claim 1, characterized in that, The array substrate includes a substrate and a first transparent electrode layer located on one side of the substrate. The first transparent electrode layer includes a plurality of electrode blocks arranged in an array. The plurality of electrode blocks are connected one-to-one with the plurality of touch signal lines. The display area is provided with a plurality of sub-pixels arranged in an array. The electrode blocks are provided with a plurality of the sub-pixels in the orthographic projection area on the substrate.
9. The array substrate according to claim 8, characterized in that, The electrode block is given a common electrode signal during the display of frames on the display panel, and a touch signal is given to the electrode block between two frames on the display panel.
10. The array substrate according to claim 8, characterized in that, The array substrate further includes a first metal layer, which is disposed in the same layer as the first transparent electrode layer. The electrode block includes a plurality of sub-electrode blocks. The first metal layer includes a gate line and a first electrode connection line. The first electrode connection line extends along a first direction within the region of the electrode block. The boundary of the sub-electrode block along the first direction overlaps with the first electrode connection line. The plurality of sub-electrode blocks arranged along a second direction within the region of the electrode block are interconnected.
11. The array substrate according to claim 10, characterized in that, The array substrate further includes a first insulating layer, a second metal layer, a second insulating layer, and a second transparent electrode layer, which are sequentially stacked on the side of the first metal layer and the first transparent electrode layer facing away from the substrate. The second metal layer includes the touch signal line, the second transparent electrode layer includes the second electrode connection line, and the array substrate further includes a first via. The orthographic projection of the first via on the substrate intersects with the orthographic projection of the touch signal line on the substrate, and the orthographic projection of the first via on the substrate intersects with the orthographic projection of the first electrode connection line on the substrate. The second electrode connection line is connected to the touch signal line and the first electrode connection line through the first via.
12. The array substrate according to claim 11, characterized in that, The second metal layer further includes a third electrode connection line, and the second transparent electrode layer further includes a fourth electrode connection line. The third electrode connection line extends along a second direction within the region of the electrode block. The third electrode connection line is located between two adjacent columns of sub-pixels. The array substrate further includes a second via. The orthographic projection of the second via on the substrate intersects with the orthographic projection of the third electrode connection line on the substrate. The orthographic projection of the second via on the substrate intersects with the orthographic projection of the first electrode connection line on the substrate. The fourth electrode connection line is connected to the third electrode connection line and the first electrode connection line through the second via.
13. A display panel, characterized in that, The array substrate includes any one of claims 1-12.
14. A method for fabricating an array substrate, characterized in that, include: A motherboard is fabricated, comprising a substrate region defined by a first cutting line, a second cutting line, a third cutting line, and a fourth cutting line connected sequentially. The first and third cutting lines extend along a first direction, and the second and fourth cutting lines extend along a second direction, intersecting the first direction. The substrate region includes a display area and a bonding area, the bonding area being located between the display area and the first cutting line. The substrate region also includes a fan-shaped trace area located between the display area and the bonding area. The display area is provided with multiple data lines and multiple touch signal lines. The bonding area is provided with multiple data pins and multiple control pins, the multiple data pins and the multiple control pins being spaced apart from each other along the first direction. The fan-shaped trace area is provided with multiple first adapter lines and multiple second adapter lines. Corresponding data lines are connected to data pins via the first adapter lines, and corresponding touch signal lines are connected to touch pads via the second adapter lines. The motherboard also includes a first metal trace, a second metal trace, and a third metal trace located on the side of the first cutting line away from the substrate area. The first metal trace is connected to a portion of the plurality of data pins, the second metal trace is connected to another portion of the plurality of data pins, and the third metal trace is connected to the plurality of control pins. A first detection signal is applied to the first metal trace and the second metal trace, and a second detection signal is applied to the third metal trace to detect the substrate region; Cutting is performed along the first cutting line, the second cutting line, the third cutting line, and the fourth cutting line to obtain an array substrate located in the substrate region.
15. The method according to claim 14, characterized in that, The first metal trace is connected to the even-numbered data pins among the plurality of data pins, and the second metal trace is connected to the odd-numbered data pins among the plurality of data pins.
16. The method according to claim 15, characterized in that, The first metal trace and the second metal trace are located on the same layer as the data line, and the third metal trace is located on the same layer as the gate line in the array substrate.