A control instruction rate matching method of a distributed controller-driver

Abstract

The application discloses a kind of control instruction rate matching methods of distributed controller-driver, it is related to distributed control technical field, including: using the clock source of driver to carry out instruction frequency detection, the frequency error numerical value of controller instruction is obtained;Interpolation cache processing is carried out to controller instruction based on the frequency error numerical value of controller instruction, and the frequency error information of instruction cache is obtained;According to the frequency error numerical value of controller instruction and the frequency error information of instruction cache, dynamic cycle adjustment is carried out, and control instruction rate matching result is obtained.The application completes frequency detection and dynamic cycle adjustment independently by driver, without the participation of controller clock calibration, avoids the occupation of calibration instruction to communication bandwidth, significantly improves system communication efficiency;Combined with interpolation cache processing, clock deviation can be compensated in real time, the instruction frequency error is controlled in extremely low range, effectively reduces system fluctuation risk, and without modifying communication protocol, completely compatible with existing hardware architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of distributed control, and particularly relates to a control instruction rate matching method of a distributed controller-driver. BACKGROUND

[0002] In the existing distributed controller-driver combination, the controller and the driver usually use different clock sources respectively. Due to the frequency deviation of the clock sources, the cumulative error will cause periodic jitter of the data over time, and then the synchronization error between the position instruction sent by the controller and the actual execution time of the driver. The traditional synchronization scheme mainly depends on the controller sending clock calibration instructions to the driver, and the deviation is eliminated by periodic correction, but this process needs to occupy the limited communication bandwidth, and the transmission delay of the calibration instruction will introduce new synchronization error. Especially in the high-frequency control scene, the accumulation of clock deviation will cause the instruction execution time to deviate, causing the system response to lag or overshoot, and even causing the equipment to run unstably. In addition, the traditional method has high customization requirements for the communication protocol, and it is difficult to be compatible with the controller-driver combination of different manufacturers, which limits the universality and expansibility of the system.

[0003] Therefore, there is an urgent need for a control instruction rate matching method of a distributed controller-driver to solve the problems in the prior art. SUMMARY

[0004] The purpose of the present application is to provide a control instruction rate matching method of a distributed controller-driver to solve the problems of frequency mismatch between instruction sending and reading caused by independent clock sources of the controller and the driver, and the bandwidth occupation and poor compatibility of the traditional synchronization scheme.

[0005] To achieve the above purpose, the present application provides a control instruction rate matching method of a distributed controller-driver, comprising the following steps:

[0006] S1, detecting the instruction frequency by using the clock source of the driver to obtain the frequency error value of the controller instruction;

[0007] S2, performing interpolation cache processing on the controller instruction based on the frequency error value of the controller instruction to obtain the frequency error information of the instruction cache;

[0008] S3, dynamically adjusting the period according to the frequency error value of the controller instruction and the frequency error information of the instruction cache to obtain the control instruction rate matching result.

[0009] Optionally, S1, detecting the instruction frequency by using the clock source of the driver to obtain the frequency error value of the controller instruction, comprises:

[0010] A clock source of a driver is used to initialize a double timer, which includes a first timer and a second timer;

[0011] A real control instruction period is obtained by using the first timer according to the clock source of the driver;

[0012] A theoretical control instruction period is generated by using the second timer;

[0013] A frequency error value of a controller instruction is obtained by comparing the real control instruction period with the theoretical control instruction period.

[0014] Optionally, the step of obtaining the frequency error value of the controller instruction by comparing the real control instruction period with the theoretical control instruction period includes:

[0015] A real controller instruction frequency and a theoretical controller instruction frequency are respectively calculated by using the real control instruction period and the theoretical control instruction period;

[0016] An error calculation is performed on the real controller instruction frequency and the theoretical controller instruction frequency to obtain a relative frequency error of the real controller instruction frequency and the theoretical controller instruction frequency as a relative frequency error of the controller instruction;

[0017] A reference time interval is set based on the relative frequency error of the controller instruction and a relative frequency error of a corresponding historical controller instruction;

[0018] The frequency error value of the controller instruction is obtained according to the reference time interval and the relative frequency error of the controller instruction.

[0019] Optionally, the step S2 of performing interpolation cache processing on the controller instruction based on the frequency error value of the controller instruction to obtain frequency error information of instruction cache includes:

[0020] An interpolation multiple and a frequency error threshold are set according to the frequency error value of the controller instruction;

[0021] It is determined whether the frequency error value of the controller instruction is greater than or equal to the frequency error threshold, if yes, a linear interpolation is obtained as a smoothing interpolation algorithm, and a first operation is performed, otherwise, a spline interpolation is obtained as the smoothing interpolation algorithm, and the first operation is performed;

[0022] The first operation is that the interpolation cache processing is performed on the controller instruction by using the interpolation multiple and the smoothing interpolation algorithm to obtain the frequency error information of the instruction cache.

[0023] Optionally, the controller instruction is subjected to interpolation cache processing by using the interpolation multiple and the smooth interpolation algorithm to obtain frequency error information of the instruction cache, including:

[0024] The controller instruction is subjected to smooth interpolation processing by using the interpolation multiple and the smooth interpolation algorithm to obtain a smooth interpolation controller instruction sequence.

[0025] The smooth interpolation controller instruction sequence is subjected to cache processing to obtain a cache instruction change amount.

[0026] According to the cache instruction change amount, the interpolation multiple and the theoretical control instruction period, frequency error information of the instruction cache is obtained.

[0027] Optionally, S3, dynamic period adjustment is performed according to the frequency error value of the controller instruction and the frequency error information of the instruction cache to obtain a control instruction rate matching result, including:

[0028] The frequency error value of the controller instruction and the frequency error information of the instruction cache are subjected to weighted fusion to obtain a comprehensive error value.

[0029] According to the comprehensive error value, a dynamic period adjustment parameter is determined.

[0030] The carrier period of the controller is adjusted by using the dynamic period adjustment parameter to obtain a control instruction rate matching result.

[0031] Optionally, the frequency error value of the controller instruction and the frequency error information of the instruction cache are subjected to weighted fusion to obtain a comprehensive error value, including:

[0032] According to the frequency error value of the controller instruction, a frequency error threshold of the controller instruction is set as a coarse error threshold.

[0033] It is judged whether the frequency error value of the controller instruction is greater than the coarse error threshold. If yes, a frequency error value weight of a first controller instruction and a frequency error information weight of a first instruction cache are obtained as a weight distribution result, and a second operation is performed. Otherwise, a frequency error value weight of a second controller instruction and a frequency error information weight of a second instruction cache are obtained as a weight distribution result, and a second operation is performed.

[0034] The second operation is that the frequency error value of the controller instruction and the frequency error information of the instruction cache are subjected to weighted fusion processing based on the weight distribution result to obtain a comprehensive error value.

[0035] Optionally, according to the comprehensive error value, a dynamic period adjustment parameter is determined, including:

[0036] According to the comprehensive error value, a comprehensive error threshold value is set;

[0037] It is judged whether the comprehensive error value is greater than the comprehensive error threshold value, if yes, a dynamic cycle adjustment parameter is obtained by using a lookup table method according to the comprehensive error value, otherwise, the comprehensive error value is input into a PI controller to obtain the dynamic cycle adjustment parameter.

[0038] Optionally, the carrier cycle of the controller is adjusted by using the dynamic cycle adjustment parameter to obtain a control instruction rate matching result, comprising:

[0039] The target carrier cycle is calculated by using the dynamic cycle adjustment parameter;

[0040] The carrier cycle of the controller is adjusted according to the target carrier cycle to obtain an adjusted carrier cycle;

[0041] Based on the adjusted carrier cycle, detection processing is performed to obtain an instruction cache state and a controller instruction input rate;

[0042] According to the instruction cache state and the controller instruction input rate, a control instruction rate matching determination condition is combined to obtain a control instruction rate matching result.

[0043] Optionally, the control instruction rate matching determination condition is:

[0044] The instruction cache state is stable in a preset interval, and the controller instruction input rate is less than a controller instruction input rate threshold value.

[0045] Compared with the closest prior art, the present application has the beneficial effects that:

[0046] Compared with the traditional synchronization method, the present application only needs the driver to implement the related technology, without occupying additional communication time, without the need for additional design of the related protocol of the controller and the driver, and is fully compatible with the existing controller-driver structure; the controller instruction interpolation cache is equivalent to improving the instruction issuing frequency of the controller, synchronizes the lower instruction issuing frequency of the controller itself with the higher instruction execution frequency of the driver, improves the frequency error detection precision, and at the same time ensures a wider frequency error detection range. The specific effects are as follows:

[0047] The application can complete frequency detection and rate matching independently by the driver, without the participation of the controller in clock calibration, eliminates the occupation of the communication bandwidth by the calibration instruction, and improves the system communication efficiency; the interpolation buffer processing and dynamic period adjustment are combined, the clock deviation can be compensated in real time, the frequency error of the instruction sending and reading is controlled in a very low range, and the system fluctuation risk caused by the synchronization deviation is significantly reduced; the communication protocol of the controller and the driver does not need to be modified, and the existing hardware architecture is completely compatible, so the technical solution can be directly applied to distributed systems of different manufacturers, and the universality and engineering practicability of the technical solution are greatly improved; the dynamic period adjustment mechanism can adapt to the dynamic change of the controller instruction frequency, and even in the scene that the controller load fluctuation causes the instruction sending frequency to be unstable, the efficient rate matching effect can still be maintained. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0049] Figure 1 A flowchart of a distributed controller-driver control instruction rate matching method according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0051] The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0052] As shown in Figure 1 , the embodiment of the present application provides a distributed controller-driver control instruction rate matching method, which comprises:

[0053] S1, using the clock source of the driver to detect the instruction frequency, and obtaining the frequency error value of the controller instruction;

[0054] The instruction frequency detection layer: the driver calculates the time interval of the controller's instruction in real time through its own clock source, compares it with the theoretical reference time interval, and detects the frequency error between the controller and the driver. This step can automatically identify a wide range of frequency deviations, avoiding the complexity of additional communication and protocol synchronization in traditional solutions. This step realizes efficient and independent detection of the controller's instruction frequency, providing basic data support for subsequent synchronous regulation.

[0055] S2, based on the frequency error value of the controller instruction, the controller instruction is interpolated and cached to obtain the frequency error information of the instruction cache;

[0056] The interpolation cache extraction layer: the driver smoothes the received controller instruction through interpolation algorithm, generates multiple intermediate instructions and caches. The change of the amount of effective data in the cache reflects more detailed frequency error information. This step improves the virtual multiple of the instruction issuing frequency, expanding the accuracy range of error detection. This step not only ensures high resolution of error detection, but also is compatible with the original low-frequency instruction mode of the controller, enhancing the synchronization adaptability of the system.

[0057] S3, according to the frequency error value of the controller instruction and the frequency error information of the instruction cache, dynamic cycle adjustment is performed to obtain the control instruction rate matching result;

[0058] The driver combines the coarse error (instruction frequency detection layer) and fine error (interpolation cache extraction layer) information, adjusts the carrier frequency through table lookup or PI controller dynamic adjustment, so as to adjust the consumption speed of the instruction cache. This step realizes the stepless adjustment of the carrier frequency, ensuring the accurate synchronization of the controller instruction and the driver execution time. This step significantly improves the synchronization accuracy and system stability, while not modifying the existing communication protocol or increasing the burden of the controller, and is fully compatible with the existing hardware architecture.

[0059] In summary, steps S1 to S3 realize instruction synchronization by the driver autonomously detecting the frequency error of the controller instruction and dynamically adjusting the carrier frequency. Specifically, it includes three steps: first, the driver detects the frequency error (coarse error) of the controller instruction using its own clock source; second, the instruction is smoothed and the finer frequency error information (fine error) is extracted through interpolation cache; finally, the carrier frequency is dynamically adjusted in combination with the coarse and fine errors to match the instruction rate. This scheme does not require additional communication protocols or controller modifications, is compatible with existing architectures, and at the same time expands the error detection range and improves the synchronization accuracy through interpolation cache, effectively solving the problem of instruction execution asynchronization caused by clock source deviation, improving system stability and control accuracy.

[0060] As a possible implementation, in the above embodiment, step S1 can specifically include the following steps:

[0061] S1-1, initializing double timers based on the clock source of the driver;

[0062] The driver uses its high-precision clock source to complete the initialization operation of the double timers (first timer and second timer), where the driver realizes the controller instruction issuing frequency detection through the two timers, the first timer is used to measure the time interval (actual period) of the actual controller instruction issuing, and the second timer is based on the preset theoretical instruction period (such as a fixed time reference) to run, and the clock source uses a temperature-compensated crystal oscillator or a thermostat crystal oscillator. The two timers use a synchronous counter architecture, and the counting pulses are directly derived from the standard clock signal after frequency division processing of the driver clock source, for example, the 10MHz clock source is divided by 1MHz, ensuring that the timing accuracy reaches 1 microsecond.

[0063] During the initialization process, the system synchronously calibrates the double timers, sends a reset signal through the internal bus, clears the initial count values of the two timers, and keeps the starting time strictly synchronized, with a synchronization error ≤ 1 clock cycle. This step realizes the synchronous initialization of the double timers by sharing the same high-stability clock source, ensures that the timing references of the actual control instruction period and the theoretical control instruction period are completely consistent, avoids the error accumulation problem caused by the difference in timing references from the source, and provides a high-consistency time reference for subsequent frequency error calculation.

[0064] To avoid counting errors caused by timer overflow, the embodiment also sets a dynamic overflow warning mechanism: when the count value of the timer reaches 90% of the maximum range, an interrupt signal is triggered, and the controller will automatically record the current count value and reset the counter in the interrupt response, ensuring the continuity of the timing process. In addition, the double timers are linked with the clock source calibration module of the driver, and the count reference is updated synchronously with the automatic calibration of the clock source every hour, eliminating the accumulated error in long-term operation.

[0065] S1-2, using the first timer to obtain the actual control instruction period according to the clock source of the driver;

[0066] The first timer is configured in "event-triggered counting mode", which triggers timing by capturing the edge signal (such as rising edge / falling edge) of the controller instruction issuing, records the time stamp of adjacent instructions in real time, and calculates the actual control instruction period based on the driver clock source. Specifically as follows:

[0067] When the signal conditioning circuit of the driver detects the edge signal of the control command, it immediately sends a start signal to the first timer, which starts to accumulate the count; when the next edge of the same type is detected, a stop signal is sent, and the counter stops counting. The counting result of the first timer is transmitted in real time to the operation unit through a special data bus, and the operation unit divides the count value by the frequency of the driver clock source (such as 1 MHz clock source corresponding to 1 microsecond per count unit), and the time interval of two adjacent command edges, i.e. the actual control command period, is obtained. In addition, in order to improve the detection accuracy, a multi-cycle average method is used to record the measurement values of M (M≥5) actual control command periods, and the arithmetic mean value after removing the maximum and minimum values is taken as the final actual control command period.

[0068] This step can accurately capture the time interval of the command signal through real-time counting triggered by the edge, and the multi-cycle average method effectively suppresses the measurement fluctuation caused by instantaneous noise interference, so that the measurement error of the actual control command period is reduced; the high-speed transmission of the special data bus ensures that the counting result is transmitted without delay, providing high-fidelity raw data for subsequent error calculation.

[0069] S1-3, generating a theoretical control command period through the second timer;

[0070] The second timer is configured in a "fixed period output mode" to generate a theoretical control command period. The timer runs independently and is not affected by the actual behavior of the controller, and always provides a stable theoretical period reference. Its working principle is as follows: according to the preset theoretical control command frequency (such as 100Hz corresponding to a period of 10ms), the comparison register value is configured, and the automatic reload mode is used to continuously fix the time interval (for example, the counting is triggered once every 1ms). The specific steps are as follows:

[0071] The theoretical control command frequency set by the user is received through the configuration interface F ref The operation unit converts it into a theoretical period T ref =1 / F ref , and the number of clock pulses corresponding to the period T refThe second timer writes the comparison register of the second timer with the value of the clock source frequency. The second timer adopts an automatic reload mode, and when the count reaches the value of the comparison register, an interrupt is automatically triggered and the counter is reset to start counting the next period, while outputting a synchronization pulse signal as a marker of the theoretical instruction period. For example, if the theoretical period is 1 ms and the clock source frequency is 1 MHz, the value of the comparison register is set to 1000 (1 ms = 1000 microseconds, corresponding to 1000 count units). When the second timer counts to 1000, a theoretical period completion signal is generated, which can be used for subsequent comparison with the actual instruction period. In addition, the system supports dynamic modification of the theoretical control instruction frequency, and by writing a new comparison register value, the second timer can switch to a new theoretical period within 1 clock cycle, adapting to the control requirements under different working conditions.

[0072] The automatic reload counting mode of this step ensures stable output of the theoretical control instruction period, and the accuracy is only determined by the stability of the driver clock source, avoiding the drift of the theoretical period caused by software calculation delay; the dynamic switching function improves the flexibility of the system, and the theoretical period parameters can be updated in real time according to the adjustment of the control strategy, providing a reliable reference for dynamic comparison of frequency errors.

[0073] S1-4, comparing the actual control instruction period with the theoretical control instruction period to obtain a frequency error value of the controller instruction;

[0074] This step calculates the frequency error value of the controller instruction by comparing the actual control instruction period with the theoretical control instruction period, avoiding rounding errors in the frequency conversion process and making the error calculation more accurate.

[0075] In summary, after the driver is started, the steps S1-1 to S1-4 first start the clock source, enter the controller instruction issuing frequency detection phase, and calculate the actual control instruction period and the theoretical control instruction period through two timers, and then compare them in real time to obtain a frequency error value in a wide range. The clock source of the driver is used as a reference to detect the frequency of the controller instruction in real time, and the clock source of the driver has high stability and accuracy, which can provide a reliable reference standard for frequency detection. This process initializes the double timer by means of the high-precision clock source of the driver, effectively avoiding detection errors caused by unstable external reference sources, ensuring that the actual and theoretical control instruction period timing references are consistent, and ensuring the timing range and continuity; the first timer is used in combination with the multi-period averaging method to accurately obtain the actual period, suppressing noise interference; the second timer generates a stable theoretical period in an automatic reload mode and supports dynamic switching; the comparison of the periods obtains the frequency error, which facilitates the improvement of the accuracy, flexibility and maintainability of the control instruction rate matching, and provides a reliable basis for dynamic adjustment of the control period.

[0076] As a possible implementation, in the above embodiment, step S1-4 can specifically include the following steps:

[0077] S1-4-1, using the actual control instruction period and the theoretical control instruction period, respectively calculating the actual controller instruction frequency and the theoretical controller instruction frequency;

[0078] The actual control instruction period obtained by the first timer T 1, that is, the driver execution period, through the inverse relationship between frequency and period, the actual controller instruction frequency is calculated, that is:

[0079] The actual controller instruction frequency f 1=1 / T 1;

[0080] At the same time, according to the system preset theoretical control instruction period T 0, that is, the theoretical instruction period of the controller, the theoretical controller instruction frequency is also calculated through the inverse relationship, that is:

[0081] The theoretical controller instruction frequency f 0=1 / T 0;

[0082] This step converts the period difference originally in time unit into frequency parameter which reflects the "fast / slow" characteristics of instruction sending more intuitively, and intuitively reflects the clock source deviation of the controller and the driver, providing standardized input for subsequent relative frequency error calculation.

[0083] S1-4-2, error calculation is performed on the actual controller instruction frequency and the theoretical controller instruction frequency, and the relative frequency error of the actual controller instruction frequency and the theoretical controller instruction frequency is obtained as the relative frequency error of the controller instruction;

[0084] By calculating the difference between the actual controller instruction frequency and the theoretical controller instruction frequency, and then dividing the difference by the theoretical controller instruction frequency and multiplying by 100%, the relative frequency error is obtained as the relative frequency error of the controller instruction, and the calculation formula is as follows:

[0085] delta f =[( f 1- f 0) / f 0]×100%

[0086] Wherein, delta f The relative frequency error of the controller instruction.

[0087] The process eliminates the influence of the absolute value of the frequency on error evaluation, can more accurately reflect the deviation proportion of the actual frequency from the theoretical frequency, for example, the severity difference of the same absolute error at different theoretical frequencies, and can obtain unified and objective evaluation through the relative error, thereby providing a standardized quantitative index for subsequent threshold judgment.

[0088] S1-4-3, setting a reference time interval based on the relative frequency error of the controller instruction and the relative frequency error of the corresponding historical controller instruction;

[0089] By analyzing the relative frequency error of the current controller instruction and the sequence of the relative frequency error of the corresponding historical controller instruction in the past period of time, the fluctuation law, change trend and stability of the error are observed, and then the reference time interval is dynamically set. For example, if the historical error fluctuates less in the past 50 ms, such as within ±0.5%, and the difference between the current error and the historical error is <1%, the reference time interval is set to 50 ms (reflecting the stable state of the error); if the error fluctuates more than ±5% in the past 20 ms, such as from -10% to +8%, the reference time interval is set to 20 ms (capturing high-frequency fluctuations). In this embodiment, the reference time interval is dynamically updated according to the stability of the error, wherein the interval is increased to reduce the amount of calculation when the error is stable, and the interval is reduced to improve the response speed when the error fluctuates.

[0090] This step extends the error analysis at a single time point to trend analysis in the time dimension by introducing the reference time interval, avoids misjudgment caused by instantaneous error, improves the robustness of error detection, and at the same time dynamically adjusts the interval size according to the error characteristics, ensuring the accuracy of error detection while considering the system calculation efficiency.

[0091] S1-4-4, obtaining the frequency error value of the controller instruction according to the reference time interval and the relative frequency error of the controller instruction;

[0092] According to the set reference time interval, the change of the relative frequency error of the controller instruction in the time interval, for example, whether the error change is within the preset threshold, whether there is abnormal fluctuation, etc., the frequency error value of the controller instruction is determined. If the change amount of the relative frequency error in the reference time interval (such as 50 ms) is ≤ the preset threshold (such as ±1%), the average relative error in the time period is taken as the final frequency error value (such as -16.5%); if the change amount > the threshold (such as from -10% to -20% in 50 ms), the maximum deviation value (such as -20%) in the time period is taken and marked as “abnormal fluctuation”. In this embodiment, the final frequency error value can be described in combination with the error size and stability.

[0093] The error value output by this step not only contains the deviation size information, but also integrates the stability characteristics in the time dimension, making the error evaluation more comprehensive and providing more practical decision-making basis for the calibration of the controller, fault diagnosis, and adjustment of the system control strategy.

[0094] In summary, steps S1-4-1 to S1-4-4 obtain frequency error values with a wide range and both precision and practicality through quantitative analysis and trend judgment in the time dimension, accurately reflecting the deviation degree of the controller command and providing an operable basis for system optimization, such as triggering calibration, alarm, or adjusting the control strategy according to the error value.

[0095] As a possible implementation, in the above embodiment, step S2 can specifically include the following steps:

[0096] S2-1, setting an interpolation multiple and a frequency error threshold according to the frequency error value of the controller command;

[0097] The driver first presets two key parameters according to the system control accuracy requirement: an interpolation multiple N (such as 16 times) and a frequency error threshold Δ f th (for example, ±3%). The interpolation multiple N = floor ( T 0 / T 1) determines the time resolution of the command sequence, and the higher the multiple, the higher the subsequent error detection precision, but the greater the calculation load. Among them, floor (∙) represents the floor function; the frequency error threshold is used to distinguish between significant errors (coarse errors) that require fast response and small errors (fine errors) that require high-precision processing. When the detected command frequency error exceeds the threshold, the system needs to prioritize processing speed rather than precision. The settings of these two parameters need to consider the maximum allowed deviation of the controller, the calculation capability of the driver, and the smoothness requirement of the motion control.

[0098] In addition, the frequency error threshold in this embodiment is set to 3%, which takes into account the typical instantaneous error characteristics of 1%~5% of the industrial-grade independent clock, the tolerance of the system to errors exceeding 3% that can cause "periodic jitter of data", and the corresponding relationship with the "command frequency detection layer (coarse error detection)", ensuring that large errors can trigger linear interpolation and other corresponding processing.

[0099] S2-2, judging whether the frequency error value of the controller command is greater than or equal to the frequency error threshold, if yes, obtaining linear interpolation as the smoothing interpolation algorithm, and performing S2-3, otherwise, obtaining spline interpolation as the smoothing interpolation algorithm, and performing S2-3;

[0100] The driver selects an appropriate smooth interpolation algorithm, such as linear interpolation or cubic spline interpolation, based on the detected controller command frequency error (coarse error) and a set threshold. When the coarse error is |Δ f 粗 When |≥3%, linear interpolation algorithms with low computational cost and fast response speed are preferred. Their characteristic of requiring no additional communication time allows for rapid coverage of a large range of errors with low computational cost. When the coarse error |Δ f 粗 When the error rate is less than 3%, smoothness is prioritized, such as in precision motion control. Spline interpolation algorithms, which offer better fitting results, are chosen to enhance command smoothness. Polynomial fitting is used to extract frequency error values ​​within a smaller range, avoiding jitter in precision control. The choice of interpolation algorithm is related to the frequency error value of the controller command. An error-adaptive interpolation algorithm is selected, balancing computational efficiency and interpolation accuracy, ensuring that the interpolation results cover the error range while meeting real-time requirements.

[0101] S2-3. Use the interpolation factor and the smooth interpolation algorithm to perform interpolation caching on the controller instructions to obtain the frequency error information of the instruction cache.

[0102] The driver smoothly interpolates the controller's commands based on a set interpolation factor (e.g., 16x) using a selected smooth interpolation algorithm (linear / spline). This converts a single controller command into multiple commands, which are then buffered. The difference in the effective data volume within the buffer contains frequency error information between the controller and the driver. Due to the interpolation buffer, this information includes a small range of frequency error values. By detecting the dynamic changes in the number of effective commands in the buffer (reflecting the frequency matching status), the originally minute controller-driver frequency error (±0.1% level) is amplified into a quantifiable and detectable difference in the buffer state. This allows for the extraction of small-range frequency error values, ultimately forming the frequency error information of the command buffer. This interpolation buffering mechanism significantly improves the sensitivity of frequency error detection while maintaining command continuity through high-frequency processing.

[0103] In summary, steps S2-1 to S2-3 achieve dynamic matching of the algorithm through threshold grading, which ensures processing efficiency while taking into account instruction smoothness. This effectively compensates for the inconsistency of instruction transmission and obtains more refined error characteristics through cache analysis, providing a precise basis for subsequent control cycle adjustment and improving the response speed and stability of the entire control system.

[0104] As one possible implementation, in the above embodiments, step S2-3 may specifically include the following steps:

[0105] S2-3-1. Based on the interpolation factor, the smooth interpolation algorithm is used to perform smooth interpolation processing on the controller instructions to obtain a smooth interpolated controller instruction sequence;

[0106] The driver performs real-time interpolation processing on the received controller instructions based on a preset interpolation multiple (such as 16 times) and a selected smooth interpolation algorithm (linear or spline interpolation). Through the interpolation algorithm between adjacent instruction points, a single instruction of the controller is converted into multiple instructions, wherein the linear interpolation adopts uniform segmentation, and the spline interpolation maintains high-order continuity. During the insertion process, the theoretical timestamp offset of the instruction is calculated according to the frequency error value, to ensure that the parameters (such as position and speed instructions) of the intermediate instructions present a continuous transition state on the time axis. For example, if the original instructions result in uneven time intervals due to frequency errors, intermediate values conforming to the error trend are supplemented in the intervals with excessively large intervals through the interpolation algorithm, so that the entire instruction sequence has no obvious jumps in time and parameter dimensions, and finally a continuous and smooth interpolation instruction sequence, i.e., the smooth interpolation result of the controller instructions, is formed.

[0107] The process supplements reasonable intermediate instructions at positions with excessively large instruction intervals or jumps by performing operations on the original controller instruction sequence, so that the originally discontinuous instruction sequence due to frequency fluctuations becomes continuous and smooth, effectively eliminating the instruction discontinuity caused by frequency errors, and improving the time continuity and data integrity of the instruction sequence.

[0108] Taking linear interpolation as an example (interpolation multiple N = 16): two consecutive instruction points P k and P k+1 are obtained, the intermediate point P interp ( i ) is calculated, and then a 16 times instruction stream of the original frequency is formed, i.e., the controller instruction sequence of smooth interpolation is obtained. The intermediate point calculation formula is as follows:

[0109] P interp ( i )= P k +[( P k+1- P k )× i / N ]( i = 1, 2, …, 15)

[0110] wherein, i is the instruction point sequence number. For example, if P k = 0, P k+1 = 100, the sequence after interpolation is [0, 6.25, 12.5, …, 93.75, 100].

[0111] S2-3-2, cache processing the smooth interpolation controller instruction sequence to obtain a cache instruction change amount;

[0112] The controller instruction sequence after the smooth interpolation processing is stored in a preset cache space in chronological order to form a temporary data buffer area. At this time, the instruction density in the cache has been improved to a level suitable for the driver execution frequency through the interpolation multiple. The number of valid instructions in the cache area is detected in real time. When there is a frequency error between the controller and the driver, the storage speed of the instructions (determined by the controller instruction frequency) and the consumption speed (determined by the driver execution frequency) will not match, resulting in a cumulative or decreasing trend of the number of instructions in the cache. By recording the increase and decrease of the number of cache instructions per unit time, the cache instruction change amount can be obtained. This step provides an intuitive quantitative carrier for the embodiment of the frequency error through cache processing. The cache instruction change amount directly reflects the degree of frequency deviation between the controller and the driver.

[0113] S2-3-3, obtaining frequency error information of the instruction cache according to the cache instruction change amount, the interpolation multiple, and the theoretical control instruction period;

[0114] The cache instruction change amount ΔC is converted into a precise frequency error signal. The actual frequency deviation Δf is calculated by the formula Δf = ΔC / (I × T0), where I is the interpolation multiple, and T0 is the theoretical control instruction period. The error signal has an amplification effect of the interpolation multiple level. For example, 16 times interpolation can increase the detection sensitivity by 16 times and can identify small frequency deviations. For example, when the interpolation multiple is 16, the frequency deviation corresponding to the unit value of the cache instruction change amount is 1 / 16 of the original instruction frequency deviation. f C N T f N T

[0115] This step converts the cache instruction change amount into a specific frequency error value. Due to the effect of the interpolation multiple, the range of the error value is reduced, and the actual frequency deviation can be more accurately reflected. The finally integrated instruction cache frequency error information provides accurate and detailed data basis for subsequent control period dynamic adjustment.

[0116] ​​​​​​​In summary, steps S2-3-1 to S2-3-3 can effectively compensate for the discontinuity of instruction data through interpolation processing, improving the integrity and continuity of the instruction sequence, and the cache operation enhances the system's ability to resist instruction transmission fluctuations. The frequency error information obtained by the cache further refines the data dimension of the frequency error, which helps to improve the accuracy of subsequent adjustment. Interpolation cache processing focuses on a smaller range of frequency error values. For example, when the interpolation multiple is 16, the execution frequency of the driver is set to 16 times the controller instruction frequency. The corresponding period error will increase or decrease the number of valid instructions in the cache. By setting a threshold, the instruction consumption speed can be dynamically adjusted according to the increase or decrease in the number of valid instructions caused by the period error, and the frequency error information of the instruction cache is ultimately obtained.

[0117] As a possible implementation, in the above embodiment, step S3 can specifically include the following steps:

[0118] S3-1, weighting and fusing the frequency error value of the controller instruction and the frequency error information of the instruction cache to obtain a comprehensive error value;

[0119] According to the characteristics of the two types of errors, weights are assigned, for example, the cache error has a higher weight due to its more refined weight. By weighted calculation and combining time correlation correction conflict items, a comprehensive error value is obtained. This step can eliminate the limitations of a single error source and form a unified evaluation index that can fully reflect the frequency deviation of the system, providing accurate and comprehensive error basis for subsequent adjustment.

[0120] S3-2, determining a dynamic period adjustment parameter according to the comprehensive error value;

[0121] According to the comprehensive error value, a dynamic adjustment parameter is generated by table lookup method or PI controller. The table lookup method matches the preset adjustment strength according to the error size; the PI controller realizes smooth adjustment through proportional-integral operation. Double error fusion ensures fast response (coarse error) and high-precision synchronization (fine error), avoiding over-adjustment or under-adjustment problems caused by a single error source.

[0122] S3-3, adjusting the carrier period of the controller using the dynamic period adjustment parameter to obtain a control instruction rate matching result;

[0123] According to the obtained adjustment parameter, the carrier period is adjusted to change the instruction cache consumption rate, and the rate matching situation is detected. If the deviation is within the threshold, it is determined that the matching is successful, otherwise the adjustment is repeated. This process realizes dynamic rate matching through closed-loop adjustment to ensure stable operation of the system.

[0124] In summary, the controller instruction and the frequency error of the instruction cache are fused to obtain a comprehensive error value, and the dynamic period adjustment parameter is determined according to the comprehensive error value, and finally the carrier period is adjusted by using the parameter, the rate dynamic matching is realized through closed loop detection, and the stable operation of the system is ensured.

[0125] As a possible implementation, in the above embodiment, step S3-1 can specifically include the following steps:

[0126] S3-1-1, setting the frequency error threshold value of the controller instruction as the coarse error threshold value according to the frequency error value of the controller instruction;

[0127] According to the frequency error value Δ f coarse The coarse error threshold value is dynamically set as the critical value for distinguishing between large deviation and small deviation, and the coarse error threshold value is ±1% in the embodiment. When Δ f coarse When the threshold value is exceeded, it is determined that there is a significant clock deviation in the system, and the coarse error dominant adjustment strategy needs to be used preferentially; otherwise, the fine adjustment mode is entered. The threshold value can be configured according to the actual application scene, for example, set to ±2% in a high dynamic scene and ±0.5% in a fine control scene. This step can realize automatic classification of error states and provide a basis for subsequent weight allocation, avoiding oscillation caused by frequent switching of adjustment modes.

[0128] S3-1-2, judging whether the frequency error value of the controller instruction is greater than the coarse error threshold value, if yes, obtaining the frequency error value weight of the first controller instruction and the frequency error information weight of the first instruction cache as the weight allocation result, and executing S3-1-3, otherwise, obtaining the frequency error value weight of the second controller instruction and the frequency error information weight of the second instruction cache as the weight allocation result, and executing S3-1-3;

[0129] By comparing the frequency error and the coarse error threshold value, different weight combinations are selected. When a large deviation is detected, the system preferentially adopts the coarse error dominant fast adjustment strategy to ensure that the system state is pulled back to the safe range in a short time; when the error is reduced to below the threshold value, the fine error dominant fine adjustment mode is automatically switched to, and the system state is continuously optimized. Specifically:

[0130] |Δ f coarse |>threshold value (large deviation mode): the first weight combination, that is, the frequency error value weight of the first controller instruction W coarse =0.8, the frequency error information weight of the first instruction cache W fine= 0.2, focusing on fast coarse error suppression of main deviation;

[0131] |Δ f coarse |≤ threshold (small deviation mode): second weight combination, i.e. the frequency error value weight of the second controller instruction W coarse = 0.2, the frequency error information weight of the second instruction cache W fine = 0.8, depending on fine error to achieve fine tuning.

[0132] The weight values in this embodiment can be self-tuned online. This dynamic weight distribution mechanism enables the system to quickly respond when significant deviation occurs, and to maintain high control precision under stable working conditions, ultimately achieving a perfect balance between response speed and steady-state accuracy.

[0133] S3-1-3, based on the weight distribution result, weighted fusion processing is performed on the frequency error value of the controller instruction and the frequency error information of the instruction cache to obtain a comprehensive error value;

[0134] Based on the allocated weight, the frequency error value Δ f coarse of the controller instruction is weighted and fused with the frequency error information Δ f fin of the instruction cache.

[0135] Δ f total = W coarse ⋅Δ f coarse + W fine ⋅Δ f fine

[0136] Wherein, Δ f total is the comprehensive error value after fusion. The output comprehensive error value is used for subsequent carrier period and duty cycle co-adjustment, which provides a more comprehensive and accurate error reference for subsequent adjustment, avoiding the one-sidedness of adjustment caused by a single error source. In addition, before fusion, Δ f coarse is subjected to moving average filtering, and Δ f fine is subjected to ±5% change rate limiting to suppress noise interference.

[0137] In summary, steps S3-1-1 to S3-1-3 achieve adaptive adjustment of the weight, highlighting the role of the cache error information optimized by interpolation when the error is large, and retaining the dominance of the original instruction error when the error is small, so that the integrated error value can more accurately reflect the actual deviation state of the system, providing a more reliable error basis for subsequent adjustment, and improving the flexibility and accuracy of error fusion.

[0138] As a possible implementation, in the above embodiment, step S3-2 can specifically include the following steps:

[0139] S3-2-1, setting an integrated error threshold according to the integrated error value;

[0140] The setting of the integrated error threshold is based on the response demand and adjustment accuracy of the system to the deviation, and is determined in combination with the influence degree of the deviation on the rate matching of the control instruction in actual operation. Here, the integrated error threshold is set to 0.1, that is, when |Δ f total |>0.1, it is determined that there is a large deviation; when |Δ f total |≤0.1, it is determined that there is a small deviation. The setting of this threshold not only considers the need for rapid adjustment to prevent obvious rate mismatch, abnormal instruction caching and other problems in the system under large deviation, but also takes into account the need for fine adjustment to ensure control accuracy under small deviation, and can effectively distinguish different deviation levels to provide clear and explicit judgment criteria for subsequent selection of appropriate adjustment mode.

[0141] S3-2-2, judging whether the integrated error value is greater than the integrated error threshold, if yes, acquiring a dynamic period adjustment parameter according to the integrated error value using a lookup table method, otherwise, inputting the integrated error value into a PI controller to acquire a dynamic period adjustment parameter;

[0142] When the integrated error value exceeds the preset integrated error threshold, it indicates that the current deviation of the system is large, and rapid adjustment is needed to avoid further expansion of the deviation. At this time, the dynamic period adjustment parameter is acquired by using the lookup table method. This method is to pre-establish a correspondence table between the integrated error value and the dynamic period adjustment parameter according to a large amount of experimental data and simulation results, which covers the best adjustment parameters such as period shortening or lengthening amount corresponding to different ranges of integrated error values. In actual application, only the matching adjustment parameter needs to be found in the correspondence table according to the current integrated error value. The advantage of this method is fast response, which can quickly respond to large errors, ensure that the system returns to a relatively stable state in a short time, and avoid problems such as instruction cache overflow or idling caused by adjustment delay.

[0143] When the integrated error value is within the integrated error threshold range, the system deviation is small, and fine adjustment is needed to achieve accurate matching of the control instruction rate. The PI controller (proportional-integral controller) can quickly respond to the current error through the proportional link and eliminate the steady-state error through the integral link, which is very suitable for this small deviation adjustment scenario. After inputting the integrated error value into the PI controller, the proportional link outputs the corresponding adjustment amount according to the size of the error, so that the adjustment speed is proportional to the error size; the integral link accumulates the error and outputs the adjustment amount according to the accumulated amount to eliminate the small deviation that exists for a long time. Through the comprehensive action of the PI controller, accurate dynamic periodic adjustment parameters can be output, so that the system gradually tends to be stable under the condition of small deviation, high-precision matching of the control instruction rate is achieved, and the adverse effects of frequent and violent adjustment on system stability are avoided.

[0144] As a possible implementation, in the above embodiment, step S3-3 can specifically include the following steps:

[0145] S3-3-1, calculating a target carrier period using the dynamic periodic adjustment parameter;

[0146] First, the reference carrier period of the current controller is determined, i.e., the initial period without adjustment, and then the target carrier period is calculated according to the dynamic periodic adjustment parameter. Assuming that the period adjustment amount is ±5%, if the adjustment parameter is to increase by 5%, the target carrier period = reference carrier period x (1+5%); if the adjustment parameter is to decrease by 5%, the target carrier period = reference carrier period x (1-5%).

[0147] S3-3-2, adjusting the carrier period of the controller according to the target carrier period to obtain an adjusted carrier period;

[0148] The controller is internally provided with a carrier period adjustment module, and the calculated target carrier period is input into the module. The module adjusts the current carrier period to the target value by changing the clock signal frequency or the counting period, etc. During the adjustment process, the smoothness of the period change is detected in real time to avoid system oscillation caused by instantaneous large adjustment, for example, for ±5% adjustment under large deviation, the smooth transition can be achieved by phased fine adjustment. This step converts the theoretically calculated target period into the actual running period of the controller, laying a foundation for changing the instruction cache consumption rate.

[0149] S3-3-3, detecting the instruction cache state and the controller instruction input rate based on the adjusted carrier period;

[0150] After adjusting the carrier period, the real-time filling amount of the instruction cache, i.e., the number of instructions not executed in the current cache, and the input rate of the control instruction, i.e., the number of instructions input per unit time, are continuously collected.

[0151] S3-3-4, obtaining a control instruction rate matching result according to the instruction cache state and the control instruction input rate combined with the control instruction rate matching determination condition;

[0152] When the real-time filling amount of the instruction cache and the controller instruction input rate meet the control instruction rate matching determination condition, it is determined that the control instruction rate matching is successful as the control instruction rate matching result; if the real-time filling amount of the instruction cache and the controller instruction input rate do not meet the control instruction rate matching determination condition, it is determined that the control instruction rate matching is unsuccessful as the control instruction rate matching result, and at the same time, it is necessary to return to the comprehensive error calculation link to obtain the adjustment parameter and adjust the period again until the matching condition is reached. Through closed-loop detection and feedback, this step ensures that the system ultimately realizes stable rate matching.

[0153] In summary, steps S3-3-1 to S3-3-4 combine the dynamic period adjustment parameter and the reference carrier period to calculate the target period, and smooth the carrier period, and then detect the cache state and the instruction input rate to obtain the matching result. Through the closed-loop feedback mechanism, this process realizes the dynamic matching of the control instruction rate, effectively improves the control accuracy and stability of the system, and avoids the problems of instruction cache overflow or idling caused by rate mismatch.

[0154] Further, the control instruction rate matching determination condition is:

[0155] The instruction cache state is stable in a preset interval, and the controller instruction input rate is less than a controller instruction input rate threshold.

[0156] The matching determination condition is set as: when the cache filling amount is stable in a preset interval, and the deviation of the input rate and the cache consumption rate determined by the carrier period, i.e., the controller instruction input rate threshold, is less than 5%. The preset interval of this embodiment is set to 30%-70% of the total capacity.

[0157] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0158] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0159] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0160] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0161] Finally, it should be noted that the above-mentioned embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the same. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalent replaced without departing from the spirit and scope of the present application, and any modification or equivalent replacement should be covered within the scope of protection of the claims of the present application.

Claims

1. A method for matching control command rates between a distributed controller and a driver, characterized in that, include: S1. Utilize the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command, including: The dual timers are initialized based on the clock source of the driver, and the dual timers include a first timer and a second timer; The actual control command cycle is obtained using the first timer based on the clock source of the driver; The theoretical control command cycle is generated using the second timer; The actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command, including: The actual controller command frequency and the theoretical controller command frequency are calculated using the actual control command cycle and the theoretical control command cycle, respectively. The error between the actual controller command frequency and the theoretical controller command frequency is calculated, and the relative frequency error between the actual controller command frequency and the theoretical controller command frequency is obtained as the relative frequency error of the controller command. A reference time interval is set based on the relative frequency error of the controller command and the relative frequency error of the corresponding historical control command. The frequency error value of the controller command is obtained based on the relative frequency error between the reference time interval and the controller command. S2. Based on the frequency error value of the controller command, perform interpolation buffering processing on the controller command to obtain the frequency error information of the command buffer, including: Based on the frequency error value of the controller command, set the interpolation factor and the frequency error threshold; Determine whether the frequency error value of the controller command is greater than or equal to the frequency error threshold. If so, obtain linear interpolation as a smooth interpolation algorithm and execute the first operation; otherwise, obtain spline interpolation as a smooth interpolation algorithm and execute the first operation. The first operation is as follows: using the interpolation factor and the smooth interpolation algorithm to perform interpolation caching on the controller instructions, and obtaining the frequency error information of the instruction cache; S3. Perform dynamic periodic adjustment based on the frequency error value of the controller command and the frequency error information of the command cache to obtain the control command rate matching result, including: The frequency error value of the controller command is weighted and fused with the frequency error information of the command cache to obtain a comprehensive error value; Based on the comprehensive error value, determine the dynamic periodic adjustment parameters; The carrier period of the controller is adjusted using the dynamic period adjustment parameters to obtain the control command rate matching result.

2. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, The controller instructions are interpolated and cached using the interpolation factor and the smooth interpolation algorithm to obtain frequency error information of the instruction cache, including: Based on the interpolation factor, the controller instructions are smoothly interpolated using the smooth interpolation algorithm to obtain a smoothly interpolated controller instruction sequence. The controller instruction sequence of the smooth interpolation is cached to obtain the change in the cached instructions; Based on the change in cached instructions, the interpolation factor, and the theoretical control instruction cycle, the frequency error information of the instruction cache is obtained.

3. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, The frequency error value of the controller command and the frequency error information of the command cache are weighted and fused to obtain a comprehensive error value, including: Based on the frequency error value of the controller command, set the frequency error threshold of the controller command as the coarse error threshold; Determine whether the frequency error value of the controller instruction is greater than the coarse error threshold. If so, obtain the frequency error value weight of the first controller instruction and the frequency error information weight of the first instruction cache as the weight allocation result, and perform the second operation. Otherwise, obtain the frequency error value weight of the second controller instruction and the frequency error information weight of the second instruction cache as the weight allocation result, and perform the second operation. The second operation is as follows: based on the weight allocation result, the frequency error value of the controller instruction and the frequency error information of the instruction cache are weighted and fused to obtain a comprehensive error value.

4. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, Based on the comprehensive error value, the dynamic periodic adjustment parameters are determined, including: Based on the comprehensive error value, a comprehensive error threshold is set; Determine whether the overall error value is greater than the overall error threshold. If so, obtain the dynamic periodic adjustment parameter using a lookup table based on the overall error value. Otherwise, input the overall error value into the PI controller to obtain the dynamic periodic adjustment parameter.

5. The control command rate matching method for a distributed controller-driver according to claim 1, characterized in that, Adjusting the carrier period of the controller using the dynamic period adjustment parameters to obtain the control command rate matching result includes: The target carrier period is calculated using the aforementioned dynamic period adjustment parameters; The carrier period of the controller is adjusted according to the target carrier period to obtain the adjusted carrier period; Based on the adjusted carrier period, detection processing is performed to obtain the instruction buffer status and the controller instruction input rate; Based on the instruction cache status and the controller instruction input rate combined with the control instruction rate matching determination condition, the control instruction rate matching result is obtained.

6. The control command rate matching method for a distributed controller-driver according to claim 5, characterized in that, The control command rate matching determination condition is as follows: The instruction cache state is stable within a preset range, and the controller instruction input rate is less than the controller instruction input rate threshold.

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