Multi-domain modular multiplication algorithm device and modular multiplication operation method

Abstract

The embodiment of the invention provides a multi-domain modular multiplication algorithm device and a modular multiplication operation method. The multi-domain modular multiplication algorithm device comprises an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit and an output unit. The multi-domain multiplication unit is constructed by multi-domain multiplication subunits at the lowest level step by step; the input unit receives input data, and the input data comprises first sub-data, second sub-data and configuration data; inputting the input data into a target multi-domain multiplication subunit in the multi-domain multiplication unit; the target multi-domain multiplication subunit performs multiplication operation of a target operation domain on the first subdata and the second subdata by utilizing multi-level multi-domain multiplication subunits under the target multi-domain multiplication subunit to obtain a target operation result; the multi-domain fast modular reduction unit performs reduction operation of a target operation domain on the target operation result to obtain a modular multiplication algorithm result; and the output unit outputs a modular multiplication algorithm result. According to the scheme, modular multiplication operation of data with various input bit widths and different operation domains can be supported.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cryptographic operation, in particular to a multi-domain modular multiplication algorithm and a modular multiplication method. BACKGROUND

[0002] Modular multiplication algorithm is one of the core operations of cryptography, and is widely used in encryption algorithms such as Elliptic Curve Cryptography (ECC), asymmetric encryption algorithm (SM2) based on ECC, and Rivest-Shamir-Adleman (RSA).

[0003] Current modular multiplication algorithm includes Wallace tree modular multiplication algorithm and Montgomery modular multiplication algorithm. These modular multiplication algorithms take fixed-bit-width operation data as input and perform modular multiplication operation in a specified operation domain, and cannot support modular multiplication operation of operation data with multiple input bit widths and different operation domains. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a multi-domain modular multiplication algorithm and a modular multiplication method to support modular multiplication operation of operation data with multiple input bit widths and different operation domains. The specific technical solutions are as follows:

[0005] In a first aspect, the embodiments of the present application provide a multi-domain modular multiplication algorithm, which includes an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit and an output unit; the input unit is connected with the multi-domain multiplication unit, the multi-domain multiplication unit is connected with the multi-domain fast modular reduction unit, and the multi-domain fast modular reduction unit is connected with the output unit; the multi-domain multiplication unit includes multi-level multi-domain multiplication subunits, and in the multi-domain multiplication unit, the multi-domain multiplication subunit of a non-lowest level includes a plurality of multi-domain multiplication subunits of a next level;

[0006] The input unit receives input data, the input data includes first sub-data, second sub-data and configuration data, the configuration data indicates a target operation domain where modular multiplication operation is located, and effective bit widths of the first sub-data and the second sub-data; the input data is input into a target multi-domain multiplication subunit corresponding to the effective bit widths in the multi-domain multiplication unit;

[0007] The target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data by using multi-level multi-domain multiplication subunits under the target multi-domain multiplication subunit, to obtain a target operation result; and the target operation result is input into the multi-domain fast modular reduction unit;

[0008] The multi-domain fast modulo reduction unit performs a reduction operation of the target operation domain on the target operation result to obtain the modulo multiplication algorithm result; and inputs the modulo multiplication algorithm result into the output unit;

[0009] The output unit outputs the modulo multiplication algorithm result.

[0010] In some embodiments, the configuration data includes a first bit width field and a second bit width field; the first bit width field carries a bit width encoding value indicating the effective bit width; and the second bit width field carries a domain encoding value indicating the target operation domain.

[0011] The input unit inputs the input data into a target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit, including:

[0012] The input unit determines, according to a correspondence relationship between an input bit width, the bit width encoding value and the domain encoding value, an input bit width corresponding to the bit width encoding value carried by the first bit width field and the domain encoding value carried by the second bit width field as the effective bit width of the first sub-data and the second sub-data; determines a target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit; and inputs the input data into the target multi-domain multiplication subunit.

[0013] In some embodiments, the configuration data further includes a third bit width field carrying an enable encoding value indicating enabling / disabling of a multiplier.

[0014] The input unit determines a target multi-domain multiplication subunit corresponding to the effective bit width and the enable encoding value in the multi-domain multiplication unit.

[0015] The multi-domain fast modulo reduction unit performs a reduction operation of the target operation domain on the target operation result to obtain the modulo multiplication algorithm result in a case where the enable encoding value indicates disabling of the multiplier.

[0016] The multi-domain fast modulo reduction unit inputs the target operation result into the output unit in a case where the enable encoding value indicates enabling of the multiplier; and the output unit outputs the target operation result.

[0017] In some embodiments, the multi-domain multiplication subunit of the non-lowest level further includes a multi-input multi-domain adder and a first register; the multi-input multi-domain adder is connected with a plurality of multi-domain multiplication subunits of a next level; the multi-input multi-domain adder is connected with the first register; and the first register is connected with a plurality of multi-domain multiplication subunits of a previous level.

[0018] The target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data to obtain a target operation result, including:

[0019] The lowest level multi-domain multiplication subunit under the target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data to obtain an intermediate operation result, and inputs the intermediate operation result into a multiple-input multiple-domain adder of a higher level multi-domain multiplication subunit;

[0020] The multiple-input multiple-domain adder of the non-lowest level multi-domain multiplication subunit under the target multi-domain multiplication subunit performs addition operation of the target operation domain on the received intermediate operation result to obtain a new intermediate operation result; and writes the new intermediate operation result into the first register;

[0021] If the non-lowest level multi-domain multiplication subunit is a non-highest level multi-domain multiplication subunit, the first register inputs the new intermediate operation result into the multiple-input multiple-domain adder of the higher level multi-domain multiplication subunit; if the non-lowest level multi-domain multiplication subunit is a highest level multi-domain multiplication subunit, the first register takes the new intermediate operation result as the target operation result.

[0022] In some embodiments, the lowest level multi-domain multiplication subunit includes an encoding module, a multi-domain Wallace tree compression module, a first multi-domain fast summation module, and a second register;

[0023] The encoding module is connected with the multi-domain Wallace tree compression module, the multi-domain Wallace tree compression module is connected with the first multi-domain fast summation module, and the first multi-domain fast summation module is connected with the second register;

[0024] The lowest level multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data to obtain an intermediate operation result, including:

[0025] In the lowest level multi-domain multiplication subunit, the encoding module performs encoding operation on the first sub-data by using base coefficients to obtain a plurality of groups of partial products, and inputs the plurality of groups of partial products into the multi-domain Wallace tree compression module;

[0026] In the lowest level multi-domain multiplication subunit, the multi-domain Wallace tree compression module performs compression summation operation of the target operation domain on the received plurality of groups of partial products to obtain a first compression operation result, and inputs the first compression operation result into the first multi-domain fast summation module;

[0027] In the lowest level multi-domain multiplication subunit, the first multi-domain fast summation module performs addition operation of the target operation domain on the received first compressed operation result to obtain an intermediate operation result, and writes the intermediate operation result into the second register.

[0028] In some embodiments, the target operation domain is a prime number domain, and the first multi-domain fast summation module performs addition operation of the target operation domain on the received first compressed operation result to obtain an intermediate operation result, including: the first multi-domain fast summation module performs serial carry addition operation on the received first compressed operation result to obtain an intermediate operation result.

[0029] The target operation domain is a binary domain, and the first multi-domain fast summation module performs addition operation of the target operation domain on the received first compressed operation result to obtain an intermediate operation result, including: the first multi-domain fast summation module performs exclusive or operation on the received first compressed operation result to obtain an intermediate operation result.

[0030] In some embodiments, the multi-input multi-domain adder includes a multi-domain compression module and a second multi-domain fast summation module; the multi-domain compression module is connected with the second multi-domain fast summation module, and the second multi-domain fast summation module is connected with the first register.

[0031] The multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit performs addition operation of the target operation domain on the received intermediate operation result to obtain a new intermediate operation result, including:

[0032] In the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit, the multi-domain compression module performs compressed summation operation of the target operation domain on the received intermediate operation result to obtain a second compressed operation result, and inputs the second compressed operation result into the second multi-domain fast summation module.

[0033] In the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit, the second multi-domain fast summation module performs addition operation of the target operation domain on the received second compressed operation result to obtain a new intermediate operation result, and writes the new intermediate operation result into the first register.

[0034] In some embodiments, in the multi-domain multiplication unit, the non-lowest level multi-domain multiplication subunit includes four next level multi-domain multiplication subunits, the multi-input multi-domain adder is a four-input multi-domain adder, and the encoding module is a base-4 booth encoding module.

[0035] In some embodiments, the multi-domain fast modular reduction unit comprises an input subunit, a plurality of reduction subunits corresponding to the operation domains, and a third register; the input subunit is connected with each reduction subunit corresponding to the operation domains, and each reduction subunit corresponding to the operation domains is connected with the third register;

[0036] The multi-domain fast modular reduction unit performs the reduction operation of the target operation domain on the target operation result to obtain the modular multiplication algorithm result, comprising:

[0037] The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain;

[0038] The target reduction subunit performs the reduction operation on the target operation result to obtain the modular multiplication algorithm result, and writes the modular multiplication algorithm result into the third register.

[0039] In some embodiments, the configuration data indicates enabling / disabling the multiplier; the input subunit is further connected with the third register;

[0040] The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain, comprising: the input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain when the configuration data indicates disabling the multiplier;

[0041] The input subunit writes the target operation result into the third register when the configuration data indicates enabling the multiplier.

[0042] In some embodiments, the target operation domain is a prime number domain, and the multi-domain fast modular reduction unit performs the reduction operation of the target operation domain on the target multiplication operation result to obtain the modular multiplication algorithm result, comprising: the multi-domain fast modular reduction unit performs addition and subtraction operation and shift operation on the target multiplication operation result to obtain the modular multiplication algorithm result;

[0043] The target operation domain is a binary domain, and the multi-domain fast modular reduction unit performs the reduction operation of the target operation domain on the target operation result to obtain the modular multiplication algorithm result, comprising: the multi-domain fast modular reduction unit performs state machine operation and exclusive OR operation on the target operation result to obtain the modular multiplication algorithm result.

[0044] In a second aspect, the embodiments of the present application provide a modular multiplication operation method, applied to a multi-domain modular multiplication algorithm device, the multi-domain modular multiplication algorithm device comprising an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit and an output unit; the input unit is connected with the multi-domain multiplication unit, the multi-domain multiplication unit is connected with the multi-domain fast modular reduction unit, and the multi-domain fast modular reduction unit is connected with the output unit; the multi-domain multiplication unit comprises multi-level multi-domain multiplication sub-units, and in the multi-domain multiplication unit, the multi-domain multiplication sub-units in a non-lowest level comprise a plurality of multi-domain multiplication sub-units in a next level; the method comprises:

[0045] The input unit receives input data, the input data comprising first sub-data, second sub-data and configuration data, the configuration data indicating a target operation domain where the modular multiplication operation is located, and effective bit widths of the first sub-data and the second sub-data; the input data is input into a target multi-domain multiplication sub-unit corresponding to the effective bit widths in the multi-domain multiplication unit;

[0046] The target multi-domain multiplication sub-unit performs multiplication operation on the first sub-data and the second sub-data in the target operation domain by using the multi-domain multiplication sub-units in a plurality of levels under the target multi-domain multiplication sub-unit, to obtain a target operation result; and the target operation result is input into the multi-domain fast modular reduction unit;

[0047] The multi-domain fast modular reduction unit performs reduction operation on the target operation result in the target operation domain, to obtain the modular multiplication algorithm result; and the modular multiplication algorithm result is input into the output unit;

[0048] The output unit outputs the modular multiplication algorithm result.

[0049] The embodiments of the present application have the following beneficial effects:

[0050] In the technical scheme provided by the embodiments of the present application, the input data received by the input unit indicates an operation domain (i.e. a target operation domain) where the modular multiplication operation is located, and indicates effective bit widths of operation data. The multi-domain multiplication unit and the multi-domain fast modular reduction unit support operations in multiple operation domains. The multi-domain multiplication unit and the multi-domain fast modular reduction unit respectively perform operations on operation data with the effective bit widths indicated by the input data in the target operation domain indicated by the input data, to obtain the required modular multiplication algorithm result, and then output the modular multiplication algorithm result. In the embodiments of the present application, different operation data can have different effective bit widths, and the operation domains can also be different. By indicating the operation domain and the effective bit widths by the input data, modular multiplication operations on operation data with multiple input bit widths and in different operation domains are realized.

[0051] Of course, implementing any product or method of the present application does not necessarily require all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and other embodiments can be obtained by those skilled in the art based on these drawings.

[0053] Figure 1 A structural schematic diagram of a multi-domain multiplication algorithm provided by the embodiment of the present application;

[0054] Figure 2 A schematic diagram of the building relationship between two-level multi-domain multiplication sub-units provided by the embodiment of the present application;

[0055] Figure 3 A structural schematic diagram of a 576-bit wide multi-domain multiplication unit provided by the embodiment of the present application;

[0056] Figure 4 A structural schematic diagram of a multi-domain multiplication sub-unit of the lowest level provided by the embodiment of the present application;

[0057] Figure 5a A schematic diagram of the input and output signals of a common 3:2 compressor;

[0058] Figure 5b A schematic diagram of the structure of a common 3:2 compressor;

[0059] Figure 5c A schematic diagram of the input and output signals of a dual-domain 3:2 compressor provided by the embodiment of the present application;

[0060] Figure 5d A schematic diagram of the structure of a dual-domain 3:2 compressor provided by the embodiment of the present application;

[0061] Figure 6a A schematic diagram of the input and output signals of a common 4:2 compressor;

[0062] Figure 6b A schematic diagram of the structure of a common 4:2 compressor;

[0063] Figure 6c A schematic diagram of the input and output signals of a dual-domain 4:2 compressor provided by the embodiment of the present application;

[0064] Figure 6d A schematic diagram of the structure of a dual-domain 4:2 compressor provided by the embodiment of the present application;

[0065] Figure 7a A schematic diagram of the input and output signals of a common 5:2 compressor;

[0066] Figure 7b A schematic diagram of the structure of a common 5:2 compressor;

[0067] Figure 7c A schematic diagram of the input and output signals of a dual-domain 5:2 compressor provided by embodiments of the present application;

[0068] Figure 7d A schematic diagram of the structure of a dual-domain 5:2 compressor provided by embodiments of the present application;

[0069] Figure 8 A schematic diagram of the structure of a first multi-domain fast-sum module provided by embodiments of the present application;

[0070] Figure 9 A schematic diagram of the structure of a dual-domain fast-sum module provided by embodiments of the present application;

[0071] Figure 10a A first schematic diagram of the structure of a multi-domain fast-mod-reduction unit 13 provided by embodiments of the present application;

[0072] Figure 10b A second schematic diagram of the structure of a multi-domain fast-mod-reduction unit 13 provided by embodiments of the present application;

[0073] Figure 11 A schematic diagram of the structure of a dual-domain modular multiplication algorithm provided by embodiments of the present application;

[0074] Figure 12a A first partial schematic diagram of the structure of a dual-domain multiplication unit provided by embodiments of the present application;

[0075] Figure 12b A second partial schematic diagram of the structure of a dual-domain multiplication unit provided by embodiments of the present application;

[0076] Figure 12c A third partial schematic diagram of the structure of a dual-domain multiplication unit provided by embodiments of the present application;

[0077] Figure 12d A fourth partial schematic diagram of the structure of a dual-domain multiplication unit provided by embodiments of the present application;

[0078] Figure 13 A schematic diagram of the structure of an 18-bit dual-domain multiplication subunit provided by embodiments of the present application;

[0079] Figure 14 A schematic diagram of the compression array of a dual-domain Wallace tree compression module provided by embodiments of the present application;

[0080] Figure 15A structural schematic diagram of a 36-bit 4-input dual-domain adder provided for an embodiment of the present application is shown in FIG. 1.

[0081] Figure 16 A structural schematic diagram of a dual-domain fast modular reduction unit provided for an embodiment of the present application is shown in FIG. 2.

[0082] Figure 17 A flowchart of a modular multiplication method provided for an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0084] For the sake of understanding, the terms appearing in the embodiments of the present application will be explained below.

[0085] Modular multiplication (MM): an operation of performing multiplication on a finite field. In elliptic curve cryptography, it is often necessary to perform modular multiplication on data in a finite field to ensure that the result is within the range of the finite field.

[0086] RSA (Rivest-Shamir-Adleman): a non-symmetric encryption algorithm based on large integer factorization, widely used in digital signature, key exchange and other fields. Although RSA has some limitations in some aspects, it is still one of the commonly used encryption algorithms in many secure communication protocols and systems.

[0087] ECC: by using point operation on an elliptic curve, to realize functions such as encryption and digital signature. Compared with RSA algorithm, ECC has shorter key length and higher security under the same security, suitable for use in resource-limited environment.

[0088] SM2: an elliptic curve public key cryptography algorithm standard, used in digital signature, key exchange and other fields. Compared with ECC, SM2 differs in some parameter selection and algorithm details, but as a whole belongs to the category of elliptic curve cryptography.

[0089] Modular multiplication algorithm is one of the core operations in cryptography, widely used in ECC, SM2, RSA and other encryption algorithms. In these encryption algorithms, modular multiplication plays a crucial role. For example, in ECC algorithm, modular multiplication is the basis for implementing point addition and scalar multiplication, while point addition and scalar multiplication are the core of ECC encryption, signature and key exchange. In RSA algorithm, modular exponentiation relies on modular multiplication, and the efficiency of modular multiplication directly affects the encryption and decryption speed and signature verification performance of RSA.

[0090] In addition, modular multiplication algorithm is also widely used in other cryptography fields, such as Diffie-Hellman key exchange, Digital Signature Algorithm (DSA) and coding theory based on finite field.

[0091] In these scenarios, efficient implementation of modular multiplication is crucial for improving system performance and security.

[0092] In practical applications, many cryptography algorithms need to support modular multiplication of different operation domains at the same time. Among them, the operation domain can include prime field (GF(p)) and binary field (GF(2^n)) and the like.

[0093] Although modular multiplication algorithm can be implemented by software, compared with software implementation, modular multiplication algorithm has significant advantages in performance, power consumption and security and the like through hardware implementation. Traditional modular multiplication hardware implementation is usually optimized for a single operation domain and a single bit width, and cannot efficiently support multiple input bit width data and multiple operation domain operations at the same time.

[0094] To solve the above problems, the embodiment of the present application provides a multi-domain modular multiplication algorithm, as shown in Figure 1 The input unit 11, the multi-domain multiplication unit 12, the multi-domain fast modular reduction unit 13 and the output unit 14; the input unit 11 is connected with the multi-domain multiplication unit 12, the multi-domain multiplication unit 12 is connected with the multi-domain fast modular reduction unit 13, and the multi-domain fast modular reduction unit 13 is connected with the output unit 14; the multi-domain multiplication unit 12 includes multi-level multi-domain multiplication subunits, and in the multi-domain multiplication unit 12, the multi-domain multiplication subunit of the non-lowest level includes a plurality of multi-domain multiplication subunits of the next level;

[0095] The input unit 11 receives input data, and the input data includes first sub-data, second sub-data and configuration data, the configuration data indicating a target operation domain where the modular multiplication operation is located, and effective bit widths of the first sub-data and the second sub-data; the input data is input into the target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit;

[0096] The target multi-domain multiplication subunit utilizes a multi-layer multi-domain multiplication subunit under the target multi-domain multiplication subunit to perform multiplication operation in a target operation domain on the first sub-data and the second sub-data, to obtain a target operation result; and the target operation result is input into the multi-domain fast modulus reduction unit 13.

[0097] The multi-domain fast modulus reduction unit 13 performs reduction operation in the target operation domain on the target operation result, to obtain a modulus multiplication algorithm result; and the modulus multiplication algorithm result is input into the output unit 14.

[0098] The output unit 14 outputs the modulus multiplication algorithm result.

[0099] In the technical scheme provided by the embodiments of the present application, the input data received by the input unit indicates an operation domain (i.e. a target operation domain) in which the modulus multiplication operation is located, and indicates the effective bit width of the operation data. The multi-domain multiplication unit and the multi-domain fast modulus reduction unit support operation in multiple operation domains. The multi-domain multiplication unit and the multi-domain fast modulus reduction unit perform operation on the operation data of the effective bit width indicated by the input data in the target operation domain indicated by the input data, to obtain the required modulus multiplication algorithm result, and then output the modulus multiplication algorithm result. In the embodiments of the present application, the effective bit width of different operation data can be different, and the operation domain can also be different. By indicating the operation domain and the effective bit width through the input data, modulus multiplication operation in multiple input bit width operation data and different operation domains is realized.

[0100] In the embodiments of the present application, the input unit 11 (input) can also be referred to as a data dispatch unit. The input unit 11 receives data input by a user or other hardware, such as input data. The input data can include the following two parts of information:

[0101] 1) operation data, i.e. first sub-data and second sub-data.

[0102] In the embodiments of the present application, the first sub-data and the second sub-data can be a key that needs to be subjected to modulus multiplication operation, or the first sub-data and the second sub-data can be data that needs to be subjected to multiplication operation.

[0103] 2) configuration data (config).

[0104] In the embodiments of the present application, the configuration data is configuration information included in the input data. The configuration data indicates the target operation domain in which the modulus multiplication operation is located, and the configuration data also indicates the effective bit width of the first sub-data and the second sub-data.

[0105] For example, the input data includes first sub-data A and second sub-data B, and the bit width of the first sub-data A and the second sub-data B is 571 bits. In this case, the first sub-data A can be represented as A[570:0], and the second sub-data B can be represented as B[570:0]. The configuration data indicates that the effective bit width of the operation data is 283. In this case, the effective number data of the first sub-data A with the bit width of 571 bits can be represented as A'[282:0], and the effective number data of the second sub-data B with the bit width of 571 bits can be represented as B'[282:0].

[0106] In some embodiments, the configuration data can include a first bit width field and a second bit width field. The first bit width field carries a bit width encoding value indicating an effective bit width, and the second bit width field carries a domain encoding value indicating a target operation domain. The encoding value carried by the first bit width field is the bit width encoding value, and the encoding value carried by the second bit width field is the domain encoding value. The bit width of the configuration data can be determined according to the number of operation domains supported by the multi-domain modular multiplication algorithm and the number of effective bit widths.

[0107] For example, the multi-domain modular multiplication algorithm supports two operation domains, i.e., a prime number domain and a binary domain, and the number of effective bit widths supported by the multi-domain modular multiplication algorithm is 5. In this case, the bit width of the configuration data can be 4 bits, where the bit width of 3 bits corresponds to the first bit width field, and the bit width of 1 bit corresponds to the second bit width field. For example, the bit width of the configuration data can be represented as config[3:0], where config[0] is the second bit width field, and config[3:1] is the first bit width field. The correspondence between the encoding values of the first bit width field and the second bit width field and the effective bit width and the target operation domain can be seen from the following Table 1.

[0108] Table 1

[0109]

[0110] In the case where the configuration data can include a first bit width field and a second bit width field, the first bit width field carries a bit width encoding value indicating an effective bit width, and the second bit width field carries a domain encoding value indicating a target operation domain, the input unit 11 can determine, according to the correspondence between the input bit width, the bit width encoding value, and the domain encoding value, the input bit width corresponding to the bit width encoding value carried by the first bit width field and the domain encoding value carried by the second bit width field as the effective bit width of the first sub-data and the second sub-data, determine the target multi-domain multiplication sub-unit corresponding to the effective bit width in the multi-domain multiplication unit 12, and input the input data to the target multi-domain multiplication sub-unit.

[0111] The above table 1 is taken as an example for illustration. The configuration data config[3:0] = '1000'. According to config[3:0] = '1000', the table 1 is inquired, and the input unit 11 can determine that the target operation domain is a binary domain, and the effective bit width is 409 bits. Then, the input unit 11 inputs the input data into the target multi-domain multiplication subunit corresponding to the 409-bit bit width.

[0112] In the embodiment of the present application, the multi-domain multiplication unit 12 is used to implement the multiplication function of different effective bit widths of multi-operation domains. In combination with the mathematical model of the large number multiplier, the multi-domain multiplication unit 12 is built step by step using the underlying multi-domain multiplier (i.e., the lowest level multi-domain multiplication subunit). Specifically, the multi-domain multiplication unit 12 can include multi-level multi-domain multiplication subunits, and in the multi-domain multiplication unit 12, the multi-domain multiplication subunit at a non-lowest level includes a plurality of multi-domain multiplication subunits at a next level.

[0113] The bit width of the multi-domain multiplication subunit is the bit width of the multiplier and the multiplicand input when the multi-domain multiplication subunit performs multiplication operation. The bit width of the multi-domain multiplication subunit at the lowest level can be designed according to actual needs. For example, the bit width of the multi-domain multiplication subunit at the lowest level is 18 bits, that is, the multi-domain multiplication subunit at the lowest level can perform multiplication operation of two 18-bit data.

[0114] In the embodiment of the present application, the number of multi-domain multiplication subunits at a non-lowest level included in each multi-domain multiplication subunit at the non-lowest level can be determined according to the multiplication algorithm implementation.

[0115] For example, for a * b operation, the effective bit widths of a and b are m, and the following multiplication algorithm is used to implement a * b:

[0116]

[0117] Wherein, a M represents the high a L represents the low b M represents the high b L represents the low In this case, each multi-domain multiplication subunit at a non-lowest level can include four multi-domain multiplication subunits at a next level, and each multi-domain multiplication subunit at the next level corresponds to one partial product, as shown in Figure 2 The dashed box represents the multi-domain multiplication subunit at level n, and the multi-domain multiplication subunit at level n includes four multi-domain multiplication subunits at level n-1, specifically: M b MThe partial product corresponding to the multi-domain multiplication subunit 1 of the level n-1, the multi-domain multiplication subunit 1 is configured with a shift module of left shift m bits, a M b L The partial product corresponding to the multi-domain multiplication subunit 2 of the level n-1, the multi-domain multiplication subunit 2 is configured with a shift module of left shift m / 2 bits, a L b M The partial product corresponding to the multi-domain multiplication subunit 3 of the level n-1, the multi-domain multiplication subunit 3 is configured with a shift module of left shift m / 2 bits, a L b L The partial product corresponding to the multi-domain multiplication subunit 4 of the level n-1.

[0118] In the embodiment of the application, the multi-domain multiplication subunit of each level performs multiplication operation on data of a corresponding bit width range, the maximum value of the bit width range is the bit width of the multi-domain multiplication subunit of the level, and the minimum value of the bit width range is the bit width of the multi-domain multiplication subunit of the next level. The input unit 11 determines the multi-domain multiplication subunit corresponding to the bit width range to which the effective bit width of the multi-domain multiplication unit 12 belongs as a target multi-domain multiplication subunit, and inputs the input data into the target multi-domain multiplication subunit.

[0119] For example, the bit width of the multi-domain multiplication subunit of the lowest level is 18 bits. Each multi-domain multiplication subunit of a non-lowest level can include four multi-domain multiplication subunits of the next level. The bit width of the multi-domain multiplication unit is 576 bits, that is, the bit width of the multi-domain multiplication subunit of the highest level in the multi-domain multiplication unit is 576 bits.

[0120] At this time, the multi-domain multiplication unit with a bit width of 576 bits includes six levels of multi-domain multiplication subunits, as shown in the following table: Figure 3 The multi-domain multiplication subunit of the level 1 is the multi-domain multiplication subunit of the lowest level, that is, the multi-domain multiplication subunit with a bit width of 18 bits, and the multi-domain multiplication subunit with a bit width of 18 bits outputs a multiplication result of 36 bits. The bit width range corresponding to the multi-domain multiplication subunit with a bit width of 18 bits is 0-18 bits, that is, the high bits of the operation data with an effective bit width in the range of 0-18 bits are padded with 0 to 18-bit data, and the 18-bit multi-domain multiplication subunit is input.

[0121] The multi-domain multiplication subunit of the level 2 includes four multi-domain multiplication subunits with a bit width of 18 bits, that is, the multi-domain multiplication subunit of the level 2 is a multi-domain multiplication subunit with a bit width of 36 bits, and the multi-domain multiplication subunit with a bit width of 36 bits outputs a multiplication result of 72 bits. The bit width range corresponding to the multi-domain multiplication subunit with a bit width of 36 bits is 19-36 bits, that is, the high bits of the operation data with an effective bit width in the range of 19-36 bits are padded with 0 to 36-bit data, and the 36-bit multi-domain multiplication subunit is input.

[0122] The 3-level multi-domain multiplication subunit includes 4 36-bit-width multi-domain multiplication subunits, i.e., the 3-level multi-domain multiplication subunit is a 72-bit-width multi-domain multiplication subunit, and the 72-bit-width multi-domain multiplication subunit outputs a 144-bit multiplication result; the 72-bit-width multi-domain multiplication subunit corresponds to a bit-width range of 37-72 bits, i.e., the high bits of operation data with an effective bit-width in the range of 37-72 bits are padded with 0 to 72-bit data, and the 72-bit-width multi-domain multiplication subunit is inputted.

[0123] The 4-level multi-domain multiplication subunit includes 4 72-bit-width multi-domain multiplication subunits, i.e., the 4-level multi-domain multiplication subunit is a 144-bit-width multi-domain multiplication subunit, and the 144-bit-width multi-domain multiplication subunit outputs a 288-bit multiplication result; the 144-bit-width multi-domain multiplication subunit corresponds to a bit-width range of 73-144 bits, i.e., the high bits of operation data with an effective bit-width in the range of 73-144 bits are padded with 0 to 144-bit data, and the 144-bit-width multi-domain multiplication subunit is inputted.

[0124] The 5-level multi-domain multiplication subunit includes 4 144-bit-width multi-domain multiplication subunits, i.e., the 5-level multi-domain multiplication subunit is a 288-bit-width multi-domain multiplication subunit, and the 288-bit-width multi-domain multiplication subunit outputs a 576-bit multiplication result; the 288-bit-width multi-domain multiplication subunit corresponds to a bit-width range of 145-288 bits, i.e., data with an effective bit-width in the range of 145-288 bits is inputted to the 288-bit-width multi-domain multiplication subunit according to 288 bits.

[0125] The 6-level multi-domain multiplication subunit includes 4 288-bit-width multi-domain multiplication subunits, i.e., the 6-level multi-domain multiplication subunit is a 576-bit-width multi-domain multiplication subunit, and the 576-bit-width multi-domain multiplication subunit outputs a 1152-bit multiplication result; the 576-bit-width multi-domain multiplication subunit corresponds to a bit-width range of 289-576 bits, i.e., the high bits of operation data with an effective bit-width in the range of 289-576 bits are padded with 0 to 576-bit data, and the 576-bit-width multi-domain multiplication subunit is inputted.

[0126] The input unit 11 inputs operation data to a multi-domain multiplication subunit (e.g., a target multi-domain multiplication subunit) corresponding to a bit-width range to which the effective bit-width of the operation data belongs, so that the algorithm running rate can be effectively improved, and the calculation resources of the multi-domain modular multiplication algorithm device can be fully utilized.

[0127] In some embodiments, the configuration data can further include a third bit-width field, and the third bit-width field carries an enable code value indicating enabling / disabling of the multiplier;

[0128] The input unit 11 determines the target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit, which can include that the input unit 11 determines the target multi-domain multiplication subunit corresponding to the effective bit width and the enable encoding value in the multi-domain multiplication unit.

[0129] The multi-domain fast modular reduction unit 13 performs a reduction operation on the target operation result in the target operation domain when the enable encoding value indicates to disable the multiplier, to obtain a modular multiplication algorithm result.

[0130] The multi-domain fast modular reduction unit 13 inputs the target operation result to the output unit 14 when the enable encoding value indicates to enable the multiplier; and the output unit 14 outputs the target operation result.

[0131] The third bit width field carries the encoding value, i.e., the enable encoding value. The bit width of the configuration data can be determined according to the number of operation domains supported by the multi-domain modular multiplication algorithm, the number of effective bit widths, and whether the multi-domain modular multiplication algorithm supports enabling the multiplier.

[0132] For example, the multi-domain modular multiplication algorithm supports two operation domains, i.e., a prime number domain and a binary domain, the number of effective bit widths supported by the multi-domain modular multiplication algorithm is 5, and the multi-domain modular multiplication algorithm does not support enabling the multiplier. In this case, the bit width of the configuration data can be 4 bits, of which 3 bits are the first bit width field and 1 bit is the second bit width field.

[0133] For another example, the multi-domain modular multiplication algorithm supports two operation domains, i.e., a prime number domain and a binary domain, the number of effective bit widths supported by the multi-domain modular multiplication algorithm is 5, and the multi-domain modular multiplication algorithm supports enabling the multiplier. In this case, the bit width of the configuration data can be 5 bits, of which 3 bits are the first bit width field, 1 bit is the second bit width field, and 1 bit is the third bit width field. For example, the bit width of the configuration data can be represented as config[4:0], of which config[0] is the second bit width field, config[3:1] is the first bit width field, and config[5] is the third bit width field. config[5] is an enable signal (e.g., bypass_en) bit, config[5] = '0' indicates to disable the multiplier, and config[5] = '1' indicates to enable the multiplier, i.e., config[5] = '1' is the enable signal. The correspondence between the encoding values of the first bit width field and the second bit width field and the effective bit width and the target operation domain can be referred to Table 1 as shown below.

[0134] In the embodiments of the present application, the enable signal indicates to use the multi-domain multiplication subunit to perform multiplication operation without reduction operation; the domain multiplication subunit can be configured with an enable entry, and the multi-domain multiplication subunit configured with the enable entry can receive the enable signal and perform multiplication operation.

[0135] When the multiplier is enabled or disabled, the correspondence between the effective bit width and the multi-domain multiplication subunit can be the same. That is, each level of the multi-domain multiplication subunit is equipped with an enable entry, and the multi-domain multiplication subunit with the enable entry can independently execute the corresponding multiplier function. This allows for the use of multi-domain multiplication subunits with more matched bit widths to perform multiplication operations, reducing the clock cycles consumed by the multiplication operation.

[0136] The correspondence between the effective bit width and the multi-domain multiplication subunit can also be different when the multiplier is enabled and disabled. That is, an enable entry is configured in the multi-domain multiplication subunit at a specified level. The multi-domain multiplication subunit with the enable entry can independently execute the corresponding multiplier function, thereby reducing the number of enable entries and reducing the structural complexity of the multi-domain modular multiplication algorithm.

[0137] Input unit 11 determines the corresponding target multi-domain multiplication subunit based on the effective bit width and enable code value indicated by the configuration data, and then the target multi-domain multiplication subunit performs the multiplication operation. After obtaining the target operation result, the target multi-domain multiplication subunit can input the target operation result and configuration data into the multi-domain fast modulo reduction unit 13.

[0138] If the configuration data indicator enables the multiplier, the multi-domain fast modular reduction unit 13 will not perform reduction operations on the target operation result, but will directly input the target operation result into the output unit 14 to realize the multiplication operation function; if the configuration data indicator de-enables the multiplier, the multi-domain fast modular reduction unit 13 will perform reduction operations on the target operation domain of the target operation result to obtain the modular multiplication algorithm result, and input the modular multiplication algorithm result into the output unit 14 to realize the modular multiplication operation function.

[0139] Still with Figure 3 The 576-bit wide multi-domain multiplication unit shown is an example. In this multi-domain multiplication unit, the multi-domain multiplication sub-units at levels 4 to 6 are configured with enable entries.

[0140] In this multi-field multiplication unit, when the multiplier is disabled, the bit width range of the first-level multi-field multiplication subunit is 0 to 18 bits, the bit width range of the second-level multi-field multiplication subunit is 19 to 36 bits, the bit width range of the third-level multi-field multiplication subunit is 37 to 72 bits, the bit width range of the fourth-level multi-field multiplication subunit is 73 to 144 bits, the bit width range of the fifth-level multi-field multiplication subunit is 145 to 288 bits, and the bit width range of the sixth-level multi-field multiplication subunit is 289 to 576 bits.

[0141] In the case of enabling the multiplier, the bit width range corresponding to the 4-level multi-field multiplication subunit is 0-144 bits, the bit width range corresponding to the 5-level multi-field multiplication subunit is 145-288 bits, and the bit width range corresponding to the 6-level multi-field multiplication subunit is 289-576 bits, as shown in Table 2.

[0142] Table 2

[0143] Bit width range Dual domain multiplication sub-unit [571,289] 576 [288,145] 288 [144,0] 144

[0144] In the embodiments of the present application, the multiplier is enabled / disabled through the third bit width field, and the multi-field modular multiplication algorithm can implement modular multiplication operations of different bit width keys and multiplication operations of different data, thereby expanding the application range of the multi-field modular multiplication algorithm and improving the utilization rate of the multi-field modular multiplication algorithm.

[0145] In some embodiments, the multi-field multiplication subunit of the non-lowest level further includes a multi-input multi-field adder connected with the plurality of multi-field multiplication subunits of the next level. The multi-input multi-field adder is an adder supporting multi-input and multi-operation field calculation. The number of input channels of the multi-input multi-field adder is the same as the number of the multi-field multiplication subunits of the next level included in the multi-field multiplication subunit of the non-lowest level. For example, the multi-field multiplication subunit of the non-lowest level includes four multi-field multiplication subunits of the next level, and the multi-input multi-field adder is a 4-input multi-field adder.

[0146] In this case, the target multi-field multiplication subunit can obtain the target operation result by the following steps:

[0147] The multi-field multiplication subunit of the lowest level of the target multi-field multiplication subunit performs multiplication operation in the target operation field on the first sub-data and the second sub-data to obtain an intermediate operation result, and inputs the intermediate operation result into the multi-input multi-field adder of the multi-field multiplication subunit of the next level.

[0148] The multi-input multi-field adder of the multi-field multiplication subunit of the non-lowest level of the target multi-field multiplication subunit performs addition operation in the target operation field on the received intermediate operation result to obtain a new intermediate operation result. If the multi-field multiplication subunit of the non-lowest level is the multi-field multiplication subunit of the non-highest level, the new intermediate operation result is input into the multi-input multi-field adder of the multi-field multiplication subunit of the next level. If the multi-field multiplication subunit of the non-lowest level is the multi-field multiplication subunit of the highest level, the new intermediate operation result is taken as the target operation result, and then the target operation result is input into the multi-field fast modular reduction unit 13.

[0149] In the embodiments of the present application, the target multi-domain multiplication subunit includes at least one level of multi-domain multiplication subunits. According to the multiplication algorithm, the target multi-domain multiplication subunit splits the first sub-data and the second sub-data level by level to obtain operation data (i.e., the multiplier and the multiplicand) of the bit width of the multi-domain multiplication subunit at the lowest level; and inputs the operation data obtained by the splitting into the multi-domain multiplication subunit at the lowest level.

[0150] At the target multi-domain multiplication subunit, the multi-domain multiplication subunit at the lowest level determines the target operation domain according to the configuration data, performs multiplication operation of the target operation domain on the input operation data, and obtains the multiplication operation result as the intermediate operation result. The intermediate operation result is input into the multi-input multi-domain adder of the multi-domain multiplication subunit at the upper level as one input of the multi-domain multiplication subunit at the upper level.

[0151] At the target multi-domain multiplication subunit, the multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level and the non-highest level determines the target operation domain according to the configuration data, performs addition operation of the target operation domain on the received intermediate operation result, and obtains the addition operation result as the new intermediate operation result. The new intermediate operation result is input into the multi-input multi-domain adder of the multi-domain multiplication subunit at the upper level as one input of the multi-domain multiplication subunit at the upper level.

[0152] At the target multi-domain multiplication subunit, the multi-input multi-domain adder of the multi-domain multiplication subunit at the highest level determines the target operation domain according to the configuration data, performs addition operation of the target operation domain on the received intermediate operation result, and obtains the addition operation result as the target operation result.

[0153] To obtain better timing path and performance and avoid data loss and operation failure, the multi-domain multiplication subunit at the non-lowest level can further include a register (e.g., a first register). The bit width of the first register is greater than or equal to the output bit width of the multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level. The multi-input multi-domain adder is connected to a plurality of multi-domain multiplication subunits at the next level, the multi-input multi-domain adder is connected to the first register, and the first register is connected to a plurality of multi-domain multiplication subunits at the upper level.

[0154] At the target multi-domain multiplication subunit, the multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level and the non-highest level writes the new intermediate operation result obtained into the first register of the multi-domain multiplication subunit at the non-lowest level and the non-highest level. The first register inputs the intermediate operation result into the multi-input multi-domain adder of the multi-domain multiplication subunit at the upper level.

[0155] The multi-input multi-domain adder of the highest level multi-domain multiplication subunit writes the new intermediate operation result into a first register of the highest level multi-domain multiplication subunit, and the first register inputs the intermediate operation result as a target operation result into the multi-domain fast modulo reduction unit 13.

[0156] The modular multiplication operation is implemented by the multi-domain multiplication unit built step by step in combination with the fast modulo reduction unit. Only one multiplication operation is performed in the entire modular multiplication algorithm, that is, the multiplication operation performed by the lowest level multi-domain multiplication subunit, which greatly improves the modular multiplication efficiency, and makes the multi-domain modular multiplication algorithm provided in the embodiment more suitable for elliptic curve modular multiplication operations in SM2, ECC and the like, and the modular multiplication operation has better throughput performance.

[0157] In some embodiments, as shown in Figure 4 The lowest level multi-domain multiplication subunit can include an encoding module 41, a multi-domain Wallace tree compression module 42, a first multi-domain fast summation module 43 and a second register 44. The encoding module 41 is connected with the multi-domain Wallace tree compression module 42. The multi-domain Wallace tree compression module 42 is connected with the first multi-domain fast summation module 43. The first multi-domain fast summation module 43 is connected with the second register 44. The second register 44 is connected with the multi-input multi-domain adder of the multi-domain multiplication subunit of the previous level.

[0158] In the embodiment, the lowest level multi-domain multiplication subunit performs multiplication operation on the first sub-data and the second sub-data in the target operation domain to obtain an intermediate operation result, which can be:

[0159] In the lowest level multi-domain multiplication subunit, the encoding module 41 performs encoding operation on the first sub-data by using the base coefficient to obtain a plurality of groups of partial products, and inputs the plurality of groups of partial products into the multi-domain Wallace tree compression module 42.

[0160] In the lowest level multi-domain multiplication subunit, the multi-domain Wallace tree compression module 42 performs compression summation operation on the plurality of groups of partial products received in the target operation domain to obtain a first compression operation result, and inputs the first compression operation result into the first multi-domain fast summation module 43.

[0161] In the lowest level multi-domain multiplication subunit, the first multi-domain fast summation module 43 performs addition operation on the first compression operation result received in the target operation domain to obtain an intermediate operation result, and writes the intermediate operation result into the second register 44.

[0162] In the embodiments of the present application, the encoding module 41 can be a Radix-2 Booth encoding module, a Radix-4 Booth encoding module, a Radix-8 Booth encoding module or a Radix-16 Booth encoding module. The encoding module 41 is configured to encode the multiplicand.

[0163] The Radix-2 Booth encoding algorithm can eliminate 2-bit continuous "1", but the level of the addition tree is not reduced for the hardware circuit, and instead, the encoding circuit is introduced. Compared with the Radix-2 Booth encoding algorithm, the Radix-4 Booth encoding algorithm can reduce the partial sum of the multiplication accumulation by half, and the partial product only involves shift and complement calculation. In addition, although the Radix-8 Booth encoding algorithm and the Radix-16 Booth encoding algorithm can reduce the number of partial products, they increase the complex encoding circuit, causing the increase of circuit delay and area. Therefore, in the embodiments of the present application, the encoding module 41 preferably adopts the Radix-4 Booth encoding algorithm, that is, the encoding module 41 is a Radix-4 Booth encoding module.

[0164] Radix-4 Booth encoding algorithm base coefficient Coef i is:

[0165] Coef i =-2B i+1 +B i + B i-1 (1)

[0166] In formula (1), B i+1 , B i , B i-1 represent adjacent three-bit binary digits of the multiplicand, B i+1 is the highest bit, B i is the middle bit, and B i-1 is the lowest bit.

[0167] Based on formula (1), A*B can be written as:

[0168] A*B=A*(-2B n-1 +B n-2 +B n-3 )2 n-2 +A*(-2B n-3 +B n-4 +B n-5 )2 n-4 +…+A*(-2B5+B4+B3)2 4 +A*(-2B3+B2+B1)22 + (-2B1+ B0+ B -1 )2 0 (2)

[0169] In formula (2), A is a multiplier, B is a multiplicand, B i+1 , B i , B i-1 represent adjacent three-bit binary bits of the multiplicand, i = 0,..., n-2, and n is the bit width of A and B.

[0170] For each group of A and B multiplication, the partial product operation can refer to Table 3

[0171] Table 3

[0172]

[0173]

[0174] As can be seen from the above table, using the Radix-4 Booth encoding algorithm, only the complement operation or the shift operation of the multiplier A is needed to complete the calculation of the partial product. For example, when the bit width of A and B is 18 bits (i.e., n = 18), using the Radix-4 Booth encoding algorithm, 9 groups of partial products will be generated.

[0175] The modulo operation is the calculation of the Galois field. Taking the bit width of A as n bits as an example. In the prime field, the multiplier A is an unsigned number, 2A = {A, 0}, represents the bit-by-bit complement of A. Therefore, the maximum bit width of the multiplier A is (n+1) bits. The Radix-4 Booth encoding module is a partial product generation module, which only generates the The calculation of -A required The +1 operation later is performed in the multi-field Wallace tree compression module 42.

[0176] In the binary field, addition and subtraction operations are equivalent to XOR operations, so the operations of -2A and -A are the same as +2A and -A. The obtained multiple groups of partial products are sent to the multi-field Wallace tree compression module 42 for compression and summation operation, and the result is output.

[0177] The encoding module 41 encodes A*B into a series of A, -A, +2A, -2A, and sends it to the multi-field Wallace tree compression module 42 for compression and summation operation.

[0178] The multi-domain Wallace tree compression module 42 determines the target operation domain according to the configuration data (such as mod, i.e. config[0]), and then performs a compression summation operation of the Wallace tree on the received multiple sets of partial products in the target operation domain, and the obtained result is the first compression operation result.

[0179] The multi-domain Wallace tree compression module 42 is used to compress and sum the partial products, and outputs two results of summation and carry. The core device of the multi-domain Wallace tree compression module 42 is a multi-domain compressor. In the embodiment of the application, the multi-domain compressor is a dual-domain compressor (compressor), and the binary domain and the prime number domain are taken as examples. The dual-domain compressor used by the multi-domain Wallace tree compression module 42 can include a 3:2 compressor, a 4:2 compressor, and a 5:2 compressor.

[0180] For the 3:2 compressor:

[0181] The input and output signals of the ordinary 3:2 compressor are as shown in Figure 5a The input signals of the ordinary 3:2 compressor include the carry input c in , the partial products x1 and x2, and the output signals include the summation output sum and the carry output carry. The structure of the ordinary 3:2 compressor is as shown in Figure 5b The input and output relationship expression of the ordinary 3:2 compressor is as follows:

[0182]

[0183] carry=(x1·x2)+(x1·c in )+(x2·c in ) (4)

[0184] In the formula (3) and the formula (4), sum is the summation output, carry is the carry output, carry can also be represented as c out , x1 and x2 are the partial products, and c in is the carry input.

[0185] The ordinary 3:2 compressor takes the carry input c in , the partial products x1 and x2 as the input signals, and outputs sum and carry through internal XOR modules, MUXs and the like.

[0186] The input and output signals of the dual-domain 3:2 compressor are as shown in Figure 5c The input signals of the dual-domain 3:2 compressor include the carry input c in, partial products x1 and x2, and an operation field identifier mod, where mod=0 represents a binary field and mod=1 represents a prime field. The output signal of the dual-field 3:2 compressor includes a sum output sum and a carry output carry. The structure of the dual-field 3:2 compressor is shown in Fig. 2, where, compared with a common 3:2 compressor, the dual-field 3:2 compressor is connected with an AND module at the carry output port of the selector, one input of the AND module is the output of the selector, and the other input is the operation field identifier mod, so as to realize compression operation in different operation fields through the mod. Figure 5d

[0187]

[0188] In formula (5) and formula (6), sum is the sum output, carry is the carry output, x1 and x2 are partial products, c in is the carry input, and mod is the operation field identifier.

[0189] When mod=1, x1+x2+c in =sum+2*carry.

[0190] When mod=0, x1+x2+c

[0191] The dual-field 3:2 compressor takes the carry input c in , partial products x1 and x2, and an operation field identifier mod as input signals, and outputs sum and carry through internal XOR module, selector (MUX), AND module and the like, where sum is valid and carry is invalid in a binary field, and both sum and carry are valid in a prime field.

[0192] For a 4:2 compressor:

[0193] The input and output signals of the common 4:2 compressor are shown in Fig. 3, where the input signals of the common 4:2 compressor include the carry input c in , partial products x1-x4, and the output signals include the sum output sum, the carry output carry and the extra carry output c out . The structure of the common 4:2 compressor is shown in Fig. 4. Figure 6a Figure 6b

[0194] The common 4:2 compressor takes the carry input c in , partial products x1-x4 as input signals, and outputs sum, carry and c out through internal XOR / XNOR module, selector (MUX) and the like. ​​​

[0195] The input and output signals of the dual-domain 4:2 compressor are shown in Figure 6c The input signals of the dual-domain 4:2 compressor include the carry input c in , x1-x4, and the operation domain identifier mod, where mod=0 represents the binary domain and mod=1 represents the prime number domain. The output signals of the dual-domain 4:2 compressor include the sum output sum, the carry output carry, and the extra carry output c out . The structure of the dual-domain 4:2 compressor is shown in Figure 6d Compared with the common 4:2 compressor, the dual-domain 4:2 compressor is connected with an AND module at the carry and c out outputs of the selector, one input of the AND module is the output of the selector, and the other input is the operation domain identifier mod, so that the compression operation in different operation domains is realized through mod. The input and output relationship expression of the dual-domain 4:2 compressor is as follows:

[0196]

[0197] In the formula (7) to formula (9), sum is the sum output, carry is the carry output, c out is the extra carry output, x1-x4 are partial products, c in is the carry input, and mod is the operation domain identifier.

[0198] When mod=1: x1+x2+x3+x4+c in =Sum+2*(carry+c out );

[0199] When mod=0:

[0200] The dual-domain 4:2 compressor takes c in , x1-x4, and mod as input signals, and outputs sum, carry, and c out after processing by internal XOR modules, MUXs, AND modules, etc. In the binary domain, sum is valid, and carry and c out are invalid; in the prime number domain, sum, carry, and c out are all valid.

[0201] The design of the dual-domain 4:2 compressor has low delay, shortens the delay of the critical path, and actually only has 1.5 times the delay of the full adder, and makes the output delays of sum, carry, and c out consistent, avoiding the inconsistency of the pseudo sum and the carry c outThe generation time of the carry signal is different from that of the pseudo signal, which causes the carry signal generated at a high speed to wait for the pseudo signal generated at a low speed, and causes the compression speed to decrease and the power consumption to increase.

[0202] For the 5:2 compressor:

[0203] The use of the 5:2 compressor can further reduce the number of partial product compression stages and accelerate the speed of partial product compression. The input and output signals of the ordinary 5:2 compressor are as shown in Figure 7a The input signals of the ordinary 5:2 compressor include carry inputs c in1 ~c in2 , partial products x1~x5, and the output signals include a sum output sum, a carry output carry, and additional carry outputs c out1 ~c out2 . The structure of the ordinary 5:2 compressor is as shown in Figure 7b

[0204] The ordinary 5:2 compressor takes the carry inputs c in1 ~c in2 and the partial products x1~x5 as input signals, and outputs the sum, the carry, and c out1 ~c out2 after processing by internal XOR / XNOR modules, selectors (MUX), and the like.

[0205] The input and output signals of the dual-domain 5:2 compressor are as shown in Figure 7c The input signals of the dual-domain 5:2 compressor include carry inputs c in1 ~c in2 , x1~x5, and an operation domain identifier mod, where mod=0 represents the binary domain and mod=1 represents the prime number domain. The output signals of the dual-domain 5:2 compressor include a sum output sum, a carry output carry, and additional carry outputs c out1 ~c out2 . The structure of the dual-domain 5:2 compressor is as shown in Figure 7d Compared with the ordinary 5:2 compressor, the dual-domain 5:2 compressor is connected with an AND module at the carry and c out1 ~c out2 outputs of the selector, one input of the AND module is the output of the selector, and the other input is the operation domain identifier mod, and the compression operation in different operation domains is realized through the mod.

[0206] The input and output relationship expressions of the dual-domain 5:2 compressor are as follows:

[0207] ​

[0208] In the formulas (10)-(13), sum is a summation output, carry is a carry output, c out1 ~ c out2 is an extra carry output, x1-x5 are partial products, c in1 ~ c in2 is a carry input, and mod is an operation field identifier.

[0209] When mod = 1: x1+x2+x3+x4+x5+c in1 + c in2 = Sum+2*(carry+c out1 + c out2 );

[0210] When mod = 0:

[0211] The dual-field 5:2 compressor takes c in1 ~ c in2 , x1-x5, and mod as input signals, and processes them through internal XOR modules, MUXs, AND modules, etc., to output sum, carry, and c out1 ~ c out2 . In the binary field, sum is valid, carry and c out1 ~ c out2 are invalid; in the prime field, sum, carry, and c out1 ~ c out2 are all valid.

[0212] The multi-field Wallace tree compression module can complete fast accumulation of all partial products to generate two input signals (i.e., the first compression operation result), i.e., summation (i.e., pseudo sum) and carry (carry). The two input signals are input into the first multi-field fast summation module 43.

[0213] The first multi-field fast summation module 43 can adopt a structure combining a look-ahead carry adder with a tree adder, and use 4-bit group look-ahead carry adders to form a look-ahead carry adder of a required bit number. For example, Figure 8The first multi-domain fast summation module 43 shown includes a plurality of addition operator modules of operation domains, such as addition operator modules of operation domains 1 to n, each of which can be implemented by a tree adder. Optionally, the tree adder can be implemented by a selection adder and an advanced carry adder. The output signals of different operation domains output by the multi-domain Wallace tree compression module 42 are input into the first multi-domain fast summation module 43, and the first multi-domain fast summation module 43 inputs the input signals into the addition operator modules of different operation domains in the first multi-domain fast summation module 43 according to configuration data (such as mod) to perform addition operations of corresponding operation domains.

[0214] In some embodiments, the target operation domain can be a prime number domain or a binary domain. At this time, the addition operation corresponding to the prime number domain can be a serial carry addition operation (SCA), and the addition operation corresponding to the binary domain can be an exclusive or (XOR) operation. At this time, the first multi-domain fast summation module 43 is a dual-domain fast summation module, the structure of which is shown in the figure. Figure 9

[0215] Specifically, the target operation domain is a prime number domain; in the multi-domain multiplication subunit of the lowest level, the first multi-domain fast summation module 43 performs a serial carry addition operation (SCA) on the received compressed operation result to obtain an intermediate operation result. Further, the first multi-domain fast summation module 43 writes the intermediate operation result into the second register 44.

[0216] The target operation domain is a binary domain; in the multi-domain multiplication subunit of the lowest level, the first multi-domain fast summation module 43 performs an exclusive or (XOR) operation on the received compressed operation result to obtain an intermediate operation result. Further, the first multi-domain fast summation module 43 writes the intermediate operation result into the second register 44.

[0217] In the embodiments of the present application, the functions implemented by the dual-domain fast summation module in the prime number domain and the binary domain are inconsistent: in the prime number domain, the two output signals of the Wallace tree compression operation are subjected to an SCA operation. The SCA operation can be implemented by a selection carry adder; in the binary domain, the Wallace tree compression operation is compensated by XOR, because the Wallace tree compression operation lacks the XOR operation.

[0218] ​In the embodiments of the present application, if the lowest-level multi-domain multiplication subunit is the target multi-domain multiplication subunit, the second register 44 directly inputs the intermediate operation result written as the target operation result into the multi-domain fast modulus reduction unit 13; if the lowest-level multi-domain multiplication subunit is not the target multi-domain multiplication subunit, the second register 44 inputs the intermediate operation result into the multi-input multi-domain adder of the multi-domain multiplication subunit at the upper level.

[0219] The multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level receives the intermediate operation result from the multi-domain multiplication subunit at the next level, performs addition operation in the target operation domain on the received intermediate operation result, obtains a new intermediate operation result, and writes the obtained new intermediate operation result into the first register of the multi-domain multiplication subunit.

[0220] If the multi-domain multiplication subunit at the non-lowest level is not the multi-domain multiplication subunit at the highest level, i.e., the multi-domain multiplication subunit at the non-lowest level is not the target multi-domain multiplication subunit, the first register of the multi-domain multiplication subunit inputs the intermediate operation result into the multi-input multi-domain adder of the multi-domain multiplication subunit at the upper level.

[0221] If the multi-domain multiplication subunit at the non-lowest level is the multi-domain multiplication subunit at the highest level, i.e., the multi-domain multiplication subunit at the non-lowest level is the target multi-domain multiplication subunit, the first register of the multi-domain multiplication subunit can directly input the intermediate operation result as the target operation result into the multi-domain fast modulus reduction unit 13.

[0222] In some embodiments, the multi-input multi-domain adder includes a multi-domain compression module and a second multi-domain fast summation module; the multi-domain compression module is connected with the second multi-domain fast summation module, and the second multi-domain fast summation module is connected with the first register. The multi-domain compression module is connected with the multi-domain multiplication subunit at the next level (the first register of the multi-domain multiplication subunit at the next level), and the first register is connected with the multi-domain multiplication subunit at the upper level (the multi-domain compression module of the multi-domain multiplication subunit at the upper level).

[0223] The multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level performs addition operation in the target operation domain on the received intermediate operation result to obtain a new intermediate operation result, which includes:

[0224] In the multi-input multi-domain adder of the multi-domain multiplication subunit at the non-lowest level, the multi-domain compression module performs compression summation operation in the target operation domain on the received intermediate operation result to obtain a second compression operation result, and inputs the second compression operation result into the second multi-domain fast summation module.

[0225] In the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit, the second multi-domain fast summation module performs addition operation of the target operation domain on the received second compressed operation result to obtain a new intermediate operation result, and writes the new intermediate operation result into the first register.

[0226] In the embodiments of the present application, the multi-domain compression module can adopt multi-domain Wallace tree compression operation, and the structure of the multi-domain compression module can refer to the related description of the multi-domain Wallace tree compression module 42. In the addition operation process of the multi-input multi-domain adder, the multi-domain compressor (such as a multi-domain 3:2 compressor) is integrated to perform compressed summation operation on the multi-input data, which can further improve the operation efficiency.

[0227] The structure of the second multi-domain fast summation module can refer to the related description of the first multi-domain fast summation module 43. For example, the target operation domain is a prime domain; in the non-lowest level multi-domain multiplication subunit, the second multi-domain fast summation module performs serial carry addition operation on the received compressed operation result to obtain a new intermediate operation result. Then, the second multi-domain fast summation module writes the new intermediate operation result into the first register. The target operation domain is a binary domain; in the non-lowest level multi-domain multiplication subunit, the second multi-domain fast summation module performs exclusive OR operation on the received compressed operation result to obtain a new intermediate operation result. Then, the second multi-domain fast summation module writes the new intermediate operation result into the first register.

[0228] In the embodiments of the present application, the multi-domain fast modulo reduction unit 13 is used to reduce the output of the upper multi-domain multiplication unit to ensure that the final output result of the modulo multiplication is located in the specified operation domain. The structure of the multi-domain fast modulo reduction unit 13 can refer to Figure 10a As shown, the multi-domain fast modulo reduction unit 13 includes an input subunit (IN) 131, a plurality of reduction subunits 132 of operation domains (such as operation domain 1 to operation domain n), and a third register 133. The input subunit 131 is connected with each reduction subunit 132 corresponding to each operation domain, and each reduction subunit 132 corresponding to each operation domain is connected with the third register 133. The input subunit 131 is connected with the multi-domain multiplication unit 12 (such as the first register and the second register in the multi-domain multiplication unit 12).

[0229] In the multi-domain fast modulo reduction unit 13, the input subunit 131 inputs the target operation result into the target reduction subunit corresponding to the target operation domain; the target reduction subunit performs reduction operation on the target operation result to obtain a modulo multiplication algorithm result, and writes the modulo multiplication algorithm result into the third register 133.

[0230] In the embodiment of the present application, the register (such as the first register or the second register) of the target multi-domain multiplication subunit inputs the target operation result and the configuration data into the input subunit 131. The input subunit 131 determines the target operation domain according to the configuration data, and then inputs the target operation result into the reduction subunit 132 (i.e., the target reduction subunit) corresponding to the target operation domain. The target reduction subunit performs reduction operation on the received target operation result, and the obtained operation result is the modular multiplication algorithm result. Then, the target reduction subunit writes the modular multiplication algorithm result into the third register 133.

[0231] The reduction manners of different operation domains are different. In the embodiment of the present application, the reduction subunits for different operation domains are respectively designed according to the standard of the National Institute of Standards and Technology (NIST).

[0232] For the prime number domain, the reduction subunit can include an addition-subtraction operation module and a shift operation module, that is, the reduction operation of the prime number domain includes addition-subtraction operation and shift operation. For the binary domain, the reduction subunit can include a state machine operation module and an exclusive OR operation module, that is, the reduction operation of the binary domain includes state machine operation and exclusive OR operation.

[0233] Correspondingly, when the target operation domain is the prime number domain, the multi-domain fast modular reduction unit 13 can perform addition-subtraction operation and shift operation on the target multiplication operation result to obtain the modular multiplication algorithm result; when the target operation domain is the binary domain, the multi-domain fast modular reduction unit 13 can perform state machine operation and exclusive OR operation on the target multiplication operation result to obtain the modular multiplication algorithm result.

[0234] In the embodiment of the present application, the input subunit 131 can determine the target operation domain and the effective bit width according to the configuration data, and then read the target operation result and input the read target operation result into the target reduction subunit corresponding to the target operation domain. The target reduction subunit performs reduction operation on the received data to obtain the modular multiplication algorithm result, and writes the modular multiplication algorithm result into the third register 133.

[0235] In order to improve the operation efficiency and simplify the structure of the multi-domain fast modular reduction unit 13, the bit width of the target operation result read by the input subunit 131 can be the maximum output bit width of the multi-domain multiplication unit 12. In this way, the input subunit 131 can read the target operation result from the first register / second register of the multi-domain multiplication unit 12 by using a unified bit width (i.e., the maximum output bit width). If the effective bit width of the target operation result is smaller than the maximum output bit width, the maximum output bit width of data is obtained by using the high-bit zero padding manner. The input subunit 131 does not need to switch the size of the bit width of the read data.

[0236] Correspondingly, the reduction subunit 132 performs reduction operation on the data according to the maximum output bit width, to obtain the modular multiplication algorithm result of the maximum effective bit width supported by the multi-domain modular multiplication algorithm device, and then write into the third register 133. The bit width of the third register 133 can be the maximum effective bit width supported by the multi-domain modular multiplication algorithm device, which can meet the modular multiplication operation requirement of each operation domain.

[0237] In the embodiment of the application, the third register 133 adopts the register of the maximum effective bit width supported by the multi-domain modular multiplication algorithm device, which can meet the modular multiplication operation requirement of each operation domain, reduce the area of the multi-domain modular multiplication algorithm device, and reduce the cost of the multi-domain modular multiplication algorithm device.

[0238] In the embodiment of the application, in order to further reduce the area of the multi-domain modular multiplication algorithm device and reduce the cost of the multi-domain modular multiplication algorithm device, the third register 133 can adopt a register of a smaller bit width, such as the minimum effective bit width supported by the multi-domain modular multiplication algorithm device, which is not limited.

[0239] In the embodiment of the application, the reduction operation of the operation data of different bit widths of each operation domain can reuse one reduction subunit, such as the adder and the shift module in the corresponding fast reduction subunit for the operation data of different bit widths of the prime number domain, and the state machine and the exclusive or operation module in the corresponding reduction subunit for the operation data of different bit widths of the binary domain. The reduction operation of the operation data of different bit widths of each operation domain is fused into the design of one reduction subunit, which can further reduce the area of the multi-domain modular multiplication algorithm device and reduce the cost of the multi-domain modular multiplication algorithm device.

[0240] In the embodiment of the application, the multi-domain modular multiplication algorithm device can support the function of enabling the multiplier. In this case, the configuration data can indicate enabling / disabling the multiplier; the input subunit 131 can also be connected with the third register 133, as shown in FIG. 13B. Figure 10b The way of indicating enabling / disabling the multiplier by the configuration data can refer to the related description of the third bit width field, which will not be repeated here.

[0241] In this case, the input subunit 131 inputs the target operation result into the target reduction subunit corresponding to the target operation domain when the configuration data indicates disabling the multiplier; and the input subunit 131 writes the target operation result into the third register 133 when the configuration data indicates enabling the multiplier.

[0242] In this embodiment, the bit width of the third register 133 can be the maximum effective bit width supported by the multi-domain modular multiplication algorithm, which can meet the modular multiplication operation requirements of each operational domain. When the multiplier is enabled, the bit width of the target operation result obtained by the input subunit 131 may be greater than the maximum effective bit width. In this case, the input subunit 131 can divide the read target operation result into multiple groups of data, apply them multiple times, and write these multiple groups of data into the third register 133 sequentially.

[0243] In this embodiment, the third register 133 is a register with the maximum effective bit width supported by the multi-domain modular multiplication algorithm. While meeting the modular multiplication operation requirements of each operation domain, it reduces the area of ​​the multi-domain modular multiplication algorithm and the cost of the multi-domain modular multiplication algorithm.

[0244] The following uses a multi-domain modular multiplication algorithm as an example of a two-domain modular multiplication algorithm (e.g., ...). Figure 11 As shown, the multi-field multiplication unit is a two-field multiplication unit, and the multi-field fast modular reduction unit is a two-field fast modular reduction unit, supporting both prime and binary fields. The lowest-level multi-field multiplication subunit has a bit width of 18 bits as an example. The structure of the two-field multiplication unit is as follows... Figure 12a to Figure 12d As shown, each level of the non-lowest level dual-domain multiplication subunit includes four next-level dual-domain multiplication subunits, a shift module for left shifting, a 4-input dual-domain adder, and a register with the corresponding bit width. For example, a dual-domain multiplication subunit with a bit width of 576 bits includes four 288-bit dual-domain multiplication subunits, a shift module for left shifting by 288 bits and 576 bits, and a register with a bit width of 1152 bits. The correspondence between the encoded values ​​of the first and second bit width fields and the effective bit width and target operation domain can be seen in Table 1 below. In this case, the maximum effective bit width supported by the dual-domain modular multiplication algorithm is 571 bits.

[0245] The input unit of the dual-domain modular multiplication algorithm receives two operation data with a bit width of 571 bits, namely A[570:0] and B[570:0], and at the same time, it receives configuration data config[5:0].

[0246] (1) config[5:0] indicates to enable the multiplier, i.e. config[5] = '0'.

[0247] The input unit inputs A[570:0] and B[570:0] into a corresponding dual-domain multiplication subunit (i.e., a target dual-domain multiplication subunit) according to config[5:0]. For example, if config[5:0] indicates a prime field and the corresponding effective bit width is 224 bits, and 288 bits > 224 bits, the input unit can input A[570:0] and B[570:0] into a dual-domain multiplication subunit with a bit width of 288 bits. In this embodiment of this application, the bit width of the target dual-domain multiplication subunit is greater than the effective bit width of the operation data. To improve the operation efficiency, the target dual-domain multiplication subunit is a dual-domain multiplication subunit with the smallest bit width among the dual-domain multiplication subunits with a bit width greater than the effective bit width of the operation data.

[0248] After the dual-domain multiplication subunit receives A[570:0] and B[570:0], the dual-domain multiplication subunit implements a multiplication algorithm, such as the multiplication algorithm of a*b described above, to split A[570:0] and B[570:0]. Finally, A[570:0] and B[570:0] with an effective bit width of 224 bits are split into a plurality of groups of partial products with a bit width of 18 bits, and each group of partial products is {a M b M , a M b L , a L b M , a L b L} respectively. Each group of partial products {a m b M , a M b L , a L b M , a L b L} is input into four dual-domain multiplication subunits with a bit width of 18 bits included in a dual-domain multiplication subunit with a bit width of 36 bits.

[0249] The structure of each dual-domain multiplication subunit with a bit width of 18 bits is shown in Figure 13 . The dual-domain multiplication subunit with a bit width of 18 bits includes a multiplier a[17:0] and a multiplicand b[17:0] with a bit width of 18 bits, and a mod input base-4 Booth encoding module. The base-4 Booth encoding module performs an encoding operation and outputs nine groups of partial products to a dual-domain Wallace tree compression module. The dual-domain Wallace tree compression module performs a compression summation operation on the nine groups of partial products according to mod input by the base-4 Booth encoding module, and outputs two compression operation results with a bit width of 36 bits to a dual-domain fast summation module.

[0250] Here, the dual-domain Wallace tree compression module can use a compression array shown in Figure 14 to perform a compression summation operation on the nine groups of partial products.Figure 14 Each row represents a group of partial products, and each column corresponds to a bit. The dashed rectangular frame containing 3 circles represents performing dual-domain 5:2 compression, the dashed rectangular frame containing 2 circles represents performing dual-domain 4:2 compression, and the dashed rectangular frame containing 1 circle represents performing dual-domain 3:2 compression. The dual-domain Wallace tree compression module can also use other compression arrays, which are not limited.

[0251] The structure of the dual-domain fast summation module is shown in Figure 9 The dual-domain fast summation module inputs two compressed operation results with a bit width of 36 bits into the corresponding addition operation sub-module according to the mod input by the dual-domain Wallace tree compression module. If the mod indicates a prime field, the dual-domain fast summation module inputs the two compressed operation results with a bit width of 36 bits into the SCA sub-module to perform addition operation. If the mod indicates a binary field, the dual-domain fast summation module inputs the two compressed operation results with a bit width of 36 bits into the XOR sub-module to perform addition operation, that is, XOR compensation operation. The dual-domain fast summation module writes the operation result sum[35:0] with a bit width of 36 bits into a register (that is, a second register), and then inputs the operation result into the 4-input dual-domain adder of the dual-domain multiplication sub-unit with a bit width of 36 bits after left shifting by 18 bits or 36 bits through a shift module.

[0252] After receiving the four operation results with a bit width of 18 bits output by the dual-domain multiplication sub-unit, the 4-input dual-domain adder of the dual-domain multiplication sub-unit performs compression summation and addition operation in the target operation field, and writes the operation result sum[71:0] with a bit width of 72 bits into a register, and then inputs the operation result into the 4-input dual-domain adder of the dual-domain multiplication sub-unit with a bit width of 72 bits after left shifting by 36 bits or 72 bits through a shift module. Taking the compression summation operation of the 4-input dual-domain adder as an example, which can be a dual-domain 3:2 compression operation, the structure of the 4-input dual-domain adder with a bit width of 36 bits is shown in Figure 15 The dashed rectangular frame containing 1 circle represents performing dual-domain 3:2 compression, Figure 15 The upper numbers represent bits. That is, after the 4-input dual-domain adder performs compression summation operation on the four operation results, the dual-domain fast summation processing is performed. The compression summation operation can refer to the dual-domain Wallace tree compression processing, and the dual-domain fast summation processing can refer to the dual-domain fast summation processing shown in Figure 9 The difference is only that the data bit width input / output by the dual-domain fast summation module becomes 72 bits. In the embodiment of the present application, the 4-input dual-domain adder can also use a full adder, which is not limited.

[0253] The 4-input dual-domain adder of the dual-domain multiplication subunit with a bit width of 72 bits receives the operation results output by the dual-domain multiplication subunit with a bit width of 36 bits, performs compression sum and addition operation of the target operation domain on the four operation results, and writes the operation result with a bit width of 144 bits into the register. Then, the operation result with a bit width of 144 bits is input into the 4-input dual-domain adder of the dual-domain multiplication subunit through left shifting of 72 bits or 144 bits by the shifting module. The compression sum operation of the 4-input dual-domain adder can be a dual-domain 3:2 compression operation. After the compression sum operation of the four operation results by the 4-input dual-domain adder, the dual-domain fast sum processing is performed. The compression sum operation can refer to the dual-domain Wallace tree compression processing, and the dual-domain fast sum processing can refer to the dual-domain fast sum processing as shown in FIG. 8, and the difference is that the data bit width of the input / output of the dual-domain fast sum module is changed to 144 bits. Figure 9

[0254] The 4-input dual-domain adder of the dual-domain multiplication subunit with a bit width of 144 bits receives the operation results output by the dual-domain multiplication subunit with a bit width of 72 bits, performs compression sum and addition operation of the target operation domain on the four operation results, and writes the operation result with a bit width of 288 bits into the register. Then, the operation result with a bit width of 288 bits is input into the 4-input dual-domain adder of the dual-domain multiplication subunit through left shifting of 144 bits or 288 bits by the shifting module. The compression sum operation of the 4-input dual-domain adder can be a dual-domain 3:2 compression operation. After the compression sum operation of the four operation results by the 4-input dual-domain adder, the dual-domain fast sum processing is performed. The compression sum operation can refer to the dual-domain Wallace tree compression processing, and the dual-domain fast sum processing can refer to the dual-domain fast sum processing as shown in FIG. 9, and the difference is that the data bit width of the input / output of the dual-domain fast sum module is changed to 288 bits. Figure 9

[0255] The 4-input dual-domain adder of the dual-domain multiplication subunit with a bit width of 288 bits receives the operation results output by the dual-domain multiplication subunit with a bit width of 144 bits, performs compression sum and addition operation of the target operation domain on the four operation results, and writes the operation result with a bit width of 576 bits into the register (i.e., the first register). As described above, the dual-domain multiplication subunit with a bit width of 288 bits is the target dual-domain multiplication subunit. Therefore, the operation result with a bit width of 576 bits is the target operation result.

[0256] After the operation result with a bit width of 576 bits is written into the register (i.e., the first register), the input subunit of the dual-domain fast modulus reduction unit reads the operation result with a bit width of 576 bits from the register (i.e., the first register), and obtains 1152-bit data by filling 0 in the high bit (as shown in FIG. 10). Figure 16 ​​The data shown [1151:0] are input into the corresponding reduction subunit according to config[5:0], and the read data are input into the corresponding reduction subunit to obtain a reduction operation result (i.e. a result of the modular multiplication algorithm) of 571 bits, and then the result of the modular multiplication algorithm is written into a register [570:0] of a bit width of 571 bits (i.e. a third register). The output unit reads the result of the modular multiplication algorithm out[570:0] from the register [570:0] of the bit width of 571 bits, and outputs out[570:0] (i.e. result[570:0]).

[0257] In the embodiment of the present application, the number of clock cycles (Cycle) required for the modular multiplication operation of the keys of different lengths (i.e. operation data of different effective bit widths) is shown in Table 4.

[0258] Table 4

[0259]

[0260] In the embodiment of the present application, the multi-domain modular multiplication algorithm includes multiple levels of hardware modules, such as an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit and an output unit. After each level of hardware module completes the corresponding function, the result is transmitted to the next level of hardware module, and then the hardware module can execute the processing of the next data without waiting for the output of the processing of the current data before processing the next data. The pipeline architecture design can greatly improve the performance of the modular multiplication operation, further improve the efficiency of the modular multiplication, and improve the throughput performance of the modular multiplication operation.

[0261] (2) config[5:0] indicates enabling the multiplier, i.e. config[5] = '1'.

[0262] In the embodiment of the present application, the enabling entry can be configured on the specified double-domain multiplication subunit, such as the multiplication enabling entry configured on the double-domain multiplication subunit of a bit width of 144 bits, 288 bits or 576 bits. The operation data of different effective bit width ranges use the corresponding double-domain multiplication subunit, so that the operation data of a smaller effective bit width uses the double-domain multiplication subunit with a smaller number of clock cycles, thereby improving the utilization and efficiency of the double-domain multiplication subunit. The relationship between the effective bit width range of the operation data, the bit width of the used double-domain multiplication subunit and the number of required clock cycles is shown in Table 5.

[0263] Table 5

[0264] Effective bit width range Dual domain multiplication sub-unit Number of clock cycles required [571,289] 576 6 [288,145] 288 5 [144,0] 144 4

[0265] The input unit inputs A[570:0] and B[570:0] into the corresponding dual-domain multiplication subunit (i.e., the target dual-domain multiplication subunit) according to config[5:0]. For example, if config[5:0] indicates a prime field and the corresponding effective bit width is 224 bits, 288 bits>224 bits, according to Table 2, the input unit can input A[570:0] and B[570:0] into the dual-domain multiplication subunit with a bit width of 288 bits.

[0266] The processing of the dual-domain multiplication subunit after receiving A[570:0] and B[570:0] can be referred to the related description when config[5:0] indicates to disable the multiplier.

[0267] After the 4-input dual-domain adder of the dual-domain multiplication subunit with a bit width of 288 bits writes the operation result with a bit width of 576 bits into the register (i.e., the first register), the input subunit of the dual-domain fast modular reduction unit reads the operation result with a bit width of 576 bits from the register (i.e., the first register), obtains data with a bit width of 1152 bits by padding 0 to the high bits, and inputs the read data into the register[570:0] (i.e., the third register) with a bit width of 571 bits according to config[5]=‘1’. Figure 16 The output unit reads the multiplication algorithm result out[570:0] from the third register[570:0] with a bit width of 571 bits, and outputs out[570:0] (i.e., result[570:0]).

[0268] In the embodiment of the present application, the input subunit of the dual-domain fast modular reduction unit can determine the effective bit width (e.g., 224 bits) according to config[3:1], 224 bits*2=448 bits<571 bits, and thus can determine the number of times of writing data into the third register, i.e., once, that is, writing data into the third register once can complete the writing of the multiplication algorithm result. Correspondingly, the output unit reads data (i.e., the multiplication algorithm result) from the third register with a bit width of 571 bits once, and outputs an effective signal vld once to complete the output of out[570:0].

[0269] In the embodiment of the present application, the input subunit of the dual-domain fast modular reduction unit determines the effective bit width according to config[3:1], e.g., 384 bits, 384 bits*2=768 bits>571 bits, and 768 bits<571 bits*2, and thus can determine the number of times of writing data into the third register, i.e., twice. Correspondingly, the output unit reads data from the third register with a bit width of 571 bits twice, and outputs an effective signal vld twice and out[570:0] twice to complete the output of the multiplication algorithm result.

[0270] In the embodiments of the present application, the algorithm can be dynamically switched by enabling the entry and configuring the data, and the multi-domain modular multiplication operation or multiplication operation is performed.

[0271] The embodiments of the present application provide a multi-domain modular multiplication algorithm device, which conforms to the modular multiplication operation of various key lengths of industry standards, can be widely applied to SM2, ECC, asymmetric algorithm protocol, and has the following advantages:

[0272] (1) The fast modular multiplication operation of prime number domain and binary domain can be met.

[0273] (2) The fusion design method of the dual-domain multiplication unit and the underlying multiplication unit is given, and the hardware resource overhead is greatly reduced.

[0274] (3) The dual-domain modular multiplication algorithm device supports various key lengths, and performance optimization and pipeline design are made, which significantly improves the throughput performance of different key length operations.

[0275] Corresponding to the above-mentioned multi-domain modular multiplication algorithm device, the embodiments of the present application also provide a modular multiplication operation method, as shown in Figure 17 The multi-domain modular multiplication algorithm device includes an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit and an output unit; the input unit is connected with the multi-domain multiplication unit, the multi-domain multiplication unit is connected with the multi-domain fast modular reduction unit, and the multi-domain fast modular reduction unit is connected with the output unit; the multi-domain multiplication unit includes a multi-level multi-domain multiplication subunit, and in the multi-domain multiplication unit, the multi-domain multiplication subunit of a non-lowest level includes a plurality of multi-domain multiplication subunits of a next level. The method includes the following steps:

[0276] Step S1701, the input unit receives input data, the input data includes first sub-data, second sub-data and configuration data, the configuration data indicates a target operation domain where the modular multiplication operation is located, and effective bit widths of the first sub-data and the second sub-data; the input data is input into a target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit;

[0277] Step S1702, the target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data by using the multi-domain multiplication subunits of a plurality of levels under the target multi-domain multiplication subunit, to obtain a target operation result; and the target operation result is input into the multi-domain fast modular reduction unit;

[0278] Step S1703, the multi-domain fast modular reduction unit performs reduction operation of the target operation domain on the target operation result, to obtain a modular multiplication algorithm result; and the modular multiplication algorithm result is input into the output unit;

[0279] Step S1704, the output unit outputs the modular multiplication algorithm result.

[0280] In the technical scheme provided by the embodiment, the input data received by the input unit indicates an operation domain (i.e., a target operation domain) in which the modular multiplication operation is located, and indicates the effective bit width of the operation data. The multi-domain multiplication unit and the multi-domain fast modular reduction unit support operations in multiple operation domains. The multi-domain multiplication unit and the multi-domain fast modular reduction unit perform operations on the operation data with the effective bit width indicated by the input data in the target operation domain indicated by the input data, to obtain the required modular multiplication algorithm result, and then output the modular multiplication algorithm result. In the embodiment, different operation data can have different effective bit widths, and the operation domains can also be different. By indicating the operation domain and the effective bit width through the input data, modular multiplication operations on operation data with multiple input bit widths and in different operation domains are realized.

[0281] In some embodiments, the configuration data includes a first bit width field and a second bit width field; the first bit width field carries a bit width code value indicating the effective bit width; and the second bit width field carries a domain code value indicating the target operation domain.

[0282] In step S1701, the input data is input into the target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit, which can include:

[0283] The input unit determines, according to the correspondence between the input bit width, the bit width code value, and the domain code value, the input bit width corresponding to the bit width code value carried by the first bit width field and the domain code value carried by the second bit width field as the effective bit width of the first sub-data and the second sub-data; determines the target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit; and inputs the input data into the target multi-domain multiplication subunit.

[0284] In some embodiments, the configuration data can further include a third bit width field, and the third bit width field carries an enable code value indicating enabling / disabling of the multiplier.

[0285] The input unit determines the target multi-domain multiplication subunit corresponding to the effective bit width and the enable code value in the multi-domain multiplication unit.

[0286] The modular multiplication operation method can further include:

[0287] In the case where the enable code value indicates disabling of the multiplier, the multi-domain fast modular reduction unit performs reduction operation on the target operation result in the target operation domain to obtain the modular multiplication algorithm result.

[0288] In the case where the enable code value indicates enabling of the multiplier, the multi-domain fast modular reduction unit inputs the target operation result into the output unit; and the output unit outputs the target operation result.

[0289] In some embodiments, the non-lowest level multi-domain multiplication subunit further comprises a multi-input multi-domain adder and a first register, the multi-input multi-domain adder is connected with a plurality of multi-domain multiplication subunits of a next level, the multi-input multi-domain adder is connected with the first register, and the first register is connected with a plurality of multi-domain multiplication subunits of a previous level;

[0290] In this case, in step S1702, the target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data by using the multi-domain multiplication subunits of a plurality of levels below the target multi-domain multiplication subunit to obtain a target multiplication operation result, which can include:

[0291] The lowest level multi-domain multiplication subunit below the target multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data to obtain an intermediate operation result, and inputs the intermediate operation result into the multi-input multi-domain adder of the multi-domain multiplication subunit of the previous level;

[0292] The multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit below the target multi-domain multiplication subunit performs addition operation of the target operation domain on the received intermediate operation result to obtain a new intermediate operation result; and writes the new intermediate operation result into the first register;

[0293] If the non-lowest level multi-domain multiplication subunit is a non-highest level multi-domain multiplication subunit, the first register inputs the new intermediate operation result into the multi-input multi-domain adder of the multi-domain multiplication subunit of the previous level; if the non-lowest level multi-domain multiplication subunit is a highest level multi-domain multiplication subunit, the first register takes the new intermediate operation result as the target operation result.

[0294] In some embodiments, the lowest level multi-domain multiplication subunit comprises an encoding module, a multi-domain Wallace tree compression module, a first multi-domain fast summation module, and a second register; the encoding module is connected with the multi-domain Wallace tree compression module, the multi-domain Wallace tree compression module is connected with the first multi-domain fast summation module, and the first multi-domain fast summation module is connected with the second register;

[0295] The above lowest level multi-domain multiplication subunit performs multiplication operation of the target operation domain on the first sub-data and the second sub-data to obtain an intermediate operation result, which can include:

[0296] In the lowest level multi-domain multiplication subunit, the encoding module performs encoding operation on the first sub-data by using base coefficients to obtain a plurality of groups of partial products, and inputs the plurality of groups of partial products into the multi-domain Wallace tree compression module;

[0297] In the lowest-level multi-domain multiplication subunit, the multi-domain Wallace tree compression module performs a compressed summation operation in the target operation domain on the received multiple groups of partial products to obtain a first compressed operation result, and inputs the first compressed operation result into the first multi-domain fast summation module;

[0298] In the lowest-level multi-domain multiplication subunit, the first multi-domain fast summation module performs an addition operation in the target operation domain on the received first compressed operation result to obtain an intermediate operation result, and writes the intermediate operation result into the second register.

[0299] In some embodiments, the target operation domain is a prime domain;

[0300] The first multi-domain fast summation module performs an addition operation in the target operation domain on the received first compressed operation result to obtain an intermediate operation result can include that the first multi-domain fast summation module performs a serial carry addition operation on the received first compressed operation result to obtain an intermediate operation result.

[0301] In some embodiments, the target operation domain is a binary domain;

[0302] The first multi-domain fast summation module performs an addition operation in the target operation domain on the received first compressed operation result to obtain an intermediate operation result can include that the first multi-domain fast summation module performs an exclusive-OR operation on the received first compressed operation result to obtain an intermediate operation result.

[0303] In some embodiments, the multi-input multi-domain adder can include a multi-domain compression module and a second multi-domain fast summation module; the multi-domain compression module is connected to the second multi-domain fast summation module, and the second multi-domain fast summation module is connected to the first register;

[0304] The multi-input multi-domain adder of the non-lowest-level multi-domain multiplication subunit performs an addition operation in the target operation domain on the received intermediate operation result to obtain a new intermediate operation result can include that:

[0305] In the multi-input multi-domain adder of the non-lowest-level multi-domain multiplication subunit, the multi-domain compression module performs a compressed summation operation in the target operation domain on the received intermediate operation result to obtain a second compressed operation result, and inputs the second compressed operation result into the second multi-domain fast summation module;

[0306] In the multi-input multi-domain adder of the non-lowest-level multi-domain multiplication subunit, the second multi-domain fast summation module performs an addition operation in the target operation domain on the received second compressed operation result to obtain a new intermediate operation result, and writes the new intermediate operation result into the first register.

[0307] In some embodiments, in the multi-domain multiplication unit, the multi-domain multiplication subunit of a non-lowest level includes 4 multi-domain multiplication subunits of a next level, the multi-input multi-domain adder is a 4-input multi-domain adder, and the encoding module is a base-4 booth encoding module.

[0308] In some embodiments, the multi-domain fast modulus reduction unit includes an input subunit, a plurality of reduction subunits corresponding to a plurality of operation domains, and a third register; the input subunit is connected to each reduction subunit corresponding to an operation domain, and each reduction subunit corresponding to an operation domain is connected to the third register.

[0309] In step S1703, the multi-domain fast modulus reduction unit performs reduction operation on the target operation result in the target operation domain to obtain the modulus multiplication algorithm result, which can include:

[0310] The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain.

[0311] The target reduction subunit performs reduction operation on the target operation result to obtain the modulus multiplication algorithm result, and writes the modulus multiplication algorithm result into the third register.

[0312] In some embodiments, the configuration data indicates enabling / disabling the multiplier; the input subunit is further connected to the third register.

[0313] The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain, which can include: the input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain when the configuration data indicates disabling the multiplier.

[0314] The above modulus multiplication operation method can further include: the input subunit writes the target operation result into the third register when the configuration data indicates enabling the multiplier.

[0315] In some embodiments, the target operation domain is a prime number domain, and the reduction operation of the prime number domain includes addition / subtraction operation and shift operation.

[0316] In step S1703, the multi-domain fast modulus reduction unit performs reduction operation on the target operation result in the target operation domain to obtain the modulus multiplication algorithm result, which can include:

[0317] The multi-domain fast modulus reduction unit performs addition / subtraction operation and shift operation on the target operation result to obtain the modulus multiplication algorithm result.

[0318] In some embodiments, the target operation domain is a binary domain, and the reduction operation of the binary domain includes state machine operation and XOR operation.

[0319] In step S1703, the multi-domain fast modulus reduction unit performs a reduction operation on the target operation result in the target operation domain to obtain the modulus multiplication algorithm result, which can include:

[0320] The multi-domain fast modulus reduction unit performs a state machine operation and an XOR operation on the target multiplication operation result to obtain the modulus multiplication algorithm result.

[0321] In the above embodiments, the implementation can be wholly or partially achieved by software, hardware, firmware, or any combination thereof. When implemented by software, the implementation can be wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer instructions wholly or partially generate the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server, or data center to another via wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, Solid State Disk (SSD)), etc.

[0322] It should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0323] The various embodiments in the specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. In particular, for the method embodiment, since it is basically similar to the multi-domain modular multiplication algorithmic implement embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the multi-domain modular multiplication algorithmic implement embodiment.

[0324] The above only describes the preferred embodiments of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-domain modular multiplication algorithm, characterized in that, It includes an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit, and an output unit; the input unit is connected to the multi-domain multiplication unit, the multi-domain multiplication unit is connected to the multi-domain fast modular reduction unit, and the multi-domain fast modular reduction unit is connected to the output unit; the multi-domain multiplication unit includes multiple levels of multi-domain multiplication sub-units, and in the multi-domain multiplication unit, the non-lowest level multi-domain multiplication sub-unit includes multiple multi-domain multiplication sub-units of the next lower level; The input unit receives input data, which includes first sub-data, second sub-data, and configuration data. The configuration data indicates the target operation domain where the modular multiplication operation is located, as well as the effective bit width of the first sub-data and the second sub-data. The input data is then input into the target multi-domain multiplication sub-unit corresponding to the effective bit width in the multi-domain multiplication unit. The target multi-domain multiplication subunit utilizes multiple levels of multi-domain multiplication subunits under the target multi-domain multiplication subunit to perform multiplication operations on the first sub-data and the second sub-data using the target operation domain to obtain the target operation result; the target operation result is then input into the multi-domain fast modular reduction unit. The multi-domain fast modular reduction unit performs a reduction operation on the target operation domain of the target operation result to obtain the modular multiplication algorithm result; and inputs the modular multiplication algorithm result into the output unit; The output unit outputs the result of the modular multiplication algorithm.

2. The multi-domain modular multiplication algorithm according to claim 1, characterized in that, The configuration data includes a first width field and a second width field; the first width field carries a width encoding value indicating the effective width; the second width field carries a field encoding value indicating the target operation field. The input unit inputs the input data into the target multi-domain multiplication subunit corresponding to the effective bit width in the multi-domain multiplication unit, including: The input unit determines the input bit width corresponding to the bit width encoding value carried by the first bit width field and the field encoding value carried by the second bit width field according to the correspondence between the input bit width, the bit width encoding value and the field encoding value, and uses it as the effective bit width of the first sub-data and the second sub-data; Determine the target multi-domain multiplication sub-unit corresponding to the effective bit width in the multi-domain multiplication unit; input the input data into the target multi-domain multiplication sub-unit.

3. The multi-domain modular multiplication algorithm according to claim 2, characterized in that, The configuration data also includes a third bit-width field, which carries an enable code value indicating whether the multiplier is enabled or disabled. The input unit determines the target multi-domain multiplication sub-unit corresponding to the effective bit width in the multi-domain multiplication unit, including: the input unit determines the target multi-domain multiplication sub-unit corresponding to the effective bit width and the enable coding value in the multi-domain multiplication unit; When the enable code value indicates that the multiplier is disabled, the multi-domain fast modular reduction unit performs a reduction operation on the target operation domain of the target operation result to obtain the modular multiplication algorithm result. When the enable code value indicates that the multiplier is enabled, the multi-domain fast modular reduction unit inputs the target operation result into the output unit; the output unit outputs the target operation result.

4. The multi-domain modular multiplication algorithm according to claim 1, characterized in that, The non-lowest level multi-domain multiplication subunit further includes a multi-input multi-domain adder and a first register. The multi-input multi-domain adder is connected to multiple multi-domain multiplication subunits at the next level, and the multi-input multi-domain adder is connected to the first register. The first register is connected to multiple multi-domain multiplication subunits at the previous level. The target multi-domain multiplication subunit utilizes multiple levels of multi-domain multiplication subunits under the target multi-domain multiplication subunit to perform multiplication operations on the first sub-data and the second sub-data using the target operational domain, obtaining the target operation result, including: Under the target multi-domain multiplication subunit, the lowest-level multi-domain multiplication subunit performs multiplication of the target operation domain on the first sub-data and the second sub-data to obtain an intermediate operation result, and inputs the intermediate operation result into the multi-input multi-domain adder of the next higher-level multi-domain multiplication subunit; Under the target multi-domain multiplication subunit, the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit performs the addition operation of the target operation domain on the received intermediate operation result to obtain a new intermediate operation result; and writes the new intermediate operation result into the first register. If the non-lowest level multi-domain multiplication subunit is not the highest level multi-domain multiplication subunit, then the first register inputs the new intermediate operation result into the multi-input multi-domain adder of the next higher level multi-domain multiplication subunit; if the non-lowest level multi-domain multiplication subunit is the highest level multi-domain multiplication subunit, then the first register uses the new intermediate operation result as the target operation result.

5. The multi-domain modular multiplication algorithm according to claim 4, characterized in that, The lowest-level multi-domain multiplication subunit includes an encoding module, a multi-domain Wallace tree compression module, a first multi-domain fast summation module, and a second register. The encoding module is connected to the multi-domain Wallace tree compression module, the multi-domain Wallace tree compression module is connected to the first multi-domain fast summation module, and the first multi-domain fast summation module is connected to the second register. The lowest-level multi-domain multiplication subunit performs multiplication of the target operation domain on the first sub-data and the second sub-data to obtain intermediate operation results, including: In the lowest-level multi-domain multiplication subunit, the encoding module uses the basis coefficients to encode the first sub-data to obtain multiple sets of partial products, and inputs the multiple sets of partial products into the multi-domain Wallace tree compression module; In the lowest-level multi-domain multiplication subunit, the multi-domain Wallace tree compression module performs compression and summation operations on the target operational domain for the received multiple sets of partial products to obtain a first compression operation result, and inputs the first compression operation result into the first multi-domain fast summation module; In the lowest-level multi-domain multiplication subunit, the first multi-domain fast summation module performs addition operations on the target operation domain of the received first compression operation result to obtain an intermediate operation result, and writes the intermediate operation result into the second register.

6. The multi-domain modular multiplication algorithm according to claim 5, characterized in that, The target operation domain is a prime number domain. The first multi-domain fast summation module performs addition operations on the target operation domain on the received first compression operation result to obtain an intermediate operation result, including: the first multi-domain fast summation module performs serial carry addition operations on the received first compression operation result to obtain an intermediate operation result. The target operation domain is a binary domain. The first multi-domain fast summation module performs an addition operation on the target operation domain on the received first compression operation result to obtain an intermediate operation result, including: the first multi-domain fast summation module performs an XOR operation on the received first compression operation result to obtain an intermediate operation result.

7. The multi-domain modular multiplication algorithm according to claim 4, characterized in that, The multi-input multi-domain adder includes a multi-domain compression module and a second multi-domain fast summation module; the multi-domain compression module is connected to the second multi-domain fast summation module, and the second multi-domain fast summation module is connected to the first register; The multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit performs addition operations on the target operation domain of the received intermediate operation result to obtain a new intermediate operation result, including: In the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit, the multi-domain compression module performs compression and summation operations on the target operation domain of the received intermediate operation results to obtain a second compression operation result, and inputs the second compression operation result into the second multi-domain fast summation module; In the multi-input multi-domain adder of the non-lowest level multi-domain multiplication subunit, the second multi-domain fast summation module performs addition operation on the target operation domain of the received second compression operation result to obtain a new intermediate operation result, and writes the new intermediate operation result into the first register.

8. The multi-domain modular multiplication algorithm according to claim 4, characterized in that, In the multi-domain multiplication unit, the non-lowest level multi-domain multiplication subunit includes 4 next-level multi-domain multiplication subunits, the multi-input multi-domain adder is a 4-input multi-domain adder, and the encoding module is a radix-4 booth encoding module.

9. The multi-domain modular multiplication algorithm according to claim 1, characterized in that, The multi-domain fast modulo reduction unit includes an input subunit, multiple reduction subunits corresponding to multiple operational domains, and a third register; the input subunit is connected to the reduction subunit corresponding to each operational domain, and the reduction subunit corresponding to each operational domain is connected to the third register; The multi-domain fast modular reduction unit performs a reduction operation on the target operation domain of the target operation result to obtain the modular multiplication algorithm result, including: The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain; The target reduction subunit performs a reduction operation on the target operation result to obtain the modular multiplication algorithm result, and writes the modular multiplication algorithm result into the third register.

10. The multi-domain modular multiplication algorithm according to claim 9, characterized in that, The configuration data indicates whether to enable or disable the multiplier; the input subunit is also connected to the third register; The input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain, including: when the configuration data indicates that the multiplier is disabled, the input subunit inputs the target operation result into the target reduction subunit corresponding to the target operation domain; When the configuration data indicates that the multiplier is enabled, the input subunit writes the target operation result into the third register.

11. The multi-domain modular multiplication algorithm according to claim 1, characterized in that, The target operation domain is a prime number domain. The multi-domain fast modular reduction unit performs reduction operations on the target operation domain of the target multiplication operation result to obtain the modular multiplication algorithm result, including: the multi-domain fast modular reduction unit performs addition, subtraction and shift operations on the target multiplication operation result to obtain the modular multiplication algorithm result; The target computation domain is a binary domain. The multi-domain fast modular reduction unit performs reduction operations on the target computation result to obtain the modular multiplication algorithm result, including: the multi-domain fast modular reduction unit performs state machine operations and XOR operations on the target computation result to obtain the modular multiplication algorithm result.

12. A modular multiplication method, characterized in that, An algorithm for multi-domain modular multiplication is applied, comprising an input unit, a multi-domain multiplication unit, a multi-domain fast modular reduction unit, and an output unit; the input unit is connected to the multi-domain multiplication unit, the multi-domain multiplication unit is connected to the multi-domain fast modular reduction unit, and the multi-domain fast modular reduction unit is connected to the output unit; the multi-domain multiplication unit comprises multiple levels of multi-domain multiplication sub-units, wherein the non-lowest level multi-domain multiplication sub-units include multiple multi-domain multiplication sub-units at the next lower level; the method includes: The input unit receives input data, which includes first sub-data, second sub-data, and configuration data. The configuration data indicates the target operation domain where the modular multiplication operation is located, as well as the effective bit width of the first sub-data and the second sub-data. The input data is then input into the target multi-domain multiplication sub-unit corresponding to the effective bit width in the multi-domain multiplication unit. The target multi-domain multiplication subunit utilizes multiple levels of multi-domain multiplication subunits under the target multi-domain multiplication subunit to perform multiplication operations on the first sub-data and the second sub-data using the target operation domain, thereby obtaining the target operation result; The target calculation result is input into the multi-domain fast modular reduction unit; The multi-domain fast modular reduction unit performs a reduction operation on the target operation domain of the target operation result to obtain the modular multiplication algorithm result; and inputs the modular multiplication algorithm result into the output unit; The output unit outputs the result of the modular multiplication algorithm.

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