Server starting method, electronic equipment and storage medium

Abstract

The invention discloses a server starting method, electronic equipment and a storage medium, and the method comprises the steps: controlling a basic input / output system to enter a hardware initialization stage after receiving a server starting instruction, recognizing the target mainboard configuration of a server mainboard according to the pin state of a group of pins of a universal input / output interface, and starting the server mainboard according to the target mainboard configuration. And automatically searching a target link configuration table matched with the target mainboard configuration from the link configuration table set. In other words, under the condition that the mainboard configuration of the server mainboard changes, the link configuration information matched with each mainboard configuration can be automatically adapted according to the pin state value of the universal input and output interface. According to the method and the device, the technical problem of relatively high complexity in the process of configuring adaptive bus link configuration information for different mainboards in related technologies is solved, and the technical effect of improving the starting efficiency of the server is realized.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a server startup method, electronic device, and storage medium. Background Technology

[0002] In existing server hardware configuration management, the lanes (transmission links) of the HSIO (High Speed ​​I / O) bus on the server motherboard are typically configured during the design phase according to a predefined hardware layout. This configuration information is embedded in the server's management engine.

[0003] However, the above method of processing bus link configuration information can only meet the default hardware configuration of the server motherboard. When the type and layout of the server motherboard's hardware components change, it is necessary to recompile the BIOS (Basic Input Output System) image and manually update the bus link configuration information in the management engine to adapt to the new hardware layout. This not only consumes a lot of time but also increases the complexity of the configuration process. It also increases the server's startup time under the condition of hardware layout changes, causing technical problems of low efficiency during server startup. Summary of the Invention

[0004] This application provides a server startup method, electronic device, and storage medium to at least solve the problem of low efficiency during server startup under conditions of hardware layout changes in the related art.

[0005] According to one aspect of the embodiments of this application, a server startup method is provided, comprising: responding to a server startup command, controlling the server's basic input / output system to enter a hardware initialization phase; determining a target motherboard configuration of the server motherboard based on the pin states of a general-purpose input / output interface, wherein the target motherboard configuration includes types of hardware components, the types of hardware components including at least one of a serial interface hard disk, a solid-state hard disk, a graphics processor, and a modular network device; searching a target link configuration table set that matches the target motherboard configuration from a link configuration table set, wherein the link configuration table set is used to describe link configuration information that matches different motherboard configurations obtained by signal multiplexing of the actual number of transmission links supported by the central processing unit; and starting the server based on the link configuration information in the target link configuration table.

[0006] According to another aspect of the embodiments of this application, a server startup apparatus is also provided, comprising: a control unit, configured to control the server's basic input / output system to enter a hardware initialization phase in response to a server startup command; a first processing unit, configured to determine a target motherboard configuration of the server motherboard based on the pin states of a general-purpose input / output interface, wherein the target motherboard configuration includes the type of hardware components, the type of hardware components including at least one of a serial interface hard disk, a solid-state hard disk, a graphics processor, and a modular network device; a first lookup unit, configured to look up a target link configuration table matching the target motherboard configuration from a link configuration table set, wherein the link configuration table set is used to describe link configuration information matching different motherboard configurations obtained by signal multiplexing of the actual number of transmission links supported by the central processing unit; and a startup unit, configured to start the server based on the link configuration information in the target link configuration table.

[0007] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the steps of any of the above-described server startup methods through the computer program.

[0008] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to perform the steps of any of the above-described server startup methods when it is run.

[0009] According to another aspect of the embodiments of this application, a computer program product or computer program is provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of any of the above-described server startup methods.

[0010] Using the embodiments provided in this application, during the server startup process, the basic input / output system enters the hardware initialization phase. Based on the pin status values ​​of the general-purpose input / output interfaces, the motherboard configuration of the server motherboard is determined. Then, based on the motherboard configuration, the target link configuration information that meets the hardware configuration of the current server motherboard is found from the link configuration table set. In other words, when faced with diverse server hardware configurations, the target motherboard configuration can be quickly determined and the matching target link configuration table can be found using only the pin status values ​​of the general-purpose input / output interfaces. This simplifies the allocation of HSIO bus lanes and the bandwidth splitting of transmission links, reduces configuration time, and achieves the technical effect of improving server startup efficiency. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram illustrating an application scenario of a server startup method according to an embodiment of this application.

[0013] Figure 2 This is a flowchart of an optional server startup method according to an embodiment of this application.

[0014] Figure 3 This is a schematic diagram of the physical design of an optional server motherboard according to an embodiment of this application.

[0015] Figure 4 This is a schematic diagram of an optional HSIO link connection according to an embodiment of this application.

[0016] Figure 5 This is a schematic diagram illustrating the allocation of HSIO resources under different optional hardware configurations according to an embodiment of this application.

[0017] Figure 6 This is an overall flowchart of an optional server startup method according to an embodiment of this application.

[0018] Figure 7 This is a swimlane diagram of an optional server startup method according to an embodiment of this application.

[0019] Figure 8 This is a structural block diagram of an optional server startup device according to an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0021] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0022] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] According to one aspect of the embodiments of this application, a server startup method is provided. Optionally, in this embodiment, the above-described server startup method may be applied to, but is not limited to, [examples of applications such as...]. Figure 1 In the hardware scenario shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0024] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the server startup method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the server device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0025] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0026] The embodiments of this application can be applied, but are not limited to, scenarios where the hardware configuration of the server motherboard changes, and where the HSIO bus lane multiplexing settings can be quickly adapted according to different hardware requirements. For ease of understanding, specific examples of several application scenarios are given below.

[0027] (1) Management of multi-configuration servers in data centers: In large-scale data center environments, servers may need to be reconfigured due to changes in load requirements, such as changing from storage-intensive configurations to compute-intensive configurations. The technical solution of this application allows maintenance personnel to quickly reconfigure the server motherboard by simply setting the jumper caps on the GPIO (General-purpose input / output) pins, without physically disassembling or recompiling the BIOS image, thus simplifying the server hardware configuration process.

[0028] (2) Dynamic allocation of cloud computing resources: In a cloud environment, users' demand for computing resources changes dynamically. The technical solution of this application can automatically identify the CPU (Central Processing Unit) model and the number of HSIO bus lanes, and dynamically adjust the bandwidth allocation and port enabling of PCI (Peripheral Component Interconnect) links to ensure that the cloud server can adjust hardware resources according to real-time needs, thereby achieving efficient resource utilization and rapid response.

[0029] (3) Flexible deployment of edge computing devices: Edge computing devices typically need to operate under different physical environments and network conditions. The technical solution of this application allows the device to adapt to different edge application needs through software configuration updates without changing the hardware, such as adding or reducing storage, network interfaces, or adjusting PCI link bandwidth allocation, which provides convenience for on-site upgrades and configuration changes of edge computing devices.

[0030] (4) Enhanced server security and compliance: Preventing unauthorized configurations and ensuring hardware compliance are crucial during server use. The technical solution of this application introduces a GPIO verification mechanism to ensure that the server BIOS image corresponds one-to-one with the motherboard, effectively preventing unsupported hardware configurations, enhancing server security and stability, and facilitating rapid verification of server hardware configuration information during compliance checks.

[0031] By applying the technical solution of this application to the above scenarios, not only are the problems in traditional server configuration management solved, but technical support is also provided for the efficient and flexible deployment of servers.

[0032] The server startup method of this application embodiment can be executed by a server device, or by a server device in combination with at least one of a terminal device (which can also be understood as input / output device 108). The server startup method of this application embodiment can also be executed by a client installed on the terminal device.

[0033] Taking the server startup method in this embodiment as an example, Figure 2 This is a flowchart illustrating an optional server startup method according to an embodiment of this application, as shown below. Figure 2 As shown, the process of this method may include steps S202 to S208.

[0034] Step S202: In response to the server's startup command, control the server's basic input / output system to enter the hardware initialization phase.

[0035] Step S204: Based on the pin status of the general purpose input / output interface, determine the target motherboard configuration of the server motherboard, wherein the target motherboard configuration includes the type of hardware components, and the type of hardware components includes at least one of serial interface hard disk, solid-state hard disk, graphics processor and modular network device.

[0036] Step S206: Search for a target link configuration table that matches the target motherboard configuration from the link configuration table set, wherein the link configuration table set is used to describe link configuration information that matches different motherboard configurations obtained by signal multiplexing of the actual number of transmission links supported by the central processing unit.

[0037] Step S208: Start the server based on the link configuration information in the target link configuration table.

[0038] In related technologies, to improve the utilization of CPU peripherals, PCI links can be configured in multiple modes, such as USB (Universal Serial Bus) mode, SATA (Serial ATA, an interface for storage devices) mode, and PCI mode. That is, a single PCI link mode can be configured as multiple non-PCI link modes. However, a technical issue arises here: in the ME (Management Engine) configuration interface, how do you configure the HSIO bus lanes (transmission links or links) according to hardware design requirements, setting them to PCI links, USB links, or SATA links, etc.? Furthermore, when configuring PCI links, different bandwidths can be set according to, but are not limited to, the bandwidth requirements of the PCI link, such as x8, x4x4, x4x2x2, x2x2x4, x2x2x2x2, etc.

[0039] If the HSIO bus is not used, it is set to "Unused". When the HSIO is set as a SATA device interface, the HSIO bus lane needs to be set to SATA interface mode; if SATA mode is not used, it is set to "Not set to SATA mode". For the HSIO bus lane set as a PCI link, the corresponding port controlling the PCI link needs to be enabled, and the enabling and enabling settings of the PCI link port need to be configured according to the specific splitting situation. If the server motherboard only has one configuration, the above solution has no technical problems. However, if the server motherboard hardware configuration or link changes, the ME configuration will need to be adjusted to adapt to meet the server's HSIO link settings. This results in different server motherboard hardware configurations requiring different ME configurations, making it impossible to set and apply multiple HSIO parameters through a single BIOS image.

[0040] In other words, for server motherboards with various form factors, each hardware configuration requires a separate BIOS image and ME profile, increasing the complexity and cost of server hardware management and maintenance. It also reduces server boot efficiency.

[0041] Since the HSIO bus supported by the CPU typically contains 20 HSIO bus lanes, and each lane is a multiplexed signal, it can be used as a PCI link or a non-PCI link, such as a SATA link interface or a USB link interface. Therefore, the ME configuration needs to be set according to the hardware design. For example, HSIO lanes 0-7 are set as PCI links, lanes 8-9 are set as PCI links for network card devices, lanes 10-11 are set as PCI links for the BMC management chip, lanes 12-13 are set as SATA links, lanes 14-15 are set to Unused if not used, lane 16 is set as a USB link interface (USB device), and lanes 17-19 are set to Unused if not used.

[0042] Because each PCI link can be reused as a SATA interface link, and Lanes 12-13 of the HSIO link are already configured as SATA interfaces, Lanes 12 and 13 are set as SATA links in the SATA interface settings, while the other lanes are set as non-SATA links in the SATA interface. The above only sets the lanes for the HSIO links and does not split the configured PCI links. Regarding the splitting of the PCI links here, since there are two x8 PCI link controllers, and Lanes 0-7 of the HSIO bus are configured as PCI links with x8 bandwidth, it is only necessary to enable the first controller of the PCI link and enable RP0. RP1-RP3 need to be disabled because RP0 can be used as the enable controller for x8, as well as for enabling x4 and x2. Lanes 8-15 of the HSIO bus are the C1 controllers for the PCI links and need to be enabled. Since two x2 lanes and four lanes are unused, they are set to x2x2x4 mode. That is, RP4, RP5, and RP6 are enabled, and RP7 is disabled. The above is the default link configuration information for ME. However, the default link configuration information can only support the configuration of one fixed HSIO bus lane. If other configurations are required, ME needs to be reconfigured or multiple BIOS images need to be compiled to allow for arbitrary changes to different configurations.

[0043] To address this issue, the BIOS code is designed to dynamically support multiple different link configurations when multiple types of link configuration information are involved. For example, if four types of link configurations exist, these four configurations can be set as four separate link configuration tables. The specific configuration of the server motherboard is determined by reading GPIO or sensitive key information, and then the corresponding configuration information is loaded. The loaded configuration tables then replace or overwrite the settings in the ME.

[0044] The technical solution proposed in this application is an improvement solution to solve the above problems. Before explaining the technical solution of this application, the meaning of the professional terms or technical terms involved will be briefly introduced first.

[0045] HSIO bus Lane: refers to the transmission link on the high-speed input / output bus provided by the CPU. Each lane can be configured with different signal types, such as PCI, USB, SATA, etc.

[0046] General Purpose Input / Output Interface (GPIO): A type of input / output pin that can be controlled by software and is used for the identification and verification of hardware configurations.

[0047] Link configuration table set: This set contains HSIO bus lane configuration information for various server motherboard configurations. The appropriate link configuration table is selected by indexing GPIO status (status value, such as high or low level).

[0048] In this embodiment, the physical design of the server motherboard may be, but is not limited to, as follows: Figure 3 As shown below, Figure 3 A brief description of each component is provided.

[0049] CPU: Enables high-speed data exchange with various devices via HSIO links. HSIO includes 20 lanes, each of which can be multiplexed for different signal types such as PCIe (point-to-point serial link), SATA, and USB to support diverse peripheral needs.

[0050] ME (Management Engine): Built into the CPU, it is responsible for functions such as server power-on management and remote management. The ME initializes and controls the server's basic hardware resources by reading preset configuration information, such as the signal type and bandwidth allocation of the HSIO bus link.

[0051] BIOS (Basic Input / Output System): The server's boot program, responsible for detecting hardware status during server startup, loading the correct ME configuration, and ensuring the server starts up as expected.

[0052] SATA Interface: An interface link used to connect SATA storage devices. Specific lanes in HSIO (such as Lane 12-Lane 13) are configured for SATA signals to enable data read and write functions for storage devices.

[0053] PCI slots: Expansion card devices that support PCIe links, such as network cards, RAID (disk array) cards, NVMe hard drives (non-volatile memory high-speed interface solid-state drives), etc. Through dynamic splitting and bandwidth allocation of HSIO links, different PCI slots can be configured as x8, x4, or x2 PCIe links as needed to meet the bandwidth requirements of different devices.

[0054] USB interface: Used to connect USB devices, such as keyboards, mice, and external storage devices. Lane 16 in the HSIO bus is configured for USB signals to ensure the proper use of USB devices.

[0055] BMC (Baseboard Management Controller): Responsible for out-of-band management and monitoring of the server. Specific lanes in HSIO (such as Lane 10-Lane 11) are configured to support PCIe links for the BMC so that the BMC can operate independently of the main CPU and operating system.

[0056] GPIO (General Purpose Input / Output): Used to read critical information such as Board ID (the board identifier of the server motherboard) to identify different motherboard configurations. By detecting the GPIO status, the server can determine the motherboard model at startup, load the corresponding link configuration information, and even perform a crash procedure if the configuration information cannot be determined, ensuring hardware safety.

[0057] LPC (Low Pin Count) / SPI (Serial Peripheral Interface) / PCI: Provides a low-speed communication link between the BMC management chip and other components on the motherboard, ensuring that the server's management functions can continue to operate even when the network is disconnected.

[0058] The aforementioned hardware components are tightly interconnected via carefully designed HSIO links, forming a complex signal transmission network. For example, HSIO lanes 0-7 and 8-15 are configured as PCIe links, supporting x8 and x2x2x2x2 or x2x2x4 bandwidth modes respectively. Lanes 12-13 are specifically configured for SATA signals, while Lane 16 carries USB signals. Furthermore, the enable / disable status of HSIO bus lanes and bandwidth allocation are adjusted through dynamically loaded link configuration information in the BIOS, ensuring stable server operation under various hardware configurations. Finally, through GPIO verification, the server ensures compatibility between its hardware configuration and the BIOS image, preventing unauthorized hardware access and enhancing overall server security.

[0059] It should be noted that the "x8" mentioned above refers to a bandwidth configuration mode for a PCI Express (PCIe) link, specifically meaning that the link is configured with 8 data transmission channels. The PCI Express standard allows links to operate with different numbers of data channels, which are usually represented by "x" (Cross) followed by a number, such as x1, x2, x4, x8, etc. The larger the number, the faster the data transmission speed.

[0060] When server motherboard designs need to support multiple hardware configurations, the x8 bandwidth configuration mode allows for flexible splitting of HSIO links. For example, an x8 link can be split into two x4 links or four x2 links to accommodate different peripheral requirements. This ability to split and reconfigure, combined with dynamically loaded configuration information in the BIOS system, enables the server to intelligently adapt to different hardware environments without requiring physical hardware changes or recompiling the BIOS image, thus improving server deployment efficiency and device compatibility.

[0061] In the implementation of the technical solution of this application, after the server receives the boot command, the BIOS will first identify the CPU model. This information is crucial for determining the number of HSIO bus lanes that the CPU can support.

[0062] For ease of understanding, in this embodiment, Figure 4 The technical solution of this application will be explained using the HSIO link connection diagram shown as an example.

[0063] like Figure 4As shown, assuming the current CPU model supports 20 lanes on the HSIO bus, each lane is a multiplexed signal that can be used as a PCI link or a non-PCI link, such as a SATA link interface or a USB link interface. Therefore, the ME configuration needs to be set according to the hardware design. For example, HSIO links Lane 0-Lane 7 are set as PCI links, Lane 8-Lane 9 are set as PCI link network card devices, Lane 10-Lane 11 are set as PCI link BMC management chip devices, Lane 12-Lane 13 are set as SATA link interfaces, Lane 14-Lane 15 are set to Unused state if not used, Lane 16 is set as a USB link interface, i.e., a USB device, and Lane 17-Lane 19 are set to Unused state if not used. Since each PCI link can be reused as a SATA interface link, and Lane 12-Lane 13 of the HSIO link have already been set as SATA interfaces, Lane 12 and Lane 13 are set as SATA links in the SATA interface settings, and the other lanes are set as non-SATA link interfaces in the SATA interface.

[0064] After determining the target motherboard model (which can also be understood as the target motherboard configuration or target motherboard hardware configuration) based on the GPIO pin state combinations, the BIOS searches for the target link configuration table from the link configuration table set. The BIOS pre-stores a set of link configuration tables, with each table corresponding to a motherboard configuration. Based on the target motherboard configuration, the BIOS loads the corresponding target link configuration table from the configuration table set.

[0065] Finally, the BIOS uses information from the target link configuration table to update the HSIO bus lane configuration, including but not limited to the number of lanes and bandwidth allocation. After configuration is complete, the server will boot with the new settings to ensure all hardware components are functioning correctly.

[0066] Based on the above description, the relevant technologies mainly involve configuring the HSIO bus lanes in the ME configuration according to the hardware engineer's design, setting multiplexed signals such as SATA, PCI, USB, and Unused. When the HSIO bus is configured for SATA function, the corresponding HSIO bus lane is assigned to the SATA interface, and the lanes for non-SATA interfaces are set to non-SATA mode. Simultaneously, based on the lane signals allocated from the HSIO bus to the PCI bus, the PCI controller performs bandwidth splitting and port enabling settings, thus enabling the ME configuration to manage the HSIO bus lanes.

[0067] However, a limitation of this technology is that it can only implement one HSIO bus lane configuration, and cannot guarantee that the HSIO bus settings cannot be dynamically adjusted after changing the motherboard configuration or replacing the CPU. To address this, the PEI (Hardware Initialization) phase in the BIOS code determines various possible link configuration information, such as reducing or utilizing some HSIO bus lanes, disabling lanes allocated to SATA, disabling HSIO bus lanes, reconfiguring bandwidth allocation for HSIO bus lanes allocated to PCI links, or disabling or splitting some ports. All of these can be configured through a static variable table set in the BIOS code.

[0068] Meanwhile, to ensure the safety and reliability of the server motherboard, two sets of GPIO are introduced. One set of GPIO is used to determine whether the motherboard configuration supports the CPU model; if not, a crash is initiated. The other set of GPIO is used to determine which configuration the current motherboard needs to support. Based on the GPIO combination, different link configuration information is loaded according to the different motherboard configurations. The GPIO combinations can be expanded beyond these four sets. One set is the default ME configuration, and the confirmed configuration information can also be updated to the ME configuration, overwriting the initial settings in ME. If the motherboard has many configurations, the GPIO settings can be adjusted using jumpers to adjust the usage of different configurations. This allows for arbitrary configuration changes and switching without changing the hardware motherboard or CPU model, making it convenient and quick. The usage process of the above two sets of GPIO will be described in detail below with specific examples.

[0069] The embodiments of this application not only simplify the management process of server hardware configuration, but also improve the flexibility of the system, enabling a single BIOS image to adapt to diverse hardware combinations, reducing maintenance costs and time losses caused by hardware changes, while also enhancing system security. By verifying the GPIO status, the use of unauthorized configurations is effectively prevented, ensuring the stable operation of the server and data security.

[0070] In an exemplary embodiment, the above-described determination of the target motherboard configuration of the server motherboard based on the pin status of the general-purpose input / output interface includes: determining the board identifier of the server motherboard based on the pin status of the general-purpose input / output interface, wherein there is a mapping relationship between the motherboard configuration of the server motherboard, the board identifier, and the link configuration table in the link configuration table set; and determining the target motherboard configuration of the server motherboard based on the board identifier.

[0071] As described in the above embodiments, different CPU models may support different numbers of HSIO bus lanes, or the number of HSIO bus lanes may be the same, but the signal type and bandwidth information of each lane may be different. For example, it may support 20 HSIO bus lanes, while other models may only support 16 or 12 lanes.

[0072] The BIOS determines the actual number of HSIO bus lanes supported by the CPU model. For example, for 20 lanes. It also queries the ME (Member of Equipment) to check the preset number of HSIO bus lanes. If the actual number differs from the preset number, the BIOS determines the target motherboard configuration based on the pin states of the general purpose input / output (GPIO) interfaces.

[0073] In an optional example, before determining the target motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface, the method further includes: reading the processor model of the central processing unit; determining the actual number of transmission links of the data transmission bus supported by the central processing unit based on the processor model; and, if the actual number is inconsistent with the preset number of transmission links set in the server's management engine, determining the motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface.

[0074] In other words, when the server starts up, it will read the model of the central processing unit on the server motherboard in advance, and obtain the actual number of HSIO bus lanes supported by the central processing unit of that current model based on the processor model.

[0075] Compare the actual number with the preset number of HSIO bus lanes set in the management engine. If the two are inconsistent, read the status of the input / output interfaces and determine the motherboard configuration of the server motherboard based on the GPIO pin status.

[0076] If the target motherboard configuration of the server motherboard is determined to be different from the default motherboard configuration based on the GPIO pin status, the target link configuration table that matches it is searched from the link configuration table set.

[0077] Typically, multiple board identifiers are determined based on different combinations of the high or low voltage levels of two or more GPIO pins, with each GPIO pin state corresponding to a single board identifier. The BIOS system then reads a set of preset GPIO pin states. These different combinations of GPIO pin states are associated with multiple motherboard configurations on the server motherboard.

[0078] Each board identifier indicates a type of motherboard configuration, which means that a mapping or index relationship between the server motherboard configuration and the board identifier needs to be created in advance.

[0079] After obtaining the board identifier, the BIOS system uses this information to look up the target motherboard configuration in a preset mapping table. The mapping table records in detail the specific motherboard configuration corresponding to different board identifiers. For example, the 0x00 board identifier described in the above embodiment corresponds to a motherboard configuration with 4 NVMe drives, while 0x01 corresponds to a motherboard configuration with 4 SATA hard drives.

[0080] In this embodiment, the system identifies a specific board installed on the server motherboard by reading the state of the GPIO pins. After obtaining the board identifier, the system determines the corresponding target motherboard configuration through a mapping table. The target motherboard configuration indicates the specific hardware configuration of the server motherboard, such as the layout and number of interfaces like PCIe, SATA, and USB.

[0081] Specifically, such as Figure 3 As shown, based on the high / low level of GPIO4 and GPIO5, four different combinations of Board IDs are formed. These four different board IDs are used to indicate four different motherboard configurations (which can also be understood as the hardware configuration or hardware layout of the server motherboard).

[0082] For example, a board identifier of 0x00 or 00 indicates a 4NVME configuration (motherboard + baseboard + 4NVME board); a board identifier of 0x01 or 01 indicates a 4SATA ​​configuration (motherboard + baseboard + 4SATA ​​board); a board identifier of 0x10 or 10 indicates a 3.5"HDD (Hard Disk Drive) configuration (motherboard + baseboard + 3.5"HDD board); a board identifier of 0x11 or 11 indicates a CPU + OCP (Open Compute Project) configuration (motherboard + baseboard + 3.5"HDD board), and so on.

[0083] Obviously, Figure 3 The combination of four GPIO pin states shown is used to indicate four different motherboard configurations and is only an example, not a limitation.

[0084] In another alternative embodiment, reading the processor model of the central processing unit includes: in response to a server startup command, controlling the server's basic input / output system to perform a hardware initialization task; and reading the processor model of the central processing unit by performing the hardware initialization task.

[0085] When the server receives the boot command, the BIOS system enters the PEI stage and executes a series of hardware initialization tasks. These tasks include, but are not limited to, CPU and memory checks, peripheral device checks, and system clock settings, to ensure that the server system can boot in a stable hardware environment.

[0086] For example, when the server is about to start up, the BIOS system first checks whether the memory modules are properly connected, then initializes the PCI bus, checks the status of each PCI device, and ensures that network cards, storage devices, etc. can operate normally.

[0087] During initialization, the BIOS system reads the CPU's processor model. This information is crucial for determining the server's hardware configuration and the available HSIO bus lanes. For example, when the server boots up, the BIOS detects that the CPU is model 1, which supports 20 HSIO bus lanes, the first 8 of which can be configured as PCIe x8, and the rest as SATA, USB, or other non-PCIe links. With this information, the BIOS can accurately load the HSIO configuration that matches the CPU model.

[0088] As can be seen, during the initialization task, the BIOS reads and confirms the CPU's processor model. This information will be used to determine the number and configurable range of HSIO bus lanes, as well as to load the corresponding link configuration information.

[0089] Through the hardware initialization task performed by the BIOS system, the server can automatically identify and adapt to the current hardware configuration, including the processor model, thereby loading the correct HSIO bus lane settings at startup, providing a foundation for subsequent dynamic link adjustments.

[0090] By performing hardware initialization and processor model reading during the server startup phase, the system is able to make corresponding configuration adjustments based on the latest server motherboard hardware information, enhancing the server's compatibility and adaptability to different hardware configurations and improving overall operating efficiency and performance.

[0091] By analyzing GPIO pin states to determine the board identifier and combining this with the CPU model, the system can intelligently match the target configuration type of the server motherboard, enabling dynamic selection of the appropriate link configuration table from a single BIOS image. This mechanism avoids the cumbersome process of frequently updating the BIOS image due to hardware configuration changes, simplifies server configuration management, and improves data center operational efficiency. Simultaneously, it ensures the stability and compatibility of the server under different hardware combinations, providing a technical foundation for dynamic adjustment of hardware resources and effectively addressing the diverse needs of server application scenarios.

[0092] In an exemplary embodiment, determining the board identifier of the server motherboard based on the pin status of the general-purpose input / output interface includes: reading a first status value of a first pin in the general-purpose input / output interface; reading a second status value of a second pin in the general-purpose input / output interface; and determining the board identifier of the server motherboard based on the first status value and the second status value.

[0093] As can be seen from the description of the above embodiments, such as Figure 3 As shown, based on the high / low level states of GPIO4 and GPIO5, four different combinations of Board IDs are formed, which are used to indicate four different motherboard configurations.

[0094] For example, when both GPIO4 and GPIO5 are low, the first combination is formed based on the level state of the two pins, that is, the first board identifier is 0x00 or 00; when GPIO4 is low and GPIO5 is high, the second combination is formed, that is, the second board identifier is 0x01 or 01; when GPIO4 is high and GPIO5 is low, the third combination is formed, that is, the third board identifier is 0x10 or 10; when both GPIO4 and GPIO5 are high, the fourth combination is formed, that is, the fourth board identifier is 0x11 or 11.

[0095] By creating a mapping relationship between each board identifier and a preset motherboard configuration, each board identifier can indicate a specific motherboard configuration. For example, 0x00 represents a 4 NVME configuration (motherboard + baseboard + 4 NVME board); 0x01 represents a 4 SATA configuration (motherboard + baseboard + 4 SATA board); 0x10 represents a 3.5" HDD configuration (motherboard + baseboard + 3.5" HDD board); 0x11 represents a CPU + OCP configuration (motherboard + baseboard + 3.5" HDD board), and so on.

[0096] Obviously, the above method of determining the mapping relationship between the board identifier and the motherboard configuration based on the combination of the level states of the two pins GPIO4 and GPIO5 is only an example and is not limited to it.

[0097] The board identifier is an abstraction of the server motherboard's hardware configuration, containing the specific layout and quantity of interfaces such as PCIe, SATA, and USB. This board identifier is also used to select the most suitable link configuration table from a pre-defined set of link configuration tables. The link configuration table details how to rationally allocate the HSIO bus lanes, split PCI link bandwidth, and enable or disable corresponding interface ports based on the specific hardware configuration on the server motherboard. Ultimately, the BIOS system will complete the effective configuration of the HSIO bus lanes based on the selected link configuration table, ensuring that the server can boot smoothly according to the current hardware layout and provide the necessary network and storage capabilities, without needing to rewrite and compile the BIOS image for every hardware change.

[0098] By employing refined GPIO status reading, the system enables rapid identification and dynamic matching of server motherboard configurations, thereby determining their hardware layout. This eliminates the inconvenience of frequent BIOS image updates required due to hardware configuration changes, shortens the time needed for motherboard configuration identification and adjustment, and improves the server's responsiveness and flexibility in diverse deployment scenarios.

[0099] In an exemplary embodiment, the above-mentioned method of searching for a target link configuration table that matches the target motherboard from the link configuration table set includes: comparing the target hardware configuration information indicated by the target motherboard configuration with the default hardware configuration information to obtain a target comparison result; and if the target comparison result indicates that the target hardware configuration information and the default hardware configuration information are inconsistent, searching for a target link configuration table that matches the target motherboard configuration from the link configuration table set.

[0100] Assume the server's default hardware configuration information is stored in the BIOS configuration file, which contains different hardware layouts and hardware types. Compare the default hardware configuration information in the retrieved ME with the target hardware configuration information to obtain the target comparison result.

[0101] If the comparison results show that the hardware configuration information is inconsistent, the BIOS system will query the link configuration table set.

[0102] In addition, it can be assumed that the BIOS configuration file also contains default link configuration information. For example, it may contain default allocation information for a set of HSIO bus lanes, such as lanes 0 to 15 being allocated to PCIe links, and lanes 16 and 17 being allocated to USB links. When the server starts up, the BIOS system first reads the target hardware configuration information based on the GPIO status, and then looks up the link configuration table that maps to the target hardware configuration information.

[0103] By comparing the link configuration information in the link configuration table with the default link configuration information in ME, if the two are inconsistent, the target link configuration table that matches the target motherboard configuration is searched from the link configuration table set.

[0104] By comparing the target hardware configuration information with the default hardware configuration information, the system can intelligently identify hardware configuration differences and automatically select the matching link configuration table, thus achieving dynamic optimization and allocation of server hardware resources. This effectively avoids the cumbersome process of frequently modifying the BIOS image due to changes in hardware layout, shortens configuration adaptation time, and enhances the server's flexibility when facing diverse hardware combinations.

[0105] In an exemplary embodiment, the above-mentioned method of searching for a target link configuration table that matches the target motherboard configuration from the link configuration table set includes: finding the target link configuration table based on the mapping relationship between the target motherboard configuration and the link configuration tables in the link configuration table set.

[0106] In this embodiment, by maintaining the mapping relationship between the motherboard configuration, board identifier, and link configuration table in the link configuration table set of the server motherboard, these link configuration information are mapped one-to-one with the motherboard configuration, forming a fast search and location mechanism.

[0107] This includes a table containing all possible motherboard configurations and their corresponding link configurations. For example, for motherboard A with a 4NVME configuration, its link configuration table might indicate that the HSIO bus Lane [7:0] is allocated to the PCIe link, and Lane [13:12] is allocated to the SATA interface; while for motherboard B with a 4SATA ​​configuration, the link configuration table might show a mixed layout where the HSIO bus Lane [7:0] is split into SATA and PCIe links, etc. The mapping relationship can be stored in a database table or array structure. By mapping these link configuration information one-to-one with the motherboard configuration, the purpose of quickly finding the appropriate link configuration information for different motherboard configurations can be achieved.

[0108] In other words, once the motherboard configuration of the current server is determined, the target link configuration table that matches the motherboard configuration can be quickly found using the above mapping relationship. This process does not require traversing the entire configuration table set, but rather achieves accurate searching of the target link configuration table directly based on the key parameter of motherboard configuration.

[0109] Using the pre-created mapping relationships, the target link configuration table that matches the target motherboard configuration can be quickly found. This lookup process is efficient and accurate, ensuring that the system can immediately apply the configuration information that best suits the current hardware layout without searching through the configuration table set, thus improving the system's response speed to hardware configuration changes.

[0110] In an exemplary embodiment, the above-described method of searching for the target link configuration table matching the target motherboard configuration from the link configuration table set includes: reading the third state value of the third pin in the general-purpose input / output interface; reading the fourth state value of the fourth pin in the general-purpose input / output interface; determining the configuration table identifier of each link configuration table in the link configuration table set based on the third state value and the fourth state value; searching for a target configuration table identifier that matches the target board identifier from the configuration table identifiers based on the target board identifier corresponding to the target motherboard configuration; and finding the target link configuration table from the link configuration table set based on the target configuration table identifier, wherein there is a mapping relationship between the target motherboard configuration, the target board identifier, and the link configuration tables in the link configuration table set, and there is a one-to-one correspondence between the target configuration table identifier and the target link configuration table.

[0111] When the server starts up and enters the PEI (hardware initialization) phase, the system first reads the third pin in the GPIO and records its third state value. Assume that the state value of this pin is 0.

[0112] Then, read the fourth pin of the GPIO and record its fourth state value. If the state value of the fourth pin is 1, combine it with the read value of the third pin to construct a specific configuration table identifier.

[0113] For example, such as Figure 3 As shown, assuming the third pin is GPIO0 and the fourth pin is GPIO1, when both the third and fourth state values ​​are 0, the configuration table identifier is 0x00 or 00; when the third state value is 0 and the fourth state value is 1, the configuration table identifier is 0x01 or 01; when the third state value is 1 and the fourth state value is 0, the configuration table identifier is 0x10 or 10; when both the third and fourth state values ​​are 1, the configuration table identifier is 0x11 or 11.

[0114] As described in the above embodiments, there is a mapping relationship between the server motherboard configuration, the board identifier, and the link configuration table in the link configuration table set. Therefore, based on the target board identifier corresponding to the target motherboard configuration in the above embodiments, a target configuration table identifier matching the target board identifier is searched from the configuration table identifiers.

[0115] The target link configuration table is retrieved from the link configuration table set based on the target configuration table identifier. The target board identifier is determined by the status values ​​of the first and second pins described in the above embodiments. This will not be elaborated further here.

[0116] In other words, by using the status values ​​of the third and fourth pins of the GPIO pins, the system can determine a unique configuration table identifier for each link configuration table. This identifier is used to locate the target link configuration table. The system utilizes the mapping relationship between configuration table identifiers and target motherboard configurations to accurately match the target configuration table identifier that matches the target motherboard hardware layout. Finally, based on the target configuration table identifier, the system quickly locates and loads the corresponding target link configuration table, enabling dynamic adjustment and optimization of server hardware resources.

[0117] It should be noted that for the same motherboard configuration, the values ​​of its board identifier and its configuration table identifier may be the same or different, and no limitation is made in this embodiment.

[0118] In this embodiment, by combining GPIO status values ​​with link configuration table identifiers and mapping the configuration table identifiers to motherboard configurations, the system can quickly and accurately find link configuration information suitable for the current hardware layout, avoiding the time-consuming and complex process of traditional manual configuration and improving the server's startup efficiency and hardware resource utilization efficiency.

[0119] In an exemplary embodiment, the method further includes: at least one parameter among the multiple parameters contained in any two link configuration tables in the link configuration table set has a different value: the number of transmission links of the data transmission bus, bandwidth splitting information, configuration information of the transmission links, bandwidth length, and status information of the bandwidth splitting port.

[0120] Let's continue with the explanation using the four possible motherboard configurations described in the above embodiments. And let's assume that during the HSIO resource allocation process, the allocation of HSIO[19:8] is fixed, while HSIO[7:0] is flexibly allocated according to different motherboard configurations. Here, HSIO[19:8] represents... Figure 4 The HSIO bus lanes shown are numbered 8 to 19, and HSIO[7:0] represents lanes 0 to 7 of the HSIO bus.

[0121] For board identifiers of 0x00 or 00, it indicates that the current server motherboard hardware configuration is 4NVME (motherboard + baseboard + 4NVME board); board identifier of 0x01 or 01 indicates 4SATA ​​(motherboard + baseboard + 4SATA ​​board); board identifier of 0x10 or 10 indicates 3.5HDD (motherboard + baseboard + 3.5HDD board); board identifier of 0x11 or 11 indicates CPU + OCP (motherboard + baseboard + 3.5HDD board), etc.

[0122] You can, but are not limited to, configure the link configuration information in the link configuration table set that matches the four motherboard configurations mentioned above, using the following methods. For details, please refer to... Figure 5 The configuration result is shown.

[0123] (1) 4NVME configuration: HSIO[7:0] is divided into PCIe x8 and then into 4 x4 via PCIe switch.

[0124] In this context, PCIe x8 means that eight lanes are combined to form a single PCIe interface, providing eight times the bandwidth. The input PCIe signals are then redistributed or split by a PCIe switch, resulting in four x4 links. In other words, the original x8 PCIe signal is split into four independent x4 PCIe links, each with sufficient bandwidth to support one NVMe SSD (Non-Volatile Memory Express Solid State Drive). Therefore, through this splitting method, the server can simultaneously connect to and efficiently access four high-speed NVMe SSDs.

[0125] (2) 4SATA ​​configuration: HSIO[7:0] is divided into [7:4]SATAx4, and HSIO[3:0] is divided into PCIEx4.

[0126] Lanes 4 through 7 of the HSIO bus are configured for SATA interface use and are grouped into a SATAx4 interface. SATAx4 means that these four lanes are integrated into a single high-speed SATA interface, providing higher bandwidth and data transfer rates than traditional SATA interfaces. Normally, a SATA interface consists of only one lane; this configuration utilizes four lanes to provide greater bandwidth to meet the demands of high-speed SATA storage devices.

[0127] Meanwhile, HSIO[3:0] being divided into PCIe x4 indicates that lanes 0 through 3 are reserved for building a PCIe x4 interface. PCIe is a high-speed serial computer expansion bus standard that can be used to connect various types of high-speed peripheral devices, such as graphics cards, network cards, and RAID cards. By configuring these four lanes as PCIe x4, the server can maintain at least one high-speed PCIe slot for installing additional PCIe devices to expand computing, storage, or networking capabilities.

[0128] In summary, the 4SATA ​​configuration is a hybrid setup. Four lanes on the HSIO are used to create a high-speed SATAx4 interface to support four SATA storage devices, while the other four lanes are used to build a high-speed PCIe x4 interface to maintain the server's PCIe x4 expansion capabilities. This configuration flexibly balances storage and scalability requirements while maximizing CPU resource utilization.

[0129] (3) 3.5 HDD configuration: HSIO[7:0] is divided into [7:4] HDDx4, and [3:0] is divided into PCIEx4.

[0130] The first eight lanes of HSIO (HSIO[7:0]) are allocated to two different interface types: HDD and PCIe. Specifically, lanes 4 through 7 are configured as HDD interface links supporting high-speed transmission and are labeled HDDx4. These four lanes are used in combination to provide a larger data transfer bandwidth for a SATA device. 3.5-inch hard drives typically require high data transfer rates, so using HDDx4 can meet the performance requirements of large-capacity hard drives.

[0131] Meanwhile, lanes 0 through 3 are reserved and configured as a PCIe x4 interface to support high-performance PCIe devices, such as RAID cards, network adapters, or other high-speed I / O expansion cards.

[0132] The above configuration ensures the server has a hard disk drive (HDD) interface while retaining PCIe expansion capabilities, allowing the installation of additional PCIe devices to enhance server functionality. This design enables the server to effectively balance the performance requirements of storage and external devices, making it particularly suitable for applications requiring large hard disk storage space but where PCIe expandability cannot be accommodated. By rationally allocating the HSIO bus lanes, the server can dynamically adjust its I / O resources without replacing hardware to adapt to different business and workload demands.

[0133] (4) GPU+OCP configuration: HSIO[7:0] is allocated as PCIe x8 and divided into 2 x8 via PCIe switch.

[0134] Here, HSIO[7:0] refers to the first 8 lanes of the HSIO bus. These 8 lanes are uniformly configured as PCIe interfaces for connecting various high-performance peripheral devices. x8 indicates that this interface has the transmission capacity of 8 lanes, which can provide high data transmission bandwidth.

[0135] These eight lanes of PCIe x8 interfaces are further divided into two independent PCIe x8 interfaces via a PCIe switch or transfer switch. The role of the PCIe switch is to route and switch signals between multiple PCIe devices, thereby enabling multiple devices to share PCIe bus resources. In a GPU+OCP configuration, the single PCIe x8 interface is split into two x8 interfaces by a PCIe switching chip, which can be used to connect the GPU and other high-performance PCIe devices, such as network interface cards or storage devices.

[0136] In this way, the server can efficiently support two high-speed PCIe x8 devices even with limited physical HSIO resources. This configuration not only improves the server's ability to support graphics-intensive tasks but also increases its flexibility and scalability in areas such as high-performance computing, machine learning, and data centers. Especially under resource constraints, the PCIe switch enables efficient resource utilization and dynamic configuration, meeting the requirements for high-bandwidth, low-latency device connectivity.

[0137] It should be noted that the configuration parameters in the above link configuration table include, but are not limited to, the number of HSIO bus lanes, bandwidth splitting, HSIO link settings, SATA link settings, bandwidth splitting port enable or disable settings, bandwidth length settings, etc.

[0138] The bandwidth allocation information varies depending on hardware requirements. Under x8 bandwidth requirements, all lanes may be allocated to a single PCIe link; while in x4x2x2 mode, the same number of lanes will be split into three links, each with a bandwidth of x4, x2, and x2 respectively. The differences in bandwidth allocation details across configuration tables, such as the combination of lanes allocated to different bandwidth links, are key parameters for the system to identify different hardware configuration requirements.

[0139] Each lane may be configured as PCIe, SATA, USB, or Unused in different hardware configurations. For example, Lane 12 may be part of a PCIe link in a 4NVME configuration, but may be configured as a SATA link in a 4SATA ​​configuration. This variability in configuration information ensures that the system can accurately apply the appropriate link settings for different hardware layouts.

[0140] The bandwidth length parameter reflects the maximum data transfer rate that the link can support. For example, in a PCIe x8 link, the bandwidth length is 8, while in a PCIe x4 link, the bandwidth length is 4. This parameter directly affects server performance and resource utilization efficiency, and is crucial for the system to flexibly switch between different configurations.

[0141] Besides bandwidth splitting, port status (enabled or disabled) also affects link resource allocation. For example, in x8 mode, all RPs (Root Ports) may be enabled, while in x2x2x4 mode, only RP4, RP5, and RP6 are enabled, and the remaining RPs are disabled. This difference ensures that the system can adjust PCIe link resource allocation according to specific needs, optimizing server performance.

[0142] By ensuring the consistency of key parameters across each configuration table in the link configuration table set, a high degree of flexibility in server hardware configuration and precise resource allocation are achieved. This mechanism can accurately identify and adapt to different hardware layout requirements, thereby quickly loading the most suitable link configuration information upon server startup, optimizing data transmission efficiency, improving server performance and operational stability, while reducing the time and cost required to maintain complex hardware configurations.

[0143] As described in the above embodiments, the reason why multiple link configuration information in multiple link configuration tables can be generated is because the 20 lane links supported by the CPU are all multiplexed signal links. This allows the same transmission link to support different types of hardware components, such as serial interface hard drives, solid-state drives, graphics processors, and modular network devices, depending on different motherboard configurations.

[0144] For ease of understanding, the following specific embodiments of signal multiplexing are also provided in the embodiments of this application.

[0145] Example 1: Assume that the first link configuration table in the link configuration table set matches the first motherboard configuration. In the first link configuration table, the first group of links among the actual number of transmission links supported by the central processing unit is set as high-speed serial differential signal links, and the second group of links is set as universal serial bus links. In this case, a first part of the links in the first group are set as storage device interface links in a link configuration table in the link configuration table set that is different from the first link configuration table, or a second part of the links in the first group are set as hard disk drive links in a link configuration table in the link configuration table set that is different from the first link configuration table.

[0146] Combination Figure 5 As shown, it is assumed that the first group of links in the 20 lane links currently supported by the CPU is pre-configured as high-speed serial differential signal links, i.e. PCIe links, and the second group of links is pre-configured as universal serial bus links, i.e. USB links.

[0147] The first set of links may be, but is not limited to, as follows: Figure 5The first group of links shown consists of 16 lane links numbered 0-7 and 8-15. The second group of links may include, but is not limited to, the four links numbered 16-19.

[0148] Suppose that the first part of the links in the first group of links (such as the lane links numbered 0 to 12) can also be set as SATA links in other link configuration tables besides the first link configuration table, or that the second part of the links in the first group of links (such as the lane links numbered 13 to 16) can also be set as disk drive links, i.e. HDD links, in other link configuration tables besides the first link configuration table.

[0149] Therefore, by multiplexing the signals of the first part of the first group of links mentioned above, we can obtain the following Example 2.

[0150] Example 2: Configure a second link configuration table in the link configuration table set that matches the second motherboard configuration, wherein, in the second link configuration table, the first part of the first group of links in the actual number of transmission links supported by the central processing unit is set as the storage device interface link, and the third part of the first group of links other than the first part of links is set as the high-speed serial differential signal link.

[0151] In particular, Example 2 is obtained by multiplexing and adjusting the first part of the link based on a pre-fixed configuration method in Example 1.

[0152] Similarly, by multiplexing the signals of the second part of the links in the first group of links described above, the following embodiment 3 can be obtained.

[0153] Example 3: Configure a third link configuration table in the link configuration table set that matches the third motherboard configuration, wherein, in the third link configuration table, the second part of the first group of links in the actual number of transmission links supported by the central processing unit is set as the hard disk drive link, and the fourth part of the first group of links other than the second part of the links is set as the high-speed serial differential signal link.

[0154] Among them, Example 3 is obtained by multiplexing and adjusting the second part of the link based on a pre-fixed configuration method in Example 1.

[0155] It should be noted that the above method of multiplexing and adjusting the first or second part of the links in the first group of links is only an example and is not limited thereto.

[0156] In addition to adjusting the signal multiplexing of the first group of links, the first group of links and the second group of links can also be adjusted for multiplexing at the same time, thus obtaining the following embodiment 4.

[0157] Example 4: Configure a fourth link configuration table in the link configuration table set that matches the fourth motherboard configuration, wherein, in the fourth link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the hard disk drive links, and the fifth part of the links in the first group other than the second part is set as the high-speed serial differential signal links; at least some of the links in the second group are set as the storage device interface links, and the target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

[0158] Clearly, at least some of the links in the second group of links mentioned above include some or all of the links in lanes numbered 13 to 16. That is, in the fourth link configuration table, the type of lanes numbered 13 to 15 can be multiplexed from Universal Serial Bus (USB) links to SATA links, or all lanes numbered 13 to 16 can be multiplexed as SATA links. This embodiment does not limit this.

[0159] By pre-fixing the lane link information in the first link configuration table, and based on this fixed configuration method, various link configuration tables as shown in Embodiments 2 to 4 are obtained according to different multiplexing methods. This achieves multiple link configuration tables that can adapt to various motherboard configurations by multiplexing lanes with as few changes as possible under a limited number of lane links.

[0160] In an exemplary embodiment, starting the server based on the link configuration information in the target link configuration table includes: starting a basic input / output system based on the link configuration information in the target link configuration table, wherein the basic input / output system is used to initialize the hardware environment during the server startup process; and starting the server in response to the completion of the startup of the basic input / output system.

[0161] When the server starts, it first determines the link configuration information that is compatible with the server motherboard's hardware layout through a series of mechanisms. Based on this information, the server can accurately locate the target link configuration table in the link configuration table set. For example, if the server detects that the hardware configuration requirement is 4NVME, the system will read the link configuration information in the corresponding configuration table, including details such as the HSIO bus lane allocation, bandwidth splitting, and port enable status. This information will be used to guide the BIOS boot process. The BIOS performs initial configuration of the server's hardware environment based on the information in the target link configuration table, ensuring that all transmission links (such as PCIe, SATA, and USB) are activated with the correct signal type, bandwidth, and port status, laying the foundation for subsequent operating system loading and server functionality.

[0162] After completing the hardware environment initialization, the BIOS system notifies the server's main system (such as the operating system) that its hardware resources are ready and it can begin higher-level boot tasks. At this stage, the server will boot the operating system and execute applications and services based on the BIOS initialization results. For example, after completing BIOS initialization in a 4NVME configuration, the server will enable all necessary PCIe links to ensure uninterrupted high-speed data transmission, supporting applications such as high-performance computing or big data storage. This process seamlessly integrates BIOS initialization and server boot, minimizing boot latency and improving the user's perception of system responsiveness.

[0163] By implementing a refined BIOS initialization process and seamless boot phase coordination, the server can boot quickly and accurately under different hardware configurations, ensuring efficient resource utilization and stable system operation, and providing users with an efficient and reliable server boot experience. This approach not only improves server boot speed but also enhances its adaptability to changing hardware environments, reduces maintenance costs, and improves overall system performance.

[0164] In an exemplary embodiment, after searching for a target link configuration table that matches the target motherboard configuration in the link configuration table set, the above method further includes at least one of the following: writing the target link configuration information back to the management engine of the server; and updating the target link configuration information in the management engine.

[0165] After matching the target link configuration information corresponding to the current server motherboard configuration according to the method in the above embodiments, the target link configuration information is updated in the startup parameter settings of the hardware control platform. Simultaneously, the target hardware configuration information can also be updated and written back to the ME. When the update is complete, the server will start according to the target hardware configuration information upon subsequent startup.

[0166] During server startup, the BIOS system loads and applies the corresponding target link configuration table based on the detected hardware configuration information. To ensure that the management engine can continuously monitor and maintain the correct link status during server operation, the system needs to write back the currently effective target link configuration information to the ME. For example, assuming the server's current hardware configuration is 4NVME, after completing hardware initialization, the BIOS will write back detailed information about the HSIO bus: Lanes 0-7 are configured as PCIe links, Lanes 8-9 are configured for PCIe network card devices, Lanes 10-11 are configured for the BMC management chip, Lanes 12-13 are configured as SATA interfaces, and Lanes 14-15 are set to unused status. This allows the ME to keep track of the latest link configuration status in real time and make adjustments or diagnose faults when necessary.

[0167] During server operation, hardware configuration changes may occur, such as plugging or unplugging PCIe devices or adjusting the usage requirements of SATA or USB interfaces. To ensure that these changes are reflected and processed in a timely manner at the system level, the server triggers the BIOS to reread and confirm the latest hardware configuration requirements, update the target link configuration table, and then write the updated link configuration information back to the ME, achieving real-time synchronization of link configuration information.

[0168] By employing the above methods, it is ensured that the server can maintain accurate control and timely adjustments to the link status throughout its entire lifecycle, in the face of changing hardware environments. This enhances the server's stability and responsiveness, reduces maintenance costs, and improves overall system performance.

[0169] In an exemplary embodiment, the above method further includes at least one of the following: after the server starts up, writing back or updating the target link configuration information to the management engine; after restarting the server, writing back or updating the target link configuration information to the management engine.

[0170] This embodiment further refines the strategy for managing link configuration information during the server startup and restart process, particularly emphasizing the importance of writing back or updating the determined target link configuration information to the management engine after the server completes one startup or restart. This ensures that the server can accurately maintain the correct link configuration state regardless of whether it is the initial startup or after a restart, thereby guaranteeing efficient data transmission and stable system operation.

[0171] This is because once the server completes the boot process, the BIOS has initialized all necessary links based on the hardware configuration information and confirmed key parameters such as link bandwidth, signal type, and port enable status. To ensure the management engine continuously tracks and manages this information, after booting, the system writes the target link configuration information back to the management engine, updating its internal configuration data.

[0172] After a server reboot, to quickly restore the system to its correct operating state, the system will re-execute the BIOS hardware initialization process, reload the target link configuration table, and write back or update the latest configuration information to the ME. For example, if the server reboots after a hardware upgrade, the BIOS will re-detect the hardware configuration changes. If the HSIO bus lane originally used for SATA is now allocated to PCIe devices, then during the reboot process, these changed link configuration information will be synchronized to the ME, ensuring that the server can immediately adapt to the new hardware layout after rebooting, maintaining high performance and stability.

[0173] By adopting the above approach, not only can the server flexibly adjust the link configuration in a changing hardware environment, but the real-time monitoring and management capabilities of the management engine are also enhanced, reducing the risk of system instability caused by hardware changes and improving the server's response speed and overall performance.

[0174] In an exemplary embodiment, after updating the target link configuration information to the management engine, the method further includes: starting the server by loading the target link configuration information from the management engine.

[0175] In other words, if the target hardware configuration information is consistent with the default hardware configuration information, the server can be started by directly loading the default link configuration information.

[0176] Specifically, the system determines whether the current server motherboard's hardware configuration is consistent with the system's default hardware configuration by reading CPU model information and GPIO status values.

[0177] If the two match, the system does not need to go through a complex dynamic configuration lookup and loading process. Instead, it directly reads the pre-saved default link configuration information from the server's management engine (ME). This means that if the current hardware layout matches the system's preset default hardware layout, no additional calculations or searches are needed; the default link configuration information in the ME can be loaded directly, thus solving the problems of computing resources and time.

[0178] It is easy to understand that if the hardware configuration of the current server motherboard is consistent with the system's default hardware configuration, the method in the above embodiments can also be referred to, and the default link configuration information can be found from the link configuration table set according to the mapping relationship between the current server motherboard configuration and the link configuration table.

[0179] In other words, if the default link configuration information corresponding to the default link configuration information is also pre-saved in the link configuration table set, you can choose to either directly load the default link configuration information in the ME or search for the default link configuration information from the link configuration table set according to the motherboard configuration.

[0180] For example, for a 4NVME configuration, the system loads the corresponding HSIO bus lane settings, including allocating HSIO[7:0] to the PCIe link and controlling it through the C0 controller, while setting HSIO[13:12] to SATA mode, and setting non-SATA lanes to non-SATA mode accordingly, ensuring that each lane is correctly initialized to the predetermined signal type. In addition, the system will automatically adjust the bandwidth allocation of the PCIe link, port enable status, and other hardware interface settings according to the default configuration to complete the server startup preparation.

[0181] By quickly retrieving and loading default link configuration information directly from the management engine, the server startup process is accelerated. This avoids redundant dynamic configuration lookups and loading when hardware configurations remain unchanged, reducing the computational burden and latency during the startup phase.

[0182] In an exemplary embodiment, after starting the server based on the link configuration information in the target link configuration table, the method further includes: controlling the server to enter a shutdown state; adjusting the state value of the pins of the general-purpose input / output interface by performing a jump cap operation on the pins of the input / output interface to obtain the adjusted pin state value; and updating the mapping relationship between the adjusted pin state value, the motherboard configuration of the server motherboard, and the link configuration table in the link configuration table set.

[0183] In this embodiment, the status values ​​of the configured GPIO pins can be adjusted, but are not limited to, by adjusting the correspondence between the board identifier and the motherboard configuration of the server motherboard through jumper pins.

[0184] Furthermore, only after the server enters a shutdown state can maintenance personnel adjust the status values ​​of GPIO pins using physical jumper caps to match new hardware configuration information. Jumper cap operation is a simple and effective hardware setting method. By inserting or removing jumpers between specific pins, the state of GPIO pins can be changed, thereby indirectly affecting the server's link configuration strategy. For example, by using jumper cap operation, the combined state of GPIO0 and GPIO1 can be adjusted from 0x00 to 0x01, thus instructing the server to switch Lane 12-Lane 13 of the HSIO bus from SATA mode to PCIe mode to meet higher performance computing requirements.

[0185] When the server restarts, the BIOS rereads the modified GPIO status values ​​during the PEI phase, loads the matching link configuration information, and realizes the reallocation and optimization of hardware resources.

[0186] In other words, by physically adjusting the GPIO pin states while the server is powered off, and combining this with the automatic loading of configuration information by the BIOS when the server restarts, a complete dynamic hardware configuration adjustment mechanism is formed, providing powerful support for the server in complex and ever-changing business environments.

[0187] The above processing method greatly facilitates on-site server maintenance and configuration adjustment. It eliminates the need for complex physical disassembly and assembly operations, and the link configuration can be changed simply by adjusting the jumper cap, thereby improving the flexibility and efficiency of server maintenance.

[0188] As described in the above embodiments, after adjusting the GPIO state by using jumper caps, the system will automatically update the mapping relationship between the adjusted pin state value and the server motherboard configuration, and synchronously update the link configuration table set to ensure that all relevant components can recognize and apply the latest configuration information.

[0189] For example, when the status values ​​of GPIO0 and GPIO1 change to 0x11, the system establishes a mapping between the board identifier 0x11 and the motherboard configuration of GPU+OCP, and updates the allocation of the HSIO bus lane in the link configuration table. For example, HSIO[7:0] is adjusted from the default SATAx4 and PCIEx4 mode to the PCIEx8 mode that supports GPU and OCP to adapt to the new hardware layout.

[0190] The system automatically detects changes in the GPIO pin status and updates the mapping relationship between the related motherboard configuration and link configuration table to ensure the synchronization of configuration information.

[0191] When the server restarts, the BIOS loads the updated mapping relationship and initializes hardware resources based on the latest link configuration information to optimize server performance.

[0192] By dynamically adjusting the GPIO pin status values ​​and their mapping relationship with the motherboard configuration and link configuration tables, real-time synchronization and optimization of server hardware configuration information are achieved. This enhances the server's adaptability to hardware changes, reduces startup latency caused by configuration updates, and improves operational efficiency.

[0193] At the same time, it ensures that the software's understanding of hardware resources is consistent with the actual state, avoiding system instability and data transmission anomalies that may be caused by configuration errors, and improving the overall performance and reliability of the server.

[0194] In an exemplary embodiment, before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: determining multiple motherboard configurations of the server motherboard based on the server's hardware architecture; and creating a set of link configuration tables that match the multiple motherboard configurations.

[0195] Server hardware architecture analysis is a fundamental task. By studying the server hardware architecture, we can identify a variety of possible hardware configurations for the server motherboard. Each hardware configuration corresponds to a different device layout and HSIO bus lane usage strategy.

[0196] For example, suppose the current server hardware architecture allows for three different motherboard configurations: the first configuration emphasizes high-speed data processing, equipped with more PCIe links and a high-end GPU; the second configuration is geared towards storage-intensive applications, with more SATA and NVMe interfaces; and the third configuration is cost-effective, focusing on balancing computing and storage resources. Through detailed hardware layout and resource requirement analysis, the HSIO bus lane configuration requirements for each hardware layout were determined, providing a reference for the subsequent creation of the link configuration table.

[0197] After determining multiple configurations of the server motherboard, a dedicated link configuration table can be created for each motherboard configuration, but is not limited to. These configuration tables contain detailed HSIO bus lane configuration information, including the lane's multiplexed signal type (such as PCI, SATA, USB), bandwidth allocation (such as PCIe x8, x4 x4, x2 x2 x2 x2, etc.), and port enable status.

[0198] For example, for high-speed computing motherboards, the link configuration table will prioritize the efficient use of PCIe links, potentially allocating all HSIO[7:0] lanes to two PCIe x8 link controllers. Storage motherboards, on the other hand, may allocate some lanes to SATA or NVMe to enhance storage capacity. By constructing such a comprehensive set of link configuration tables, servers can flexibly switch between different motherboard configurations to adapt to diverse business scenarios and performance requirements.

[0199] By analyzing the server's hardware architecture, multiple configurations of the server motherboard were identified, and a set of matching link configuration tables was pre-created for each configuration. This strategy enhances the server's adaptability to diverse hardware configurations, enabling the server to flexibly adjust the allocation and use of the HSIO bus lanes across different motherboard configurations based on their respective characteristics and requirements, without recompiling the BIOS image. Simultaneously, by pre-planning the link configurations, the server can quickly load the correct link configuration information at startup, shortening initialization time, improving system response speed and resource utilization efficiency, and ensuring stable and efficient operation when facing complex and ever-changing business scenarios.

[0200] In an exemplary embodiment, before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: setting default link configuration information in the server's management engine in advance based on the server's hardware architecture, wherein the default link configuration information includes the signal type and bandwidth information of each transmission link.

[0201] In this embodiment, before the server starts, the default link configuration information can be set in the management engine ME in the following ways, but not limited to:

[0202] (1) Configure the lane links of HSIO according to the hardware design diagram, and configure the lane links of HSI0 bus according to the design of the EE engineer. For example, HSIO bus Lane0-lane11 is set as PCI link, Lane12 is set as SATA link, Lane16 is set as USB link interface, and other unused lanes are set as Unused. Unused lanes of HSIO bus can be planned in advance.

[0203] (2) After the HSIO bus of the SATA link interface is set to SATA mode, Lane 16 needs to be assigned as the SATA bus, and the HSIO link of the non-SATA bus can be assigned as the non-SATA link. At the same time, Lane 0-lane 15 of the HSIO bus that is assigned the PCI link should be set according to the bandwidth of the PCI link. Lane 0-lane 7 is the first controller and the bandwidth is x8, that is, RP0 is set to enable, RP1-RP3 is set to disable, and Lane 8-lane 15 is the second controller and needs to be split into x2x2x2x2 or x2x2x4 mode. At this time, the status of RP4-RP7 is RP4 and RP5 enabled, and the status of RP6 and RP7 is set to disable or RP6 is set to disable.

[0204] At this point, all the above link configuration information has been set in ME and identified as a default link configuration information supported by the CPU model.

[0205] As can be seen from the description in the above embodiments, the default link configuration information can be, but is not limited to, directly loading the default link configuration information in ME to start the BIOS when the hardware configuration of the current server motherboard is determined to be the default hardware configuration based on the GPIO pin status.

[0206] By pre-setting default link configuration information in the management engine, the server startup process is accelerated and the link configuration is made available instantly. This mechanism allows the server to begin initializing the signal types and bandwidth allocation of the HSIO bus lane before reading the CPU model, reducing startup latency and improving system response speed.

[0207] In one exemplary embodiment, the method further includes: performing a crash procedure on the server if the motherboard configuration of the server motherboard is not identified based on the pin status of the general-purpose input / output interface.

[0208] Upon receiving the server boot command, the BIOS reads a set of preset GPIO states during the PEI stage. These GPIO state values ​​correspond to the server motherboard configuration. For example, the combination of high and low levels on the GPIO pins determines the board identifier as 0x00, indicating a default configuration supporting 4NVMe. Similarly, each GPIO state combination corresponds to a specific motherboard configuration, thus enabling automatic identification of the server motherboard.

[0209] The system determines whether the motherboard configuration is supported by the CPU model based on the GPIO pin status. If it is, the system loads the default link configuration information directly from the ME or searches for the target link configuration table from the link configuration table set, as described in the above embodiments. However, if it is not (e.g., the motherboard configuration is not recognized), the system performs a crash procedure on the BIOS in the server, which in turn crashes the server.

[0210] If the BIOS fails to identify the corresponding motherboard configuration through GPIO status during server startup, it means that the current server motherboard configuration number may not be supported by the CPU, or its hardware configuration may be outside the expected range. In this case, the server will immediately execute a crash procedure, terminating the startup process to prevent potential system instability or security risks from subsequent operations.

[0211] Downtime handling is a protective measure that prevents the server from starting up when the correctness of the server motherboard's hardware configuration is uncertain, thus ensuring the consistency and security of the server hardware.

[0212] By employing a motherboard configuration identification and crash handling mechanism based on GPIO status during the server startup phase, the hardware security and system stability of the server are enhanced. This ensures the consistency and predictability of server hardware configuration, avoiding system failures and potential security risks caused by hardware incompatibility or configuration errors.

[0213] To facilitate understanding, the following will be combined with... Figure 6 The overall flowchart shown further describes the server startup method described above.

[0214] S602, responding to the server startup command.

[0215] S604, the BIOS system enters the PEI stage.

[0216] This means entering the hardware initialization phase.

[0217] S606, the BIOS reads the CPU model and obtains the number of HSIO bus lanes.

[0218] The number of HSIO bus lanes supported by different CPU models may be the same or different.

[0219] S608, is the number of lanes on the HSIO bus consistent with the number of lanes set in the HSIO bus in ME?

[0220] If they match, the HSIO bus lane settings in the ME are loaded directly, which means the default link configuration information in the ME is loaded directly. Otherwise, step S610 is executed.

[0221] It should be noted that before executing step S602, the default link configuration information is set in the ME by executing the following steps S601-1 to S601-4.

[0222] S601-1, HSIO bus multiplexing signals set the actual enable signals, such as SATA, PCI, USB, and unused PCI links are set to Unused state.

[0223] For S601-2, the HSIO bus settings require that the lanes for SATA interfaces be assigned as SATA lanes, and the lanes for non-SATA interfaces be assigned as non-SATA lanes.

[0224] S601-3 enables the two x8 bandwidth controllers for lanes 0-15 of the HSIO bus.

[0225] S601-4, according to the hardware design, configures RP0~RP7 to be split according to x8 bandwidth.

[0226] For example, if x8x2x2x4, then RP0, RP4, RP5, and RP6 will be enabled, while RP1, RP2, RP3, and RP7 will be disabled.

[0227] S610, BIOS finds and reads the number of HSIO bus lanes corresponding to the CPU model.

[0228] S612, BIOS reads GPIO to confirm whether the motherboard configuration is a known motherboard.

[0229] If yes, proceed to step S614; otherwise, proceed to step S624.

[0230] The S614 BIOS reads the configuration GPIO to determine the current hardware configuration information of the server motherboard.

[0231] S616 determines whether the current hardware configuration information determined based on the GPIO pin status is the same as the default hardware configuration information indicated by board identifier 0x00.

[0232] If yes, proceed to step S626; otherwise, proceed to step S618.

[0233] After confirming the corresponding configuration information, the S618 will set the number of HSIO bus lanes, bandwidth splitting status, HSIO link settings, SATA link settings, bandwidth splitting port enable / disable settings, bandwidth length settings, etc.

[0234] Specifically, if it is determined that the current server motherboard's hardware configuration is not the default hardware configuration, the target link configuration table that matches the current hardware configuration is found from the link configuration table.

[0235] S620 updates the current configuration information to the management engine settings.

[0236] S622, the BIOS system boots up according to the confirmed configuration information.

[0237] S624, BIOS executes crash handling.

[0238] S626: If the server motherboard has the default hardware configuration, it will directly execute the default link configuration information in ME to start the BIOS.

[0239] As another alternative embodiment, combined with Figure 7 The swimlane diagram shown further explains the server startup method described above. It describes the interaction flow between different execution entities, categorized by their respective execution roles.

[0240] (1) Server

[0241] Server startup: After the server hardware detects the startup signal, it activates the startup process to prepare for subsequent BIOS and ME interactions.

[0242] (2) Management Engine (ME)

[0243] Load HSIO bus Lane settings in the management engine: When the server starts, ME reads the default HSIO configuration and initializes the HSIO bus, including setting lane signal multiplexing (such as PCIe, SATA, USB) and the Unused state of unused lanes.

[0244] HSIO Configuration Adjustment: Based on the dynamic configuration information transmitted by the BIOS, ME updates the configuration parameters of the HSIO bus, such as SATA port allocation, PCIe link bandwidth splitting, and port enabling.

[0245] (3) BIOS system

[0246] Entering the PEI stage: When the server starts, the BIOS enters the PEI (Pre-Initialization) stage to begin preliminary detection of the CPU and hardware resources.

[0247] Read CPU model and obtain HSIO bus lane number: The BIOS reads the CPU model and confirms the number of HSIO bus lanes supported by the CPU, which is the basis for dynamic configuration of PCI links.

[0248] HSIO Quantity Consistency Verification: The BIOS verifies whether the number of HSIO bus lanes matches the number of HSIO bus lanes configured in the ME. If they match, the system will continue booting according to the default configuration; if they do not match, the BIOS will query the actual number of HSIOs supported by the CPU.

[0249] GPIO read confirmation of motherboard configuration: The BIOS first confirms whether the motherboard configuration matches the supported configuration by reading the GPIO status. If they match, it continues to read the GPIO to obtain specific hardware configuration information (hardware type and hardware layout); if they do not match, it performs a crash to ensure hardware safety.

[0250] Dynamically load configuration information: If the BIOS determines that the current server's hardware configuration is not the default hardware configuration based on the configuration information read from GPIO, it will search for and dynamically load the HSIO bus lane settings contained in the target link configuration table from the link configuration table set according to the server motherboard configuration. This includes dynamic configurations such as the number of lanes, bandwidth allocation, and port enable status.

[0251] Update platform boot parameters: The BIOS updates the dynamically loaded configuration information to the platform boot parameters to ensure that the server initializes and starts according to the confirmed configuration.

[0252] Configuration information is synchronized to ME: The BIOS can selectively update the confirmed configuration information to ME, overwriting the original configuration and achieving dynamic adjustment.

[0253] The core of this technical solution lies in the following: The default hardware configuration and default link configuration information of the server motherboard are initially configured in the BIOS ME configuration file. During server startup, when the BIOS enters the PEI stage, it reads a preset set of GPIO signals to confirm whether the motherboard configuration meets expectations. If it does not meet expectations, the BIOS is crashed. Simultaneously, the number of HSIO bus lanes is confirmed, and the actual link configuration information required by the current server motherboard and CPU model is confirmed by reading another set of GPIO signals. The final target link configuration information is then confirmed through GPIO signals, and different HSIO settings are loaded. The HSIO settings can dynamically adjust the CPU's HSIO bus lane multiplexing signals, supported lanes, SATA ports, USB ports, PCI ports, and PCI link bandwidth splitting. This eliminates the need to individually configure the ME configuration information for each link configuration corresponding to diverse hardware configurations, and to perform recompile and flashing operations. In other words, by maximizing the settings, it can achieve backward compatibility with multiple sub-configurations without updating the BIOS image. The HSIO bus lane settings and usage can be dynamically adjusted via GPIO jumpers, and the motherboard ID can be verified via GPIO, ensuring the server's security, reliability, and stability.

[0254] The BIOS image was initially adapted to maximize the motherboard's hardware configuration by configuring the HSIO bus lane multiplexing signals for interfaces such as SATA, USB, and PCI, as well as the bandwidth allocation and port enable settings for PCI ports. This adaptation result was then set in the ME (Memory Management) module and compiled into the BIOS image. However, when multiple hardware configurations were present, the ME configuration needed to be re-adapted and recompiled, resulting in excessive time, manpower, and resources. To address this, multiple configuration tables for HSIO bus lane multiplexing settings were added to the BIOS code. Different HSIO bus lane settings were dynamically loaded, eliminating the need to modify the ME configuration or adjust motherboard hardware settings. Only GPIO or other methods were required to confirm the necessary configuration information. This reduced the number of HSIO bus lane settings and allowed for adjustments to HSIO bus lane signal multiplexing, PCI link bandwidth allocation, and port enable settings. Furthermore, the introduction of GPIO ensured a one-to-one support relationship between the current BIOS image and the motherboard, preventing technical issues caused by incompatibility with the server motherboard. Additionally, a crash handling mechanism was implemented for motherboard configuration incompatibility, improving motherboard utilization efficiency.

[0255] This application's technical solution boasts strong replicability and scalability. By pre-configuring the actual usage of the motherboard's HSIO bus in the BIOS ME, when the server boots, the BIOS checks the motherboard's GPIO combinations during the PEI stage to see if they support the current motherboard. If not, a crash occurs; if supported, the BIOS retrieves the GPIO signal values ​​corresponding to the server motherboard's hardware configuration. GPIO signal values ​​can be controlled via physical jumpers. After confirming the link configuration information by reading the GPIO settings, the BIOS loads the corresponding HSIO parameter settings according to the BIOS link configuration information. At this point, based on the hardware design, some ports can be disabled or enabled, such as PCI bandwidth allocation, enabling or disabling PCI ports, enabling or disabling SATA interfaces, and enabling or disabling USB ports. Furthermore, a single BIOS configuration can dynamically support multiple motherboard configurations without requiring adjustments to the motherboard design or hardware disassembly. A single BIOS image can also be extended to support different configurations on different motherboards, offering convenience and speed without requiring maintenance personnel to physically disassemble and modify the motherboards in the data center. In summary, adopting the technical solution of this application can improve the security and reliability of the server motherboard, as well as the CPU's utilization efficiency and cost-effectiveness.

[0256] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0257] According to another aspect of the embodiments of this application, a server startup device is also provided, the structural schematic diagram of which is shown below. Figure 8 As shown, the system includes the following modules: a control unit 802, used to control the server's basic input / output system to enter the hardware initialization phase in response to a server startup command; a first processing unit 804, used to determine the target motherboard configuration of the server motherboard based on the pin status of the general-purpose input / output interface, wherein the target motherboard configuration includes the type of hardware components, the type of hardware components including at least one of serial interface hard disk, solid-state hard disk, graphics processor, and modular network device; a first lookup unit 806, used to look up a target link configuration table matching the target motherboard configuration from a link configuration table set, wherein the link configuration table set describes link configuration information matching different motherboard configurations obtained by signal multiplexing of the actual number of transmission links supported by the central processing unit; and a startup unit 808, used to start the server based on the link configuration information in the target link configuration table.

[0258] The specific execution steps involved in the various calculation processes, service configurations, and anomaly warnings in the above modules can be referred to the descriptions in the above embodiments, and will not be repeated here.

[0259] Obviously, the server startup apparatus described above can be used to implement the server startup method provided in the above embodiments, and details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0260] It should be noted that the control unit 802 in this embodiment can be used to execute the above step S202, the first processing unit 804 in this embodiment can be used to execute the above step S204, the second search unit 806 in this embodiment can be used to execute the above step S206, and the startup unit 808 in this embodiment can be used to execute the above step S208.

[0261] In an exemplary embodiment, the first processing unit 804 includes: a first processing module, configured to determine the board identifier of the server motherboard based on the pin status of the general input / output interface, wherein there is a mapping relationship between the motherboard configuration of the server motherboard, the board identifier, and the link configuration table in the link configuration table set; and a second processing module, configured to determine the target motherboard configuration of the server motherboard based on the board identifier.

[0262] In an exemplary embodiment, the first processing module includes: a first reading submodule for reading a first state value of a first pin in the general-purpose input / output interface; a second reading submodule for reading a second state value of a second pin in the general-purpose input / output interface; and a first processing submodule for determining the board identifier of the server motherboard based on the first state value and the second state value.

[0263] In one exemplary embodiment, the apparatus further includes: a reading unit, configured to read the processor model of the central processing unit before determining the target motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface; a second processing unit, configured to determine the actual number of transmission links of the data transmission bus supported by the central processing unit based on the processor model; and a third processing unit, configured to determine the motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface if the actual number is inconsistent with the preset number of transmission links set in the server's management engine.

[0264] In an exemplary embodiment, the first lookup unit 806 includes: a comparison module, configured to compare the target hardware configuration information indicated by the target motherboard configuration with the default hardware configuration information to obtain a target comparison result; and a first lookup module, configured to, when the target comparison result indicates that the target hardware configuration information and the default hardware configuration information are inconsistent, search the link configuration table set for a target link configuration table that matches the target motherboard configuration.

[0265] In an exemplary embodiment, the first lookup module includes: a third reading submodule for reading a third state value of a third pin in a general-purpose input / output interface; a fourth reading submodule for reading a fourth state value of a fourth pin in the general-purpose input / output interface; a second processing submodule for determining the configuration table identifier of each link configuration table in the link configuration table set based on the third state value and the fourth state value; a third processing submodule for searching for a target configuration table identifier that matches the target board identifier from the configuration table identifiers based on the target board identifier corresponding to the target motherboard configuration; and a first lookup submodule for finding the target link configuration table from the link configuration table set based on the target configuration table identifier, wherein there is a mapping relationship between the target motherboard configuration, the target board identifier, and the link configuration tables in the link configuration table set, and there is a one-to-one correspondence between the target configuration table identifier and the target link configuration table.

[0266] In an exemplary embodiment, the above apparatus further includes: at least one parameter among the multiple parameters contained in any two link configuration tables in the link configuration table set has a different value: the number of transmission links of the data transmission bus, bandwidth splitting information, configuration information of the transmission links, bandwidth length, and status information of the bandwidth splitting port.

[0267] In an exemplary embodiment, the above apparatus further includes: a first configuration unit, configured to configure a first link configuration table in the link configuration table set that matches the first motherboard configuration, wherein in the first link configuration table, a first group of links among the actual number of transmission links supported by the central processing unit is configured as high-speed serial differential signal links and a second group of links is configured as universal serial bus links; wherein a first portion of the links in the first group are configured as storage device interface links in a link configuration table in the link configuration table set that is different from the first link configuration table, or a second portion of the links in the first group are configured as hard disk drive links in a link configuration table in the link configuration table set that is different from the first link configuration table.

[0268] In an exemplary embodiment, the above apparatus further includes: a second configuration unit, configured to configure a second link configuration table in the link configuration table set that matches the second motherboard configuration, wherein in the second link configuration table, the first part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the storage device interface link, and the third part of the links in the first group of links other than the first part of the links is set as the high-speed serial differential signal link.

[0269] In an exemplary embodiment, the above apparatus further includes: a third configuration unit, configured to configure a third link configuration table in the link configuration table set that matches a third motherboard configuration, wherein in the third link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is configured as the hard disk drive links, and the fourth part of the links in the first group of links other than the second part of the links is configured as the high-speed serial differential signal links.

[0270] In one exemplary embodiment, the above apparatus further includes: a fourth configuration unit, configured to configure a fourth link configuration table in the link configuration table set that matches a fourth motherboard configuration, wherein in the fourth link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is configured as the hard disk drive links, and the fifth part of the links in the first group of links other than the second part is configured as the high-speed serial differential signal links; at least some of the links in the second group of links are configured as the storage device interface links, and the target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

[0271] In one exemplary embodiment, the above apparatus further includes: a fourth processing unit, configured to, after searching for a target link configuration table that matches the target motherboard configuration in the set of link configuration tables, perform at least one of the following: write the target link configuration information back to the management engine of the server; update the target link configuration information to the management engine.

[0272] In one exemplary embodiment, the above apparatus further includes a fifth processing unit, configured to start the server by loading the target link configuration information in the management engine.

[0273] In one exemplary embodiment, the above apparatus further includes: a sixth processing unit, configured to control the server to enter a shutdown state; an adjustment unit, configured to adjust the state value of the pins of the general-purpose input / output interface by performing a jump cap operation on the pins of the input / output interface to obtain adjusted pin state values; and an update unit, configured to update the mapping relationship between the adjusted pin state values, the motherboard configuration of the server motherboard, and the link configuration table in the link configuration table set.

[0274] In one exemplary embodiment, the apparatus further includes: a seventh processing unit, configured to, before controlling the server's basic input / output system to enter the hardware initialization phase in response to a server startup command, determine multiple motherboard configurations of the server motherboard based on the server's hardware architecture; and create a set of link configuration tables matching the multiple motherboard configurations.

[0275] In one exemplary embodiment, the above apparatus further includes: an eighth processing unit, configured to, before controlling the server's basic input / output system to enter the hardware initialization phase in response to a server's startup command, pre-set default link configuration information in the server's management engine based on the server's hardware architecture, wherein the default link configuration information includes signal type and bandwidth information of each transmission link.

[0276] In one exemplary embodiment, the above apparatus further includes a ninth processing unit, configured to perform a crash procedure on the server if the motherboard configuration of the server motherboard is not identified based on the pin status of the general-purpose input / output interface.

[0277] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0278] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described server startup method embodiments.

[0279] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-described server startup method embodiments when it is run.

[0280] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0281] According to another aspect of the embodiments of this application, a computer program product is also provided, the computer program product including a computer program, which, when executed by a processor, implements the steps in any of the above-described server startup method embodiments.

[0282] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described server startup method embodiments.

[0283] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0284] The above provides a detailed description of a server startup method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server startup method, characterized in that, include: In response to the server's startup command, the server's basic input / output system is controlled to enter the hardware initialization phase; Based on the pin states of the general purpose input / output interface, the target motherboard configuration of the server motherboard is determined, wherein the target motherboard configuration includes the type of hardware components, and the type of hardware components includes at least one of serial interface hard disk, solid-state hard disk, graphics processor and modular network device; The target link configuration table that matches the target motherboard configuration is found in the link configuration table set, wherein the link configuration table set is used to describe the link configuration information that matches different motherboard configurations by signal multiplexing of the actual number of transmission links supported by the central processing unit. The server is started based on the link configuration information in the target link configuration table.

2. The method according to claim 1, characterized in that, The determination of the target motherboard configuration of the server motherboard based on the pin states of the general-purpose input / output interface includes: Based on the pin status of the general input / output interface, the board identifier of the server motherboard is determined, wherein there is a mapping relationship between the motherboard configuration of the server motherboard, the board identifier, and the link configuration table in the link configuration table set; Based on the board identifier, the target motherboard configuration of the server motherboard is determined.

3. The method according to claim 2, characterized in that, The process of determining the board identifier of the server motherboard based on the pin states of the general-purpose input / output interface includes: Read the first state value of the first pin in the general-purpose input / output interface; Read the second state value of the second pin in the general-purpose input / output interface; Based on the first status value and the second status value, the board identifier of the server motherboard is determined.

4. The method according to claim 1, characterized in that, Before determining the target motherboard configuration of the server motherboard based on the pin states of the general purpose input / output interface, the method further includes: Read the processor model of the central processing unit; Based on the processor model, determine the actual number of transmission links of the data transmission bus supported by the central processing unit; If the actual number is inconsistent with the preset number of transmission links set in the server's management engine, the motherboard configuration of the server motherboard is determined based on the pin status of the general input / output interface.

5. The method according to claim 1, characterized in that, The step of searching the link configuration table set for the target link configuration table that matches the target motherboard includes: Compare the target hardware configuration information indicated by the target motherboard configuration with the default hardware configuration information to obtain the target comparison result; If the target comparison result indicates that the target hardware configuration information is inconsistent with the default hardware configuration information, the target link configuration table that matches the target motherboard configuration is searched from the link configuration table set.

6. The method according to claim 5, characterized in that, The step of searching the link configuration table set for the target link configuration that matches the target motherboard configuration includes: Read the third state value of the third pin in the general purpose input / output interface; Read the fourth state value of the fourth pin in the general-purpose input / output interface; Based on the third state value and the fourth state value, the configuration table identifier of each link configuration table in the link configuration table set is determined; Based on the target board identifier corresponding to the target motherboard configuration, search for the target configuration table identifier that matches the target board identifier from the configuration table identifiers; Based on the target configuration table identifier, the target link configuration table is found from the link configuration table set. There is a mapping relationship between the target motherboard configuration, the target board identifier, and the link configuration tables in the link configuration table set. The target configuration table identifier and the target link configuration table have a one-to-one correspondence.

7. The method according to claim 5, characterized in that, The method further includes: At least one parameter among the multiple parameters contained in any two link configuration tables in the link configuration table set has a different value: the number of transmission links of the data transmission bus, bandwidth splitting information, configuration information of the transmission links, bandwidth length, and status information of the bandwidth splitting port.

8. The method according to claim 1, characterized in that, The method further includes: Configure a first link configuration table in the link configuration table set that matches the first motherboard configuration, wherein, in the first link configuration table, the first group of links in the actual number of transmission links supported by the central processing unit is set as a high-speed serial differential signal link and the second group of links is set as a universal serial bus link. Specifically, the first part of the links in the first group of links is set as a storage device interface link in a link configuration table that is different from the first link configuration table in the link configuration table set; or, the second part of the links in the first group of links is set as a hard disk drive link in a link configuration table that is different from the first link configuration table in the link configuration table set.

9. The method according to claim 8, characterized in that, The method further includes: Configure a second link configuration table in the link configuration table set that matches the second motherboard configuration, wherein, in the second link configuration table, the first part of the first group of links in the actual number of transmission links supported by the central processing unit is set as the storage device interface link, and the third part of the first group of links other than the first part of links is set as the high-speed serial differential signal link.

10. The method according to claim 8, characterized in that, The method further includes: Configure a third link configuration table in the link configuration table set that matches the third motherboard configuration, wherein in the third link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the hard disk drive links, and the fourth part of the links in the first group other than the second part of the links is set as the high-speed serial differential signal links.

11. The method according to claim 8, characterized in that, The method further includes: Configure a fourth link configuration table in the link configuration table set that matches the fourth motherboard configuration. In the fourth link configuration table, the second part of the links in the first group of the actual number of transmission links supported by the central processing unit is set as the hard disk drive links, and the fifth part of the links in the first group other than the second part is set as the high-speed serial differential signal links. At least some of the links in the second group are set as the storage device interface links. The target link configuration table is one of the first link configuration table, the second link configuration table, the third link configuration table, and the fourth link configuration table.

12. The method according to claim 1, characterized in that, After searching the link configuration table set for a target link configuration that matches the target motherboard configuration, the method further includes at least one of the following: Write the target link configuration information back to the management engine of the server; Update the target link configuration information to the management engine.

13. The method according to claim 12, characterized in that, After updating the target link configuration information to the management engine, the method further includes: The server is started by loading the target link configuration information from the management engine.

14. The method according to claim 1, characterized in that, The method further includes: Control the server to enter a shutdown state; By performing a jumper operation on the pins of the input / output interface, the state values ​​of the pins of the general-purpose input / output interface are adjusted to obtain the adjusted pin state values; Update the mapping relationship between the adjusted pin status values, the motherboard configuration of the server motherboard, and the link configuration table in the link configuration table set.

15. The method according to claim 1, characterized in that, Before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: Based on the server's hardware architecture, determine multiple motherboard configurations for the server's motherboard; Create a set of link configuration tables that match the multiple motherboard configurations.

16. The method according to claim 1, characterized in that, Before controlling the server's basic input / output system to enter the hardware initialization phase in response to the server's startup command, the method further includes: Based on the server's hardware architecture, default link configuration information is pre-set in the server's management engine, wherein the default link configuration information includes the signal type and bandwidth information of each transmission link.

17. The method according to any one of claims 1 to 16, characterized in that, The method further includes: If the motherboard configuration of the server motherboard is not identified based on the pin status of the general input / output interface, the server shall be shut down.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the server startup method as described in any one of claims 1 to 17.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the server startup method as described in any one of claims 1 to 17.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the server startup method as described in any one of claims 1 to 17.

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