Chip performance verification method, system and device and computer storage medium

Abstract

The invention discloses a chip performance verification method, system and device and a computer storage medium, and relates to the technical field of storage. Performance verification scene information for performing performance verification on a Raid chip is acquired; obtaining original chip configuration information corresponding to the performance verification scene information; generating a test model of the Raid chip according to the performance verification scene information and the original chip configuration information; generating target chip configuration information according to the test model; performing chip form construction according to the target chip configuration information to obtain a test chip; and performing performance test on the test chip according to the performance verification scene information to obtain a performance test result. According to the Raid chip performance verification method and device, Raid chip performance verification is advanced to a prototype verification stage from chip firmware adaptation, deeper-level problems of the Raid chip can be found earlier, then the iteration period of hardware is shortened, the modification cost is reduced, and rapid convergence of chip hardware performance is promoted.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a chip performance verification method, system, device and computer storage medium. BACKGROUND

[0002] A Raid (Redundant Arrays of Independent Disks) chip is a component for realizing the function of a disk array. The chip improves the performance and reliability of a storage system by managing the data distribution and redundancy check of multiple hard disks. The performance of the Raid chip under different Raid levels and different configurations is an index of the chip. Therefore, the performance of the Raid chip needs to be detected. For example, the FIO (Flexible I / O Tester) tool can be used to detect the performance of the Raid chip, such as IOPS (Input / Output Operations Per Second) and bandwidth.

[0003] However, the adaptation of the NVME device driver relied on by the FIO tool requires the Raid chip to have complete firmware to support the driver loading behavior. Therefore, the chip firmware adaptation is usually performed after the completion of the chip firmware adaptation, and the subsequent performance verification cannot be performed. The chip firmware adaptation is in the late stage of the chip design process. If hardware problems are found at this time, the design modification will have the technical bottleneck of long iteration period and high cost, and complex hardware problems in multiple dimensions may occur.

[0004] To sum up, how to promote the rapid convergence of the hardware performance of the Raid chip is a problem to be solved by the technical personnel in the field. SUMMARY

[0005] The purpose of the present application is to provide a chip performance verification method which can solve the technical problem of how to promote the rapid convergence of the hardware performance of the Raid chip to some extent. The present application also provides a chip performance verification system, an electronic device and a computer readable storage medium.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] A chip performance verification method comprises the following steps:

[0008] obtaining performance verification scene information for verifying the performance of a Raid chip;

[0009] obtaining original chip configuration information corresponding to the performance verification scene information;

[0010] According to the performance verification scene information and the original chip configuration information, a test model of the Raid chip is generated;

[0011] According to the test model, target chip configuration information is generated;

[0012] According to the target chip configuration information, a chip form is constructed to obtain a test chip;

[0013] According to the performance verification scene information, performance testing is performed on the test chip to obtain a performance test result.

[0014] In an example embodiment, the original chip configuration information corresponding to the performance verification scene information is obtained, including:

[0015] The original chip configuration information corresponding to the performance verification scene information is obtained, and the original chip configuration information includes a Raid level, a number of disks, a storage unit size value, a number of strips, and a fixed parameter;

[0016] According to the performance verification scene information and the original chip configuration information, the test model of the Raid chip is generated, including:

[0017] The total number of disks mounted by the Raid chip is determined;

[0018] The maximum number of namespaces supported by the Raid chip is determined;

[0019] All performance verification scene information corresponding to each type of original chip configuration information is counted;

[0020] The original chip configuration information is combined by type to obtain a test model with a number of disks less than or equal to the total number of disks and a number of namespaces less than or equal to the maximum number of namespaces;

[0021] According to the original chip configuration information combined into the test model, the performance verification scene information corresponding to the test model is determined.

[0022] In an example embodiment, the target chip configuration information is generated according to the test model, including:

[0023] According to the test model, target chip configuration information is generated, and the target chip configuration information includes a Raid level, a number of disks, a storage unit size value, a namespace size value, a number of namespaces, a fixed parameter, and a block size value. The namespace size value includes the product value of the number of disks, the storage unit size value, and the number of strips in the test model.

[0024] In the example embodiment, the chip form construction according to the target chip configuration information obtains a test chip, including:

[0025] The chip form construction according to the Raid level, the number of disks, the storage unit size value, the fixed parameter and the block size value in the target chip configuration information obtains a test chip;

[0026] According to the number of namespaces and the fixed parameter in the target chip configuration information, the controller data structure of the test chip is constructed;

[0027] According to the number of namespaces in the target chip configuration information, the available namespace list of the test chip is constructed;

[0028] According to the namespace size value and the block size value in the target chip configuration information, the namespace data structure of the test chip is constructed.

[0029] In the example embodiment, the performance test of the test chip according to the performance verification scenario information obtains a performance test result, including:

[0030] Load a test driver;

[0031] In the test model, a test model is selected;

[0032] In the performance verification scenario information corresponding to the selected test model, performance verification scenario information is selected;

[0033] Based on the test driver, a test command corresponding to the selected performance verification scenario information is run to perform performance test on the test chip;

[0034] The IOPS value and the BW value of the test chip under the selected performance verification scenario information are collected;

[0035] The IOPS value and the BW value are taken as the performance test result of the test chip under the selected performance verification scenario information.

[0036] In the example embodiment, after the performance test result of the test chip under the selected performance verification scenario information is collected, it further includes:

[0037] Detect whether all the performance verification scenario information corresponding to the selected test model has been selected;

[0038] In response to not selecting all the performance verification scenario information corresponding to the selected test model, return to execute the step of selecting performance verification scenario information in the performance verification scenario information corresponding to the selected test model;

[0039] in response to selecting all the performance verification scene information corresponding to the selected test model, detecting whether all the test models are selected;

[0040] in response to not selecting all the test models, resetting the test chip and returning to the step of selecting a test model in the test model.

[0041] In an example embodiment, after the performance test on the test chip according to the performance verification scene information to obtain the performance test result, the method further comprises:

[0042] generating a performance index table of the Raid chip according to the performance verification scene information, the original chip configuration information, the test command and the performance test result.

[0043] A chip performance verification system comprises:

[0044] a performance verification information acquisition module configured to acquire performance verification scene information for performance verification of a Raid chip;

[0045] an original configuration information acquisition module configured to acquire original chip configuration information corresponding to the performance verification scene information;

[0046] a test model generation module configured to generate a test model of the Raid chip according to the performance verification scene information and the original chip configuration information;

[0047] a target configuration information generation module configured to generate target chip configuration information according to the test model;

[0048] a chip construction module configured to construct a chip form according to the target chip configuration information to obtain a test chip;

[0049] a performance test module configured to perform a performance test on the test chip according to the performance verification scene information to obtain a performance test result.

[0050] An electronic device comprises:

[0051] a memory configured to store a computer program;

[0052] a processor configured to implement the steps of the chip performance verification method according to any one of the above when executing the computer program.

[0053] A computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the chip performance verification method according to any one of the above.

[0054] The chip performance verification method provided in the application comprises the following steps: obtaining performance verification scene information for verifying the performance of a Raid chip; obtaining original chip configuration information corresponding to the performance verification scene information; generating a test model of the Raid chip according to the performance verification scene information and the original chip configuration information; generating target chip configuration information according to the test model; constructing a chip form according to the target chip configuration information to obtain a test chip; and performing performance testing on the test chip according to the performance verification scene information to obtain a performance testing result. Before the chip form of the Raid chip is constructed, the test model of the Raid chip is generated according to the performance verification scene information of the Raid chip and the corresponding original chip configuration information, the target chip configuration information is generated according to the test model, and then the chip form is constructed according to the target chip configuration information to obtain the test chip, so that the test chip is adapted to the performance verification scene and the chip configuration information of the Raid, thereby advancing the Raid chip performance verification to the prototype verification stage after the chip firmware adaptation is completed, which is beneficial to discovering deeper problems of the Raid chip earlier, thereby reducing the iteration cycle of the hardware and the modification cost, and promoting the rapid convergence of the chip hardware performance. The chip performance verification system, the electronic device and the computer readable storage medium provided in the application also solve the corresponding technical problems. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0056] Figure 1 A flowchart of a chip performance verification method provided in the embodiments of the present application;

[0057] Figure 2 A chip form construction flowchart;

[0058] Figure 3 A verification use case dynamic scheduling mechanism implementation flowchart;

[0059] Figure 4 A flowchart of an actual application chip performance verification method;

[0060] Figure 5 A structural schematic diagram of a chip performance verification system provided in the embodiments of the present application;

[0061] Figure 6 A structural schematic diagram of an electronic device provided in the embodiments of the present application;

[0062] Figure 7 Another structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0064] Please refer to Figure 1 , Figure 1 A flowchart of a chip performance verification method provided by an embodiment of the present application.

[0065] The chip performance verification method provided by an embodiment of the present application can include the following steps.

[0066] Step S101: Obtain performance verification scene information for performance verification of a Raid chip.

[0067] In actual application, the performance information of the Raid chip in different application scenes is different, so the performance verification of the Raid chip needs to be adapted to the corresponding scene, that is, the performance verification scene information for performance verification of the Raid chip needs to be obtained, so as to subsequently perform performance verification on the Raid chip based on the performance verification scene information. The performance verification scene information refers to the scene in which the performance verification of the Raid chip is performed, which can be flexibly set according to the actual application scene of the Raid chip, such as performance verification scene information in a Raid5.

[0068] Step S102: Obtain original chip configuration information corresponding to the performance verification scene information.

[0069] In actual application, the application of the Raid chip cannot be separated from the corresponding setting, and the settings in different application scenes are different. Therefore, in the process of performing performance verification on the Raid chip based on the performance verification scene information, the original chip configuration information corresponding to the performance verification scene information also needs to be obtained. The original chip configuration information is used to reflect the corresponding configuration of the Raid chip in this performance verification scene information, so as to subsequently perform performance verification on the Raid chip after the corresponding configuration according to the original chip configuration information.

[0070] Step S103: Generate a test model of the Raid chip according to the performance verification scene information and the original chip configuration information.

[0071] In actual application, considering that the performance verification scene information and the original chip configuration information are not absolutely one-to-one corresponding, for example, the original chip configuration information can be applied to multiple performance verification scene information, in other words, only one chip setting is needed to perform multiple performance verifications; and considering that a single performance verification can not be able to completely apply all Raid chips, that is, the Raid chips can be configured in multiple groups and then the chip verification is performed. Therefore, in order to apply the Raid chips to perform multiple performance verifications and perform multiple performance verifications by means of the same configuration, a test model of the Raid chip can be generated according to the performance verification scene information and the original chip configuration information, the test model including the original chip configuration information that can be configured in the Raid chip at a time and the performance verification scene information that can be verified after the Raid chip is configured at a time.

[0072] In the example embodiment, in the process of obtaining the original chip configuration information corresponding to the performance verification scene information, the original chip configuration information corresponding to the performance verification scene information can be obtained, as shown in Table 1, the original chip configuration information can include the Raid level, the number of disks, the storage unit size value (chunck size), the number of strips and the fixed parameter mdts, and the model number is used to distinguish different models; correspondingly, in the process of generating the test model of the Raid chip according to the performance verification scene information and the original chip configuration information, the total number of disks mounted by the Raid chip can be determined, the maximum number of namespaces supported by the Raid chip can be determined, all performance verification scene information corresponding to each type of original chip configuration information can be counted, the original chip configuration information can be combined by type, and the test model with the number of disks less than or equal to the total number of disks and the number of namespaces less than or equal to the maximum number of namespaces can be obtained. Assuming that N original chip configuration information is mapped into one test model, the number of disks required in each model is , the number of different Raid array configurations involved is N, and Less than or equal to the total number of plates, constraint N is less than or equal to the maximum number of namespaces, according to the original chip configuration information combined into the test model, the performance verification scene information corresponding to the test model is determined. In order to facilitate understanding, it is assumed that the original chip configuration information includes original chip configuration information 1, original chip configuration information 2 and original chip configuration information 3, each type of original chip configuration information corresponds to 2 kinds of performance verification scene information, then it is assumed that the original chip configuration information 1 and the original chip configuration information 2 are combined into the test model 1, and the original chip configuration information 3 is combined into the test model 2, then the performance verification scene information corresponding to the original chip configuration information 1 and the original chip configuration information 2 can be verified according to the test model 1 at the same time, only two times according to the test model 1, the verification of all performance verification scene information corresponding to the original chip configuration information 1 and the original chip configuration information 2 can be completed, and the same reason, according to the test model 2, the single performance verification scene information corresponding to the original chip configuration information 3 is verified once, and according to the test model 2, the verification is carried out twice, and the verification of all performance verification scene information corresponding to the original chip configuration information 2 can be completed.

[0073] Table 1 test model summary table

[0074]

[0075] From the implementation process, it can be known that in the process of generating the test model of the Raid chip according to the performance verification scene information and the original chip configuration information, the total number of plates mounted by the Raid chip is determined, and the maximum number of namespaces supported by the Raid chip is determined, so that the total number of plates and the maximum number of namespaces are used as constraint conditions to configure multiple original chip configuration information subsequently; and in the process of generating the test model, all performance verification scene information corresponding to each type of original chip configuration information is counted, and the original chip configuration information is combined according to the type, to obtain a test model with a plate number less than or equal to the total number of plates and a namespace number less than or equal to the maximum number of namespaces, that is, it is necessary to ensure that the plate number consumed by the test model combined by multiple original chip configuration information is less than or equal to the total number of plates, and the namespace number consumed by the test model combined by multiple original chip configuration information is less than or equal to the maximum number of namespaces, so as to ensure that the Raid chip can complete the configuration of multiple original chip configuration information at a time according to the test model, and it is necessary to determine the performance verification scene information corresponding to the test model according to the original chip configuration information combined into the test model, so that the performance verification of multiple performance verification scene information can be performed at a time according to the test model, and the performance verification of multiple groups of performance verification scene information can be performed according to the test model, thereby improving the efficiency of chip performance verification.

[0076] It should be noted that in the process of building a raid group, the physical disk is divided into units (blocks), which are raid stripes, the basic unit of raid data processing. The storage unit corresponding to each disk in the same stripe is a chunk, and the size is chunk size, which is a block. Mdts represents the maximum data transmission size that can be supported between the host and the controller. The IO command reads and writes hard disk data in block as the minimum granularity, and the size of the block can be 4KB or 512B.

[0077] In a specific application scenario, in the process of combining the original chip configuration information by type to obtain a test model with a disk number less than or equal to the total disk number and a namespace number less than or equal to the maximum namespace number, a first record tree can be generated based on the disk number required by all original chip configuration information, and the value of the root node of the first record number is greater than the value of the leaf node; according to the original chip configuration information represented by the node in the first record tree, a second record tree is generated based on the namespace number required by the original chip configuration information; starting from the root node of the latest first record number, a maximum disk number is obtained as a first traversal disk number, and it is detected whether the first traversal disk number is equal to the total disk number, if the first traversal disk number is equal to the total disk number, a single test model is generated according to the single original chip configuration information corresponding to the first traversal disk number, the node with the value equal to the first traversal disk number in the first record tree is deleted, and the node with the same position in the second record tree is deleted; if the first traversal disk number is less than the total disk number, the difference between the total disk number and the first traversal disk number is generated, starting from the root node of the latest first record number, a maximum disk number less than or equal to the difference is obtained as a second traversal disk number, and it is detected whether the sum of the values in the latest second record number at the same position as the first traversal disk number and the second traversal disk number is less than or equal to the maximum namespace number, if so, a test model is generated according to the original chip configuration information corresponding to the first traversal disk number and the second traversal disk number, and the nodes with the values equal to the first traversal disk number and the second traversal disk number in the latest first record tree are deleted, and the nodes with the same position in the latest second record tree are deleted, if not, starting from the root node of the latest first record number, a maximum disk number less than or equal to the second traversal disk number is obtained as the latest second traversal disk number, and the step of detecting whether the sum of the values in the latest second record number at the same position as the first traversal disk number and the second traversal disk number is less than or equal to the maximum namespace number is returned.

[0078] From the implementation process, it can be known that the number of disks in the original chip configuration information is converted into the first record tree of only recording the number of disks, the number of namespaces in the original chip configuration information is converted into the corresponding second record tree according to the node of the first record tree representing the original chip configuration information, so that the related information of the original chip configuration information can be known comprehensively and accurately according to the first record tree and the second record tree; and then only the maximum number of disks is obtained from the root node of the first record tree as the first traversal disk number, so that the test model can be constructed by selecting the disk number closest to the difference between the total disk number and the first traversal disk number based on the first traversal disk number, and the number of namespaces of the test model can be guaranteed to be less than or equal to the maximum number of namespaces by means of the second record number, so that the original chip configuration information can be combined quickly to obtain the test model satisfying the disk number less than or equal to the total disk number and the number of namespaces less than or equal to the maximum number of namespaces.

[0079] Step S104: generating target chip configuration information according to the test model.

[0080] Step S105: constructing the chip form according to the target chip configuration information to obtain a test chip.

[0081] Step S106: performing performance test on the test chip according to the performance verification scene information to obtain a performance test result.

[0082] In actual application, in order to realize the switching of the verification framework of the Raid chip under different performance scenes and ensure that the NVME Controller form construction and the initialization of the chip core logic are consistent, after obtaining the test model, the target chip configuration information can be generated, and the chip form is constructed based on the target chip configuration information, that is, the chip form is constructed according to the target chip configuration information to obtain a test chip, and then the performance test is performed on the test chip according to the performance verification scene information to obtain a performance test result.

[0083] In the example embodiment, considering that the Raid level, the number of disks and the chunck size are fixed parameters provided by the test model under different performance scenes, they are used to represent a kind of Raid array configuration; the namespace size is the number of disks (M i ), the chunck size (C i ) and the number of strips (T i) of the test model, the target chip configuration information includes the raid level, the number of disks, the storage unit size value, the namespace size value, the number of namespaces, the fixed parameters and the block size value, and the namespace size value includes the product of the number of disks, the storage unit size value and the number of strips in the test model. In a specific application scenario, the target chip configuration information can be represented by a table, as shown in Table 2.

[0084] Table 2: Illustration table of target chip configuration information

[0085]

[0086] In a specific application scenario, when the target chip configuration information includes a Raid level, a number of disks, a storage unit size value, a namespace size value, a number of namespaces, a fixed parameter, and a block size value, during the process of constructing a chip form according to the target chip configuration information to obtain a test chip, the chip form can be constructed according to the Raid level, the number of disks, the storage unit size value, the fixed parameter, and the block size value in the target chip configuration information to obtain a test chip. When the target chip configuration information is a table, the Raid level, the number of disks, the chunck size, and other information in the performance verification scene can be extracted based on the target chip configuration table to support the initialization of the core logic of the Raid chip, so that the corresponding form is realized inside the chip. According to the number of namespaces and the fixed parameter in the target chip configuration information, a controller data structure of the test chip is constructed, such as extracting the number of namespaces and mdts in the target chip configuration table based on the NVME1.4 standard protocol to construct the controller data structure, so as to present the maximum number of namespaces and the maximum data transmission size supported by the current chip to the host. According to the number of namespaces in the target chip configuration information, a list of available namespaces of the test chip is constructed to present the active namespaces of the current chip to the host. According to the namespace size value and the block size value in the target chip configuration information, a namespace data structure of the test chip is constructed to represent the attributes of each namespace to the host. On this basis, in order to facilitate the acquisition of the state of the chip to determine whether the chip can be used for performance verification, a chip form construction identifier can also be set after the construction of the namespace data structure of the test chip to represent that the current chip is ready and can trigger the host to initiate the loading of the NVME driver for performance verification, as shown in Figure 2 .

[0087] In the example embodiment, considering that the chip performance verification needs a driver, therefore, in the process of performing performance test on the test chip according to the performance verification scene information, and obtaining the performance test result, a test driver can be loaded, such as an NVME device driver; then in the test model, a test model is selected; in the performance verification scene information corresponding to the selected test model, performance verification scene information is selected; based on the test driver, a test command corresponding to the selected performance verification scene information is run, such as an FIO command, to perform performance test on the test chip; the IOPS value and the BW value of the test chip under the selected performance verification scene information are collected, the IOPS is an index for measuring the performance of a storage device, indicating the number of input / output operations per second that the storage device can complete, and the BW is an index for measuring the data transmission rate of a storage device, which can be represented by the amount of data transmitted per second (such as MB / s or GB / s), and the BW reflects the amount of data that the storage device can process in a unit of time, and is one of the parameters for evaluating storage performance; the IOPS value and the BW value are taken as the performance test result of the test chip under the selected performance verification scene information.

[0088] In a specific application scenario, since a single test model supports verification of multiple performance verification scene information, after collecting the performance test result of the test chip under the selected performance verification scene information, it can also be detected whether all performance verification scene information corresponding to the selected test model has been selected; in response to not selecting all performance verification scene information corresponding to the selected test model, the step of selecting performance verification scene information in the performance verification scene information corresponding to the selected test model is returned to execute; in response to selecting all performance verification scene information corresponding to the selected test model, it is detected whether all test models have been selected; in response to not selecting all test models, the test chip is reset, and the step of selecting a test model in the test model is returned to execute, and the process is as shown in Figure 3 .

[0089] In a specific application scenario, in order to facilitate the user to learn the performance test result of the Raid chip, after performing performance test on the test chip according to the performance verification scene information and obtaining the performance test result, a performance index table of the Raid chip can be generated according to the performance verification scene information, the original chip configuration information, the test command and the performance test result, at this time, the complete process of chip performance verification is as shown in Figure 4 , and the performance index table can be as shown in Table 3, wherein the verification scene, the chip configuration and the FIO command can represent the detailed information of the current verification scene, and the IOPS and the BW can represent the performance index under the current scene, wherein the IOPS represents the number of IO commands per second, and is used to reflect the throughput capacity of the storage device to handle discrete requests, and the BW represents the amount of data read / written per second, and is used to reflect the continuous transmission capacity of the storage device.

[0090] Table 3 Performance index visualization table

[0091]

[0092] The chip performance verification method provided in the application comprises the following steps: obtaining performance verification scene information for performance verification of a Raid chip; obtaining original chip configuration information corresponding to the performance verification scene information; generating a test model of the Raid chip according to the performance verification scene information and the original chip configuration information; generating target chip configuration information according to the test model; performing chip morphology construction according to the target chip configuration information to obtain a test chip; and performing performance testing on the test chip according to the performance verification scene information to obtain a performance testing result. Before chip morphology construction of the Raid chip, the test model of the Raid chip is generated according to the performance verification scene information of the Raid chip and the corresponding original chip configuration information, the target chip configuration information is generated according to the test model, and then the chip morphology construction is performed according to the target chip configuration information to obtain the test chip, so that the test chip is adapted to the performance verification scene and the chip configuration information of the Raid, thereby the Raid chip performance verification is completed in the prototype verification stage after the chip firmware adaptation, which is beneficial to finding deeper problems of the Raid chip earlier, thereby reducing the iteration cycle of the hardware and the modification cost, and promoting the rapid convergence of the chip hardware performance.

[0093] Please refer to Figure 5 , Figure 5 The structural diagram of a chip performance verification system provided in the embodiment of the application.

[0094] The chip performance verification system provided in the embodiment of the application can comprise:

[0095] The performance verification information acquisition module 101 is configured to obtain performance verification scene information for performance verification of a Raid chip.

[0096] The original configuration information acquisition module 102 is configured to obtain original chip configuration information corresponding to the performance verification scene information.

[0097] The test model generation module 103 is configured to generate a test model of the Raid chip according to the performance verification scene information and the original chip configuration information.

[0098] The target configuration information generation module 104 is configured to generate target chip configuration information according to the test model.

[0099] The chip construction module 105 is configured to perform chip morphology construction according to the target chip configuration information to obtain a test chip.

[0100] The performance test module 106 is configured to perform performance test on the test chip according to the performance verification scene information, and obtain performance test results.

[0101] The chip performance verification system provided in the embodiments of the present application can comprise:

[0102] The first obtaining unit is configured to obtain original chip configuration information corresponding to the performance verification scene information, wherein the original chip configuration information comprises a Raid level, a number of disks, a storage unit size value, a number of strips, and a fixed parameter.

[0103] The test model generating module can comprise:

[0104] The first determining unit is configured to determine a total number of disks mounted by the Raid chip.

[0105] The second determining unit is configured to determine a maximum number of namespaces supported by the Raid chip.

[0106] The first statistical unit is configured to count all performance verification scene information corresponding to each type of original chip configuration information.

[0107] The first combination unit is configured to combine the original chip configuration information by type, and obtain a test model with a number of disks less than or equal to the total number of disks and a number of namespaces less than or equal to the maximum number of namespaces.

[0108] The third determining unit is configured to determine performance verification scene information corresponding to the test model according to the original chip configuration information combined into the test model.

[0109] The chip performance verification system provided in the embodiments of the present application can comprise:

[0110] The first generating unit is configured to generate target chip configuration information according to the test model, wherein the target chip configuration information comprises a Raid level, a number of disks, a storage unit size value, a namespace size value, a number of namespaces, a fixed parameter, and a block size value, and the namespace size value comprises a product value of the number of disks, the storage unit size value, and the number of strips in the test model.

[0111] The chip performance verification system provided in the embodiments of the present application can comprise:

[0112] The first constructing unit is configured to construct a chip form according to the Raid level, the number of disks, the storage unit size value, the fixed parameter, and the block size value in the target chip configuration information, and obtain a test chip.

[0113] The second constructing unit is configured to construct a controller data structure of the test chip according to the number of namespaces and the fixed parameter in the target chip configuration information.

[0114] The third constructing unit is configured to construct a list of available namespaces of the test chip according to the number of namespaces in the target chip configuration information.

[0115] The fourth constructing unit is configured to construct a namespace data structure of the test chip according to the namespace size value and the block size value in the target chip configuration information.

[0116] The chip performance verification system provided by the embodiment of the present application can include:

[0117] The first loading unit is configured to load the test driver.

[0118] The first selecting unit is configured to select the test model in the test models.

[0119] The second selecting unit is configured to select the performance verification scenario information in the performance verification scenario information corresponding to the selected test model.

[0120] The first running unit is configured to run the test command corresponding to the selected performance verification scenario information based on the test driver, so as to perform performance testing on the test chip.

[0121] The first collecting unit is configured to collect the IOPS value and the BW value of the test chip under the selected performance verification scenario information.

[0122] The first setting unit is configured to set the IOPS value and the BW value as the performance testing result of the test chip under the selected performance verification scenario information.

[0123] The chip performance verification system provided by the embodiment of the present application can further include:

[0124] The detecting unit is configured to detect whether all the performance verification scenario information corresponding to the selected test model has been selected after the first collecting unit collects the performance testing result of the test chip under the selected performance verification scenario information; in response to that all the performance verification scenario information corresponding to the selected test model has not been selected, the step of selecting the performance verification scenario information in the performance verification scenario information corresponding to the selected test model is executed; in response to that all the performance verification scenario information corresponding to the selected test model has been selected, whether all the test models has been selected is detected; in response to that all the test models has not been selected, the test chip is reset, and the step of selecting the test model in the test models is executed.

[0125] The chip performance verification system provided by the embodiment of the present application can further include:

[0126] The performance index generation module is configured to generate a performance index table of the Raid chip according to the performance verification scene information, the original chip configuration information, the test command and the performance test result after the performance test module performs the performance test on the test chip according to the performance verification scene information and obtains the performance test result.

[0127] The present application also provides an electronic device and a computer readable storage medium, both of which have the corresponding effects of the chip performance verification method provided by the embodiments of the present application. Please refer to Figure 6 , Figure 6 FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0128] The electronic device provided by the embodiment of the present application comprises a memory 201 and a processor 202, the memory 201 stores a computer program, and the processor 202 implements the steps of the chip performance verification method described in any of the above embodiments when executing the computer program.

[0129] Please refer to Figure 7 , the other electronic device provided by the embodiment of the present application can further comprise: an input port 203 connected with the processor 202, configured to transmit the command input by the outside to the processor 202; a display unit 204 connected with the processor 202, configured to display the processing result of the processor 202 to the outside; and a communication module 205 connected with the processor 202, configured to realize the communication between the electronic device and the outside. The display unit 204 can be a display panel, a laser scanning display, etc.; the communication mode adopted by the communication module 205 includes but is not limited to Mobile High-Definition Link (MHL), Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), wireless connection: WIreless Fidelity (WiFi), Bluetooth communication technology, low-power Bluetooth communication technology, IEEE 802.11s-based communication technology.

[0130] The computer readable storage medium provided by the embodiment of the present application stores a computer program, and the computer program is executed by the processor to implement the steps of the chip performance verification method described in any of the above embodiments.

[0131] The computer readable storage medium involved in the present application includes random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0132] The computer program product provided by the embodiment of the present application comprises computer programs / instructions, which, when executed by a processor, implement the steps of the chip performance verification method described in any of the above embodiments.

[0133] The related parts of the chip performance verification system, electronic equipment, computer readable storage medium and computer program product provided by the embodiments of the present application are described in detail in the corresponding part of the chip performance verification method provided by the embodiments of the present application, and will not be described here. In addition, the parts of the above technical solutions provided by the embodiments of the present application which are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as not to be too verbose.

[0134] It should also be noted that, in this document, relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the stated elements.

[0135] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip performance verification method, characterized in that, include: Obtain performance verification scenario information for RAID chip performance verification; Obtain the original chip configuration information corresponding to the performance verification scenario information; Based on the performance verification scenario information and the original chip configuration information, a test model for the RAID chip is generated; Generate the target chip configuration information according to the test model described above; The chip form factor is constructed according to the target chip configuration information to obtain the test chip; The performance of the test chip is performed based on the performance verification scenario information to obtain the performance test results.

2. The chip performance verification method according to claim 1, characterized in that, The step of obtaining the original chip configuration information corresponding to the performance verification scenario information includes: Obtain the original chip configuration information corresponding to the performance verification scenario information. The original chip configuration information includes the Raid level, number of disks, storage unit size, number of stripes, and fixed parameters. The step of generating a test model for the RAID chip based on the performance verification scenario information and the original chip configuration information includes: Determine the total number of disks mounted on the RAID chip; Determine the maximum number of namespaces supported by the RAID chip; Collect statistics on all performance verification scenario information corresponding to each type of original chip configuration information; The original chip configuration information is combined according to type to obtain a test model in which the number of disks is less than or equal to the total number of disks and the number of namespaces is less than or equal to the maximum number of namespaces. Based on the original chip configuration information that forms the test model, the performance verification scenario information corresponding to the test model is determined.

3. The chip performance verification method according to claim 2, characterized in that, The step of generating target chip configuration information according to the test model includes: According to the test model, target chip configuration information is generated. The target chip configuration information includes RAID level, number of disks, storage unit size, namespace size, number of namespaces, fixed parameters, and block size. The namespace size includes the product of the number of disks, storage unit size, and number of stripes in the test model.

4. The chip performance verification method according to claim 3, characterized in that, The step of constructing the chip form according to the target chip configuration information to obtain the test chip includes: Based on the Raid level, number of disks, storage unit size, fixed parameters, and block size in the target chip configuration information, the chip form is constructed to obtain the test chip; Based on the number of namespaces and fixed parameters in the target chip configuration information, construct the controller data structure of the test chip; Based on the number of namespaces in the target chip configuration information, construct a list of available namespaces for the test chip; The namespace data structure of the test chip is constructed based on the namespace size and block size values ​​in the target chip configuration information.

5. The chip performance verification method according to any one of claims 2 to 4, characterized in that, The step of performing performance testing on the test chip based on the performance verification scenario information to obtain performance test results includes: Load the test driver; Select a test model from the test models; Select the performance verification scenario information from the performance verification scenario information corresponding to the selected test model; Based on the test driver, the test command corresponding to the selected performance verification scenario information is run to perform performance testing on the test chip; Collect the IOPS and BW values ​​of the test chip under the selected performance verification scenario information; The IOPS value and the BW value are used as the performance test results of the test chip under the selected performance verification scenario information.

6. The chip performance verification method according to claim 5, characterized in that, After collecting the performance test results of the test chip under the selected performance verification scenario information, the method further includes: Check whether all the performance verification scenario information corresponding to the selected test model has been selected; If none of the performance verification scenario information corresponding to the selected test model is selected, then the step of selecting performance verification scenario information from the performance verification scenario information corresponding to the selected test model is returned. In response to the fact that all the performance verification scenario information corresponding to the selected test model has been selected, it is then determined whether all the test models have been selected. If none of the test models have been selected, the test chip is reset, and the process returns to the step of selecting a test model from the test models.

7. The chip performance verification method according to claim 5, characterized in that, After performing performance testing on the test chip based on the performance verification scenario information and obtaining the performance test results, the method further includes: Based on the performance verification scenario information, the original chip configuration information, the test command, and the performance test results, a performance index table for the RAID chip is generated.

8. A chip performance verification system, characterized in that, include: The performance verification information acquisition module is used to acquire performance verification scenario information for performing performance verification on the RAID chip. The original configuration information acquisition module is used to acquire the original chip configuration information corresponding to the performance verification scenario information; The test model generation module is used to generate a test model for the Raid chip based on the performance verification scenario information and the original chip configuration information. The target configuration information generation module is used to generate target chip configuration information according to the test model. A chip construction module is used to construct a chip form according to the target chip configuration information to obtain a test chip. The performance testing module is used to perform performance testing on the test chip based on the performance verification scenario information and obtain performance test results.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip performance verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the chip performance verification method as described in any one of claims 1 to 7.

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