Display panel

Abstract

The embodiment of the invention discloses a display panel which comprises a first light-emitting device, a second light-emitting device, a first pixel circuit and a second pixel circuit, and the second light-emitting device is a tandem light-emitting diode light-emitting device. On the basis that the second cross voltage of the second light-emitting device is larger than the first cross voltage of the first light-emitting device, the second positive power supply voltage connected to the anode of the second light-emitting device is set to be larger than the first positive power supply voltage connected to the anode of the first light-emitting device, so that the light-emitting brightness of the second light-emitting device is improved in the high-brightness display mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] In the existing OLED panel, in order to improve the luminous efficiency of blue pixels, a stacked light-emitting layer is used to form a blue light device, and the blue light device is a tandem organic light emitting diode (Tandem OLED) device, and the green light device and the red light device are single-layer light-emitting layer devices. The tandem organic light emitting diode device can significantly reduce the light-emitting current, thereby reducing the power consumption of the screen. The tandem organic light emitting diode device is formed by stacking two or more organic light-emitting layers through a connecting layer.

[0003] In the research and practice process of the prior art, the inventors of the present application found that the blue light device needs a large cross-voltage. When the cathode power supply voltages of all light-emitting devices are the same, the turn-on voltages required by the blue light device and the red / green light device will be different. In the prior art, the anode terminals of all light-emitting devices are connected to a uniform positive power supply voltage VDD, which causes the luminance of the blue light device to be low when displaying at high brightness, thereby causing the luminance of the display panel to be uneven when displaying at high brightness. SUMMARY

[0004] The embodiments of the present application provide a display panel, which can improve the luminous brightness of a second light-emitting device when displaying at high brightness.

[0005] The embodiments of the present application provide a display panel, which comprises:

[0006] A first light-emitting device, a cathode of the first light-emitting device is configured to be connected to a first cathode power supply voltage;

[0007] A first pixel circuit connected to the first light-emitting device, the first pixel circuit is configured to be connected to a first positive power supply voltage, and a difference between the first positive power supply voltage and the first cathode power supply voltage is a first cross-voltage;

[0008] A second light-emitting device, which is a tandem light-emitting diode light-emitting device, a cathode of the second light-emitting device is configured to be connected to a second cathode power supply voltage;

[0009] A second pixel circuit connected to the second light-emitting device, the second pixel circuit is configured to be connected to a second positive power supply voltage, and a difference between the second positive power supply voltage and the second cathode power supply voltage is a second cross-voltage, and the second cross-voltage is greater than the first cross-voltage;

[0010] The second positive power supply voltage is greater than the first positive power supply voltage.

[0011] Optionally, in some embodiments of the present application, the display panel further comprises a first positive power line and a second positive power line, the first positive power line is connected to the first pixel circuit, the second positive power line is connected to the second pixel circuit, the first positive power line is configured to access the first positive power voltage, and the second positive power line is configured to access the second positive power voltage;

[0012] The first pixel circuit comprises a third transistor, a fifth transistor, a first storage capacitor and a first drive transistor, an input pole of the fifth transistor is connected to the first positive power line, an input pole of the third transistor, an output pole of the fifth transistor and an input pole of the first drive transistor are connected to a first voltage writing node, an output pole of the third transistor, a gate pole of the first drive transistor and one pole plate of the first storage capacitor are connected to a first threshold node;

[0013] The second pixel circuit comprises a ninth transistor, an eleventh transistor, a second storage capacitor and a second drive transistor, an input pole of the eleventh transistor is connected to the second positive power line, an input pole of the ninth transistor, an output pole of the eleventh transistor and an input pole of the second drive transistor are connected to a second voltage writing node, an output pole of the ninth transistor, a gate pole of the second drive transistor and one pole plate of the second storage capacitor are connected to a second threshold node;

[0014] The first positive power line comprises a first sub-line and a second sub-line arranged in different layers, the first sub-line extends along a first direction, the second sub-line extends along a second direction intersecting the first direction, and one second sub-line connects a plurality of first sub-lines;

[0015] The second positive power line comprises a third sub-line and a fourth sub-line arranged in different layers, the fourth sub-line and the second sub-line are arranged in the same layer and are spaced apart, the third sub-line extends along the first direction, the fourth sub-line extends along the second direction, and one fourth sub-line connects a plurality of third sub-lines;

[0016] In the first direction, the fourth sub-line and the second sub-line are arranged alternately.

[0017] Optionally, in some embodiments of the present application, the first sub-line comprises a first connecting part and a first unit, a plurality of first units are arranged in the first direction, any two adjacent first units are connected by the first connecting part, and the first unit is connected to the second sub-line;

[0018] The input pole of the fifth transistor is connected to the first unit, and the first unit covers at least part of the first voltage writing node.

[0019] Optionally, in some embodiments of the present application, the first unit comprises a first contact portion, a second contact portion, a second connecting portion and a first auxiliary portion, the second connecting portion extends along the first direction, the first contact portion and the second contact portion connect the second connecting portion, the first contact portion connects the input terminal of the fifth transistor, the second contact portion connects the second sub-line, the first auxiliary portion extends along the second direction and is connected to the side of the second connecting portion away from the first contact portion, a plurality of the first auxiliary portions are arranged along the first direction at intervals, two adjacent first auxiliary portions are connected by the first connecting portion, and the first auxiliary portion covers at least part of the first voltage write-in node.

[0020] Optionally, in some embodiments of the present application, one first contact portion corresponds to connecting the input terminals of the fifth transistors of two first pixel circuits, each first unit comprises two first auxiliary portions, the two first auxiliary portions are arranged along the first direction at intervals, one first auxiliary portion covers at least part of the first voltage write-in node of one first pixel circuit, and the other first auxiliary portion covers at least part of the first voltage write-in node of the other first pixel circuit.

[0021] Optionally, in some embodiments of the present application, the third sub-line comprises a second auxiliary portion and a third connecting portion arranged in different layers, the second auxiliary portion is arranged in the same layer as the first sub-line and is arranged at intervals, and the third connecting portion extends along the first direction, the third connecting portion connects the fourth sub-line through the second auxiliary portion.

[0022] The input terminal of the eleventh transistor is connected to the third connecting portion, and the second auxiliary portion covers at least part of the second voltage write-in node.

[0023] Optionally, in some embodiments of the present application, the third sub-line further comprises a transfer portion, the transfer portion is arranged in a layer different from the third connecting portion and the second auxiliary portion, the third connecting portion connects the second auxiliary portion through the transfer portion, and the second auxiliary portion connects the fourth sub-line.

[0024] Optionally, in some embodiments of the present application, the second auxiliary portion and the first unit are arranged alternately along the first direction.

[0025] Optionally, in some embodiments of the present application, the first pixel circuit comprises a first reset unit, the first reset unit and the anode of the first light emitting device are connected to a first reset node, and the first reset unit is configured to provide a first reset voltage to the first reset node; the turn-on voltage of the second light emitting device is greater than the turn-on voltage of the first light emitting device.

[0026] The second pixel circuit comprises a second reset unit, an anode of the second light-emitting device and the second reset unit are connected to a second reset node, and the second reset unit is configured to provide a second reset voltage to the second reset node; the second reset voltage is greater than the first reset voltage.

[0027] The display panel further comprises a first reset line and a second reset line, the first reset line is connected to an input end of the first reset unit, the second reset line is connected to an input end of the second reset unit, the first reset line is configured to access the first reset voltage, and the second reset line is configured to access the second reset voltage.

[0028] Optionally, in some embodiments of the present application, the first reset line comprises first reset sub-lines and second reset sub-lines arranged in different layers, the first reset sub-lines extend along a first direction, the second reset sub-lines extend along a second direction intersecting the first direction, and one second reset sub-line is connected to a plurality of first reset sub-lines.

[0029] The second reset line comprises third reset sub-lines and fourth reset sub-lines arranged in different layers, the fourth reset sub-lines and the second reset sub-lines are arranged in the same layer and are spaced apart, the third reset sub-lines extend along the first direction, and the fourth reset sub-lines extend along the second direction, and one fourth reset sub-line is connected to a plurality of third reset sub-lines.

[0030] In the first direction, the fourth reset sub-lines and the second reset sub-lines are arranged alternately.

[0031] Optionally, in some embodiments of the present application, the display panel comprises, in sequence, a substrate, a buffer layer, a first active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, a fourth metal layer, a sixth insulating layer, a fifth metal layer, a first planarization layer, a sixth metal layer, a second planarization layer, a seventh metal layer, a third planarization layer, a fourth planarization layer, an anode layer, and a pixel definition layer.

[0032] The gate of the first driving transistor, the gate of the second driving transistor, one plate of the first storage capacitor, one plate of the second storage capacitor and the first reset sub-line are formed in the third metal layer, the third sub-line, part of the other plate of the first storage capacitor, part of the other plate of the second storage capacitor are formed in the fourth metal layer, the third reset sub-line, the first voltage write node, the second voltage write node and the adapter are formed in the fifth metal layer, the first sub-line and the second auxiliary part are formed in the sixth metal layer, the second sub-line, the fourth sub-line, the second reset sub-line and the fourth reset sub-line are formed in the seventh metal layer.

[0033] Optionally, in some embodiments of the present application, the cathode of the second light emitting device is connected with the cathode of the first light emitting device, the first light emitting device is one of a single light emitting layer light emitting device and a serial light emitting diode light emitting device, the second light emitting device is a serial light emitting diode light emitting device, and the number of light emitting layers of the second light emitting device is greater than the number of light emitting layers of the first light emitting device.

[0034] In the display panel of the embodiments of the present application, the second cross voltage of the second light emitting device is greater than the first cross voltage of the first light emitting device, so the second positive power supply voltage connected to the anode of the second light emitting device is greater than the first positive power supply voltage connected to the anode of the first light emitting device, so that the luminance of the second light emitting device is improved in the high brightness display mode. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a top view structural schematic diagram of a display panel provided by the embodiments of the present application;

[0036] Figure 2 is an equivalent circuit diagram of a first pixel circuit in the display panel provided by the embodiments of the present application;

[0037] Figure 3 is an equivalent circuit diagram of a second pixel circuit in the display panel provided by the embodiments of the present application;

[0038] Figure 4 is a cross-sectional structural schematic diagram of a display panel provided by the embodiments of the present application;

[0039] Figure 5-1 is a planar schematic diagram of a film layer in which a first pixel circuit and a second pixel circuit in the display panel are located, provided by the embodiments of the present application;

[0040] Figure 5-2 is Figure 5-1 is an enlarged schematic diagram of the P part in FIG. 8;

[0041] Figure 6FIG. 1 is a plan view of a first active layer of a display panel provided by an embodiment of the present application;

[0042] Figure 7 FIG. 2 is a plan view of a first metal layer of the display panel provided by an embodiment of the present application;

[0043] Figure 8 FIG. 3 is a plan view of a second metal layer of the display panel provided by an embodiment of the present application;

[0044] Figure 9 FIG. 4 is a plan view of a second active layer of the display panel provided by an embodiment of the present application;

[0045] Figure 10 FIG. 5 is a plan view of a third metal layer of the display panel provided by an embodiment of the present application;

[0046] Figure 11 FIG. 6 is a plan view of a fourth metal layer of the display panel provided by an embodiment of the present application;

[0047] Figure 12 FIG. 7 is a plan view of a fifth metal layer of the display panel provided by an embodiment of the present application;

[0048] Figure 13 FIG. 8 is a plan view of a sixth metal layer of the display panel provided by an embodiment of the present application;

[0049] Figure 14 FIG. 9 is a plan view of a seventh metal layer of the display panel provided by an embodiment of the present application.

[0050] Legend of reference signs:

[0051] First direction F1; second direction F2; display panel 100; first light emitting device 11; first pixel circuit 21; second light emitting device 12; second pixel circuit 22; first cathode power supply voltage VSS1; first positive power supply voltage VDD1; second cathode power supply voltage VSS2; second positive power supply voltage VDD2; first drive transistor T1; second transistor T2; third transistor T3; fourth transistor T4; fifth transistor T5; sixth transistor T6; first storage capacitor cst1; first voltage write node A1; first threshold node Q1; first reset node C1; first data write node B1; first scan signal Nscan1; first control signal EM1; first reset voltage VI1; second control signal EM2; second scan signal Nscan2; data signal data; second drive transistor M1; eighth transistor M2; ninth transistor M3; tenth transistor M4; eleventh transistor M5; twelfth transistor M6; second storage capacitor cst2; second voltage write node A2; second threshold node Q2; second reset node C2; second data write node B2; second reset voltage VI2; first control line 51; second control line 52; first scan line 61; second scan line 62; substrate 401; buffer layer 402; first active layer 441; first insulating layer 451; first metal layer 461; second insulating layer 452; second metal layer 462; third insulating layer 453; second active layer 442; fourth insulating layer 454; third metal layer 463; fifth insulating layer 455; fourth metal layer 464; sixth insulating layer 456; fifth metal layer 465; first planar layer 471; sixth metal layer 466; second planar layer 472; seventh metal layer 467; third planar layer 473; fourth planar layer 474; anode layer 48; pixel definition layer 49; first positive power supply line 31; second positive power supply line 32; first sub-line 311; second sub-line 312; third sub-line 321; fourth sub-line 322; first reset line 41; second reset line 42; first reset sub-line 411; second reset sub-line 412; third reset sub-line 421; fourth reset sub-line 422; first connecting portion 3a; first unit 3b; first contact portion 3b1; second contact portion 3b2; second connecting portion 3b3; first auxiliary portion 3b4; second auxiliary portion 3c1; third connecting portion 3c2; adapter portion 3c3; first light shielding portion 71; second light shielding portion 72; first sub-portion c101; second sub-portion c202; third sub-portion c103; fourth sub-portion c204; fifth sub-portion c105; sixth sub-portion c206; data line s1; light transmission port tg. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the embodiments can be combined with each other but will not be described one by one, and the positional words such as "upper" and "lower" are generally used to refer to the upper and lower directions of the device in the actual use or working state, and the specific direction is the direction of the drawing surface in the drawings; and the words "inner" and "outer" are used in relation to the outline of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose a numerical requirement or establish a sequence.

[0053] The present application provides a display panel 100, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0054] Please refer to Figure 1 In Figure 1 , the first direction F1 can be a direction parallel to one side of the display panel 100 in a plan view, and can be, for example, a transverse direction of the display panel 100. The second direction F2 can be a direction parallel to the other side of the display panel 100 in a plan view, and can be a longitudinal direction of the display panel 100. However, it is not limited to this, for example, the first direction F1 and the second direction F2 can intersect non-perpendicularly.

[0055] Please refer to Figures 1 to 3 The present application provides a display panel 100, which includes a first light emitting device 11, a first pixel circuit 21, a second light emitting device 12 and a second pixel circuit 22.

[0056] Optionally, the display panel 100 can be an electroluminescent panel such as an organic light emitting diode panel, a micro light emitting diode panel or a quantum dot light emitting diode panel.

[0057] The display panel 100 will be described in detail below as an example of an organic light emitting diode panel.

[0058] In some embodiments of the present application, the cathode of the second light emitting device 12 and the cathode of the first light emitting device 11 are connected. That is, the entire display panel 100 shares one cathode layer.

[0059] Optionally, the first light emitting device 11 is one of a single light emitting layer light emitting device and a tandem light emitting diode light emitting device. The second light emitting device 12 is a tandem light emitting diode light emitting device. The number of light emitting layers of the second light emitting device 12 is greater than the number of light emitting layers of the first light emitting device 11.

[0060] It can be understood that the more light emitting layers in series in a light emitting device, the better the light emitting effect, but at the same time, the greater the start-up voltage and the cross voltage required.

[0061] It needs to be explained that the start-up voltage (threshold voltage) is the driving voltage applied to the device when the light emitting brightness is 1 candela per square meter (cd / m 2 ). The cross voltage is the difference between the anode access voltage (positive power supply voltage) and the cathode access voltage (cathode power supply voltage) of the light emitting device.

[0062] Based on this, in order to make the light emitting device with large cross voltage emit light efficiently, it is necessary to provide it with a larger positive power supply voltage to drive the light emitting device with large cross voltage to have higher brightness in high brightness display mode.

[0063] Therefore, different light emitting devices of different light emitting colors can be selected as the tandem device of multiple light emitting layers according to the actual light emitting brightness requirements.

[0064] Optionally, based on the fact that the light emitting brightness of a blue light device is lower than that of a red light device and a green light device under the same number of light emitting layers, in order to improve the uniformity of display brightness, the first light emitting device 11 is limited to be a red light device and a green light device, and the second light emitting device 12 is a blue light device.

[0065] The plurality of second light emitting devices 12 (blue light devices) are arranged along the second direction F2. A green light device and a red light device are arranged alternately along the second direction F2.

[0066] In some embodiments, the first light emitting device 11 is a single light emitting layer device, and the second light emitting device 12 is a double light emitting layer device. The first light emitting device 11 adopts a single light emitting layer architecture, which can reduce the risk of horizontal leakage current of the first light emitting device 11.

[0067] In some embodiments, the cathode of the first light emitting device 11 is configured to access a first cathode power supply voltage VSS1. The first pixel circuit 21 is connected to the first light emitting device 11. The first pixel circuit 21 is configured to access a first positive power supply voltage VDD1, and the difference between the first positive power supply voltage VDD1 and the first cathode power supply voltage VSS1 is a first cross voltage.

[0068] The second light emitting device 12 is a serial light emitting diode light emitting device. The cathode of the second light emitting device 12 is configured to be connected to a second cathode power supply voltage VSS2. The second pixel circuit 22 is connected to the second light emitting device 12. The second pixel circuit 22 is configured to be connected to a second positive power supply voltage VDD2, and a difference between the second positive power supply voltage VDD2 and the second cathode power supply voltage VSS2 is a second cross voltage, which is greater than the first cross voltage.

[0069] The second positive power supply voltage VDD2 is greater than the first positive power supply voltage VDD1.

[0070] It can be understood that, in the display panel 100 of the embodiment of the present application, the second cross voltage of the second light emitting device 12 is greater than the first cross voltage of the first light emitting device 11, so the second positive power supply voltage VDD2 connected to the anode of the second light emitting device 12 is greater than the first positive power supply voltage VDD1 connected to the anode of the first light emitting device 11, so that the luminance of the second light emitting device 12 is improved in the high-brightness display mode.

[0071] Secondly, it needs to be explained that the equivalent circuit architectures of the first pixel circuit 21 and the second pixel circuit 22 are consistent, but are not limited thereto, for example, the two can also be different.

[0072] Optionally, in some embodiments of the present application, the first pixel circuit 21 and the second pixel circuit 22 are both 6T1C circuits, but are not limited thereto, for example, 7T1C, 7T2C, 5T1C or 3T1C, etc.

[0073] Optionally, the green light device and the red light device are each connected to a first pixel circuit 21. The blue light device is connected to a second pixel circuit 22.

[0074] The second pixel circuit 22 and the two adjacent first pixel circuits 21 form a repeating unit, and the repeating units are arranged in a matrix in the first direction F1 and the second direction F2.

[0075] Please refer to Figure 2 and Figure 3 The first pixel circuit 21 includes a third transistor T3, a fifth transistor T5, a first storage capacitor cst1 and a first driving transistor T1. The input pole of the fifth transistor T5 is configured to be connected to the first positive power supply voltage VDD1, the input pole of the third transistor T3, the output pole of the fifth transistor T5 and the input pole of the first driving transistor T1 are connected to a first voltage writing node A1. The output pole of the third transistor T3, the gate of the first driving transistor T1 and one pole plate of the first storage capacitor cst1 are connected to a first threshold node Q1. The gate of the third transistor T3 is connected to a first scanning signal Nscan1. The gate of the fifth transistor T5 is connected to a first control signal EM1.

[0076] The first pixel circuit 21 comprises a first reset unit connected to a first reset node C1 and an anode of the first light emitting device 11, and configured to provide a first reset voltage VI1 to the first reset node C1.

[0077] Optionally, the first reset unit comprises a fourth transistor T4, a gate of the fourth transistor T4 being connected to the second control signal EM2, an input of the fourth transistor T4 being connected to the first reset voltage VI1, and an output of the fourth transistor T4 being connected to the first reset node C1.

[0078] The first pixel circuit 21 further comprises a second transistor T2 and a sixth transistor T6, a gate of the second transistor T2 being connected to the second scan signal Nscan2, an input of the second transistor T2 being connected to the data signal data, and an output of the second transistor T2 and an output of the first driving transistor T1 being connected to a first data write node B1. A gate of the sixth transistor T6 is connected to the second control signal EM2, an input of the sixth transistor T6 is connected to the first data write node B1, and an output of the sixth transistor T6 is connected to the first reset node C1.

[0079] Wherein, the first reset voltage VI1 is used as a reference voltage of the anode of the first light emitting device 11 before the first light emitting device 11 emits light.

[0080] Optionally, the second pixel circuit 22 comprises a ninth transistor M3, an eleventh transistor M5, a second storage capacitor cst2 and a second driving transistor M1, an input of the eleventh transistor M5 being connected to the second positive power supply voltage VDD2, an input of the ninth transistor M3, an output of the eleventh transistor M5 and an input of the second driving transistor M1 being connected to a second voltage write node A2, an output of the ninth transistor M3, a gate of the second driving transistor M1 and one plate of the second storage capacitor cst2 being connected to a second threshold node Q2. A gate of the ninth transistor M3 is connected to the first scan signal Nscan1. A gate of the eleventh transistor M5 is connected to the first control signal EM1.

[0081] The second pixel circuit 22 comprises a second reset unit connected to a second reset node C2 and an anode of the second light emitting device 12, and configured to provide a second reset voltage VI2 to the second reset node C2.

[0082] Optionally, the second reset unit comprises a tenth transistor M4, a gate of the tenth transistor M4 being connected to the second control signal EM2, an input of the tenth transistor M4 being connected to the second reset voltage VI2, and an output of the tenth transistor M4 being connected to the second reset node C2.

[0083] The second pixel circuit 22 also includes an eighth transistor M2 and a twelfth transistor M6. The gate of the eighth transistor M2 is connected to the second scan signal Nscan2, the input of the eighth transistor M2 is connected to the data signal data, and the output of the eighth transistor M2 and the output of the second driving transistor M1 are both connected to the second data writing node B2. The gate of the twelfth transistor M6 is connected to the second control signal EM2, the input of the twelfth transistor M6 is connected to the second data writing node B2, and the output of the twelfth transistor M6 is connected to the second reset node C2.

[0084] Before the second light-emitting device 12 emits light, the second reset voltage VI2 serves as the reference voltage for the anode terminal of the second light-emitting device 12.

[0085] In some embodiments, the display panel 100 further includes a first control line 51 connected to a first control signal EM1, a second control line 52 connected to a second control signal EM2, a first scan line 61 connected to a first scan signal Nscan1, and a second scan line 62 connected to a second scan signal Nscan2.

[0086] The first control line 51 connects the fifth transistor T5 and the eleventh transistor M5, and a portion of the first control line 51 is multiplexed as the gate of the fifth transistor T5 and the eleventh transistor M5. The second control line 52 connects the fourth transistor T4, the sixth transistor T6, the tenth transistor M4, and the twelfth transistor M6, and a portion of the second control line 52 is multiplexed as the gate of the fourth transistor T4, the sixth transistor T6, the tenth transistor M4, and the twelfth transistor M6. The first scan line 61 connects the third transistor T3 and the ninth transistor M3, and a portion of the first scan line 61 is multiplexed as one gate of the third transistor T3 and the ninth transistor M3. The second scan line 62 connects the second transistor T2 and the eighth transistor M2, and a portion of the second scan line 62 is multiplexed as one gate of the second transistor T2 and the eighth transistor M2.

[0087] Optionally, the fifth transistor T5, the sixth transistor T6, the eleventh transistor M5, and the twelfth transistor M6 are dual-gate series transistors. The second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor M2, the ninth transistor M3, and the tenth transistor M4 are dual-gate parallel transistors.

[0088] It should be noted that each of the above-mentioned transistors can be either a P-type transistor or an N-type transistor. Figure 2 and Figure 3 In this configuration, the first driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the second driving transistor M1, the eighth transistor M2, the ninth transistor M3, and the tenth transistor M4 are N-type transistors, while the other transistors are P-type transistors.

[0089] Please refer to Figure 4 In some embodiments, the display panel 100 comprises, in sequence, a substrate 401, a buffer layer 402, a first active layer 441, a first insulating layer 451, a first metal layer 461, a second insulating layer 452, a second metal layer 462, a third insulating layer 453, a second active layer 442, a fourth insulating layer 454, a third metal layer 463, a fifth insulating layer 455, a fourth metal layer 464, a sixth insulating layer 456, a fifth metal layer 465, a first planar layer 471, a sixth metal layer 466, a second planar layer 472, a seventh metal layer 467, a third planar layer 473, a fourth planar layer 474, an anode layer 48, and a pixel definition layer 49.

[0090] Please refer to Figures 5-1 to 5-2 Optionally, in some embodiments of the present application, the display panel 100 further comprises a first positive power line 31 and a second positive power line 32. The first positive power line 31 is connected to the first pixel circuit 21. The second positive power line 32 is connected to the second pixel circuit 22. The first positive power line 31 is configured to access a first positive power voltage VDD1. The second positive power line 32 is configured to access a second positive power voltage VDD2.

[0091] The first positive power line 31 comprises a first sub-line 311 and a second sub-line 312 arranged in different layers, the first sub-line 311 extending along a first direction F1, the second sub-line 312 extending along a second direction F2 intersecting the first direction F1, and a second sub-line 312 connecting a plurality of first sub-lines 311.

[0092] The second positive power line 32 comprises a third sub-line 321 and a fourth sub-line 322 arranged in different layers, the fourth sub-line 322 and the second sub-line 312 being arranged in the same layer and spaced apart, the third sub-line 321 extending along the first direction F1, the fourth sub-line 322 extending along the second direction F2, and a fourth sub-line 322 connecting a plurality of third sub-lines 321. In the first direction F1, the fourth sub-line 322 and the second sub-line 312 are arranged alternately.

[0093] It can be understood that the first positive power line 31 is cross-connected by the first sub-line 311 and the second sub-line 312 to form a grid shape, and the second positive power line 32 is cross-connected by the third sub-line 321 and the fourth sub-line 322 to form a grid shape, so as to reduce the impedance of the first positive power line 31 and the second positive power line 32 and improve the uniformity of signal transmission.

[0094] Optionally, in some embodiments of the present application, the turn-on voltage of the second light emitting device 12 is greater than the turn-on voltage of the first light emitting device 11. The second reset voltage VI2 is greater than the first reset voltage VI1.

[0095] The display panel 100 further comprises a first reset line 41 and a second reset line 42, the first reset line 41 is connected to the input end of the first reset unit, the second reset line 42 is connected to the input end of the second reset unit, the first reset line 41 is configured to access a first reset voltage VI1, and the second reset line 42 is configured to access a second reset voltage VI2.

[0096] That is, the first reset line 41 is connected to the input end of the fourth transistor T4, and the second reset line 42 is connected to the input end of the tenth transistor M4.

[0097] It can be understood that the turn-on voltage of the second light emitting device 12 is greater than the turn-on voltage of the first light emitting device 11, so that at the same time, the second light emitting device 12 needs a greater charging voltage, and / or the reference voltage of the second light emitting device 12 needs to be increased to reach the threshold voltage. Therefore, in the low brightness display mode, by setting the second reset voltage VI2 to be greater than the first reset voltage VI1, the reference voltage of the second light emitting device 12 is increased, the charging time is shortened, and the charging rate difference between the first light emitting device 11 and the second light emitting device 12 is reduced, so as to improve the light emitting brightness of the second light emitting device 12, and further improve the light emitting uniformity of the whole panel.

[0098] Optionally, in some embodiments of the present application, the first reset line 41 comprises a first reset sub-line 411 and a second reset sub-line 412 arranged in different layers. The first reset sub-line 411 extends along a first direction F1, and the second reset sub-line 412 extends along a second direction F2 intersecting the first direction F1. One second reset sub-line 412 is connected to a plurality of first reset sub-lines 411.

[0099] The second reset line 42 comprises a third reset sub-line 421 and a fourth reset sub-line 422 arranged in different layers. The fourth reset sub-line 422 and the second reset sub-line 412 are arranged in the same layer and are spaced apart. The third reset sub-line 421 extends along the first direction F1, and the fourth reset sub-line 422 extends along the second direction F2. One fourth reset sub-line 422 is connected to a plurality of third reset sub-lines 421.

[0100] In the first direction F1, the fourth reset sub-line 422 and the second reset sub-line 412 are arranged alternately.

[0101] It can be understood that the first reset line 41 is cross-connected by the first reset sub-line 411 and the second reset sub-line 412 to form a grid shape, and the second reset line 42 is cross-connected by the third reset sub-line 421 and the fourth reset sub-line 422 to form a grid shape, so as to reduce the impedance of the first reset line 41 and the second reset line 42, and improve the uniformity of signal transmission.

[0102] Optionally, in some embodiments of the present application, in combination with Figure 13The first sub-line 311 includes a first connection portion 3a and a first unit 3b. In the first direction F1, a plurality of first units 3b are arranged at intervals, and any two adjacent first units 3b are connected by the first connection portion 3a. The first unit 3b is connected to the second sub-line 312.

[0103] The input of the fifth transistor T5 is connected to the first unit 3b, and the first unit 3b covers at least part of the first voltage writing node A1.

[0104] It can be understood that the first unit 3b covers at least the first voltage writing node A1 to reduce the interference of the interference signal on the first voltage writing node A1, and at the same time, the area of the first sub-line 311 is increased to reduce the impedance of the first positive power supply line 31.

[0105] Optionally, in some embodiments of the present application, the first unit 3b includes a first contact portion 3b1, a second contact portion 3b2, a second connection portion 3b3, and a first auxiliary portion 3b4. The second connection portion 3b3 extends along the first direction F1. The first contact portion 3b1 and the second contact portion 3b2 are connected to the second connection portion 3b3. The first contact portion 3b1 is connected to the input of the fifth transistor T5. The second contact portion 3b2 is connected to the second sub-line 312. The first auxiliary portion 3b4 extends along the second direction F2 and is connected to the side of the second connection portion 3b3 away from the first contact portion 3b1. A plurality of first auxiliary portions 3b4 are arranged at intervals along the first direction F1. Any two adjacent first auxiliary portions 3b4 are connected by the first connection portion 3a. The first auxiliary portion 3b4 covers at least part of the first voltage writing node A1.

[0106] It can be understood that the first auxiliary portion 3b4 not only covers the first voltage writing node A1 but also serves as a connection point connecting two first units 3b, which not only saves space but also reduces the influence of the interference signal on the first voltage writing node A1.

[0107] Optionally, in some embodiments of the present application, a first contact portion 3b1 corresponds to the input of the fifth transistor T5 of two first pixel circuits 21. Each first unit 3b includes two first auxiliary portions 3b4 arranged at intervals along the first direction F1. One first auxiliary portion 3b4 covers at least part of the first voltage writing node A1 of one first pixel circuit 21, and the other first auxiliary portion 3b4 covers at least part of the first voltage writing node A1 of the other first pixel circuit 21.

[0108] It can be understood that, based on the fact that the two adjacent first pixel circuits 21 are connected to the same first positive power supply line 31, the two first auxiliary portions 3b4 are arranged in one first unit 3b, which can save layout space.

[0109] Optionally, in some embodiments of the present application, the third sub-line 321 comprises a second auxiliary part 3c1 and a third connecting part 3c2 which are arranged in different layers, and the second auxiliary part 3c1 is arranged in the same layer as the first sub-line 311 and is spaced apart from the first sub-line 311. The third connecting part 3c2 is arranged to extend along the first direction F1, and the third connecting part 3c2 is connected to the fourth sub-line 322 through the second auxiliary part 3c1.

[0110] The input terminal of the eleventh transistor M5 is connected to the third connecting part 3c2, and the second auxiliary part 3c1 covers at least part of the second voltage writing node A2.

[0111] It can be understood that the second auxiliary part 3c1 not only covers the first voltage writing node A1, thereby reducing the influence of the interference signal on the second voltage writing node A2, but also is connected in parallel to the third connecting part 3c2, thereby reducing the impedance of the second positive power supply line 32.

[0112] Optionally, in some embodiments of the present application, the third sub-line 321 further comprises a switching part 3c3 which is arranged in a different layer from the third connecting part 3c2 and the second auxiliary part 3c1. The third connecting part 3c2 is connected to the second auxiliary part 3c1 through the switching part 3c3. The second auxiliary part 3c1 is connected to the fourth sub-line 322.

[0113] It can be understood that the fourth sub-line 322 is connected to the third connecting part 3c2 through the second auxiliary part 3c1 and the switching part 3c3, thereby improving the stability of the connection and reducing the impedance of the second positive power supply line 32.

[0114] Optionally, in some embodiments of the present application, the second auxiliary part 3c1 and the first unit 3b are arranged alternately along the first direction F1, so that the second auxiliary part 3c1 and the first unit 3b are arranged in a straight line, thereby reducing the arrangement space.

[0115] Optionally, please refer to Figures 5-1 to 5-2 and Figure 6 The semiconductor material of the first active layer 441 is a silicon-based semiconductor, such as polycrystalline silicon, monocrystalline silicon or microcrystalline silicon.

[0116] The active parts of the fifth transistor T5, the sixth transistor T6, the eleventh transistor M5 and the twelfth transistor M6 are formed in the first active layer 441.

[0117] Optionally, please refer to Figures 5-1 to 5-2 and Figure 7 The first control line 51, the second control line 52, the first scan line 61 and the second scan line 62 are formed in the first metal layer 461.

[0118] In some embodiments, the display panel 100 is provided with a plurality of light transmission openings tg corresponding to the area of the optical device, so that ambient light can be received by the optical device through the light transmission openings tg, and the optical device can be a biometric module such as a camera module. The light transmission openings tg are opened in the black matrix layer.

[0119] The first control line 51 includes a first control portion 511 and a second control portion 512. The first control portion 511 is arranged along the first direction F1, and the second control portion 512 is arranged around the outer periphery of the light transmission opening tg to avoid the light transmission opening tg. In the first direction F1, the first control portion 511 and the second control portion 512 are alternately connected.

[0120] Optionally, part of the second scan line 62 is multiplexed as a gate t21 of the second transistor T2 and a gate m21 of the eighth transistor M2. Part of the first scan line 61 is multiplexed as a gate t31 of the third transistor T3 and a gate m31 of the ninth transistor M3. Part of the second control line 52 is multiplexed as a gate t41 of the fourth transistor T4 and a gate m41 of the tenth transistor M4.

[0121] Optionally, please refer to Figures 5-1 to 5-2 and Figure 8 The first light shielding portion 71 corresponds to shielding the active portion of the first drive transistor T1, and the second light shielding portion 72 corresponds to shielding the active portion of the second drive transistor M1. The first storage capacitor cst1 includes a first sub-portion c101, and the second storage capacitor cst2 includes a second sub-portion c202.

[0122] The first light shielding portion 71, the second light shielding portion 72, the first sub-portion c101, and the second sub-portion c202 are formed in the second metal layer 462.

[0123] Optionally, please refer to Figures 5-1 to 5-2 and Figure 9 The semiconductor material of the second active layer 442 is a metal oxide, such as IGZO or IGZTO.

[0124] The active portions of the first drive transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the second drive transistor M1, the eighth transistor M2, the ninth transistor M3, and the tenth transistor M4 are formed in the second active layer 442.

[0125] Optionally, please refer to Figures 5-1 to 5-2 and Figure 10The other gate t22 of the second transistor T2, the other gate t32 of the third transistor T3, the other gate t42 of the fourth transistor T4, the other gate m22 of the eighth transistor M2, the other gate m32 of the ninth transistor M3, the other gate m42 of the tenth transistor M4, one plate (the third sub-portion c103) of the first storage capacitor cst1, one plate (the fourth sub-portion c204) of the second storage capacitor cst2, and the first reset sub-line 411 are formed in the third metal layer 463, so that the other gate t22 of the second transistor T2, the other gate t32 of the third transistor T3, the other gate t42 of the fourth transistor T4, the other gate m22 of the eighth transistor M2, the other gate m32 of the ninth transistor M3, and the other gate m42 of the tenth transistor M4 do not need to be formed by using an extra metal layer, and the compactness of the layout is improved and the layout space is saved.

[0126] The gate of the first driving transistor T1 is multiplexed as the third sub-portion c103, and the gate of the second driving transistor M1 is multiplexed as the fourth sub-portion c204.

[0127] Optionally, in some embodiments, the first reset sub-line 411 includes a connecting sub-portion 41a and a bending sub-portion 41b. The connecting sub-portion 41a is arranged to extend along the first direction F1, and the bending sub-portion 41b is arranged to surround the outer periphery of the light-transmitting port tg to avoid the light-transmitting port tg. In the first direction F1, the connecting sub-portion 41a and the bending sub-portion 41b are alternately connected and arranged.

[0128] Since the other gate t42 of the fourth transistor T4 and the other gate m42 of the tenth transistor M4 are connected and adjacent to the light-transmitting port tg, the bending sub-portion 41b is arranged to surround the outer sides of the light-transmitting port tg, the other gate t42 of the fourth transistor T4, and the other gate m42 of the tenth transistor M4, so that the first reset sub-line 411 not only avoids the light-transmitting port tg, but also increases the distances between the first reset sub-line 411 and the other gate t42 of the fourth transistor T4 and the other gate m42 of the tenth transistor M4, so as to reduce the coupling effects between the first reset sub-line 411 and the other gate t42 of the fourth transistor T4 and the other gate m42 of the tenth transistor M4.

[0129] Optionally, in some embodiments, in the first direction F1, the distance between the bending sub-portion 41b and the other gate t42 of the fourth transistor T4 is a first distance L1, and in the second direction F2, the distance between the bending sub-portion 41b and the other gate t42 of the fourth transistor T4 is a second distance L2, where the second distance L2 is greater than the first distance L1 to reduce the coupling effect between the first reset sub-line 411 and the other gate t42 of the fourth transistor T4.

[0130] Optionally, in some embodiments, the other gate t22 of the second transistor T2 is connected to the gate t21 of the second transistor T2 through a via cnt to achieve double-gate parallel connection. The other gate t32 of the third transistor T3 is connected to the gate t31 of the third transistor T3 through a via cnt to achieve double-gate parallel connection. The other gate t42 of the fourth transistor T4 is connected to the gate t41 of the fourth transistor T4 through a via cnt to achieve double-gate parallel connection.

[0131] The other gate m22 of the eighth transistor M2 is connected to the gate m21 of the eighth transistor M2 through a via cnt to achieve double-gate parallel connection. The other gate m32 of the ninth transistor M3 is connected to the gate m31 of the ninth transistor M3 through a via cnt to achieve double-gate parallel connection. The other gate m42 of the tenth transistor M4 is connected to the gate m41 of the tenth transistor M4 through a via cnt to achieve double-gate parallel connection.

[0132] Optionally, please refer to Figures 5-1 to 5-2 and Figure 11 The third sub-line 321, the part of the other plate of the first storage capacitor cst1 (the fifth sub-part c105), and the part of the other plate of the second storage capacitor cst2 (the sixth sub-part c206) are formed on the fourth metal layer 464.

[0133] The first sub-part c101 is connected to the fifth sub-part c105, and the second sub-part c202 is connected to the sixth sub-part c206. The third sub-part c103 is arranged between the first sub-part c101 and the fifth sub-part c105, and the fourth sub-part c204 is arranged between the second sub-part c202 and the sixth sub-part c206.

[0134] Optionally, please refer to Figures 5-1 to 5-2 and Figure 12 The third reset sub-line 421, the first voltage write node A1, the second voltage write node A2, the switching part 3c3, the first data write node B1, the second data write node B2, the first reset node C1, the first threshold node Q1, the second reset node C2, and the second threshold node Q2 are formed on the fifth metal layer 465.

[0135] Optionally, please refer to Figures 5-1 to 5-2 and Figure 13 The first sub-line 311 and the second auxiliary part 3c1 are formed on the sixth metal layer 466.

[0136] Optionally, please refer to Figures 5-1 to 5-2 and Figure 14 The data line s1, the second sub-line 312, the fourth sub-line 322, the second reset sub-line 412, and the fourth reset sub-line 422 are formed on the seventh metal layer 467.

[0137] The second transistor T2 is connected with a data line s1, and the eighth transistor M2 is also connected with the data line s1.

[0138] Optionally, the data line s1 is connected with the second transistor T2 through multi-layer routing, so as to reduce the layout area of the data line s1.

[0139] In the display panel provided by the embodiment of the present application, the second cross voltage of the second light emitting device is greater than the first cross voltage of the first light emitting device, so the second positive power supply voltage connected with the anode of the second light emitting device is greater than the first positive power supply voltage connected with the anode of the first light emitting device, so that the luminance of the second light emitting device is improved in the high brightness display mode.

[0140] The display panel provided by the embodiment of the present application is described in detail above, and the principle and implementation mode of the present application are described by applying specific examples; the above embodiment is only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, the specific implementation mode and application range can be changed according to the idea of the present application, and the above description should not be understood as a limitation of the present application.

Claims

1. A display panel, characterized in that, include: A first light-emitting device, wherein the cathode of the first light-emitting device is configured to be connected to a first cathode power supply voltage; A first pixel circuit is connected to the first light-emitting device. The first pixel circuit is configured to be connected to a first positive power supply voltage. The difference between the first positive power supply voltage and the first cathode power supply voltage is a first voltage difference. The second light-emitting device is a series-connected light-emitting diode (LED) device, and the cathode of the second light-emitting device is configured to be connected to the second cathode power supply voltage. The second pixel circuit is connected to the second light-emitting device. The second pixel circuit is configured to be connected to a second positive power supply voltage. The difference between the second positive power supply voltage and the second cathode power supply voltage is a second cross voltage. The second cross voltage is greater than the first cross voltage. Wherein, the second positive power supply voltage is greater than the first positive power supply voltage.

2. The display panel according to claim 1, characterized in that, The display panel further includes a first positive power line and a second positive power line. The first positive power line is connected to the first pixel circuit, and the second positive power line is connected to the second pixel circuit. The first positive power line is configured to be connected to the first positive power supply voltage, and the second positive power line is configured to be connected to the second positive power supply voltage. The first pixel circuit includes a third transistor, a fifth transistor, a first storage capacitor, and a first driving transistor. The input of the fifth transistor is connected to the first positive power supply line. The input of the third transistor, the output of the fifth transistor, and the input of the first driving transistor are connected to a first voltage write node. The output of the third transistor, the gate of the first driving transistor, and one plate of the first storage capacitor are connected to a first threshold node. The second pixel circuit includes a ninth transistor, an eleventh transistor, a second storage capacitor, and a second driving transistor. The input of the eleventh transistor is connected to the second positive power supply line. The input of the ninth transistor, the output of the eleventh transistor, and the input of the second driving transistor are connected to the second voltage write node. The output of the ninth transistor, the gate of the second driving transistor, and one plate of the second storage capacitor are connected to the second threshold node. The first positive power line includes a first sub-line and a second sub-line arranged in different layers. The first sub-line extends along a first direction, and the second sub-line extends along a second direction intersecting the first direction. One second sub-line connects multiple first sub-lines. The second positive power line includes a third sub-line and a fourth sub-line arranged in different layers. The fourth sub-line and the second sub-line are arranged in the same layer and spaced apart. The third sub-line extends along the first direction, and the fourth sub-line extends along the second direction. One fourth sub-line connects multiple third sub-lines. In the first direction, the fourth sub-line and the second sub-line are alternately arranged.

3. The display panel according to claim 2, characterized in that, The first sub-line includes a first connecting portion and a first unit. In the first direction, a plurality of first units are arranged at intervals. Any two adjacent first units are connected through the first connecting portion. The first unit is connected to the second sub-line. The input terminal of the fifth transistor is connected to the first unit, and the first unit at least covers a portion of the first voltage write node.

4. The display panel according to claim 3, characterized in that, The first unit includes a first contact portion, a second contact portion, a second connecting portion, and a first auxiliary portion. The second connecting portion extends along the first direction. The first contact portion and the second contact portion are connected to the second connecting portion. The first contact portion is connected to the input terminal of the fifth transistor. The second contact portion is connected to the second sub-line. The first auxiliary portion extends along the second direction and is connected to the side of the second connecting portion away from the first contact portion. A plurality of first auxiliary portions are spaced apart along the first direction. Two adjacent first auxiliary portions are connected through the first connecting portion. The first auxiliary portion at least covers a portion of the first voltage write node.

5. The display panel according to claim 4, characterized in that, Each first contact portion is connected to the input pole of the fifth transistor of the two first pixel circuits. Each first unit includes two first auxiliary portions. The two first auxiliary portions are spaced apart along the first direction. One first auxiliary portion covers at least a portion of the first voltage write node of one first pixel circuit, and the other first auxiliary portion covers at least a portion of the first voltage write node of the other first pixel circuit.

6. The display panel according to claim 4, characterized in that, The third sub-line includes a second auxiliary part and a third connecting part arranged in different layers. The second auxiliary part and the first sub-line are arranged in the same layer and spaced apart. The third connecting part extends along the first direction and is connected to the fourth sub-line through the second auxiliary part. The input terminal of the eleventh transistor is connected to the third connection portion, and the second auxiliary portion at least covers a portion of the second voltage write node.

7. The display panel according to claim 6, characterized in that, The third sub-line further includes a transition section, which is disposed in a different layer between the third connecting section and the second auxiliary section. The third connecting section is connected to the second auxiliary section through the transition section, and the second auxiliary section is connected to the fourth sub-line.

8. The display panel according to claim 6, characterized in that, The second auxiliary part and the first unit are arranged alternately along the first direction.

9. The display panel according to claim 7, characterized in that, The first pixel circuit includes a first reset unit, the first reset unit and the anode of the first light-emitting device are connected to a first reset node, and the first reset unit is configured to provide a first reset voltage to the first reset node; the turn-on voltage of the second light-emitting device is greater than the turn-on voltage of the first light-emitting device. The second pixel circuit includes a second reset unit, the second reset unit and the anode of the second light-emitting device are connected to a second reset node, and the second reset unit is configured to provide a second reset voltage to the second reset node; the second reset voltage is greater than the first reset voltage. The display panel further includes a first reset line and a second reset line. The first reset line is connected to the input terminal of the first reset unit, and the second reset line is connected to the input terminal of the second reset unit. The first reset line is configured to be connected to the first reset voltage, and the second reset line is configured to be connected to the second reset voltage.

10. The display panel according to claim 9, characterized in that, The first reset line includes a first reset sub-line and a second reset sub-line disposed in different layers. The first reset sub-line extends along a first direction, and the second reset sub-line extends along a second direction intersecting the first direction. One second reset sub-line connects multiple first reset sub-lines. The second reset line includes a third reset sub-line and a fourth reset sub-line arranged in different layers. The fourth reset sub-line and the second reset sub-line are arranged in the same layer and spaced apart. The third reset sub-line extends along the first direction, and the fourth reset sub-line extends along the second direction. One fourth reset sub-line connects multiple third reset sub-lines. In the first direction, the fourth reset sub-line and the second reset sub-line are alternately arranged.

11. The display panel according to claim 10, characterized in that, The display panel includes a substrate, a buffer layer, a first active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, a fourth metal layer, a sixth insulating layer, a fifth metal layer, a first planarization layer, a sixth metal layer, a second planarization layer, a seventh metal layer, a third planarization layer, a fourth planarization layer, an anode layer, and a pixel definition layer, which are stacked sequentially. The gate of the first driving transistor, the gate of the second driving transistor, one plate of the first storage capacitor, one plate of the second storage capacitor, and the first reset sub-line are formed on the third metal layer. The third sub-line, a portion of the other plate of the first storage capacitor, and a portion of the other plate of the second storage capacitor are formed on the fourth metal layer. The third reset sub-line, the first voltage write node, the second voltage write node, and the transition portion are formed on the fifth metal layer. The first sub-line and the second auxiliary portion are formed on the sixth metal layer. The second sub-line, the fourth sub-line, the second reset sub-line, and the fourth reset sub-line are formed on the seventh metal layer.

12. The display panel according to claim 9, characterized in that, The cathode of the second light-emitting device is connected to the cathode of the first light-emitting device. The first light-emitting device is either a single-emitting-layer light-emitting device or a series-connected light-emitting diode light-emitting device. The second light-emitting device is a series-connected light-emitting diode light-emitting device. The number of light-emitting layers in the second light-emitting device is greater than the number of light-emitting layers in the first light-emitting device.

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