Magnetic core random access memory read reference circuit design method and system

Abstract

The invention provides a magnetic core random access memory read reference circuit design method and system, and relates to the technical field of circuit design, and the method comprises the steps: obtaining the parameter specification of a magnetic core memory, simulating and generating a bit line current distribution curve, extracting a maximum current value and a minimum current value, and dividing a current adjustment interval; selecting the median of the highest reading success rate interval as the optimal reference current; actual output currents of different temperature points are further detected, a temperature compensation model is established, a compensation circuit is designed, and finally a layout design file is obtained through conversion. According to the invention, the optimal reference current can be accurately determined, temperature compensation is realized, and the reading reliability and stability of the magnetic core memory are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, in particular to a magnetic core random memory read reference circuit design method and system. BACKGROUND

[0002] As a new type of non-volatile storage technology, magnetic core random memory (MRAM) has attracted widespread attention due to its high speed, low power consumption, unlimited write life and good integration capability. In magnetic core random memory, the reliability of read operation directly affects the overall performance of the memory, and read reference circuit design is a key link to ensure the accuracy of read operation.

[0003] The read process of traditional magnetic core random memory relies on the difference between the resistance state of the storage unit and the reference resistance, and determines whether the storage unit stores logic "0" or logic "1" by the size of the current flowing through the bit line. However, with the shrinking of process and the increase of memory capacity, the read operation of magnetic core random memory faces more and more challenges.

[0004] The traditional design method lacks comprehensive analysis of the bit line current distribution characteristics, resulting in inaccurate reference current setting, which cannot adapt to the resistance distribution changes of storage units in large-scale arrays, thereby reducing the reliability of read operation. The existing reference current design often uses empirical formula or fixed offset to determine, without fully considering the influence of process fluctuation and device aging on current distribution, making it difficult to achieve optimal read window. The traditional read reference circuit is sensitive to temperature changes, lacks effective temperature compensation mechanism, and the reference current value deviates greatly at different working temperatures, which significantly increases the read error rate in high temperature or low temperature environment, affecting the stability and reliability of the system.

[0005] There is an urgent need for a magnetic core random memory read reference circuit design method that can accurately analyze the bit line current distribution, determine the optimal reference current value and realize temperature compensation, in order to improve the accuracy and reliability of read operation. SUMMARY

[0006] The magnetic core random memory read reference circuit design method and system provided by the embodiments of the present application can solve the problems in the prior art.

[0007] In a first aspect, the present application provides a magnetic core random memory read reference circuit design method, comprising:

[0008] Obtaining the parameter specification of the target magnetic core random memory, and generating a bit line current distribution curve according to the parameter specification through a random access memory performance simulator;

[0009] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0010] detecting an actual output current of the reference circuit at different temperature points, calculating a deviation between the actual output current and the optimal reference current value, establishing a temperature compensation model according to the deviation, designing a compensation circuit based on the temperature compensation model, converting the compensation circuit into a layout design file, and completing the design of the target magnetic core random access memory read reference circuit.

[0011] generating a bit line current distribution curve by a random access memory performance simulator according to the parameter specification includes:

[0012] The parameter specification includes a working voltage range and a process parameter, a current sampling window is established according to the working voltage range, and a sampling interval of the current sampling window is adaptively adjusted by an iterative optimization algorithm until the sampling interval covers the maximum and minimum working currents of the target magnetic core random access memory;

[0013] A random access memory performance simulator is used to perform Monte Carlo current sampling on a storage cell array of the target magnetic core random access memory according to the sampling interval and the number of sampling points, and a bit line current distribution curve is generated.

[0014] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0015] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0016] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0017] The median of each current adjustment interval is taken as a test current value, a storage cell array of the target magnetic core random memory is subjected to a read operation by using the test current value, and a ratio of a successful number of the read operation to a total test number is counted to obtain a storage cell read success rate corresponding to each current adjustment interval;

[0018] Each current adjustment interval is sorted according to the storage cell read success rate, a current adjustment interval with the highest storage cell read success rate is selected, and the median of the current adjustment interval is determined as an optimal reference current value.

[0019] The actual output current of the reference circuit at different temperature points is detected, a deviation between the actual output current and the optimal reference current value is calculated, and a temperature compensation model is established according to the deviation.

[0020] The reference circuit is subjected to multi-point temperature scanning in a preset temperature range, the actual output current at each temperature point is collected, the deviation between the actual output current and the optimal reference current value is calculated, and a temperature-current response model is established according to the correspondence between the temperature points and the deviation.

[0021] The compensation circuit is converted into a layout design file, and the design of the target magnetic core random memory read reference circuit is completed.

[0022] The structure parameters and device parameters of the compensation circuit are determined according to the temperature compensation model, and the compensation circuit is divided into a temperature detection module and a compensation control module.

[0023] The device layout scheme is generated according to the structure of the compensation circuit, the layout positions of the temperature detection module and the compensation control module are optimized, and the layout design of the target magnetic core random memory read reference circuit is completed.

[0024] The second aspect of the embodiment of the application provides a magnetic core random memory read reference circuit design system, which comprises:

[0025] The first unit is configured to obtain the parameter specification of the target magnetic core random memory, and generate a bit line current distribution curve by using a random access memory performance simulator according to the parameter specification.

[0026] The second unit is configured to extract a maximum current value and a minimum current value of the bit line current distribution curve, divide a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculate a storage cell read success rate in each current adjustment interval, and select a median of a current adjustment interval with the highest storage cell read success rate as an optimal reference current value.

[0027] The third unit is configured to detect actual output currents of the reference circuit at different temperature points, calculate deviations between the actual output currents and the optimal reference current value, establish a temperature compensation model according to the deviations, design a compensation circuit based on the temperature compensation model, convert the compensation circuit into a layout design file, and complete the design of the target magnetic core random access memory read reference circuit.

[0028] In a third aspect, an electronic device is provided, comprising:

[0029] a processor;

[0030] a memory for storing processor-executable instructions;

[0031] The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0032] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0033] The present application has the following advantages:

[0034] By obtaining the target magnetic core random access memory parameter specification and generating a bit line current distribution curve using a performance simulator, the read success rate of the storage unit in different current intervals is evaluated, and the optimal reference current value is selected, thereby improving the accuracy and reliability of the read operation.

[0035] A compensation mechanism based on temperature changes is introduced, and a temperature compensation model is established by detecting the deviations between the actual output currents at different temperature points and the optimal reference current value, thereby effectively solving the read error problem caused by temperature drift in traditional design.

[0036] The theoretical design is combined with the actual circuit, and the layout design file of the compensation circuit is implemented, so that the entire read reference circuit design method is realizable and practical, and the stability and performance of the magnetic core random access memory in actual application are improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a flowchart of a magnetic core random access memory read reference circuit design method according to an embodiment of the present application;

[0038] Figure 2 FIG. 2 is a schematic diagram of a magnetic memory storage unit according to an embodiment of the present application;

[0039] Figure 3 FIG. 3 is a schematic diagram of a storage array according to an embodiment of the present application;

[0040] Figure 4For the embodiment of the present application, refer to the resistance structure schematic diagram. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the embodiment of the present application more clear, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, not all the embodiments. Based on the embodiment in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0042] The technical scheme of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0043] Figure 1 For the flowchart of the design method of the read reference circuit of the magnetic core random memory of the embodiment of the present application, as shown in Figure 1 The method comprises the following steps:

[0044] Obtaining the parameter specification of the target magnetic core random memory, generating the bit line current distribution curve through the random access memory performance simulator according to the parameter specification;

[0045] Extracting the maximum current value and the minimum current value of the bit line current distribution curve, dividing the difference value between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating the storage unit reading success rate in each current adjustment interval, and selecting the median value of the current adjustment interval with the highest storage unit reading success rate as the optimal reference current value;

[0046] Detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, establishing a temperature compensation model according to the deviation, designing a compensation circuit based on the temperature compensation model, converting the compensation circuit into a layout design file, and completing the design of the read reference circuit of the target magnetic core random memory.

[0047] In an optional embodiment, generating the bit line current distribution curve through the random access memory performance simulator according to the parameter specification comprises:

[0048] The parameter specification comprises the working voltage range and the process parameter, establishing a current sampling window according to the working voltage range, and adaptively adjusting the sampling interval of the current sampling window through an iterative optimization algorithm until the sampling interval covers the maximum and minimum working current of the target magnetic core random memory;

[0049] The random access memory performance simulator is used to perform Monte Carlo current sampling on the memory cell array of the target magnetic core random access memory according to the sampling interval and the number of sampling points, to generate a bit line current distribution curve.

[0050] The method for generating a bit line current distribution curve according to parameter specifications through a random access memory performance simulator is accurate in simulating and generating a bit line current distribution curve through adaptive current sampling window adjustment and Monte Carlo sampling technology for current characteristic analysis of a magnetic core random access memory.

[0051] The parameter specifications in the embodiment include an operating voltage range and process parameters. The operating voltage range defines the normal operating voltage interval of the target magnetic core random access memory, for example, 1.0V to 1.2V. The process parameters include transistor threshold voltage, channel length, oxide layer thickness, and other key parameters. Taking a 28nm process as an example, the transistor threshold voltage is 0.35V, the channel length is 25nm, and the oxide layer thickness is 1.2nm. These parameters are the basis for subsequent current sampling and distribution curve generation.

[0052] Based on the operating voltage range, the system establishes an initial current sampling window. For an operating voltage range of 1.0V to 1.2V, the initial sampling window can be set to 50μA to 300μA, covering the current variation interval. The determination of the sampling window takes into account the effects of operating voltage, temperature variation, and process fluctuations on current. In actual applications, the initial window cannot completely cover the maximum and minimum operating currents of the target magnetic core random access memory, so it is necessary to adaptively adjust the current sampling window through an iterative optimization algorithm.

[0053] The iterative optimization algorithm adopts a binary search strategy, which gradually adjusts the sampling window boundaries through multiple iterations. In each iteration, the system uses the current sampling window to perform preliminary current sampling on the target memory, obtaining 100 sampling points. If it is found that more than 5% of the sampling points fall outside the window boundaries, the sampling window is adjusted: for the lower boundary, if there is a current value less than the current lower boundary, the lower boundary is reduced by 25μA; for the upper boundary, if there is a current value greater than the current upper boundary, the upper boundary is increased by 25μA. After adjustment, the sampling evaluation is performed again until no more than 1% of the sampling points fall outside the boundaries, or the maximum number of iterations is reached, which is 10 times.

[0054] In a specific implementation, after the first iteration, the sampling window is adjusted to 40μA to 320μA. After five iterations of adjustment, the window is finally determined to be 30μA to 350μA, at which time 99.5% of the sampling points fall within the window range, meeting the requirement of covering the maximum and minimum operating currents of the target magnetic core random access memory.

[0055] After the sampling interval is determined, the system sets the number of sampling points, typically 10,000 points to ensure the accuracy of statistical analysis. The random access memory performance simulator performs Monte Carlo current sampling on the memory cell array of the target magnetic core random access memory according to the set sampling interval and the number of sampling points. The simulator considers process parameter fluctuations and generates randomized process parameter variations for each memory cell. For example, the transistor threshold voltage is randomly floating ±10% based on 0.35V, and the channel length is randomly floating ±8% based on 25nm.

[0056] During the Monte Carlo sampling process, the simulator builds a 256x256 size memory cell array model and randomizes parameters for each cell. In read operation mode, the simulator calculates the current value on the bit line and records the sampling result each time. The sampling current value includes read current and leakage current. The read current mainly depends on the operating voltage and transistor characteristics, and the leakage current is greatly affected by process variations.

[0057] For each sampling point, the simulator records the complete current value and the specific conditions at the time, such as operating voltage, temperature, and the degree of process parameter offset affected. In an actual case, under the condition of operating voltage of 1.1V and temperature of 85°C, the current distribution of 10,000 sampling points ranges from 32μA to 347μA, with an average of 185μA and a standard deviation of 58μA.

[0058] After sampling is complete, the system generates a bit line current distribution curve based on the sampling data, divides the sampling interval of 30μA to 350μA into 32 small intervals, counts the number of sampling points in each interval, and forms a frequency distribution histogram. Then the histogram is smoothed by an interpolation algorithm to generate a continuous probability density curve. In this embodiment, the current distribution shows a nearly normal distribution characteristic, but slightly right-skewed, which reflects the asymmetric influence of process variations on current characteristics.

[0059] To enhance the readability of the distribution curve, the system marks key statistical indicators, including the average value of 185μA, the median of 175μA, the maximum value of 347μA, and the minimum value of 32μA. At the same time, the ±3σ range is marked, i.e. 11μA to 359μA, covering 99.7% of the current distribution. These statistical indicators help designers understand the current distribution characteristics and the influence of process variations.

[0060] The finally generated bit line current distribution curve is presented in a graphical manner, with the horizontal axis representing the current value and the vertical axis representing the probability density. The curve shape reflects the current characteristic distribution of the target magnetic core random access memory under given operating voltage and process conditions, providing an important reference for memory design, performance evaluation, and reliability analysis.

[0061] Through the above specific embodiments, the designer can accurately understand and predict the current characteristics of the magnetic core random memory, optimize the circuit design to adapt to process variations, and improve product yield and reliability.

[0062] In an alternative embodiment, extracting the maximum current value and the minimum current value of the bit line current distribution curve, and dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals comprises:

[0063] Extracting the maximum current value and the minimum current value of the bit line current distribution curve, and dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals using an adaptive partitioning algorithm, wherein the adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the difference between the maximum current value and the minimum current value, and the interval width of adjacent current adjustment intervals changes nonlinearly.

[0064] Extracting the maximum current value and the minimum current value of the bit line current distribution curve, and dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals is a key technical step. This embodiment details how to achieve this process using an adaptive partitioning algorithm.

[0065] The bit line current distribution curve is usually obtained from memory array testing. In practical applications, the current detection circuit can be used to scan the current of all bit lines in the memory array, record the current value of each bit line, and generate the current distribution curve. For example, in a memory array containing 1024 bit lines, the measured current distribution range is 75 μA to 125 μA.

[0066] After obtaining the bit line current distribution curve, first perform the extreme value extraction operation, determine the maximum current value Imax and the minimum current value Imin by traversing all current values in the current distribution curve. In the above example, Imax = 125 μA and Imin = 75 μA are extracted.

[0067] Based on the extracted extreme values, calculate the bit line current range ΔI, i.e. ΔI = Imax - Imin. In the example, ΔI = 125 μA - 75 μA = 50 μA. The current range ΔI is a basic parameter for determining the number and width of current adjustment intervals.

[0068] The adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the size of the current range ΔI. The algorithm uses the following strategy: when ΔI is small, such as ΔI < 30 μA, set a small number of intervals; when ΔI is medium, such as 30 μA ≤ ΔI < 70 μA, set a medium number of intervals; when ΔI is large, such as ΔI ≥ 70 μA, set a large number of intervals.

[0069] In this example, ΔI = 50 μA belongs to the medium range, so the algorithm decides to divide the current range into 5 intervals. The dynamic determination of the number of intervals enables the method to adapt to the current distribution characteristics of different memory devices, improving the accuracy and adaptability of the adjustment.

[0070] Unlike traditional uniform division methods, the adaptive partitioning algorithm in this embodiment adopts a non-linearly varying interval width design. The interval width of adjacent current adjustment intervals varies non-linearly, specifically, the interval width gradually increases from the small current value end to the large current value end.

[0071] For the 50 μA current range in the example, the 5 intervals are divided as follows: the first interval is [75 μA, 82 μA], with a width of 7 μA; the second interval is [82 μA, 91 μA], with a width of 9 μA; the third interval is [91 μA, 102 μA], with a width of 11 μA; the fourth interval is [102 μA, 115 μA], with a width of 13 μA; and the fifth interval is [115 μA, 125 μA], with a width of 10 μA.

[0072] This non-linear division takes into account the actual characteristics of the bit line current distribution in the memory device, which generally requires more precise adjustment in the small current value region, and can use wider intervals in the large current value region. In implementation, an exponential function or a polynomial function can be used to calculate the boundary values of each interval, ensuring smooth changes in interval width.

[0073] In order to determine the precise boundaries of each interval, the adaptive partitioning algorithm also analyzes the density characteristics of the current distribution curve. In regions where the current values are more densely concentrated, narrower intervals are divided; in regions where the current values are more sparsely distributed, wider intervals are divided. This strategy ensures a balance between the accuracy and efficiency of current adjustment.

[0074] In specific implementation, the algorithm first counts the number of bit lines in each small current segment to generate a current distribution density curve. For example, in the example, the number of bit lines in each small interval within the range of 75 μA to 125 μA can be counted at a step of 0.5 μA. According to the statistical results, regions with high current distribution density are identified, such as the 85 μA-95 μA region with 40% of the bit lines, and more precise division is used in these regions.

[0075] Considering the differences in characteristics of different memory devices, the algorithm also introduces configurable parameters to optimize interval division, including the number of basic intervals, the non-linear coefficient, and the density weight factor, which can be adjusted according to different models or process memory devices. For example, for high-density memory, the non-linear coefficient can be increased to make the interval width change more significantly.

[0076] After the interval division is completed, the algorithm stores the results in the control register to provide a basis for subsequent bit line current adjustment. Each interval corresponds to a specific adjustment strategy, such as adjusting the voltage size, adjusting the step size, and adjusting the timing parameters, etc. For example, a larger current increase is applied to the bit line of the first interval [75 μA, 82 μA]; while a smaller current decrease is applied to the bit line of the fifth interval [115 μA, 125 μA].

[0077] Through the above adaptive partitioning algorithm, intelligent division of the bit line current adjustment interval is achieved, which can flexibly adjust the number and width of the intervals according to the actual current distribution characteristics, improving the performance consistency and reliability of the memory. This method is especially suitable for bit line current balancing control in large-scale integrated memory devices, effectively solving the problem that traditional fixed interval division methods are difficult to adapt to diversified current distribution.

[0078] In an optional implementation, a storage cell read success rate is calculated in each of the current adjustment intervals, and a median value of the current adjustment interval with the highest storage cell read success rate is selected as the optimal reference current value.

[0079] A median value of each of the current adjustment intervals is taken as a test current value, a storage cell array of a target magnetic core random memory is read using the test current value, a ratio of a successful number of read operations to a total number of test operations is counted to obtain a storage cell read success rate corresponding to each of the current adjustment intervals;

[0080] Each of the current adjustment intervals is sorted according to the storage cell read success rate, and a current adjustment interval with the highest storage cell read success rate is selected, and a median value of the current adjustment interval is determined as the optimal reference current value.

[0081] In practical applications, by calculating the storage cell read success rate in each current adjustment interval and selecting the median value of the current adjustment interval with the highest storage cell read success rate as the optimal reference current value, the read accuracy and stability of the magnetic core random memory can be effectively improved.

[0082] For the target magnetic core random access memory (RAM), multiple current adjustment ranges are defined. For example, the adjustable range of the reference current can be set from 0.5 μA to 10 μA, and then divided into several intervals, such as [0.5 μA, 1.5 μA], [1.5 μA, 2.5 μA], [2.5 μA, 3.5 μA], [3.5 μA, 4.5 μA], [4.5 μA, 5.5 μA], [5.5 μA, 6.5 μA], [6.5 μA, 7.5 μA], [7.5 μA, 8.5 μA], and [8.5 μA, 9.5 μA]. These current adjustment ranges can be determined based on the technical parameters and expected operating conditions of the RAM.

[0083] For each defined current adjustment range, the system calculates the midpoint as the test current value. Taking the above range as an example, the test current values ​​are 1.0μA, 2.0μA, 3.0μA, 4.0μA, 5.0μA, 6.0μA, 7.0μA, 8.0μA, and 9.0μA. The system applies each test current value to the memory cell array of the target magnetic core random access memory for read test operations.

[0084] During testing, a specific test current value is used to perform read operations on multiple memory cells in the memory cell array. To ensure the statistical significance of the test results, the number of tests is usually set to a large value; for example, for an array containing 1024×1024 memory cells, 10,000 memory cells can be randomly selected for testing. The system records the result of each read operation, including the number of successful and failed reads.

[0085] The success criterion for a read operation is that the system can correctly identify the data bit (0 or 1) stored in the memory cell. Read failures include: the inability to identify the stored data bit, or the identified data bit not matching the actual stored data bit. For each test current value, the system calculates the ratio of successful reads to the total number of tests to obtain the memory cell read success rate for the corresponding current adjustment range.

[0086] Assume that the read success rates of the storage cells obtained through actual tests for the above nine current regulation intervals are 76.5%, 85.3%, 92.7%, 97.8%, 99.2%, 98.5%, 95.3%, 89.7%, and 82.1% respectively. The system ranks the current regulation intervals according to these read success rates, from high to low, as follows: [4.5 μA, 5.5 μA] (99.2%), [5.5 μA, 6.5 μA] (98.5%), [3.5 μA, 4.5 μA] (97.8%), [6.5 μA, 7.5 μA] (95.3%), [2.5 μA, 3.5 μA] (92.7%), [7.5 μA, 8.5 μA] (89.7%), [1.5 μA, 2.5 μA] (85.3%), [8.5 μA, 9.5 μA] (82.1%), and [0.5 μA, 1.5 μA] (76.5%).

[0087] The current regulation interval with the highest read success rate of the storage cells, [4.5 μA, 5.5 μA], is selected, which has a read success rate of 99.2%, significantly higher than other intervals. The system determines the median value 5.0 μA of this interval as the optimal reference current value.

[0088] To verify the effectiveness of the selected optimal reference current value, the system can further perform more detailed tests around this current value. For example, tests can be performed in the range of 4.5 μA to 5.5 μA with a step size of 0.1 μA to obtain a more accurate optimal reference current value. Assume that through the detailed tests, it is found that the read success rate at 5.2 μA reaches 99.5%, higher than 99.2% at 5.0 μA, then 5.2 μA can be determined as the final optimal reference current value.

[0089] In actual applications, this optimal reference current value is configured into the read circuit of the target magnetic core random memory. When performing a read operation, the read circuit compares the reference current value with the current generated by the storage cell to determine the data bit stored in the storage cell. Since the current value with the highest read success rate is used as the reference, the system can minimize read errors and improve data reliability.

[0090] For different batches of magnetic core random memories or in different working environments, the optimal reference current value may change. Therefore, the system can perform the above method during the initialization phase of the magnetic core random memory or during regular maintenance to recalculate and update the optimal reference current value. This dynamic adjustment mechanism can adapt to different working conditions and maintain a high read success rate.

[0091] By the above detailed technical implementation, the method can effectively determine the optimal reference current value for the magnetic core random memory, improve the reading accuracy and stability of the memory, reduce data reading errors, prolong the service life of the memory, and enhance the overall reliability and performance of the system.

[0092] In an alternative embodiment, the actual output current of the reference circuit at different temperature points is detected, the deviation between the actual output current and the optimal reference current value is calculated, and the temperature compensation model is established according to the deviation, comprising:

[0093] In a preset temperature range, the reference circuit is subjected to multi-point temperature scanning, the actual output current at each temperature point is collected, the deviation between the actual output current and the optimal reference current value is calculated, and a temperature-current response model is established according to the correspondence between the temperature points and the deviation.

[0094] When the reference circuit is subjected to multi-point temperature scanning in a preset temperature range, the temperature range can be set to -40℃ to 125℃, which is a commonly used industrial temperature range for electronic devices. In this temperature range, the temperature points are selected for scanning, and the temperature interval can be set to 5℃, i.e. the temperature points of -40℃, -35℃, -30℃... up to 125℃ are measured respectively. To ensure measurement accuracy, high-precision temperature control equipment such as an oven can be used, with a temperature control accuracy of ±0.1℃.

[0095] For each temperature point test, the reference circuit is placed in the oven, and after the temperature is stabilized (usually 15-20 minutes are required), the actual output current is collected using a precision current measuring instrument. The resolution of the precision current measuring instrument should reach the level of 0.01μA to ensure the accuracy of the measurement. For example, at 25℃, the actual output current of the reference circuit is assumed to be 10.25μA.

[0096] After obtaining the actual output current at each temperature point, the deviation from the optimal reference current value needs to be calculated. The optimal reference current value can be determined according to the design specifications, for example, at room temperature 25℃, the optimal reference current value designed is 10.00μA. The deviation is calculated by subtracting the optimal reference current value from the actual output current. Taking the above data as an example, at 25℃, the deviation is 10.25μA - 10.00μA = 0.25μA, i.e. a deviation rate of 2.5%.

[0097] For the measurement results of the full temperature range, a series of data pairs of temperature points and corresponding deviation values can be obtained, for example, the actual current is measured to be 9.50 μA and the deviation is -0.50 μA at -40 °C, the actual current is measured to be 9.85 μA and the deviation is -0.15 μA at 0 °C, the actual current is measured to be 10.25 μA and the deviation is 0.25 μA at 25 °C, the actual current is measured to be 10.75 μA and the deviation is 0.75 μA at 75 °C, and the actual current is measured to be 11.20 μA and the deviation is 1.20 μA at 125 °C.

[0098] According to the collected data pairs of temperature points and corresponding deviations, a temperature-current response model is established. The model can be constructed by using a piecewise linear interpolation method, that is, a linear relationship is used to describe the change relationship between temperature and current deviation between adjacent temperature points. Taking the above data as an example, between -40 °C and 0 °C, the deviation changes from -0.50 μA to -0.15 μA; between 0 °C and 25 °C, the deviation changes from -0.15 μA to 0.25 μA; between 25 °C and 75 °C, the deviation changes from 0.25 μA to 0.75 μA; and between 75 °C and 125 °C, the deviation changes from 0.75 μA to 1.20 μA.

[0099] For the case of a large amount of data, a data processing software can be used to construct the temperature-current response model. By taking temperature as the independent variable and current deviation as the dependent variable, a function model describing the relationship between the two can be obtained. The model can be a polynomial fitting form, and according to the characteristics of the measurement data, different orders of fitting methods such as quadratic polynomial, cubic polynomial, etc. can be selected. For the above measurement data, a quadratic polynomial model describing the relationship between temperature and current deviation can be obtained by fitting.

[0100] To improve the accuracy of the model, the density of temperature scanning can be increased, and the temperature interval can be reduced to 2 °C in the temperature range where the current changes sharply, such as the extremely low temperature range, such as -40 °C to -20 °C, and the high temperature range, such as 100 °C to 125 °C, to obtain more detailed data. For example, in the range of -40 °C to -20 °C, measurements can be taken at temperature points of -40 °C, -38 °C, -36 °C, etc.

[0101] The established temperature-current response model needs to be verified for its accuracy. Temperature points not involved in the model establishment can be selected, such as -25 °C, 15 °C, 50 °C, 100 °C, etc. The actual output current at these temperature points is measured and compared with the predicted value of the model. If the error between the predicted value and the actual measured value is within an acceptable range, usually ±1%, it is proved that the accuracy of the model meets the requirements.

[0102] After the temperature-current response model is established, it can be used to guide the design of the compensation circuit. According to the current deviation at different temperatures predicted by the model, a corresponding compensation network can be designed to offset the influence of temperature change. For example, in view of the trend of current increase in the high temperature region shown by the above model, a compensation circuit with negative temperature coefficient can be designed to provide an adjustment in the opposite direction when the temperature rises.

[0103] According to the characteristics of the reference circuit, the compensation network can be designed to be bipolar, that is, to provide compensation in different directions in the low temperature region and the high temperature region. For example, when the temperature is lower than 25℃, the compensation network provides positive compensation to increase the output current; when the temperature is higher than 25℃, it provides negative compensation to reduce the output current, thereby maintaining the stability of the output current in the entire temperature range.

[0104] Through the above detailed temperature scanning, data acquisition, deviation calculation and model establishment process, the current output characteristics of the reference circuit at different temperatures can be accurately described, providing a reliable basis for subsequent temperature compensation, ensuring that the reference circuit can provide an output close to the optimal reference current value in the full temperature range, meeting the needs of high-precision applications.

[0105] In an optional implementation, the compensation circuit is designed based on the temperature compensation model, the compensation circuit is converted into a layout design file, and the design of the target magnetic random access memory read reference circuit includes:

[0106] According to the temperature compensation model, the structure parameters and device parameters of the compensation circuit are determined, and the compensation circuit is divided into a temperature detection module and a compensation control module.

[0107] According to the structure of the compensation circuit, a device layout scheme is generated, and the layout positions of the temperature detection module and the compensation control module are optimized, and the layout design of the target magnetic random access memory read reference circuit is completed.

[0108] When designing the compensation circuit based on the temperature compensation model, the structure parameters and device parameters of the compensation circuit are determined according to the temperature compensation model. The temperature compensation model describes the resistance variation characteristics of the magnetic random access memory read reference circuit at different temperatures. The temperature compensation model establishes a relationship model between temperature and resistance variation rate by measuring the resistance variation of a standard sample in the temperature range of-40℃ to 125℃. For example, in actual testing, when the temperature rises from 25℃ to 85℃, the magnetic tunnel junction resistance decreases by an average of 15.3%, and when the temperature decreases to-20℃, the resistance increases by an average of 11.7%.

[0109] The compensation circuit is divided into two functional modules: temperature detection module and compensation control module. The temperature detection module adopts PN junction temperature sensor design, which utilizes the negative correlation between the forward voltage of silicon diode and temperature. In the specific implementation, two identical diodes D1 and D2 are adopted, and different current densities are passed through them, usually in a ratio of 1:8. The voltage difference ΔV between the two ends of the diode is measured, which is proportional to the absolute temperature. The temperature detection module uses a bandgap reference circuit to provide a stable reference current. When the current density ratio is 1:8, the temperature coefficient is about -2 mV / ℃. At room temperature 25℃, the measured ΔV is 198 mV; at 85℃, ΔV increases to 318 mV; at -20℃, ΔV decreases to 142 mV, achieving a detection accuracy of ±1℃.

[0110] The compensation control module adopts an adjustable current source structure, which adjusts the operating current of the read reference circuit according to the voltage signal output by the temperature detection module. This module includes a voltage-to-current conversion circuit and a current distribution circuit. The voltage-to-current conversion circuit is composed of an operational amplifier and a MOSFET, which converts the temperature detection voltage into a control current proportional to temperature. The current distribution circuit uses a current mirror structure to increase the read current at high temperature and decrease the read current at low temperature according to the magnetic tunnel junction temperature characteristic curve. In the specific design, the read current is set to 50μA at the reference temperature of 25℃; when the temperature rises to 85℃, the current automatically increases to 57.6μA to compensate for the signal attenuation caused by the decrease of resistance; when the temperature drops to -20℃, the current decreases to 44.2μA to adapt to the increase of resistance.

[0111] In the device parameter design of the compensation circuit, the diode of the temperature detection module is selected with a PN junction area of 10μm×10μm, and the bias currents are set to 10μA and 80μA respectively. The operational amplifier is selected with a low offset voltage type, with an offset voltage less than 0.5mV and a common-mode rejection ratio greater than 80dB. The current mirror of the compensation control module uses well-matched PMOS transistors, and the transistor size ratio is accurately designed according to the temperature-resistance curve, with a W / L ratio of 3.5% for every 10℃ change in temperature. All transistors are designed with long channel to reduce channel modulation effect and improve current replication accuracy.

[0112] According to the determined compensation circuit structure, a device layout scheme is generated, and the layout design adopts a symmetrical layout technique, focusing on optimizing the layout position of the temperature detection module and the compensation control module. The temperature detection module is laid out on the periphery of the magnetic core cell array, maintaining a proper distance from the storage cell to avoid the influence of heat generated by storage operation on temperature detection accuracy. The detection diode adopts a concentric ring structure to reduce the influence of gradient temperature, and the distance between the two diodes is kept within 50μm to ensure the perception of the same temperature.

[0113] The compensation control module is arranged near the read reference circuit, reducing the length of signal transmission line and lowering parasitic effects. The current mirror transistor is arranged in a cross-finger structure, improving matching accuracy. The area ratio of the core transistors of the current mirror is designed to be 1:1.153:0.847, corresponding to the compensation requirements at temperature ranges of -40℃, 25℃ and 125℃. Key matching devices are designed in a dumbbell structure and a guard ring, reducing the influence of stress effects and edge effects.

[0114] During the layout optimization process, the analog circuit part is isolated by a guard ring to prevent noise coupling from the digital circuit. The power supply line is arranged separately with wide metal wiring to reduce the influence of IR drop. An isolation area is left around the temperature sensor part to avoid the influence of heat sources. Key signal lines are arranged in a differential distribution line to improve anti-interference capability. After the layout is completed, DRC and LVS checks are performed to ensure that the layout is consistent with the circuit design.

[0115] After layout implementation and simulation verification, the compensation circuit can control the temperature drift of the read reference circuit within ±3.5% in the temperature range of -40℃ to 125℃, meeting the requirements of stable operation of the magnetic core random access memory in a wide temperature range. Actual tests show that after the introduction of the compensation circuit, the read window margin is improved from 15% to 26% in the full temperature range, effectively improving the reliability of the memory at extreme temperatures, and reducing the error rate from the order of 10^-6 to the order of 10^-9.

[0116] As shown in Figures 2-4 , the method comprises:

[0117] The reference circuit is implemented in a combination of MTJ resistors and polysilicon resistors. A reference resistor is composed of an RP state MTJ and a polysilicon resistor R0. The RP state MTJ and the NMOS transistor are implemented in one column of storage units in the array. The RP state MTJ resistor used for reference can be well matched with the MTJ in the array, both of which have nearly the same process corner variation characteristics. The resistance R0 is adjusted by trimming technology to equal half the sum of RAP and RP at the process corner.

[0118] For example: the storage array adopts a structure of 512 word lines and 1056 bit lines, and is configured with 32 IOs, each IO containing 33 bit lines. The storage unit is composed of an NMOS transistor connected with an MTJ. The NMOS gate of each row is connected with the same word line, and each column of storage units is connected with the same bit line and source line. The RP state MTJ in the reference resistor is placed in the storage array, and each IO is equipped with a column of RP state MTJs for reference. The reference MTJ column is located at one quarter of the edge number of a single IO, so that the bit lines of each column of storage units and the corresponding reference units are connected to the transverse wiring of the input of the sensitive amplifier with the smallest distance difference.

[0119] The reference MTJ is consistent with the structure of the memory cell, and is selected by a MOS transistor, the gate of the MOS transistor is connected with the word line of the same row of memory cells. When reading the memory cell at a position, the reference MTJ at the corresponding position is selected. When reading the near-end cell 0, the WL0 and the reference MTJ0 are selected, and when reading the far-end cell 511, the WL511 and the reference MTJ511 are selected. The structure makes the reference cell and the memory cell have the same bit line and source line parasitic resistance in the read path. At the same time, the unselected memory cells and the reference MTJ on the same bit line have similar leakage currents.

[0120] In the read topology circuit, the memory cell and the reference circuit are connected with the two input ends of the sensitive amplifier through the clamping tubes M0 and M1. The clamping tubes M0 and M1 clamp the potentials of the nodes BL and BLR to the read voltage, and SL and SLR are grounded. The read current is consistent with the direction of the RP state, which avoids the read interference of the MTJ in the traditional reference circuit composed of the RAP state and the RP state. The read timing is divided into three stages of pre-charge, development and amplification output. In the pre-charge stage, the M3 and M4 tubes are opened to charge the SAIP and SAIN nodes to the same potential. In the development stage, the M3 and M4 tubes are closed, and the BL and BLR nodes are clamped to the same read voltage through the clamping voltage VCLAMP. The different resistances of the two branches result in different discharging speeds of the SAIP and SAIN nodes, and a potential difference is formed. In the amplification output stage, the sensitive amplifier amplifies the weak signal difference between the SAIP and SAIN nodes, and outputs the data through the latch signal.

[0121] The initialization of the reference circuit is realized by controlling the memory cell write circuit. The initialization circuit connects the low-dropout linear regulator to the N node of the reference circuit through a MOS tube. In the initialization process, the M1 tube is closed, the VINIT signal is controlled to open the M2 tube, the corresponding word line is opened, and the MTJ in the reference circuit is written into the RP state. The specific initialization process is as follows: the VCLAMP is pulled low to turn off the M0 and M1, the word line and the M2 tube are opened, the write voltage is applied to the N node, and the initialization is completed by being maintained for a certain period of time.

[0122] The design scheme introduces the leakage current similar to the bit line in the reference path, which offsets the influence of most leakage currents on the read window. The parasitic resistance of the reference cell end and the memory cell end is the same in each read process, which offsets the influence of the parasitic resistance on the read window. Only the RP state MTJ is needed in the reference circuit, and the reference circuit is arranged in a separate column in the memory array, which simplifies the initialization process and avoids the read interference problem through the design of the read current direction.

[0123] In a second aspect of the embodiment of the application, a magnetic core random memory read reference circuit design system is provided, comprising:

[0124] The first unit is configured to acquire a parameter specification of a target magnetic core random access memory, and generate a bit line current distribution curve according to the parameter specification by using a random access memory performance simulator.

[0125] The second unit is configured to extract a maximum current value and a minimum current value of the bit line current distribution curve, divide a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculate a storage unit read success rate in each of the current adjustment intervals, and select a median value of a current adjustment interval with a highest storage unit read success rate as an optimal reference current value.

[0126] The third unit is configured to detect an actual output current of a reference circuit at different temperature points, calculate a deviation between the actual output current and the optimal reference current value, establish a temperature compensation model according to the deviation, design a compensation circuit based on the temperature compensation model, convert the compensation circuit into a layout design file, and complete the design of the target magnetic core random access memory read reference circuit.

[0127] In a third aspect, an electronic device is provided, comprising:

[0128] a processor;

[0129] a memory for storing processor-executable instructions;

[0130] The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0131] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0132] The present application can be a method, device, system and / or computer program product. The computer program product can include a computer-readable storage medium having computer-readable program instructions loaded thereon, which are used to execute various aspects of the present application.

[0133] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for designing a read reference circuit for a magnetic core random access memory, characterized in that, include: Obtain the parameter specifications of the target magnetic core random access memory, and generate a bit line current distribution curve based on the parameter specifications using a random access memory performance simulator; Extract the maximum and minimum current values ​​from the bit line current distribution curve, divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals, calculate the memory cell read success rate in each current adjustment interval, and select the median of the current adjustment interval with the highest memory cell read success rate as the optimal reference current value. The actual output current of the reference circuit at different temperature points is detected, the deviation between the actual output current and the optimal reference current value is calculated, and a temperature compensation model is established based on the deviation. A compensation circuit is designed based on the temperature compensation model, and the compensation circuit is converted into a layout design file to complete the design of the target magnetic core random access memory read reference circuit.

2. The method according to claim 1, characterized in that, Based on the aforementioned parameter specifications, a bitline current distribution curve is generated using a random access memory performance simulator, including: The parameter specifications include the operating voltage range and process parameters. A current sampling window is established based on the operating voltage range. The sampling interval of the current sampling window is adaptively adjusted through an iterative optimization algorithm until the sampling interval covers the maximum and minimum operating current of the target magnetic core random access memory. A random access memory performance simulator is used to perform Monte Carlo current sampling on the memory cell array of the target magnetic core random access memory according to the sampling interval and the number of sampling points, and to generate bit line current distribution curves.

3. The method according to claim 1, characterized in that, Extract the maximum and minimum current values ​​from the bit line current distribution curve, and divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals, including: The maximum and minimum current values ​​of the bit line current distribution curve are extracted, and an adaptive partitioning algorithm is used to divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals. The adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the difference between the maximum and minimum current values, and the interval width of adjacent current adjustment intervals changes non-linearly.

4. The method according to claim 1, characterized in that, Within each current adjustment range, the memory cell read success rate is calculated, and the median of the current adjustment range with the highest memory cell read success rate is selected as the optimal reference current value, including: The median value of each current adjustment range is used as the test current value. The test current value is used to perform a read operation on the memory cell array of the target magnetic core random access memory. The ratio of the number of successful read operations to the total number of tests is calculated to obtain the memory cell read success rate corresponding to each current adjustment range. Each current adjustment interval is sorted according to the success rate of the memory cell read, and the current adjustment interval with the highest success rate of the memory cell read is selected. The median value of this current adjustment interval is determined as the optimal reference current value.

5. The method according to claim 1, characterized in that, Detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, and establishing a temperature compensation model based on the deviation includes: Multi-point temperature scanning is performed on the reference circuit within a preset temperature range. The actual output current at each temperature point is collected, and the deviation between the actual output current and the optimal reference current value is calculated. Based on the correspondence between the temperature point and the deviation, a temperature-current response model is established.

6. The method according to claim 1, characterized in that, Based on the temperature compensation model, a compensation circuit is designed. This compensation circuit is then converted into a layout design file. The design of the target magnetic core random access memory read reference circuit includes: Based on the temperature compensation model, the structural and device parameters of the compensation circuit are determined, and the compensation circuit is divided into a temperature detection module and a compensation control module. Based on the structure of the compensation circuit, generate a device layout scheme, optimize the layout positions of the temperature detection module and the compensation control module, and complete the layout design of the target magnetic core random access memory read reference circuit.

7. A magnetic core random access memory read reference circuit design system for implementing the method of any one of claims 1-6, characterized in that, include: The first unit is used to obtain the parameter specifications of the target magnetic core random access memory, and generate a bit line current distribution curve based on the parameter specifications through a random access memory performance simulator. The second unit is used to extract the maximum and minimum current values ​​of the bit line current distribution curve, divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals, calculate the memory cell read success rate in each current adjustment interval, and select the median of the current adjustment interval with the highest memory cell read success rate as the optimal reference current value. The third unit is used to detect the actual output current of the reference circuit at different temperature points, calculate the deviation between the actual output current and the optimal reference current value, establish a temperature compensation model based on the deviation, design a compensation circuit based on the temperature compensation model, convert the compensation circuit into a layout design file, and complete the design of the target magnetic core random access memory read reference circuit.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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