Memory cell including electrochemical memory element and semiconductor device including same

Abstract

The invention relates to a memory cell including an electrochemical memory element and a semiconductor device including the same. A semiconductor device includes an electrochemical storage element and a control element electrically connected to each other. An electrochemical memory element includes a source line disposed on a plane, a bit line disposed spaced apart from the source line and extending in a direction perpendicular to the plane, a memory channel layer disposed to be connected to the source line and the bit line on the plane, an electrolyte layer disposed on the memory channel layer, an ion storage layer disposed on the electrolyte layer; and a floating gate electrode layer disposed on the ion storage layer. The control element includes a control channel structure disposed on the floating gate electrode layer, a control source line disposed on the control channel structure, a control gate dielectric layer disposed on a side surface of the control channel structure, and a control word line disposed on the control gate dielectric layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0059466, filed on May 3, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a memory cell and a semiconductor device including the memory cell, and more specifically, to a memory cell including an electrochemical memory element and a semiconductor device including the memory cell. Background Technology

[0004] Electrochemical storage devices are emerging as an example of non-volatile storage devices. These devices include an ion receiver layer and an ion supply layer, as well as an electrolyte layer disposed between the ion receiver layer and the ion supply layer.

[0005] Electrochemical storage devices allow ions to exchange between an ion-receiving layer and an ion-supplying layer in response to external stimuli. These devices utilize the resistive properties of the ion-receiving layer to store signal information; these properties vary depending on the concentration of ions within the layer. Since the resistance of the ion-receiving layer is inversely proportional to the ion concentration, electrochemical storage devices can achieve multi-level signals by employing different resistance states of the ion-receiving layer as signal information. Recently, research has been conducted to increase the density of storage cells by reducing the size of electrochemical storage devices. Summary of the Invention

[0006] A memory cell according to an embodiment of the present disclosure may include an electrochemical memory element and a control element electrically connected to each other. The electrochemical memory element may include a source line disposed on a plane, a bit line disposed spaced from the source line and extending in a direction perpendicular to the plane, a memory channel layer disposed on the plane to connect the source line and the bit line, an electrolyte layer disposed on the memory channel layer, an ion storage layer disposed on the electrolyte layer, and a floating gate electrode layer disposed on the ion storage layer. The control element may include a control channel structure disposed on the floating gate electrode layer, a control source line disposed on the control channel structure, a control gate dielectric layer disposed on a side surface of the control channel structure, and a control word line disposed on the control gate dielectric layer.

[0007] A semiconductor device according to an embodiment of the present disclosure may include: a substrate; a bit line extending along a first direction perpendicular to a surface of the substrate; and a plurality of memory cells sharing the bit line and configured to be spaced apart from each other on the substrate in the first direction. Each of the plurality of memory cells may include an electrochemical storage element. The electrochemical storage element may include: a source line configured to extend along a second direction in a plane perpendicular to the first direction on the substrate; a storage channel layer configured to electrically connect the source line to the bit line on the plane; an electrolyte layer disposed on the storage channel layer; an ion storage layer disposed on the electrolyte layer; and a floating gate electrode layer disposed on the ion storage layer.

[0008] A semiconductor device according to another embodiment of this disclosure may include: a substrate; a first bit line and a second bit line extending along a first direction perpendicular to a surface of the substrate; and a pair of memory cells electrically connected to corresponding bit lines of the first and second bit lines and configured to be spaced apart from each other. Each of the pair of memory cells may include an electrochemical storage element. The electrochemical storage element may include: a source line configured to extend along a second direction on a plane perpendicular to the first direction over the substrate; a storage channel layer configured to electrically connect the source line to the bit line on the plane; an electrolyte layer disposed on the storage channel layer; an ion storage layer disposed on the electrolyte layer; and a floating gate electrode layer disposed on the ion storage layer. The source lines of the pair of memory cells may be electrically connected to each other. Attached Figure Description

[0009] Figure 1 This is a circuit diagram of a storage unit according to an embodiment of the present disclosure.

[0010] Figure 2 A schematic cross-sectional view of a storage cell according to an embodiment of the present disclosure is provided.

[0011] Figure 3 and Figure 4 A schematic cross-sectional view illustrating an operation method of a storage cell according to an embodiment of the present disclosure.

[0012] Figure 5 and Figure 6 The graph illustrating the conductivity of the storage channel layer relative to the write voltage applied to the storage cell according to an embodiment of the present disclosure is shown for illustrative purposes.

[0013] Figure 7 and Figure 8 This is a circuit diagram of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 9 A schematic cross-sectional view is provided to illustrate a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 10 To show Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line I-I'.

[0016] Figure 11 It is shown Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line II-II'.

[0017] Figure 12 It is shown Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line III-III'.

[0018] Figure 13 It is shown Figure 9 A diagram of a semiconductor device shown along line IV-IV' and plotted on the xy plane.

[0019] Figure 14 This is a circuit diagram of a semiconductor device according to another embodiment of the present disclosure.

[0020] Figure 15 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0021] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 17 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0023] Figures 18 to 20 This is a schematic cross-sectional view illustrating the arrangement of memory cells in a semiconductor device according to various embodiments of the present disclosure. Detailed Implementation

[0024] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (such as the width and thickness of the components) are enlarged to clearly illustrate the components of each device. The terminology used herein may correspond to words chosen with regard to their function in the embodiments, and the meaning of the terms may be interpreted differently by those skilled in the art to which the embodiments pertain. If a term is explicitly and specifically defined, it may be interpreted according to the definition. Unless otherwise defined, the terminology used herein (including technical and scientific terms) has the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0025] Furthermore, unless explicitly used otherwise in the context, the singular form of a word should be understood to include the plural form. It should be understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, number, step, operation, component, element, part, or combination thereof, but are not intended to exclude the presence or possible addition of one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0026] The terminology used in this application specification is chosen with reference to the functionality of the presented embodiments, and the meaning of the term may vary depending on the intent or practice of users or operators in the art. The meaning of the terminology used follows the definition as defined herein, and in the absence of a specific definition, may be interpreted as meaning commonly accepted by those skilled in the art.

[0027] Figure 1 This is a circuit diagram of a memory cell according to an embodiment of the present disclosure. (See reference...) Figure 1 The memory cell MC includes a control element CT and an electrochemical memory element ECM, which are electrically connected to each other. The control element CT can be a field-effect transistor device, which is turned on according to a gate signal applied to the control gate electrode CG. The control element CT transmits the voltage of the control source line CSL to the floating gate electrode FG of the electrochemical memory element ECM. The electrochemical memory element ECM can be a non-volatile memory device, which stores signal information in the channel CH of the transistor device according to the write voltage applied to the floating gate electrode FG.

[0028] See Figure 1 The control element CT includes a control gate electrode CG electrically connected to the control word line CWL, a control source electrode ST electrically connected to the control source line CSL, a control drain electrode DT electrically connected to the floating gate electrode FG of the electrochemical storage element ECM, and a control channel CCH between the control source electrode ST and the control drain electrode DT.

[0029] The electrochemical storage element ECM includes a floating gate electrode FG electrically connected to the control drain electrode DT of the control element CT, a source electrode SE electrically connected to the source line SL, a drain electrode DE electrically connected to the bit line BL, and a storage channel CH located between the source electrode SE and the drain electrode DE. The storage channel CH can be used as a storage layer to store the signal information of the storage cell MC.

[0030] In this embodiment, the write operation of the memory cell MC can be performed as follows. Based on the voltage signal applied to the control word line CWL, the control element CT (which is a field-effect transistor) is turned on or off. When the control element CT is on, the voltage of the control source line CSL is applied to the floating gate electrode FG of the electrochemical memory element ECM through the control source electrode ST, the control channel CCH, and the control drain electrode DT. During the write operation, ground voltage is applied to the source electrode SE and the drain electrode DE of the electrochemical memory element ECM.

[0031] In one embodiment, the control element CT is an N-type field-effect transistor. When a positive gate voltage is applied from the control word line CWL to the control gate electrode CG of the control element CT, the control element CT is turned on. While the control element CT is turned on, when a positive control voltage is applied to the control source line CSL, a first positive write voltage is applied to the floating gate electrode FG. While the control element CT is turned on, when a negative control voltage is applied to the control source line CSL, a second negative write voltage is applied to the floating gate electrode FG.

[0032] In another embodiment, the control element CT is a P-type field-effect transistor. When a negative gate voltage is applied from the control word line CWL to the control gate electrode CG of the control element CT, the control element CT is turned on. While the control element CT is turned on, when a positive control voltage is applied to the control source line CSL, a first positive write voltage is applied to the floating gate electrode FG. While the control element CT is turned on, when a negative control voltage is applied to the control source line CSL, a second negative write voltage is applied to the floating gate electrode FG.

[0033] When the first write voltage is applied to the floating gate electrode FG, according to the following reference Figure 3 The described operating method allows for an increase in the conductivity value of the storage channel CH of the electrochemical storage element ECM. This increased conductivity value of the storage channel CH is maintained even after the control element CT is turned off. The increased conductivity value can be stored as a first signal information in the electrochemical storage element ECM of the storage cell MC. When a second write voltage is applied to the floating gate electrode FG, according to reference... Figure 4 The described operating method allows for a reduction in the conductivity value of the storage channel CH of the electrochemical storage element ECM. This reduced conductivity value of the storage channel CH is maintained even after the control element CT is turned off. This reduced conductivity value of the storage channel CH can be stored as a second signal in the electrochemical storage element ECM of the storage cell MC.

[0034] According to embodiments of this disclosure, each of the first write voltage and the second write voltage can be applied in the form of a pulsed voltage via the control word line CWL and the control source line CSL of the control element CT. As described later, the conductivity value of the storage channel CH of the electrochemical storage element ECM can vary linearly according to the number of pulsed voltages. Therefore, the electrochemical storage element ECM can use multiple different channel conductivities that vary linearly to store multi-level signal information.

[0035] In one embodiment, arithmetic operations on the memory cell MC can be performed as follows. With the control element CT off, a predetermined source voltage is applied to the source line SL. The source voltage input to the source electrode SE is multiplied by the conductivity value of the storage channel CH and output to the bit line BL in the form of a bit line current. Therefore, arithmetic operations can be performed on the signal information stored in the electrochemical storage element ECM of the memory cell MC.

[0036] The various embodiments of this disclosure described below include those having Figure 1 The circuit configuration includes a memory cell and a semiconductor device comprising the memory cell. The memory cell may have a structure in which electrochemical storage elements and control elements are stacked in three dimensions on a substrate. The semiconductor device may have a three-dimensional structure in which memory cells are sequentially stacked on a substrate.

[0037] Figure 2 A schematic cross-sectional view of a storage cell according to an embodiment of the present disclosure is shown. See also... Figure 2 The memory cell M includes an electrochemical memory element (ECMD) and a control element (CTD) electrically connected to each other. The ECMD includes a source line 501, a memory channel layer 110, and a bit line 502 disposed on a plane 101S of the substrate 101. The source line 501 and bit line 502 can be conductive patterned structures. Furthermore, the ECMD includes an electrolyte layer 120 disposed on the memory channel layer 110, an ion storage layer 130 disposed on the electrolyte layer 120, and a floating gate electrode layer 140 disposed on the ion storage layer 130. The CTD includes a control channel structure 150 disposed on the floating gate electrode layer 140 of the ECMD, and a control source line 503 disposed on the control channel structure 150. Additionally, the CTD includes a control gate dielectric layer (not shown) disposed on a side surface of the control channel structure 150 and a control word line 504 configured to cover the control gate dielectric layer.

[0038] See Figure 2The substrate 101 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, and indium gallium zinc oxide (IGZO), or combinations of two or more thereof. The substrate 101 may be doped with n-type or p-type dopants to have a predetermined conductivity. Although not shown, the substrate 101 includes well regions doped with n-type or p-type dopants.

[0039] A storage channel layer 110 is disposed on a plane 101S of the substrate 101. The storage channel layer 110 includes ions that can exchange with the ion storage layer 130. The ions may include, for example, hydrogen (H) ions, lithium (Li) ions, sodium (Na) ions, potassium (K) ions, oxygen (O) ions, or combinations of two or more thereof. Furthermore, the storage channel layer 110 may include a material that receives ions. Examples of materials that can receive ions include metals, metal oxides, metal chalcogenides, polysilicon, or combinations of two or more thereof.

[0040] refer to Figure 2 Source line 501 and bit line 502 are disposed on surface 101S of substrate 101. Source line 501 and bit line 502 are each electrically connected to corresponding ends of opposite sides of storage channel layer 110. Both source line 501 and bit line 502 may include conductive material. Conductive material may include, for example, doped semiconductor material, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide. Conductive material may include, for example, n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more thereof.

[0041] Source line 501 and bit line 502 can be linear conductive patterns extending in different directions. Bit line 502 can include a pattern structure extending along a first direction (i.e., the z-direction) perpendicular to plane 101S. Source line 501 can include a pattern structure extending along a second direction (i.e., the y-direction) perpendicular to the first direction on plane 101S. Figure 2 In this configuration, source line 501 and bit line 502 are configured to contact the memory channel layer 110, but this disclosure is not necessarily limited to this. Other conductive layers may be added between source line 501 and memory channel layer 110 and / or between bit line 502 and memory channel layer 110.

[0042] See Figure 2, The electrolyte layer 120 is disposed on the storage channel layer 110. The electrolyte layer 120 provides a path for ions to move between the storage channel layer 110 and the ion storage layer 130. Specifically, when an electric field is formed between the storage channel layer 110 and the floating gate electrode layer 140, the ions in the ion storage layer 130 can pass through the electrolyte layer 120 and move to the storage channel layer 110, or the ions in the storage channel layer 110 can pass through the electrolyte layer 120 and move to the ion storage layer 130. The electrolyte layer 120 can be formed of a variety of materials depending on the type of ions. As described below, the electrolyte layer 120 can include a variety of materials depending on the material of the ion storage layer 130.

[0043] In Figure 2 Among them, the electrolyte layer 120 and the storage channel layer 110 are arranged to completely overlap each other in the z direction, but the present disclosure is not necessarily limited thereto. In some other embodiments, the electrolyte layer 120 and the storage channel layer 110 can be arranged to partially overlap each other in the z direction. In some other embodiments, the electrolyte layer 120 can be arranged to cover at least a part of the upper surface of the storage channel layer 110 and also the source line 501. In some other embodiments, different from the illustration of Figure 2 , the electrolyte layer 120 can be arranged to be separated from the source line 501 and the bit line 502 in the lateral direction (e.g., the x direction). Therefore, the electrolyte layer 120 can be kept in a non-contact state not only with the source line 501 but also with the bit line 502.

[0044] See Figure 2 , The ion storage layer 130 is disposed on the electrolyte layer 120. The ion storage layer 130 can include ions that move between layers. When an electric field is formed between the storage channel layer 110 and the floating gate electrode layer 140, the ion storage layer 130 can provide ions to the storage channel layer 110 or can receive ions from the storage channel layer 110.

[0045] In an embodiment, the ion storage layer 130 can include, for example, palladium hydride, magnesium hydride, yttrium hydride, hydrogen-containing silicon, hydrogen-containing gallium arsenide, or a combination of two or more of them. The electrolyte layer 120 can include a proton exchange polymer, a metal-organic framework, sulfonated graphene, a polymer-graphene composite, or a combination of two or more of them. In addition, the storage channel layer 110 can include palladium (Pd), magnesium (Mg), yttrium (Y), or a combination of two or more of them.

[0046] In another embodiment, the ion storage layer 130 can include, for example, Li x MO2 (0 < x ≤ 1, where M includes at least one of titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), and nickel (Ni)), Na xMO₂(0 < x ≤ 1, where M includes at least one of iron (Fe), cobalt (Co), manganese (Mn), nickel (Ni), and copper (Cu)), K x MnO₂(0 < x ≤ 1), K x CoO₂(0 < x ≤ 1), or a combination of two or more thereof. The electrolyte layer 120 may include, for example, lithium phosphorus oxynitride (LiPON), sulfonated tetrafluoroethylene - based fluoropolymer - copolymer, polystyrene - based film, sulfonated polyimide (SPI) - based film, polyphosphazene - based film, polybenzimidazole (PBI) - based film, or a combination of two or more thereof. In addition, the storage channel layer 110 may include, for example, tungsten oxide (WO₃), molybdenum sulfide (MoS₂), tungsten sulfide (WS₂), tin sulfide (SnS₂), or a combination of two or more thereof.

[0047] In another embodiment, the ion storage layer 130 may include gadolinium oxide (GdO x (0 < x ≤ 1)), molybdenum oxide (MoO x (0 < x ≤ 1)), tungsten oxide (WO 3-x (0 < x ≤ 1)), copper oxide (CuO), titanium oxide (TiO₂), or a combination of two or more thereof. The electrolyte layer 120 may include, for example, hafnium oxide (HfO₂), zirconium oxide (ZrO₂), yttria - stabilized zirconia (YSZ), barium - cerium - yttrium oxide (Ba - Ce - Y - O), zirconium - scandium oxide (Zr - Sc - O), or a combination of two or more thereof. In addition, the storage channel layer 110 may include, for example, tungsten oxide (WO₃), molybdenum oxide (MoO₃), cerium oxide (CeO₃), iron oxide (Fe₃O₄), zirconium oxide (ZrO₂), cobalt oxide (CoO), vanadium pentoxide (V₂O₅), titanium oxide (TiO₂), strontium titanate (SrTiO₃), yttrium oxide (Y₂O₃), or a combination of two or more thereof.

[0048] In Figure 2 , the ion storage layer 130 and the electrolyte layer 120 are arranged to completely overlap each other in the z - direction, but the present disclosure is not necessarily limited thereto. In some embodiments, the ion storage layer 及电解质层120 may be arranged to partially overlap each other in the z - direction. In addition, in Figure 2 , the figure shows the ion storage layer 130 in contact with the bit line 502, but the present disclosure is not necessarily limited thereto. In some embodiments, the ion storage layer 130 may be disposed on the electrolyte layer 120 and spaced apart from the bit line 502 in the lateral direction (e.g., the x - direction). Thus, the ion storage layer 130 may be kept in a non - contact state with the bit line 502.

[0049] Reference Figure 2A floating gate electrode layer 140 is disposed on the ion storage layer 130. The floating gate electrode layer 140 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0050] The floating gate electrode layer 140 is configured to be spaced apart from and electrically insulated from the bit line 502 in the lateral direction (e.g., the x-direction). Figure 2 In the diagram, the floating gate electrode layer 140 is shown to completely overlap with the ion storage layer 130 in the z-direction, but this disclosure is not necessarily limited to this. The floating gate electrode layer 140 may be configured to partially overlap with the ion storage layer 130 in the z-direction.

[0051] refer to Figure 2 The control channel structure 150 of the control element CTD is disposed on the floating gate electrode layer 140 of the electrochemical storage element ECMD. The control channel structure 150 of the control element CTD can be stacked on the floating gate electrode layer 140 in the z-direction. The control channel structure 150 may include a pillar structure connecting the floating gate electrode layer 140 to the control source line 503. The pillar structure may have the shape or structure of a polygonal pillar, a cylinder, or an elliptical pillar.

[0052] The control channel structure 150 is configured to overlap with the floating gate electrode layer 140 in a first direction (i.e., the z-direction). The control channel structure 150 is configured to be spaced apart from the bit line 502 in a lateral direction (e.g., the x-direction). Therefore, the control channel structure 150 is electrically insulated from the bit line 502.

[0053] The control channel structure 150 may include, for example, a semiconductor material, a conductive metal oxide, a transition metal chalcogenide, or a combination of two or more thereof. The control channel structure 150 may have n-type semiconductor characteristics or p-type semiconductor characteristics.

[0054] As an example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or a combination of two or more thereof. The semiconductor material may include n-type or p-type dopants. As another example, the conductive metal oxide may include indium oxide (In₂O₃), indium gallium zinc oxide (InGaZnO₄), zinc oxide (ZnO), indium gallium oxide (InGaO₃), or a combination of two or more thereof. The conductive metal oxide may include dopants. Dopants may include titanium (Ti), tungsten (W), silicon (Si), or a combination of two or more thereof.

[0055] A control source line 503 is disposed on the control channel structure 150. In one embodiment, the control source line 503 is disposed on the control channel structure 150 in the z-direction. The control source line 503 may be a linear conductive pattern extending in one direction. In one embodiment, the control source line 503 may include a pattern structure extending in a second direction (i.e., the y-direction) in a plane perpendicular to the first direction (i.e., the z-direction). The control source line 503 may include a conductive material substantially the same as the conductive material described for the source line 501 or bit line 502.

[0056] A control gate dielectric layer (not shown) is disposed on a side surface of the control channel structure 150. As an example, the control gate dielectric layer may be disposed in the xz plane. The control gate dielectric layer is configured to have a predetermined thickness on its side surface in the second direction (i.e., the y-direction). A control word line 504 is disposed on the control gate dielectric layer along the second direction (i.e., the y-direction). The control gate dielectric layer may be configured to be covered by the control word line 504. The arrangement of the control gate dielectric layer and the control word line 504 will be described below. Figure 11 The arrangement of the control gate dielectric layers 1600, 1600', 2600 and 2600' and the control word lines 2030 and 2030' will be described in more detail.

[0057] A control gate dielectric layer is disposed between the control word line 504 and the control channel structure 150, and can be used as the gate dielectric layer of a control element CTD (a field-effect transistor). The control gate dielectric layer may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more thereof.

[0058] See Figure 2 The control word line 504 extends along a third direction, which is located on a plane parallel to the first direction (e.g., the xz plane) and not parallel to the first direction (i.e., the z-direction). In an embodiment, the third direction can be the x-direction, which is perpendicular to both the first and second directions. Therefore, the bit line 502, the control source line 503, and the control word line 504 can each extend in a direction perpendicular to each other.

[0059] The control word line 504 is arranged to be spaced apart from the bit line 502 in a second direction (i.e., the y-direction). Therefore, the control word line 504 can be electrically insulated from the bit line 502. The control word line 504 may comprise a conductive material substantially the same as the conductive material described for the reference source line 501 or the bit line 502.

[0060] exist Figure 2 In this process, an interlayer insulating layer can be disposed in the space between numbered components disposed on the substrate 101. The interlayer insulating layer can be used to electrically insulate two numbered components from each other.

[0061] In some embodiments, the electrochemical storage element (ECMD) is disposed on a plane above the substrate 101, rather than directly on the substrate 101. In this case, the source line 501, the storage channel layer 110, and the bit line 502 are disposed on the same plane above the substrate 101. The control circuit structure or interconnect structure for controlling or driving the storage cell M can be disposed between the substrate 101 and the plane on which the electrochemical storage element (ECMD) is disposed.

[0062] Figure 3 and Figure 4 This is a schematic cross-sectional view illustrating an operation method of a storage cell according to an embodiment of the present disclosure. Specifically, Figure 3 schematically shown Figure 2 The first write operation of storage unit M. Figure 4 schematically shown Figure 2 The second write operation of the storage unit M. Figure 5 and Figure 6 This is a schematic diagram illustrating the conductivity value of the storage channel layer relative to the write voltage applied to the storage cell according to an embodiment of the present disclosure.

[0063] refer to Figure 3 The first write operation can be performed as follows: A gate voltage of threshold voltage or higher is applied to control word line 504 to turn on control element CTD and form a conductive channel in control channel structure 150. In one embodiment, when control channel structure 150 has p-type semiconductor characteristics, the gate voltage can be positive. In another embodiment, when control channel structure 150 has n-type semiconductor characteristics, the gate voltage can be negative.

[0064] When the control element CTD is turned on, a positive first control voltage is applied to the control source line 503. This first control voltage can apply a positive first write voltage to the floating gate electrode layer 140 of the electrochemical memory element ECMD through a conductive channel. In this case, ground voltage is applied to the source line 501 and bit line 502 of the electrochemical memory element ECMD. Figure 3In this context, the process of applying the first write voltage is denoted as 'PF'.

[0065] A first write voltage creates an electric field between the floating gate electrode layer 140 and the storage channel layer 110. In one embodiment, the electric field causes positive ions distributed within the ion storage layer 130 to move through the electrolyte layer 120 to the storage channel layer 110. Figure 3 In this embodiment, the process of moving positive ions is shown as 'MV1'. For example, positive ions may include hydrogen (H) ions, lithium (Li) ions, sodium (Na) ions, potassium (K) ions, or combinations of two or more of them. In another embodiment (not shown), an electric field moves negatively charged oxygen ions distributed within the storage channel layer 110 to the ion storage layer 130. As the oxygen ions move, positively charged oxygen vacancies are created in the storage channel layer 110.

[0066] As a result, due to the first write voltage, the concentration of positive ions or oxygen vacancies in the storage channel layer 110 increases. With the increase in the concentration of positive ions or oxygen vacancies in the storage channel layer 110, the channel conductivity of the storage channel layer 110 increases. Figure 3 In the figure, positive ions or oxygen vacancies distributed in the storage channel layer 110 are indicated by the reference numeral "I".

[0067] After the channel conductivity of the storage channel layer 110 increases, the control voltage is removed to turn off the control element CTD. Therefore, the first write voltage applied to the floating gate electrode layer 140 is removed. Even after the first write voltage is removed, the storage channel layer 110 can still maintain the increased channel conductivity, allowing the electrochemical memory element ECMD to store the channel conductivity as signal information.

[0068] In one embodiment, the channel conductivity of the storage channel layer 110 can increase linearly in proportion to the concentration of positive ions or oxygen vacancies. Therefore, the storage channel layer 110 can store multiple channel conductivities adjusted according to a first write voltage.

[0069] In one embodiment, the first write voltage may be provided in the form of a pulsed voltage. Specifically, when the control element CTD is turned on, a first control voltage in the form of a pulsed voltage is applied to the control source line 503, so that the first write voltage in the form of a pulsed voltage can be applied to the floating gate electrode layer 140.

[0070] See Figure 5 As the number of pulses of the first write voltage applied to the floating gate electrode layer 140 increases, the amount of positive ions moving from the ion pool layer 130 to the storage channel layer 110 or the amount of oxygen ions moving from the storage channel layer 110 to the ion storage layer 130 also increases. Therefore, the channel conductivity of the storage channel layer 110 will... Figure 5The number of pulses increases linearly in proportion to the first write voltage. Therefore, multiple channel conductivity values ​​can be effectively used to store multi-level signal information, wherein the multiple channel conductivity values ​​of the storage channel layer 110 change in a linear relationship.

[0071] refer to Figure 4 The second write operation can be performed as follows. As described above, a gate voltage of threshold voltage or higher is applied to control word line 504 to turn on control element CTD and form a conductive channel in control channel structure 150.

[0072] When the control element CTD is turned on, a second control voltage with negative polarity is applied to the control source line 503. This second control voltage can apply a second write voltage with negative polarity to the floating gate electrode layer 140 of the electrochemical memory element ECMD through a conductive channel. In this case, ground voltage is applied to the source line 501 and bit line 502 of the electrochemical memory element ECMD. Figure 4 In this context, the process of applying the second write voltage is denoted as "NF".

[0073] A second write voltage creates an electric field between the floating gate electrode layer 140 and the storage channel layer 110. In one embodiment, the electric field causes positive ions distributed within the storage channel layer 110 to move through the electrolyte layer 120 to the ion storage layer 130. Figure 4 In this embodiment, the process of moving positive ions is shown as "MV2". Therefore, the concentration of positive ions in the storage channel layer 110 can be reduced. In another embodiment (not shown), an electric field causes oxygen ions distributed within the ion storage layer 130 to move to the storage channel layer 110. As the oxygen ions move, the concentration of oxygen vacancies in the storage channel layer 110 decreases.

[0074] Therefore, due to the second write voltage, the concentration of positive ions or oxygen vacancies in the storage channel layer 110 decreases. As the concentration of positive ions or oxygen vacancies in the storage channel layer 110 decreases, the channel conductivity of the storage channel layer 110 decreases.

[0075] After the channel conductivity of the storage channel layer 110 decreases, the control voltage is removed to turn off the control element CTD, and the second write voltage applied to the floating gate electrode layer 140 is removed. Even after the second write voltage is removed, the storage channel layer 110 can still maintain the reduced channel conductivity, allowing the electrochemical storage element ECMD to store the channel conductivity as signal information.

[0076] In one embodiment, the channel conductivity of the storage channel layer 110 can decrease linearly in proportion to the concentration of positive ions or oxygen vacancies. In one embodiment, the second write voltage can be provided in the form of a pulsed voltage, substantially the same as described above regarding the first write voltage.

[0077] refer to Figure 6 As the number of pulses in the second write voltage applied to the floating gate electrode layer 140 increases, the amount of positive ions moving from the storage channel layer 110 to the ion storage layer 130 or the amount of oxygen ions moving from the ion storage layer 130 to the storage channel layer 110 can increase. As a result, the channel conductivity of the storage channel layer 110 can decrease linearly in proportion to the number of pulses of the second write voltage. Therefore, multiple channel conductivity values ​​can be effectively used to store multi-level signal information, wherein the multiple channel conductivity values ​​in the storage channel layer 110 change in a linear relationship.

[0078] As described above, the electrochemical storage element according to embodiments of this disclosure can realize multi-level signal information that varies linearly in proportion to the applied write voltage. As described below, the storage cell can be applied to an in-memory computing (CiM) device that stores multi-level signal information as weights and uses these weights to perform MAC (multiplication-cumulative) operations.

[0079] Figure 7 and Figure 8 This is a circuit diagram of a semiconductor device according to an embodiment of the present disclosure. (See reference...) Figure 7 and Figure 8 The semiconductor device IC1 includes multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2. The configuration of each of the multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2 can be... Figure 1 The configurations of the memory cells MC are basically the same. Multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2 of the semiconductor device IC1 can be applied to the CiM device that performs MAC operations.

[0080] Figure 7 and Figure 8Semiconductor device IC1 is shown, wherein n memory cells MC11, MC21, ..., MCn1 are arranged in the first column L1, and n memory cells MC12, MC22, ..., MCn2 are arranged in the second column L2. However, for ease of explanation, some memory cells are omitted. Only the first memory cell MC11, the second memory cell MC21, and the nth memory cell MCn1 are shown in the first column L1, and only the first memory cell MC12, the second memory cell MC22, and the nth memory cell MCn2 are shown in the second column L2.

[0081] See Figure 7 and Figure 8 In the first column L1, the first to nth storage units MC11, MC21, ..., and MC1n share the first bit line BL1. In the second column L2, the first to nth storage units MC12, MC22, ..., and MC2n share the second bit line BL2.

[0082] In the first row C1, a pair of first memory cells MC11 and MC12 share the first control word line CWL1 and the first source line SL1. In the second row C2, a pair of second memory cells MC21 and MC22 share the second control word line CWL2 and the second source line SL2. In this way, in the nth row Cn, a pair of nth memory cells MCn1 and MCn2 share the nth control word line CWLn and the nth source line SLn.

[0083] The first to nth memory cells MC11, MC21, ..., MCn1 of the first column L1 each have corresponding control source lines CSL11, CSL21, ..., and CSLn1. Furthermore, the first to nth memory cells MC11, MC21, ..., MCn1 of the first column L1 each have corresponding floating gate electrodes FG11, FG21, ..., and FGn1, and corresponding channels CH11, CH21, ..., and CHn1. Similarly, the first to nth memory cells MC12, MC22, ..., MCn2 of the second column L2 each have corresponding control source lines CSL12, CSL22, ..., and CSLn2. Furthermore, the first to nth memory cells MC12, MC22, ..., MCn2 of the second column L2 each have corresponding floating gate electrodes FG12, FG22, ..., and FGn2, and corresponding channels CH12, CH22, ..., and CHn2.

[0084] The following is for reference Figure 7The operation of writing weights used to perform MAC operations in multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2 will be described. The weights are stored as channel conductivity G11, G21, ..., Gn1, G12, G22, ..., Gn2 in the corresponding channels CH11, CH21, ..., CHn1, CH12, CH22, ..., and CHn2 of the multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2.

[0085] First, when a threshold voltage or a higher gate voltage is applied to the first control word line CWL1, the control gate electrodes CG11 and CG12 of the pair of first memory cells MC11 and MC12 in the first row C1 are turned on. With the control gate electrodes CG11 and CG12 turned on, when control voltages V11 and V12 are applied to the pair of control source lines CSL11 and CSL12 respectively, a write voltage can be applied to the pair of floating gate electrodes FG11 and F12. Through the write voltage, channel conductivities G11 and G12 can be stored in the pair of channels CH11 and CH12 respectively.

[0086] Furthermore, when a threshold voltage or higher gate voltage is applied to the second control word line CWL2, and control voltages V21 and V22 are applied to a pair of control source lines CSL21 and CSL22, channel conductivities G21 and G22 can be stored in a pair of channels CH21 and CH22. Similarly, when a threshold voltage or higher gate voltage is applied to the nth control word line CWLn, and control voltages Vn1 and Vn2 are applied to a pair of control source lines CSLn1 and CSLn2, channel conductivities Gn1 and Gn2 can be stored in a pair of channels CHn1 and CHn2.

[0087] The channel conductivity stored in multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2 of semiconductor device IC1 forms a 2xn matrix, as shown in equation (1) below.

[0088]

[0089] In the following text, refer to Figure 8 This section will briefly describe the operation of performing MAC operations using weights stored in multiple storage units MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2.

[0090] exist Figure 8In the configuration, channel conductivities G11, G21, ..., Gn1, G12, G22, ..., and Gn2 are stored in the channels CH11, CH21, ..., CHn1, CH12, CH22, ..., and CHn2 of multiple memory cells MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2, respectively. First to nth source voltages V1, V2, ..., and Vn are applied to the first to nth source lines SL1, SL2, ..., and SLn, respectively. Subsequently, in the first column L1, a MAC operation is performed between the first to nth source voltages V1, V2, ..., and Vn and the channel conductivities G11, G21, ..., and Gn1 of the first to nth channels CH11, CH21, ..., and CHn1 to output the first line current I1 through the first line BL1. Furthermore, in the second column L2, a MAC operation is performed between the first to nth source voltages V1, V2, ..., Vn and the channel conductivities G12, G22, ..., Gn2 of the first to nth channels CH12, CH22, ..., CHn2 to output the second bit line current I2 through the second bit line BL2.

[0091] MAC operations can be performed according to the following formula (2).

[0092]

[0093] Figure 9 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure. Figure 10 It is shown Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line I-I'. Figure 11 It is shown Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line II-II'. Figure 12 It is shown Figure 9 A diagram of a semiconductor device shown on the xy plane, taken along line III-III'. Figure 13 It is shown Figure 9 A diagram of a semiconductor device shown along line IV-IV' and plotted on the xy plane.

[0094] See Figure 9 Semiconductor device 1 includes multiple memory cells. Figure 9 For convenience, some storage units have been omitted. Only the first storage unit M11, the second storage unit M21, and the nth storage unit Mn1 are shown in the first column L1. Similarly, only the first storage unit M12, the second storage unit M22, and the nth storage unit Mn2 are shown in the second column L2.

[0095] The configuration of each of the multiple storage units can be referenced above. Figure 2 The configurations of the described storage cells M are substantially the same. As an example, each of the multiple storage cells includes a control element CTD and an electrochemical storage element ECMD that are electrically connected to each other.

[0096] The circuit configuration of semiconductor device 1 can follow the reference. Figure 7 and Figure 8 The circuit diagram of the semiconductor device IC1 is described. Specifically, in the semiconductor device 1, the first to nth memory cells M11, M21, ... and Mn1 located in the first column L1 share the first bit line 1020a. Furthermore, in the semiconductor device 1, the first to nth memory cells M21, M22, ... and Mn2 located in the second column L2 share the second bit line 1020b.

[0097] Furthermore, a pair of first memory cells M11 and M12 in the first row C1 share a first control word line 1030. The pair of first memory cells M11 and M12 each have corresponding control source lines 1040a and 1040b and corresponding source lines 1010a and 1010b. Although not shown, the source lines 1010a and 1010b of the pair of first memory cells M11 and M12 can be electrically connected to each other. That is, during operation of the semiconductor device 1, the source lines 1010a and 1010b have the same potential.

[0098] In the second row C2, a pair of second memory cells M21 and M22 share a second control word line 2030. The pair of second memory cells M21 and M22 each have corresponding control source lines 2040a and 2040b and corresponding source lines 2010a and 2010b. Although not shown, the source lines 2010a and 2010b of the pair of second memory cells M21 and M22 can be electrically connected to each other. Similarly, in the nth row Cn, a pair of nth memory cells Mn1 and Mn2 share an nth control word line N030. The pair of nth memory cells Mn1 and Mn2 each have corresponding control source lines N040a and N040b and corresponding source lines N010a and N010b. Although not shown, the source lines N010a and N010b of the pair of nth memory cells Mn1 and Mn2 can be electrically connected to each other.

[0099] Although Figure 9 Not shown, but semiconductor device 1 may also include memory cells arranged along the y-direction. As an example, see reference... Figures 11 to 13The semiconductor device 1 may further include a pair of memory cells M21' and M22' spaced apart in the y-direction from the pair of second memory cells M21 and M22 disposed in the second row C2. The memory cells M21 and M21' spaced apart in the y-direction share a control source line 2040a and a source line 2010a. The memory cells M22 and M22' spaced apart in the y-direction share a control source line 2040b and a source line 2010b. Similarly, the remaining memory cells of the semiconductor device 1 may also include memory cells spaced apart in the y-direction and sharing a control source line and a source line. The memory cells may be repeatedly arranged in the y-direction.

[0100] The following is for reference Figures 9 to 13 The configuration of semiconductor device 1 will be described in more detail using multiple second memory cells M21, M21', M22, and M22' arranged in the second row C2. For convenience, located in Figure 9 The second storage cell M21 in the first column L1 is called the left storage cell M21, located in Figure 9 The second storage cell M22 in the second column L2 is called the right storage cell M22.

[0101] Reference Figures 9 to 13 Semiconductor device 1 includes a pair of first bit lines 1020a and 1020a' and a pair of second bit lines 1020b and 1020b', which extend along a first direction (i.e., the z-direction) perpendicular to the substrate. The pair of first bit lines 1020a and 1020a' and the pair of second bit lines 1020b and 1020b' are arranged to be spaced apart from each other and electrically insulated.

[0102] refer to Figure 9 and Figure 13 The left memory cell M21 includes a memory channel layer 1100 and a source line 2010a, which are arranged on a plane S21 above the substrate. The memory channel layer 1100 has a predetermined channel length along a third direction (i.e., the x-direction) perpendicular to the first and second directions.

[0103] In the left memory cell M21, the source line 2010a contacts one end of the memory channel layer 1100. Furthermore, the source line 2010a is configured to extend along a second direction (i.e., the y-direction). Therefore, the source line 2010a contacts one end of the memory channel layer 1100 of another memory cell M21', which is spaced apart from the left memory cell M21 in the second direction.

[0104] Each of the pair of first lines 1020a and 1020a' contacts the other end of the memory channel layer 1100. The pair of first lines 1020a and 1020a' are electrically connected to the source line 2010a through the corresponding memory channel layer 1100. In another memory cell M21' that shares the source line 2010a with the left memory cell M21, the other end of the memory channel layer 1100 is electrically connected to another first line 1020a', which is spaced apart from the first line 1020a in the y direction.

[0105] Similarly, the right memory cell M22 includes a memory channel layer 2100 and a source line 2010b, which are disposed on a plane S22 above the substrate. The memory channel layer 2100 has a predetermined channel length along a third direction (i.e., the x-direction).

[0106] In the right memory cell M22, the source line 2010b contacts one end of the memory channel layer 2100. Furthermore, refer to... Figure 13 The source line 2010b is configured to extend along the second direction (i.e., the y-direction). Therefore, the source line 2010b contacts one end of the storage channel layer 2100 of another storage cell M22' spaced apart from the right storage cell M22 along the second direction.

[0107] Each of the pair of second bit lines 1020b and 1020b' contacts the other end of the corresponding memory channel layer 2100. Each of the pair of second bit lines 1020b and 1020b' is electrically connected to the source line 2010b through the corresponding memory channel layer 2100. (Reference) Figure 13 In another memory cell M22' that shares source line 2010b with right memory cell M22, the other end of memory channel layer 2100 is electrically connected to another second bit line 1020b', which is spaced apart from second bit line 1020b in the y direction.

[0108] Although Figure 9 and Figure 13 Although not shown in the diagram, the source line 2010a of the left memory cell M21 and the source line 2010b of the right memory cell M22 can be electrically connected to each other. Therefore, when the semiconductor device 1 is operating, the pair of source lines 2010a and 2010b can maintain the same potential.

[0109] The configurations of source lines 2010a and 2010b, memory channel layers 1100 and 2100, first bit lines 1020a and 1020a', and second bit lines 1020b and 1020b' can be referenced above. Figure 2 The configurations of the source line 501, memory channel layer 110, and bit line 502 described are basically the same.

[0110] See Figure 9 In the left-hand storage cell M21, an electrolyte layer 1200 is disposed on the storage channel layer 1100. An ion storage layer 1300 is disposed on the electrolyte layer 1200. A floating gate electrode layer 1400 is disposed on the ion storage layer 1300. Figure 12 As shown, the floating gate electrode layer 1400 of the left memory cell M21 is spaced apart from the first bit line 1020a. Similarly, in the right memory cell M22, the electrolyte layer 2200 is disposed on the storage channel layer 2100. An ion storage layer 2300 is disposed on the electrolyte layer 2200. A floating gate electrode layer 2400 is disposed on the ion storage layer 2300. The floating gate electrode layer 2400 of the right memory cell M22 is spaced apart from the second bit line 1020b.

[0111] The configuration of electrolyte layers 1200 and 2200, ion storage layers 1300 and 2300, and floating gate electrode layers 1400 and 2400 can be the same as described above. Figure 2 The electrolyte layer 120, ion storage layer 130 and floating gate electrode layer 140 are configured in basically the same way.

[0112] See Figure 9 Control channel structures 1500 and 2500 are respectively disposed on the floating gate electrode layers 1400 and 2400 of the left memory cell M21 and the right memory cell M22. Control channel structures 1500 and 2500 can be referenced above. Figure 2 The control channel structure 150 described is basically the same. (See also...) Figure 9 and Figure 11 Both the control channel structures 1500 and 2500 are square column structures, but the shape of the column structure is not necessarily limited to this. The structure can be in the form of a cylinder, an elliptical column, or various polygonal columns.

[0113] The control channel structures 1500 and 2500 are respectively overlapped with the floating gate electrode layers 1400 and 2400 in the first direction (i.e., the z-direction). (Reference) Figure 11 The control channel structures 1500 and 2500 are configured to be spaced apart from the first and second bit lines 1020a, 1020a', 1020b and 1020b' in the lateral direction (e.g., the x direction).

[0114] Control gate dielectric layers 1600 and 2600 are respectively disposed on the side surfaces of control channel structures 1500 and 2500. (Reference) Figure 11 Control gate dielectric layers 1600 and 2600 are respectively disposed on the side surfaces of control channel structures 1500 and 2500 in the xz plane. The configuration of control gate dielectric layers 1600 and 2600 can be the same as that described above. Figure 2The configurations of the control gate dielectric layers described are basically the same.

[0115] Control word lines 2030 and 2030' are disposed on control gate dielectric layers 1600 and 2600. Control word lines 2030 and 2030' extend in a third direction (i.e., the x-direction) in the xz plane. The configuration of control word lines 2030 and 2030' can be referenced above. Figure 2 The configuration of the control word line 504 described is basically the same.

[0116] refer to Figure 11 The control word line 2030 is configured to be spaced apart from bit lines 1020a and 1020b in the second direction (i.e., the y-direction). Memory cell M21 and memory cell M22 share the control word line 2030, which is configured to contact the gate dielectric layers 1600 and 2600 of memory cells M21 and M22, respectively. The control word line 2030' is configured to be spaced apart from bit lines 1020a' and 1020b' in the second direction (i.e., the y-direction). Memory cell M21' and memory cell M22' share the control word line 2030', which is configured to contact the gate dielectric layers 1600 and 2600 of memory cells M21' and M22', respectively.

[0117] refer to Figure 9 The control source lines 2040a and 2040b can be respectively disposed on the control channel structures 1500 and 2500. The configuration of the control source lines 2040a and 2040b can be referenced above. Figure 2 The configuration of the control source pole line 503 described is basically the same.

[0118] refer to Figure 10 Control source lines 2040a and 2040b extend along a second direction (i.e., the y-direction) in the xy-plane. Control source line 2040a is spaced apart from bit lines 1020a and 1020a' in a third direction (i.e., the x-direction). Memory cells M21 and M21' share control source line 2040a. Furthermore, control source line 2040b is spaced apart from bit lines 1020b and 1020b' in a third direction (i.e., the x-direction). Memory cells M22 and M22' share control source line 2040b.

[0119] Figures 9 to 13 An interlayer insulation layer IL is provided in the space between the numbered components. The interlayer insulation layer IL is used to electrically insulate the numbered components from each other.

[0120] As described above, according to one embodiment of the present disclosure, a semiconductor device with a three-dimensional structure can be effectively implemented as follows: pairs of memory cells spaced apart in a third direction (i.e., the x-direction) share a control word line that also extends in the third direction (i.e., the x-direction), and the memory cell pairs can be stacked along a first direction (i.e., the z-direction). As described above, according to one embodiment of the present disclosure, a semiconductor device with a three-dimensional structure can be effectively implemented as follows: pairs of memory cells spaced apart in a second direction (i.e., the y-direction) share a source line and a control source line that both extend in the second direction. The memory cell pairs can be stacked along the first direction (i.e., the z-direction).

[0121] Figure 14 This is a circuit diagram of a semiconductor device according to another embodiment of the present disclosure. (Refer to...) Figure 14 , with reference to the above Figure 7 Compared to the semiconductor device IC1, the semiconductor device IC2 further includes multiple memory cells MC13, MC23, ..., MCn3, MC14, MC24, ... and MCn4 arranged in the third column L3 and the fourth column L4 along the x direction.

[0122] The configuration of multiple storage units MC13, MC23, ..., MCn3, MC14, MC24, ..., and MCn4 in the third column L3 and the fourth column L4 can be basically the same as the configuration of multiple storage units MC11, MC21, ..., MCn1, MC12, MC22, ..., and MCn2 in the first column L1 and the second column L2.

[0123] The multiple memory cells MC13, MC23, ..., MCn3 of the third column L3 store multiple channel conductivities G13, G23, ..., Gn3 in multiple channels CH13, CH23, ..., CHn3 by gate voltages applied from multiple control word lines CWL1, CWL2, ..., CWLn and write voltages applied to multiple floating gate electrodes FG13, FG23, ..., FGn3 via multiple control source lines CSL13, CSL23, ..., CSLn3. Similarly, the multiple memory cells MC14, MC24, ..., MCn4 in the fourth column L4 store multiple channel conductivities G14, G24, ..., Gn4 in multiple channels CH14, CH24, ..., CHn4 by gate voltages applied from multiple control word lines CWL1, CWL2, ..., CWLn and write voltages applied to multiple floating gate electrodes FG14, FG24, ..., FGn4 via multiple control source lines CSL14, CSL24, ..., CSLn4. Therefore, the multiple channel conductivities stored in the four columns and three rows of memory cells of the semiconductor device IC2 can be used as weights for MAC operations.

[0124] Subsequently, the first to nth source voltages V1, V2, ..., Vn are respectively input to... Figure 14 The first to nth source lines SL1, SL2, ... and SLn of the semiconductor device IC2, and accordingly, perform MAC operations on multiple memory cells MC11, MC21, ... MCn1, MC12, M22, ..., MCn2, MC13, MC23, ... MCn3, MC14, MC24, ... and MCn4.

[0125] The MAC operation can be performed as a process of obtaining the first to fourth bit line currents I1, I2, I3 and I4 output via the first to fourth bit lines BL1, BL2, BL3 and BL4 respectively. Equation (3) below shows the determinants of the MAC operation.

[0126]

[0127] As mentioned above, Figure 14 The circuit diagram shows multiple memory cells arranged in four columns and three rows, but the concept of this disclosure is not necessarily limited to this. Different numbers of memory cells arranged in various columns and rows can also be used, provided the conditions for performing MAC operations are met. Figure 14 The columns and rows shown can be arranged into a three-dimensional structure by repeating them in the horizontal direction.

[0128] Figure 15 This is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure. Figure 15 Semiconductor device 2 can follow Figure 14 The circuit diagram of semiconductor device IC2.

[0129] and Figures 9 to 13 Compared to semiconductor device 1, Figure 15 The semiconductor device 2 also includes a plurality of memory cells M13, M23, ..., Mn3, M14, M24, ... and Mn4 arranged in a third column L3 and a fourth column L4 along the x-direction. The configuration of the plurality of memory cells M13, M23, ..., Mn3, M14, M24, ... and Mn4 in the third column L3 and the fourth column L4 can be substantially the same as the configuration of the plurality of memory cells M11, M21, ..., Mn1, M12, M22, ... and Mn2 in the first column L1 and the second column L2.

[0130] like Figure 15As shown, multiple memory cells M13, M23, ..., and Mn3 in the third column L3 share the third bit line 1020c. These memory cells M13, M23, ..., and Mn3 each have corresponding source lines 1010c, 2010c, ..., and N010c, and corresponding control source lines 1040c, 2040c, ..., and N040c. Multiple memory cells M14, M24, ..., and Mn4 in the fourth column L4 share the third bit line 1020d. These memory cells M14, M24, ..., and Mn4 each have corresponding source lines 1010d, 2010d, ..., and N010d, and corresponding control source lines 1040d, 2040d, ..., and N040d.

[0131] Figure 15 A plurality of memory cells arranged in four columns and n rows in the xz plane is shown, but the concept of this disclosure is not necessarily limited thereto. Other numbers of memory cells, including multiple numbers of columns and rows extending in at least one of the x, y, and z directions, may be applied, provided that the conditions for performing MAC operations are met.

[0132] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 15 Compared to semiconductor device 2, Figure 16 The semiconductor device 3 has different arrangements of bit lines 1021a, 1021b, 1021c and 1021d and source lines 1011a, 1011b, 1011c, 1011d, 2011a, 2011b, 2011c, 2011d, N011a, N011b, N011c and N011d. Figure 16 The semiconductor device 3 can be reused Figure 14 The circuit diagram of the semiconductor device IC2.

[0133] refer to Figure 16In the first column L1, the first bit line 1021a is positioned to the left of the first to nth memory cells M11, M21, ..., and Mn1, while the source lines 1011a, 2011a, ..., and N011a are positioned to the right of the corresponding memory cells M11, M21, ..., and Mn1, respectively. In the second column L2, the second bit line 1021b is positioned to the left of the first to nth memory cells M12, M22, ..., and Mn2, while the source lines 1011b, 2011b, ..., and N011b are positioned to the right of the corresponding memory cells M12, M22, ..., and Mn2, respectively. Similarly, in the third column L3, the third bit line 1021c is positioned to the left of the first to nth memory cells M13, M23, ..., and Mn3, while the source lines 1011c, 2011c, ..., and N011c are positioned to the right of their respective first to nth memory cells M13, M23, ..., and Mn3. In the fourth column L4, the fourth bit line 1021d is positioned to the left of the first to nth memory cells M14, M24, ..., and Mn4, while the source lines 1011d, 2011d, ..., and N011d are positioned to the right of their respective first to nth memory cells M14, M24, ..., and Mn4.

[0134] As described above, in the semiconductor device according to the disclosed embodiments, the bit lines and source lines in all memory cells can be arranged in the same manner, for example, on opposite sides.

[0135] Figure 17 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. Reference Figure 17 The semiconductor device 4 includes: first to nth memory cells M11', M21', ... and Mn1' in the first column L1, which share a first bit line 1022a; and first to nth memory cells M12', M22', ... and Mn2' in the second column L2, which share a second bit line 1022b.

[0136] Each of the first to nth storage cells M11', M21', ..., Mn1', M12', M22', ..., Mn2' in the first column L1 and the second column L2 has a control element SD and an electrochemical storage element ECMD. In one embodiment, the control element SD may be a selection device.

[0137] Each control element SD includes a threshold switch layer 1700 disposed on the floating gate electrode layer 1400. Each control element SD is connected to a corresponding control source line among the control source lines 1040a, 2040a, ..., N040a, 1040b, 2040b, ... and N040b disposed on the threshold switch layer 1700 and extending along a second direction (i.e., the y-direction). The threshold switch layer 1700 is configured to contact the control source lines 1040a, 2040a, ..., N040a, 1040b, 2040b, ... and N040b, as well as the floating gate electrode layer 1400.

[0138] When a control voltage of threshold voltage or higher is applied to the threshold switching layer 1700 from the control source lines 1040a, 2040a, ..., N040a, 1040b, 2040b, ..., and N040b, a current equal to or greater than a predetermined reference current flows through the threshold switching layer 1700, thus turning the threshold switching layer 1700 on. Conversely, when a control voltage less than the threshold voltage is applied to the threshold switching layer 1700 from the control source lines 1040a, 2040a, ..., N040a, 1040b, 2040b, ..., N040b, a current less than the reference current flows through the threshold switching layer 1700, thus turning the threshold switching layer 1700 off. Therefore, the threshold switching layer 1700 can more precisely control the application of the write voltage to the floating gate electrode layer 1400 of the electrochemical memory element ECMD.

[0139] In one embodiment, the threshold switching layer 1700 comprises a resistance-changing material. As an example, the threshold switching layer 1700 comprises a metal oxide containing oxygen vacancies. The metal oxide may include, for example, tantalum oxide, hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0140] The configuration of the electrochemical storage element ECMD is combined with the above. Figure 9 The configuration of the electrochemical storage element ECMD in the semiconductor device 1 described is substantially the same. In one embodiment, in the plurality of memory cells of the semiconductor device 4, when the threshold switch layer 1700 is turned on, a write operation is performed by applying a write voltage from the control source line to the floating gate electrode layer in the memory cell, wherein the channel conductivity is stored in the channel layer. In the semiconductor device 4, the process of performing a MAC operation based on the source voltage input to the plurality of source lines and the channel conductivity of the plurality of memory cells can be the same as described above for the semiconductor device 4. Figure 9 The process described for semiconductor device 1 is basically the same.

[0141] Figures 18 to 20 This is a schematic cross-sectional view illustrating the arrangement of memory cells in a semiconductor device according to various embodiments of the present disclosure. Figures 18 to 20 The arrangement of storage cells in the memory can be used for Figures 9 to 13The arrangement of multiple memory cells in semiconductor device 1 Figure 15 The arrangement of multiple memory cells in semiconductor device 2 Figure 16 The arrangement of multiple memory cells in semiconductor device 3, and Figure 17 The arrangement of multiple memory cells in semiconductor device 4.

[0142] See Figure 18 In one embodiment, a plurality of memory cells of one of semiconductor devices 1, 2, 3, and 4 are disposed in a cell region CR of substrate 1010. A plurality of control circuits for controlling and driving the plurality of memory cells are disposed in a peripheral circuit region PR within substrate 1010. The peripheral circuit region PR does not overlap with the cell region CR in the vertical direction (i.e., the z-direction). That is, the peripheral circuit region PR may be configured to be spaced apart from the cell region CR in the lateral direction (e.g., the x-direction or the y-direction).

[0143] The connection region CNR is directly disposed above the peripheral circuit region PR. The connection region CNR can be configured to be spaced apart from the cell region CR in the lateral direction (e.g., the x-direction or the y-direction). Multiple memory cells in the cell region CR and multiple control circuits in the peripheral circuit region PR are electrically connected to each other via a three-dimensional interconnect disposed in the connection region CNR.

[0144] [refer to Figure 19 In another embodiment, a peripheral circuit region PR is disposed on a substrate 1010, and a cell region CR is disposed on the peripheral circuit region PR. The cell region CR and the peripheral circuit region PR are configured to overlap each other in a direction perpendicular to the substrate 1010 (i.e., the z-direction). Although not shown, the interconnect between the peripheral circuit region PR and the cell region CR can be disposed in the overlapping region of the peripheral circuit region PR and the cell region CR along the vertical direction (i.e., the z-direction). An interlayer insulating layer (ISR) is used instead of a connection region. Figure 18 The CNR in the cell region is set in the lateral direction (e.g., the x or y direction) of the cell region CR.

[0145] See Figure 20In another embodiment, a peripheral circuit region PR is disposed on a substrate 1010, and first to third cell regions CR1, CR2, and CR3 are sequentially disposed on the peripheral circuit region PR. Multiple control circuits in the peripheral circuit region PR control multiple memory cells in the first to third cell regions CR1, CR2, and CR3. Therefore, multiple memory cells can be efficiently stacked on a cell region basis in a direction perpendicular to the substrate 1010 (i.e., the z-direction). That is, multiple memory cells are disposed in the first cell region CR1, multiple other memory cells are disposed in the second cell region CR2, and multiple other memory cells are disposed in the third cell region CR3. Therefore, by sequentially stacking multiple cell regions on the peripheral circuit region PR, the process complexity of stacking multiple memory cells in three dimensions can be reduced, thereby reducing process costs.

[0146] The concept has been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will recognize that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered limiting but rather illustrative. The scope of the concept is not limited to the foregoing description but is defined by the appended claims, and all distinctive features within the equivalent scope should be construed as being included in the concept.

Claims

1. A storage unit comprising an electrochemical storage element and a control element electrically connected to each other, in, The electrochemical storage element includes: The source line is set on a plane; Bit lines are configured to be spaced apart from the source lines and extend in a vertical direction perpendicular to the plane; A storage channel layer is disposed on the plane to connect to the source line and the bit line; An electrolyte layer is disposed on the storage channel layer; An ion storage layer is disposed on the electrolyte layer; and A floating gate electrode layer is disposed on the ion storage layer, and The control element includes: The control channel structure is disposed on the floating gate electrode layer; A control source line is disposed on the control channel structure; A control gate dielectric layer is disposed on a side surface of the control channel structure; and The control word line is disposed on the control gate dielectric layer.

2. The storage unit according to claim 1, in, The bit line extends along a first direction, which is the vertical direction. Wherein, each of the source line and the control source line extends along a second direction perpendicular to the first direction, and The control word line extends along a third direction, which is not parallel to the first direction and lies on a plane parallel to the first direction.

3. The storage unit according to claim 1, wherein, The ion storage layer includes ions that can exchange with the storage channel layer.

4. The storage unit according to claim 3, wherein, The concentration of ions exchanged between the ion storage layer and the storage channel layer is controlled by the voltage applied to the floating gate electrode layer.

5. The storage unit according to claim 3, wherein, The ions include at least one of hydrogen (H) ions, lithium (Li) ions, sodium (Na) ions, potassium (K) ions, and oxygen (O) ions.

6. The storage unit according to claim 3, wherein, The channel conductivity of the storage channel layer varies linearly with the concentration of the ions in the storage channel layer.

7. The storage unit according to claim 1, wherein, The storage channel layer receives ions provided by the ion storage layer.

8. The storage unit according to claim 1, wherein, The storage channel layer comprises at least one of a metal, a metal oxide, a metal chalcogenide, and polysilicon.

9. The storage unit according to claim 1, in, The ion storage layer comprises at least one of palladium hydride, magnesium hydride, yttrium hydride, hydrogen-containing silicon, and hydrogen-containing gallium arsenide. The electrolyte layer comprises at least one of proton exchange polymers, metal-organic frameworks, sulfonate graphene, and polymer-graphene composite materials. The storage channel layer includes at least one of palladium (Pd), magnesium (Mg), and yttrium (Y).

10. The storage unit according to claim 1, in, The ion storage layer includes: Li x MO2, where 0 < x ≤ 1 and M includes at least one of titanium Ti, vanadium V, chromium Cr, manganese Mn, iron Fe, cobalt Co, and nickel Ni; Na x MO2, where 0 < x ≤ 1 and M includes at least one of iron Fe, cobalt Co, manganese Mn, nickel Ni, and copper Cu; K x MnO2, where 0 < x ≤ 1; and K x CoO2, where 0 < x ≤ 1, The electrolyte layer comprises at least one of lithium phosphorus nitride (LiPON), sulfonated tetrafluoroethylene vinyl fluoropolymer copolymer, polystyrene-based film, sulfonated polyimide (SPI)-based film, polyphosphazene-based film, and polybenzimidazole (PBI)-based film. The storage channel layer includes at least one of tungsten oxide (WO3), molybdenum sulfide (MoS2), tungsten sulfide (WS2), and tin sulfide (SnS2).

11. The storage unit according to claim 1, in, The ion storage layer includes: gadolinium oxide GdO x , where 0 < x ≤ 1; molybdenum oxide MoO x , where 0 < x ≤ 1; tungsten oxide WO 3-x , where 0 < x ≤ 1; copper oxide CuO; and at least one of titanium dioxide TiO2 The electrolyte layer comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), yttrium-stabilized zirconium oxide (YSZ), barium oxide-selenium-yttrium (Ba-Ce-YO), and zirconium oxide-scandium oxide (Zr-Sc-O), and... The storage channel layer includes at least one of tungsten oxide (WO3), molybdenum oxide (MoO3), selenium oxide (CeO3), iron oxide (Fe3O4), zirconium oxide (ZrO2), cobalt oxide (CoO), vanadium oxide (V2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), and yttrium oxide (Y2O3).

12. The storage unit according to claim 1, wherein, The control channel structure includes a pillar structure that connects the floating gate electrode layer to the control source electrode line.

13. A semiconductor device, comprising: Substrate; Bit lines extend along a first direction perpendicular to the surface of the substrate; as well as Multiple memory cells that share the bit lines are configured to be spaced apart from each other on the substrate in the first direction. Each of the plurality of storage cells includes an electrochemical storage element. The electrochemical storage element includes: The source line is configured to extend along a second direction on a plane perpendicular to the first direction on the substrate; A storage channel layer is configured to electrically connect the source line to the bit line on the plane; An electrolyte layer is disposed on the storage channel layer; An ion storage layer is disposed on the electrolyte layer; and A floating gate electrode layer is disposed on the ion storage layer.

14. The semiconductor device according to claim 13, wherein, Each of the plurality of memory cells also includes a control element electrically connected to the floating gate electrode layer.

15. The semiconductor device according to claim 14, wherein, The control element includes: The control channel structure is disposed on the floating gate electrode layer; A control source line is disposed on the control channel structure and extends along the second direction; A control gate dielectric layer is disposed on a side surface of the control channel structure; and The control word line contacts the control gate dielectric layer and extends along a third direction perpendicular to the first and second directions.

16. The semiconductor device according to claim 14, wherein, The control element includes: A threshold switching layer is disposed on the floating gate electrode layer; and The control source line is disposed on the threshold switch layer and extends along the second direction.

17. The semiconductor device according to claim 13, wherein, Each of the plurality of storage cells stores signal information corresponding to the conductivity value of the storage channel layer.

18. The semiconductor device according to claim 13, wherein, The ion storage layer includes ions that can exchange with the storage channel layer.

19. The semiconductor device according to claim 18, wherein, The concentration of the ions exchanged between the ion storage layer and the storage channel layer is controlled by the voltage applied to the floating gate electrode layer.

20. The semiconductor device according to claim 18, wherein, The channel conductivity of the storage channel layer varies linearly with the concentration of the ions in the storage channel layer.

21. The semiconductor device of claim 13, further comprising a plurality of control circuits for controlling the plurality of memory cells.

22. The semiconductor device according to claim 21, in, The plurality of control circuits are disposed in the peripheral circuit region located on the substrate, and The plurality of storage units are disposed in the unit region located on the peripheral circuit region.

23. A semiconductor device, comprising: Substrate; The first bit line and the second bit line extend along a first direction perpendicular to the surface of the substrate; as well as Pairs of memory cells, electrically connected to corresponding bit lines in the first and second bit lines and configured to be spaced apart from each other. Each of the paired storage cells includes an electrochemical storage element. The electrochemical storage element includes: A source line is configured to extend along a second direction on a plane perpendicular to the first direction above the substrate; A storage channel layer configured to electrically connect the source lines to the bit lines on the plane; An electrolyte layer is disposed on the storage channel layer; An ion storage layer disposed on the electrolyte layer; and A floating gate electrode layer, disposed on the ion storage layer, and The source lines of the paired memory cells are electrically connected to each other.

24. The semiconductor device according to claim 23, wherein, Each of the plurality of memory cells also includes a control element electrically connected to the floating gate electrode layer.

25. The semiconductor device according to claim 24, wherein, The control element includes: The control channel structure is disposed on the floating gate electrode layer; A control source line is disposed on the control channel structure and extends along the second direction; A control gate dielectric layer is disposed on a side surface of the control channel structure; and A control word line that contacts the control gate dielectric layer and extends along a third direction perpendicular to the first and second directions.

26. The semiconductor device according to claim 25, wherein, The paired memory cells share the control word line.

27. The semiconductor device according to claim 24, wherein, The control element includes: A threshold switching layer is disposed on the floating gate electrode layer; and The control source line is disposed on the threshold switch layer and extends along the second direction.

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